drm/amd/display: Fix surface optimization regression on Carrizo
commit 62e5a7e2333a9f5395f6a9db766b7b06c949fe7a upstream.
[Why]
DCE legacy optimization path isn't well tested under new DC optimization
flow which can result in underflow occuring when initializing X11 on
Carrizo.
[How]
Retain the legacy optimization flow for DCE and keep the new one for DCN
to satisfy optimizations being correctly applied for ASIC that can
support it.
Fixes: 34316c1e561db0 ("drm/amd/display: Optimize bandwidth on following fast update")
Reported-by: Tom St Denis <tom.stdenis@amd.com>
Tested-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Mario Limonciello <Mario.Limonciello@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
9581511948
commit
c2b484d784
@@ -2979,8 +2979,13 @@ void dc_commit_updates_for_stream(struct dc *dc,
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if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
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new_pipe->plane_state->force_full_update = true;
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}
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} else if (update_type == UPDATE_TYPE_FAST) {
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/* Previous frame finished and HW is ready for optimization. */
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} else if (update_type == UPDATE_TYPE_FAST && dc_ctx->dce_version >= DCE_VERSION_MAX) {
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/*
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* Previous frame finished and HW is ready for optimization.
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*
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* Only relevant for DCN behavior where we can guarantee the optimization
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* is safe to apply - retain the legacy behavior for DCE.
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*/
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dc_post_update_surfaces_to_stream(dc);
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}
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@@ -3039,6 +3044,12 @@ void dc_commit_updates_for_stream(struct dc *dc,
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}
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}
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/* Legacy optimization path for DCE. */
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if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) {
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dc_post_update_surfaces_to_stream(dc);
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TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
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}
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return;
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}
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