From c5e662db60beeaa2ef6778d65bde1ba5cb490d64 Mon Sep 17 00:00:00 2001 From: Will McVicker Date: Mon, 29 Aug 2022 22:22:29 +0000 Subject: [PATCH] Revert "BACKPORT: FROMLIST: PCI: dwc: Add support for 64-bit MSI target address" This reverts commit b38034b5d54e81f720d996cb26b68ac2c3bb6b56. Need to update this FROMLIST patch to pull in the v6 changes. It's been accepted into the maintainers tree now. Bug: 241473543 Change-Id: I1c829243199bf2ae4473d0979550f33496ba5f66 Signed-off-by: Will McVicker --- drivers/pci/controller/dwc/pcie-designware-host.c | 15 ++------------- drivers/pci/controller/dwc/pcie-designware.c | 8 -------- drivers/pci/controller/dwc/pcie-designware.h | 1 - 3 files changed, 2 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0861f3e748f4..110cd9f7f6eb 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -289,8 +289,6 @@ int dw_pcie_host_init(struct pcie_port *pp) struct resource *cfg_res; u64 *msi_vaddr; int ret; - bool msi_64bit = false; - u16 msi_capabilities; raw_spin_lock_init(&pci->pp.lock); @@ -368,18 +366,9 @@ int dw_pcie_host_init(struct pcie_port *pp) dw_chained_msi_isr, pp); - msi_capabilities = dw_pcie_msi_capabilities(pci); - if (msi_capabilities & PCI_MSI_FLAGS_ENABLE) - msi_64bit = msi_capabilities & PCI_MSI_FLAGS_64BIT; - - dev_dbg(dev, "Setting MSI DMA mask to %s-bit.\n", - msi_64bit ? "64" : "32"); - ret = dma_set_mask_and_coherent(dev, msi_64bit ? - DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) - dev_warn(dev, "Failed to set DMA mask to %s-bit.\n", - msi_64bit ? "64" : "32"); - + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, GFP_KERNEL); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 161ab9d3f304..d92c8a25094f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -55,14 +55,6 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); -u16 dw_pcie_msi_capabilities(struct dw_pcie *pci) -{ - u8 offset; - - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); - return dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); -} - static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, u8 cap) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 85da375d7207..10f5e073f478 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -285,7 +285,6 @@ struct dw_pcie { u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); -u16 dw_pcie_msi_capabilities(struct dw_pcie *pci); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val);