From d1096112e56a3393dc1adb12176e2aa8dfdba403 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 16 Nov 2022 16:32:59 +0000 Subject: [PATCH] Revert "usb: dwc3: core: Enable GUCTL1 bit 10 for fixing termination error after resume bug" This reverts commit 3a38985d8bfdc6b784d0f6990e8911579492518f which is commit 63d7f9810a38102cdb8cad214fac98682081e1a7 upstream. It breaks the kernel ABI for the dwc3 driver, and is not needed by Android-supported hardware, so it can be reverted. If it is determined that it needs to be added, it can be done so in an ABI-safe way in the future. Bug: 161946584 Signed-off-by: Greg Kroah-Hartman Change-Id: I61c42c2b2fbb962907b992eed70c267da2115fb4 --- drivers/usb/dwc3/core.c | 17 ----------------- drivers/usb/dwc3/core.h | 4 ---- 2 files changed, 21 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 9c200612e9bb..dd5ce37657ff 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1083,21 +1083,6 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } - /* - * When configured in HOST mode, after issuing U3/L2 exit controller - * fails to send proper CRC checksum in CRC5 feild. Because of this - * behaviour Transaction Error is generated, resulting in reset and - * re-enumeration of usb device attached. All the termsel, xcvrsel, - * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 - * will correct this problem. This option is to support certain - * legacy ULPI PHYs. - */ - if (dwc->resume_hs_terminations) { - reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); - reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; - dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); - } - if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); @@ -1440,8 +1425,6 @@ static void dwc3_get_properties(struct dwc3 *dwc) "snps,dis-del-phy-power-chg-quirk"); dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, "snps,dis-tx-ipgap-linecheck-quirk"); - dwc->resume_hs_terminations = device_property_read_bool(dev, - "snps,resume-hs-terminations"); dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, "snps,parkmode-disable-ss-quirk"); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 00c58b8c2a72..e31d1650fa21 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -262,7 +262,6 @@ #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) -#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10) /* Global Status Register */ #define DWC3_GSTS_OTG_IP BIT(10) @@ -1087,8 +1086,6 @@ struct dwc3_scratchpad_array { * change quirk. * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate * check during HS transmit. - * @resume-hs-terminations: Set if we enable quirk for fixing improper crc - * generation after resume from suspend. * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed * instances in park mode. * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk @@ -1301,7 +1298,6 @@ struct dwc3 { unsigned dis_u2_freeclk_exists_quirk:1; unsigned dis_del_phy_power_chg_quirk:1; unsigned dis_tx_ipgap_linecheck_quirk:1; - unsigned resume_hs_terminations:1; unsigned parkmode_disable_ss_quirk:1; unsigned tx_de_emphasis_quirk:1;