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12 Commits
bka ... vic

Author SHA1 Message Date
Michael Bestas
5d27721e82 b4s4: Migrade audio HAL to blueprint 
Change-Id: I589683d4f2f97b6dbc52fcaa1055a23b0cab8b06
 2025-09-22 16:41:03 +02:00
Michael Bestas
4cf2064552 b4s4: Remove userdebug/eng configuration 
Change-Id: I67b39c183415b5641e16f8ae383848e276825540
 2025-09-22 16:41:03 +02:00
Michael Bestas
fc3e2a913d b4s4: Drop unused AndroidBoard.mk 
Change-Id: I6149ebbec9ebb3687819d8c72c31ebf124056644
 2025-09-22 16:41:03 +02:00
Michael Bestas
86d0cf552f b4s4: Migrate mount point creation out of AndroidBoard.mk 
Change-Id: Id5986b8a740e45f864eecdd2bd82d9455f128d6b
 2025-09-22 16:41:03 +02:00
Michael Bestas
a3f2e0d3e7 b4s4: Drop unused in-tree kernel headers 
Change-Id: If871800764cdb47a4423c615c57267dea964bbe8
 2025-09-22 16:41:03 +02:00
Michael Bestas
31220c4439 b4s4: Resolve qtidataservices denial 
Fixes fatal crash of the dataservices app

Change-Id: I4acfa9eef648cbb36f1900cad91fc4fe19a9fe5d
 2025-09-22 16:41:03 +02:00
Michael Bestas
771cef6299 b4s4: Update namespace imports 
Change-Id: I646fb32c9cb84ac650e16f6568bdb0c214f53290
 2025-09-22 16:41:03 +02:00
Michael Bestas
475bda213b b4s4: Update display flags & packages 
Required after display HAL blueprint conversion

Change-Id: Ifc4e10703d3424607b9dc8bcc8e417d1c88cc2f3
 2025-09-22 16:41:03 +02:00
Nolen Johnson
abf67b7323 b4s4: sepolicy: Include AIDL LiveDisplay policy 
Change-Id: I6ed4f79bd17fdd214f000098ffae3ead2bf4c4da
 2025-09-22 16:41:03 +02:00
Nolen Johnson
9e4393adb4 b4s4: Migrate to AIDL LiveDisplay HAL 
Change-Id: I4e8be836e94d442b40c63a1ac7dade3c9d9c784c
 2025-09-22 16:41:03 +02:00
razorloves
caeab57a95 b4s4: Remove duplicate ipacm init entries 
These are already being done in
vendor/qcom/opensource/data-ipa-cfg-mgr-legacy-um

Change-Id: I207b1fd170a13381bdb6b0fd8178ecf15f8692f4
 2025-09-22 16:41:02 +02:00
Michael Bestas
998fbab8f6 b4s4: Remove deprecated config_mobile_tcp_buffers/networkAttributes 
Change-Id: Ieda947e283cde11cf74a01dc1b438e1deeb902c9
 2025-09-22 16:41:02 +02:00
206 changed files with 43 additions and 59342 deletions
Expand all files Collapse all files

23
BoardConfig-common.mk
View File

@@ -175,29 +175,6 @@ WIFI_FEATURE_WIFI_EXT_HAL := true
WIFI_FEATURE_IMU_DETECTION := false
WIFI_HIDL_UNIFIED_SUPPLICANT_SERVICE_RC_ENTRY := true
# Audio
BOARD_USES_ALSA_AUDIO := true
AUDIO_FEATURE_ENABLED_MULTI_VOICE_SESSIONS := true
AUDIO_FEATURE_ENABLED_SND_MONITOR := true
AUDIO_FEATURE_ENABLED_USB_TUNNEL := true
AUDIO_FEATURE_ENABLED_CIRRUS_SPKR_PROTECTION := true
BOARD_SUPPORTS_SOUND_TRIGGER := true
AUDIO_FEATURE_FLICKER_SENSOR_INPUT := true
SOUND_TRIGGER_FEATURE_LPMA_ENABLED := true
AUDIO_FEATURE_ENABLED_MAXX_AUDIO := true
BOARD_SUPPORTS_SOUND_TRIGGER_5514 := true
AUDIO_FEATURE_ENABLED_24BITS_CAMCORDER := true
# Graphics
TARGET_USES_GRALLOC1 := true
TARGET_USES_HWC2 := true
TARGET_USES_NV21_CAMERA_PREVIEW := true
# Display
TARGET_USES_DISPLAY_RENDER_INTENTS := true
TARGET_USES_COLOR_METADATA := true
TARGET_USES_DRM_PP := true
# Vendor Interface Manifest
DEVICE_MANIFEST_FILE := device/google/bonito/manifest.xml
DEVICE_MATRIX_FILE := device/google/bonito/compatibility_matrix.xml

1
BoardConfigLineage.mk
View File

@@ -15,7 +15,6 @@ TARGET_KERNEL_SOURCE := kernel/google/b4s4
TARGET_NEEDS_DTBOIMAGE := true
# Manifests
DEVICE_MANIFEST_FILE += device/google/bonito/lineage_manifest.xml
DEVICE_FRAMEWORK_COMPATIBILITY_MATRIX_FILE += vendor/lineage/config/device_framework_matrix.xml
# Partitions

1
acdbdata/OEM/sdm670-intcodec-b4-snd-card/workspaceFile.qwsp
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File diff suppressed because one or more lines are too long

1
acdbdata/OEM/sdm670-intcodec-s4-snd-card/workspaceFile.qwsp
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File diff suppressed because one or more lines are too long

60
bonito/AndroidBoard.mk
View File

@@ -1,60 +0,0 @@
LOCAL_PATH := $(call my-dir)
#A/B builds require us to create the mount points at compile time.
#Just creating it for all cases since it does not hurt.
FIRMWARE_MOUNT_POINT := $(TARGET_OUT_VENDOR)/firmware_mnt
ALL_DEFAULT_INSTALLED_MODULES += $(FIRMWARE_MOUNT_POINT)
$(FIRMWARE_MOUNT_POINT):
@echo "Creating $(FIRMWARE_MOUNT_POINT)"
@mkdir -p $(TARGET_OUT_VENDOR)/firmware_mnt
#----------------------------------------------------------------------
# Generate persist image (persist.img)
#----------------------------------------------------------------------
TARGET_OUT_PERSIST_IMG_PATH := $(PRODUCT_OUT)/persist
INTERNAL_PERSISTIMAGE_FILES := \
$(foreach pair,$(PRODUCT_COPY_FILES),\
$(if $(filter persist/%,$(call word-colon,2,$(pair))),\
$(call word-colon,1,$(pair)):$(PRODUCT_OUT)/$(call word-colon,2,$(pair))))
INSTALLED_PERSISTIMAGE_FILES := $(call copy-many-files,$(INTERNAL_PERSISTIMAGE_FILES))
INSTALLED_PERSISTIMAGE_TARGET := $(PRODUCT_OUT)/persist.img
$(INSTALLED_PERSISTIMAGE_TARGET): $(MKEXTUSERIMG) $(MAKE_EXT4FS) $(INSTALLED_PERSISTIMAGE_FILES)
$(call pretty,"Target persist fs image: $(INSTALLED_PERSISTIMAGE_TARGET)")
@mkdir -p $(TARGET_OUT_PERSIST_IMG_PATH)
$(hide) PATH=$(HOST_OUT_EXECUTABLES):$${PATH} $(MKEXTUSERIMG) -s $(TARGET_OUT_PERSIST_IMG_PATH) $@ ext4 persist $(BOARD_PERSISTIMAGE_PARTITION_SIZE)
$(hide) chmod a+r $@
$(hide) $(call assert-max-image-size,$@,$(BOARD_PERSISTIMAGE_PARTITION_SIZE))
$(call declare-1p-container,$(INSTALLED_PERSISTIMAGE_TARGET),)
$(call declare-container-license-deps,$(INSTALLED_PERSISTIMAGE_TARGET),$(INSTALLED_PERSISTIMAGE_FILES),$(INSTALLED_PERSISTIMAGE_TARGET):)
ALL_DEFAULT_INSTALLED_MODULES += $(INSTALLED_PERSISTIMAGE_TARGET)
ALL_MODULES.$(LOCAL_MODULE).INSTALLED += $(INSTALLED_PERSISTIMAGE_TARGET)
INSTALLED_RADIOIMAGE_TARGET += $(INSTALLED_PERSISTIMAGE_TARGET)
.PHONY: persistimage
persistimage: $(INSTALLED_PERSISTIMAGE_TARGET)
droidcore: $(INSTALLED_PERSISTIMAGE_TARGET)
# copy kernel headers to the build tree
$(TARGET_OUT_INTERMEDIATES)/KERNEL_OBJ/usr: $(wildcard $(PRODUCT_VENDOR_KERNEL_HEADERS)/*)
rm -rf $@
mkdir -p $@/include
cp -a $(PRODUCT_VENDOR_KERNEL_HEADERS)/. $@/include
#----------------------------------------------------------------------
# build and sign the final stage of bootloader
#----------------------------------------------------------------------
.PHONY: aboot
ifeq ($(USESECIMAGETOOL), true)
aboot: gensecimage_target gensecimage_install
else
aboot: $(INSTALLED_BOOTLOADER_MODULE)
endif

3
bonito/extract-files.py
View File

@@ -27,7 +27,8 @@ from extract_utils.main import (
namespace_imports = [
'hardware/google/interfaces',
'hardware/google/pixel',
'hardware/qcom/sdm845',
'hardware/qcom/sdm845/display',
'hardware/qcom/sdm845/gps',
'hardware/qcom/wlan/legacy',
]

15
device-common.mk
View File

@@ -79,9 +79,6 @@ PRODUCT_PRODUCT_PROPERTIES += \
ro.config.low_ram = false \
ro.lmk.log_stats = true \
# A2DP offload enabled for compilation
AUDIO_FEATURE_ENABLED_A2DP_OFFLOAD := true
# A2DP offload supported
PRODUCT_PROPERTY_OVERRIDES += \
ro.bluetooth.a2dp_offload.supported=true
@@ -94,6 +91,18 @@ persist.bluetooth.a2dp_offload.disabled=false
PRODUCT_PROPERTY_OVERRIDES += \
persist.bluetooth.a2dp_offload.cap=sbc-aac-aptx-aptxhd-ldac
# Audio
$(call soong_config_set,qtiaudio,feature_24bits_camcorder,true)
$(call soong_config_set,qtiaudio,feature_a2dp_offload,true)
$(call soong_config_set,qtiaudio,feature_cirrus_spkr_protection,true)
$(call soong_config_set,qtiaudio,feature_flicker_sensor_input,true)
$(call soong_config_set,qtiaudio,feature_hwdep_cal,true)
$(call soong_config_set,qtiaudio,feature_maxx_audio,true)
$(call soong_config_set,qtiaudio,feature_multi_voice_sessions,true)
$(call soong_config_set,qtiaudio,feature_snd_monitor,true)
$(call soong_config_set,qtiaudio,feature_usb_tunnel,true)
$(call soong_config_set,qtiaudio,feature_sound_trigger,true)
# Modem loging file
PRODUCT_COPY_FILES += \
device/google/bonito/init.logging.rc:$(TARGET_COPY_OUT_VENDOR)/etc/init/hw/init.$(PRODUCT_PLATFORM).logging.rc

8
device-lineage.mk
View File

@@ -39,7 +39,9 @@ $(call soong_config_set,lineage_health,charging_control_charging_disabled,1)
# LiveDisplay
PRODUCT_PACKAGES += \
vendor.lineage.livedisplay@2.0-service-sdm
vendor.lineage.livedisplay-service.sdm
$(call soong_config_set,livedisplay_sdm,enable_dm,false)
# Parts
PRODUCT_PACKAGES += \
@@ -60,6 +62,10 @@ PRODUCT_PACKAGES += \
PRODUCT_PACKAGES += \
disable_configstore
# Display
$(call soong_config_set,qtidisplay,drmpp,true)
$(call soong_config_set,qtidisplay,target_uses_nv21_camera_preview,true)
# Identity credential
PRODUCT_PACKAGES += \
android.hardware.identity_credential.xml

137
device.mk
View File

@@ -22,7 +22,9 @@ PRODUCT_SOONG_NAMESPACES += \
hardware/google/camera \
hardware/google/interfaces \
hardware/google/pixel \
hardware/qcom/sdm845 \
hardware/qcom/audio \
hardware/qcom/sdm845/display \
hardware/qcom/sdm845/gps \
hardware/qcom/wlan/legacy \
hardware/qcom-caf/bootctrl \
vendor/qcom/opensource/data-ipa-cfg-mgr-legacy-um
@@ -58,10 +60,6 @@ PRODUCT_PROPERTY_OVERRIDES += \
PRODUCT_PACKAGES += \
messaging
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_PACKAGES += chre_test_client
endif
LOCAL_PATH := device/google/bonito
TARGET_PRODUCT_PROP := $(LOCAL_PATH)/product.prop
@@ -100,17 +98,10 @@ PRODUCT_COPY_FILES += \
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/init.edge_sense.sh:$(TARGET_COPY_OUT_VENDOR)/bin/init.edge_sense.sh
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/init.hardware.diag.rc.userdebug:$(TARGET_COPY_OUT_VENDOR)/etc/init/hw/init.$(PRODUCT_PLATFORM).diag.rc
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/init.hardware.mpssrfs.rc.userdebug:$(TARGET_COPY_OUT_VENDOR)/etc/init/hw/init.$(PRODUCT_PLATFORM).mpssrfs.rc
else
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/init.hardware.diag.rc.user:$(TARGET_COPY_OUT_VENDOR)/etc/init/hw/init.$(PRODUCT_PLATFORM).diag.rc
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/init.hardware.mpssrfs.rc.user:$(TARGET_COPY_OUT_VENDOR)/etc/init/hw/init.$(PRODUCT_PLATFORM).mpssrfs.rc
endif
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/init.hardware.diag.rc.user:$(TARGET_COPY_OUT_VENDOR)/etc/init/hw/init.$(PRODUCT_PLATFORM).diag.rc
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/init.hardware.mpssrfs.rc.user:$(TARGET_COPY_OUT_VENDOR)/etc/init/hw/init.$(PRODUCT_PLATFORM).mpssrfs.rc
#per device
PRODUCT_COPY_FILES += \
@@ -119,6 +110,10 @@ PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/init.recovery.hardware.device.rc:recovery/root/init.recovery.bonito.rc \
$(LOCAL_PATH)/init.recovery.hardware.device.rc:recovery/root/init.recovery.sargo.rc \
# Partitions
PRODUCT_PACKAGES += \
vendor_firmware_mnt_mountpoint
MSM_VIDC_TARGET_LIST := sdm710 # Get the color format from kernel headers
MASTER_SIDE_CP_TARGET_LIST := sdm710 # ION specific settings
@@ -155,16 +150,6 @@ AB_OTA_POSTINSTALL_CONFIG += \
PRODUCT_PACKAGES += \
update_engine_sideload
PRODUCT_PACKAGES_DEBUG += \
sg_write_buffer \
f2fs_io \
check_f2fs
# The following modules are included in debuggable builds only.
PRODUCT_PACKAGES_DEBUG += \
bootctl \
update_engine_client
# Write flags to the vendor space in /misc partition.
PRODUCT_PACKAGES += \
misc_writer
@@ -223,12 +208,6 @@ PRODUCT_PACKAGES += \
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/powerhint.json:$(TARGET_COPY_OUT_VENDOR)/etc/powerhint.json
# perfstatsd
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_PACKAGES_DEBUG += \
perfstatsd
endif
# Audio fluence, ns, aec property, voice and media volume steps
PRODUCT_PROPERTY_OVERRIDES += \
ro.vendor.audio.sdk.fluencetype=fluencepro \
@@ -336,12 +315,15 @@ PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/WCNSS_qcom_cfg.ini:$(TARGET_COPY_OUT_VENDOR)/firmware/wlan/qca_cld/WCNSS_qcom_cfg.ini \
PRODUCT_PACKAGES += \
hwcomposer.$(TARGET_CHIPSET) \
hwcomposer.qcom \
android.hardware.graphics.composer@2.2-service \
gralloc.$(TARGET_CHIPSET) \
android.hardware.graphics.mapper@2.0-impl-qti-display \
vendor.qti.hardware.display.allocator@1.0-service
PRODUCT_PROPERTY_OVERRIDES += \
ro.hardware.hwcomposer=qcom
# Health HAL
PRODUCT_PACKAGES += \
android.hardware.health@2.1-impl-bonito \
@@ -355,6 +337,7 @@ PRODUCT_PACKAGES += \
PRODUCT_PACKAGES += \
lights.qcom \
hardware.google.light@1.0-service
PRODUCT_PROPERTY_OVERRIDES += \
ro.hardware.lights=qcom
@@ -427,13 +410,6 @@ PRODUCT_PACKAGES += \
android.hardware.camera.provider@2.4-service_64 \
camera.device@3.2-impl
# Google Camera HAL test libraries in debug builds
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_PACKAGES_DEBUG += \
libgoogle_camera_hal_proprietary_tests \
libgoogle_camera_hal_tests
endif
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/sensors/hals.conf:vendor/etc/sensors/hals.conf
@@ -449,13 +425,6 @@ PRODUCT_PACKAGES += \
PRODUCT_PACKAGES += \
android.hardware.contexthub@1.2-service.generic
# CHRE tools
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_PACKAGES += \
chre_power_test_client \
chre_test_client
endif
# Boot control HAL
PRODUCT_PACKAGES += \
android.hardware.boot-service.qti \
@@ -481,21 +450,13 @@ USE_QCRIL_OEMHOOK := true
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/sec_config:$(TARGET_COPY_OUT_VENDOR)/etc/sec_config
HOSTAPD := hostapd
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
HOSTAPD += hostapd_cli
endif
PRODUCT_PACKAGES += $(HOSTAPD)
WPA := wpa_supplicant.conf
WPA += wpa_supplicant
PRODUCT_PACKAGES += $(WPA)
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_PACKAGES += wpa_cli
endif
# Wifi
PRODUCT_PACKAGES += \
android.hardware.wifi-service \
@@ -528,15 +489,6 @@ PRODUCT_PACKAGES += \
android.hardware.bluetooth.audio@2.0-impl \
android.hardware.audio.service
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_PACKAGES += \
tinyplay \
tinycap \
tinymix \
tinypcminfo \
cplay
endif
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/audio_policy_configuration.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_policy_configuration.xml \
$(LOCAL_PATH)/audio_policy_configuration_a2dp_offload_disabled.xml:$(TARGET_COPY_OUT_VENDOR)/etc/audio_policy_configuration_a2dp_offload_disabled.xml \
@@ -587,23 +539,10 @@ PRODUCT_PACKAGES += \
PRODUCT_COPY_FILES += \
$(LOCAL_PATH)/gps.conf:$(TARGET_COPY_OUT_VENDOR)/etc/gps.conf
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
# Subsystem ramdump
PRODUCT_PROPERTY_OVERRIDES += \
persist.vendor.sys.ssr.enable_ramdumps=1
endif
# Subsystem silent restart
PRODUCT_PROPERTY_OVERRIDES += \
persist.vendor.sys.ssr.restart_level=modem,slpi,adsp
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
# Sensor debug flag
PRODUCT_PROPERTY_OVERRIDES += \
persist.vendor.debug.ash.logger=0 \
persist.vendor.debug.ash.logger.time=0
endif
# setup dalvik vm configs
$(call inherit-product, frameworks/native/build/phone-xhdpi-4096-dalvik-heap.mk)
@@ -615,16 +554,6 @@ PRODUCT_COPY_FILES += \
PRODUCT_PACKAGES += \
charger_res_images
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
# b/36703476: Set default log size to 1M
PRODUCT_PROPERTY_OVERRIDES += \
ro.logd.size=1M
# b/114766334: persist all logs by default rotating on 30 files of 1MiB
PRODUCT_PROPERTY_OVERRIDES += \
logd.logpersistd=logcatd \
logd.logpersistd.size=30
endif
# Dumpstate HAL
PRODUCT_PACKAGES += \
android.hardware.dumpstate@1.1-service.bonito
@@ -669,8 +598,6 @@ PRODUCT_COPY_FILES += \
device/google/bonito/vibrator/cs40l20/cs40l20.wmfw:$(TARGET_COPY_OUT_VENDOR)/firmware/cs40l20.wmfw \
device/google/bonito/vibrator/cs40l20/cs40l20.bin:$(TARGET_COPY_OUT_VENDOR)/firmware/cs40l20.bin
PRODUCT_VENDOR_KERNEL_HEADERS := device/google/bonito/sdm710/kernel-headers
# Audio ACDB data
PRODUCT_COPY_FILES += \
device/google/bonito/acdbdata/OEM/sdm670-intcodec-b4-snd-card/Bluetooth_cal.acdb:$(TARGET_COPY_OUT_VENDOR)/etc/acdbdata/OEM/sdm670-intcodec-b4-snd-card/Bluetooth_cal.acdb \
@@ -703,15 +630,6 @@ PRODUCT_COPY_FILES += \
device/google/bonito/acdbdata/OEM/sdm670-intcodec-s4-snd-card/Speaker_cal.acdb:$(TARGET_COPY_OUT_VENDOR)/etc/acdbdata/OEM/sdm670-intcodec-s4dev-snd-card/Speaker_cal.acdb \
device/google/bonito/acdbdata/adsp_avs_config.acdb:$(TARGET_COPY_OUT_VENDOR)/etc/acdbdata/adsp_avs_config.acdb
# Audio ACDB workspace files for QACT
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_COPY_FILES += \
device/google/bonito/acdbdata/OEM/sdm670-intcodec-b4-snd-card/workspaceFile.qwsp:$(TARGET_COPY_OUT_VENDOR)/etc/acdbdata/OEM/sdm670-intcodec-b4-snd-card/workspaceFile.qwsp \
device/google/bonito/acdbdata/OEM/sdm670-intcodec-s4-snd-card/workspaceFile.qwsp:$(TARGET_COPY_OUT_VENDOR)/etc/acdbdata/OEM/sdm670-intcodec-s4-snd-card/workspaceFile.qwsp \
device/google/bonito/acdbdata/OEM/sdm670-intcodec-b4-snd-card/workspaceFile.qwsp:$(TARGET_COPY_OUT_VENDOR)/etc/acdbdata/OEM/sdm670-intcodec-b4dev-snd-card/workspaceFile.qwsp \
device/google/bonito/acdbdata/OEM/sdm670-intcodec-s4-snd-card/workspaceFile.qwsp:$(TARGET_COPY_OUT_VENDOR)/etc/acdbdata/OEM/sdm670-intcodec-s4dev-snd-card/workspaceFile.qwsp
endif
# CS35L36 Speaker Tuning
PRODUCT_COPY_FILES += \
device/google/bonito/audio/crus_sp_config_b4_rx.bin:$(TARGET_COPY_OUT_VENDOR)/firmware/crus_sp_config_b4_rx.bin \
@@ -737,23 +655,11 @@ PRODUCT_PROPERTY_OVERRIDES += \
ro.radio.log_prefix="modem_log_"
# Enable modem logging for debug
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_PROPERTY_OVERRIDES += \
persist.vendor.sys.modem.diag.mdlog=true
else
PRODUCT_PROPERTY_OVERRIDES += \
persist.vendor.sys.modem.diag.mdlog=false
endif
PRODUCT_PROPERTY_OVERRIDES += \
persist.vendor.sys.modem.diag.mdlog_br_num=5
# Enable tcpdump_logger on eng
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_PROPERTY_OVERRIDES += \
persist.vendor.tcpdump.log.alwayson=false \
persist.vendor.tcpdump.log.br_num=5
endif
# Preopt SystemUI
PRODUCT_DEXPREOPT_SPEED_APPS += SystemUIGoogle # For internal
PRODUCT_DEXPREOPT_SPEED_APPS += SystemUI # For AOSP
@@ -765,12 +671,6 @@ PRODUCT_PROPERTY_OVERRIDES += \
# Enable stats logging in LMKD
TARGET_LMKD_STATS_LOG := true
# default usb oem functions
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_PROPERTY_OVERRIDES += \
persist.vendor.usb.usbradio.config=diag
endif
#Enable QTI KEYMASTER and GATEKEEPER HIDLs
KMGK_USE_QTI_SERVICE := true
@@ -812,13 +712,8 @@ PRODUCT_PROPERTY_OVERRIDES += \
ro.vendor.build.svn=60
# Vendor verbose logging default property
ifneq (,$(filter eng, $(TARGET_BUILD_VARIANT)))
PRODUCT_PROPERTY_OVERRIDES += \
persist.vendor.verbose_logging_enabled=true
else
PRODUCT_PROPERTY_OVERRIDES += \
persist.vendor.verbose_logging_enabled=false
endif
# Set support one-handed mode
PRODUCT_PRODUCT_PROPERTIES += \

112
init.hardware.diag.rc.userdebug
View File

@@ -1,112 +0,0 @@
#
# Copyright (C) 2016 The Android Open-Source Project
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
on init
chmod 666 /dev/diag
on post-fs-data
# Modem logging collection
mkdir /data/vendor/radio 0777 radio radio
mkdir /data/vendor/radio/diag_logs 0777 system system
rm /data/vendor/radio/diag_logs/logs/diag_poweron_log.qmdl
# WLAN logging collection
mkdir /data/vendor/wifi 0777 system system
mkdir /data/vendor/wifi/cnss_diag 0777 system system
mkdir /data/vendor/wifi/wlan_logs 0770 wifi wifi
service diag_mdlog_start /vendor/bin/diag_mdlog
class late_start
user shell
group system diag media_rw
socket diag_router stream 0666 system system
disabled
oneshot
service diag_mdlog_stop /vendor/bin/diag_mdlog -k
class late_start
user shell
group system diag media_rw
disabled
oneshot
on boot && property:persist.vendor.sys.modem.diag.mdlog=*
rm /data/vendor/radio/diag_logs/diag_mdlog_pid
setprop vendor.sys.modem.diag.mdlog ${persist.vendor.sys.modem.diag.mdlog}
on property:vendor.sys.modem.diag.mdlog=true && property:persist.vendor.verbose_logging_enabled=true
start diag_mdlog_start
on property:vendor.sys.modem.diag.mdlog=false
start diag_mdlog_stop
on property:persist.vendor.sys.cnss.diag_qxdm=true
start vendor.cnss_diag
on property:persist.vendor.sys.cnss.diag_qxdm=false
stop vendor.cnss_diag
on property:persist.vendor.sys.cnss.diag_txt=true
start vendor.cnss_diag_txt
on property:persist.vendor.sys.cnss.diag_txt=false
stop vendor.cnss_diag_txt
service vendor.cnss_diag /vendor/bin/cnss_diag -q -u -w
class late_start
user system
group system
disabled
oneshot
service vendor.cnss_diag_txt /vendor/bin/cnss_diag -s -f -m /data/vendor/wifi/cnss_diag/cnss_diag.conf
class late_start
user system
group system
disabled
oneshot
on property:vendor.debug.ramdump.force_crash=true
write /proc/sysrq-trigger "c"
on property:ro.vendor.bluetooth.ftm_enabled=true
start ftmd
service ftmd /vendor/bin/ftmdaemon
class late_start
user root
group bluetooth net_bt_admin misc diag net_bt
disabled
oneshot
on property:vendor.sys.logger.bluetooth=true
setprop persist.vendor.service.bdroid.snooplog true
setprop persist.vendor.service.bdroid.fwsnoop true
on property:vendor.sys.logger.bluetooth=false
setprop persist.vendor.service.bdroid.snooplog false
setprop persist.vendor.service.bdroid.fwsnoop false
on property:persist.bluetooth.btsnoopenable=true
setprop persist.vendor.service.bdroid.soclog true
on property:persist.bluetooth.btsnoopenable=false
setprop persist.vendor.service.bdroid.soclog false
on property:vendor.usb.config=*
start usbd
on property:persist.vendor.usb.usbradio.config=*
start usbd

11
init.hardware.mpssrfs.rc.userdebug
View File

@@ -1,11 +0,0 @@
on post-fs-data
# Modem Remote FS
mkdir /data/vendor/rfs 0770 vendor_rfs vendor_rfs
mkdir /data/vendor/rfs/mpss 0770 vendor_rfs vendor_rfs
mkdir /data/vendor/tombstones/rfs 0770 vendor_rfs vendor_rfs
write /data/vendor/rfs/mpss/mcfg_nv_list_flag "1"
chown vendor_rfs vendor_rfs /data/vendor/rfs/mpss/mcfg_nv_list_flag
chmod 0700 /data/vendor/rfs/mpss/mcfg_nv_list_flag
on property:vendor.sys.modem.diag.efsdump=true
chmod 0660 /data/vendor/rfs/mpss/modem_efs

8
init.hardware.rc
View File

@@ -273,9 +273,6 @@ on post-fs-data
on zygote-start
# zygote is started in common init.rc
# and now we can continue initialize /data/
mkdir /data/vendor/ipa 0770 radio radio
chown radio radio /data/vendor/ipa
# Create the directories used by the Wireless subsystem
mkdir /data/vendor/wifi 0771 wifi wifi
mkdir /data/vendor/wifi/wpa 0770 wifi wifi
@@ -618,11 +615,6 @@ service cnss-daemon /vendor/bin/cnss-daemon -n -l
user system
group system inet wifi
service ipacm /vendor/bin/ipacm
class main
user radio
group radio inet
service qti /vendor/bin/qti
class main
user radio

11
lineage_manifest.xml
View File

@@ -1,11 +0,0 @@
<manifest version="1.0" type="device">
<hal format="hidl">
<name>vendor.lineage.livedisplay</name>
<transport>hwbinder</transport>
<version>2.0</version>
<interface>
<name>IPictureAdjustment</name>
<instance>default</instance>
</interface>
</hal>
</manifest>

42
overlay/frameworks/base/core/res/res/values/config.xml
View File

@@ -144,31 +144,6 @@
<bool translatable="false" name="config_tether_upstream_automatic">true</bool>
<!-- This string array should be overridden by the device to present a list of network
attributes. This is used by the connectivity manager to decide which networks can coexist
based on the hardware -->
<!-- An Array of "[Connection name],[ConnectivityManager.TYPE_xxxx],
[associated radio-type],[priority],[restoral-timer(ms)],[dependencyMet] -->
<!-- the 5th element "resore-time" indicates the number of milliseconds to delay
before automatically restore the default connection. Set -1 if the connection
does not require auto-restore. -->
<!-- the 6th element indicates boot-time dependency-met value. -->
<string-array translatable="false" name="networkAttributes">
<item>"wifi,1,1,1,-1,true"</item>
<item>"mobile,0,0,0,-1,true"</item>
<item>"mobile_mms,2,0,2,60000,true"</item>
<item>"mobile_supl,3,0,2,60000,true"</item>
<item>"mobile_dun,4,0,2,60000,true"</item>
<item>"mobile_hipri,5,0,3,60000,true"</item>
<item>"mobile_fota,10,0,2,60000,true"</item>
<item>"mobile_ims,11,0,2,60000,true"</item>
<item>"mobile_cbs,12,0,2,60000,true"</item>
<item>"mobile_ia,14,0,2,-1,true"</item>
<item>"bluetooth,7,7,2,-1,true"</item>
<item>"ethernet,9,9,9,-1,true"</item>
<item>"mobile_emergency,15,0,2,-1,true</item>
</string-array>
<!-- This string array should be overridden by the device to present a list of radio
attributes. This is used by the connectivity manager to decide which networks can coexist
based on the hardware -->
@@ -227,23 +202,6 @@
<!-- Flag specifying whether WFC over IMS is availasble on device -->
<bool name="config_device_wfc_ims_available">true</bool>
<!-- Configure mobile tcp buffer sizes in the form:
rat-name:rmem_min,rmem_def,rmem_max,wmem_min,wmem_def,wmem_max
If no value is found for the rat-name in use, the system default will be applied.
-->
<string-array name="config_mobile_tcp_buffers">
<item>umts:131072,262144,1452032,4096,16384,399360</item>
<item>hspa:131072,262144,2441216,4096,16384,399360</item>
<item>hsupa:131072,262144,2441216,4096,16384,399360</item>
<item>hsdpa:131072,262144,2441216,4096,16384,399360</item>
<item>hspap:131072,262144,2441216,4096,16384,399360</item>
<item>edge:16384,32768,131072,4096,16384,65536</item>
<item>gprs:4096,8192,24576,4096,8192,24576</item>
<item>1xrtt:16384,32768,131070,4096,16384,102400</item>
<item>evdo:131072,262144,1048576,4096,16384,524288</item>
<item>lte:524288,1048576,8388608,262144,524288,4194304</item>
</string-array>
<!-- Config determines whether to update phone object when voice registration
state changes. Voice radio tech change will always trigger an update of
phone object irrespective of this config -->

1
sargo/AndroidBoard.mk
View File

@@ -1 +0,0 @@
../bonito/AndroidBoard.mk

3
sargo/extract-files.py
View File

@@ -27,7 +27,8 @@ from extract_utils.main import (
namespace_imports = [
'hardware/google/interfaces',
'hardware/google/pixel',
'hardware/qcom/sdm845',
'hardware/qcom/sdm845/display',
'hardware/qcom/sdm845/gps',
'hardware/qcom/wlan/legacy',
]

113
sdm710/kernel-headers/asm-generic/ioctls.h
View File

@@ -1,113 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_GENERIC_IOCTLS_H
#define __ASM_GENERIC_IOCTLS_H
#include <linux/ioctl.h>
#define TCGETS 0x5401
#define TCSETS 0x5402
#define TCSETSW 0x5403
#define TCSETSF 0x5404
#define TCGETA 0x5405
#define TCSETA 0x5406
#define TCSETAW 0x5407
#define TCSETAF 0x5408
#define TCSBRK 0x5409
#define TCXONC 0x540A
#define TCFLSH 0x540B
#define TIOCEXCL 0x540C
#define TIOCNXCL 0x540D
#define TIOCSCTTY 0x540E
#define TIOCGPGRP 0x540F
#define TIOCSPGRP 0x5410
#define TIOCOUTQ 0x5411
#define TIOCSTI 0x5412
#define TIOCGWINSZ 0x5413
#define TIOCSWINSZ 0x5414
#define TIOCMGET 0x5415
#define TIOCMBIS 0x5416
#define TIOCMBIC 0x5417
#define TIOCMSET 0x5418
#define TIOCGSOFTCAR 0x5419
#define TIOCSSOFTCAR 0x541A
#define FIONREAD 0x541B
#define TIOCINQ FIONREAD
#define TIOCLINUX 0x541C
#define TIOCCONS 0x541D
#define TIOCGSERIAL 0x541E
#define TIOCSSERIAL 0x541F
#define TIOCPKT 0x5420
#define FIONBIO 0x5421
#define TIOCNOTTY 0x5422
#define TIOCSETD 0x5423
#define TIOCGETD 0x5424
#define TCSBRKP 0x5425
#define TIOCSBRK 0x5427
#define TIOCCBRK 0x5428
#define TIOCGSID 0x5429
#define TCGETS2 _IOR('T', 0x2A, struct termios2)
#define TCSETS2 _IOW('T', 0x2B, struct termios2)
#define TCSETSW2 _IOW('T', 0x2C, struct termios2)
#define TCSETSF2 _IOW('T', 0x2D, struct termios2)
#define TIOCGRS485 0x542E
#ifndef TIOCSRS485
#define TIOCSRS485 0x542F
#endif
#define TIOCGPTN _IOR('T', 0x30, unsigned int)
#define TIOCSPTLCK _IOW('T', 0x31, int)
#define TIOCGDEV _IOR('T', 0x32, unsigned int)
#define TCGETX 0x5432
#define TCSETX 0x5433
#define TCSETXF 0x5434
#define TCSETXW 0x5435
#define TIOCSIG _IOW('T', 0x36, int)
#define TIOCVHANGUP 0x5437
#define TIOCGPKT _IOR('T', 0x38, int)
#define TIOCGPTLCK _IOR('T', 0x39, int)
#define TIOCGEXCL _IOR('T', 0x40, int)
#define TIOCPMGET 0x5441
#define TIOCPMPUT 0x5442
#define TIOCPMACT 0x5443
#define FIONCLEX 0x5450
#define FIOCLEX 0x5451
#define FIOASYNC 0x5452
#define TIOCSERCONFIG 0x5453
#define TIOCSERGWILD 0x5454
#define TIOCSERSWILD 0x5455
#define TIOCGLCKTRMIOS 0x5456
#define TIOCSLCKTRMIOS 0x5457
#define TIOCSERGSTRUCT 0x5458
#define TIOCSERGETLSR 0x5459
#define TIOCSERGETMULTI 0x545A
#define TIOCSERSETMULTI 0x545B
#define TIOCMIWAIT 0x545C
#define TIOCGICOUNT 0x545D
#ifndef FIOQSIZE
#define FIOQSIZE 0x5460
#endif
#define TIOCPKT_DATA 0
#define TIOCPKT_FLUSHREAD 1
#define TIOCPKT_FLUSHWRITE 2
#define TIOCPKT_STOP 4
#define TIOCPKT_START 8
#define TIOCPKT_NOSTOP 16
#define TIOCPKT_DOSTOP 32
#define TIOCPKT_IOCTL 64
#define TIOCSER_TEMT 0x01
#endif

217
sdm710/kernel-headers/drm/msm_drm.h
View File

@@ -1,217 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __MSM_DRM_H__
#define __MSM_DRM_H__
#include "drm.h"
#include "sde_drm.h"
#ifdef __cplusplus
#endif
#define MSM_PIPE_NONE 0x00
#define MSM_PIPE_2D0 0x01
#define MSM_PIPE_2D1 0x02
#define MSM_PIPE_3D0 0x10
#define MSM_PIPE_ID_MASK 0xffff
#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
struct drm_msm_timespec {
__s64 tv_sec;
__s64 tv_nsec;
};
#define HDR_PRIMARIES_COUNT 3
#define HDR_EOTF_SDR_LUM_RANGE 0x0
#define HDR_EOTF_HDR_LUM_RANGE 0x1
#define HDR_EOTF_SMTPE_ST2084 0x2
#define HDR_EOTF_HLG 0x3
#define DRM_MSM_EXT_HDR_METADATA
struct drm_msm_ext_hdr_metadata {
__u32 hdr_state;
__u32 eotf;
__u32 hdr_supported;
__u32 display_primaries_x[HDR_PRIMARIES_COUNT];
__u32 display_primaries_y[HDR_PRIMARIES_COUNT];
__u32 white_point_x;
__u32 white_point_y;
__u32 max_luminance;
__u32 min_luminance;
__u32 max_content_light_level;
__u32 max_average_light_level;
};
#define DRM_MSM_EXT_HDR_PROPERTIES
struct drm_msm_ext_hdr_properties {
__u8 hdr_metadata_type_one;
__u32 hdr_supported;
__u32 hdr_eotf;
__u32 hdr_max_luminance;
__u32 hdr_avg_luminance;
__u32 hdr_min_luminance;
};
#define MSM_PARAM_GPU_ID 0x01
#define MSM_PARAM_GMEM_SIZE 0x02
#define MSM_PARAM_CHIP_ID 0x03
#define MSM_PARAM_MAX_FREQ 0x04
#define MSM_PARAM_TIMESTAMP 0x05
struct drm_msm_param {
__u32 pipe;
__u32 param;
__u64 value;
};
#define MSM_BO_SCANOUT 0x00000001
#define MSM_BO_GPU_READONLY 0x00000002
#define MSM_BO_CACHE_MASK 0x000f0000
#define MSM_BO_CACHED 0x00010000
#define MSM_BO_WC 0x00020000
#define MSM_BO_UNCACHED 0x00040000
#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED)
struct drm_msm_gem_new {
__u64 size;
__u32 flags;
__u32 handle;
};
struct drm_msm_gem_info {
__u32 handle;
__u32 pad;
__u64 offset;
};
#define MSM_PREP_READ 0x01
#define MSM_PREP_WRITE 0x02
#define MSM_PREP_NOSYNC 0x04
#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
struct drm_msm_gem_cpu_prep {
__u32 handle;
__u32 op;
struct drm_msm_timespec timeout;
};
struct drm_msm_gem_cpu_fini {
__u32 handle;
};
struct drm_msm_gem_submit_reloc {
__u32 submit_offset;
__u32 or;
__s32 shift;
__u32 reloc_idx;
__u64 reloc_offset;
};
#define MSM_SUBMIT_CMD_BUF 0x0001
#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
struct drm_msm_gem_submit_cmd {
__u32 type;
__u32 submit_idx;
__u32 submit_offset;
__u32 size;
__u32 pad;
__u32 nr_relocs;
__u64 relocs;
};
#define MSM_SUBMIT_BO_READ 0x0001
#define MSM_SUBMIT_BO_WRITE 0x0002
#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
struct drm_msm_gem_submit_bo {
__u32 flags;
__u32 handle;
__u64 presumed;
};
#define MSM_SUBMIT_NO_IMPLICIT 0x80000000
#define MSM_SUBMIT_FENCE_FD_IN 0x40000000
#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000
#define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | 0)
struct drm_msm_gem_submit {
__u32 flags;
__u32 fence;
__u32 nr_bos;
__u32 nr_cmds;
__u64 bos;
__u64 cmds;
__s32 fence_fd;
};
struct drm_msm_wait_fence {
__u32 fence;
__u32 pad;
struct drm_msm_timespec timeout;
};
#define MSM_MADV_WILLNEED 0
#define MSM_MADV_DONTNEED 1
#define __MSM_MADV_PURGED 2
struct drm_msm_gem_madvise {
__u32 handle;
__u32 madv;
__u32 retained;
};
#define DISPLAY_PRIMARIES_WX 0
#define DISPLAY_PRIMARIES_WY 1
#define DISPLAY_PRIMARIES_RX 2
#define DISPLAY_PRIMARIES_RY 3
#define DISPLAY_PRIMARIES_GX 4
#define DISPLAY_PRIMARIES_GY 5
#define DISPLAY_PRIMARIES_BX 6
#define DISPLAY_PRIMARIES_BY 7
#define DISPLAY_PRIMARIES_MAX 8
struct drm_panel_hdr_properties {
__u32 hdr_enabled;
__u32 display_primaries[DISPLAY_PRIMARIES_MAX];
__u32 peak_brightness;
__u32 blackness_level;
};
struct drm_msm_event_req {
__u32 object_id;
__u32 object_type;
__u32 event;
__u64 client_context;
__u32 index;
};
struct drm_msm_event_resp {
struct drm_event base;
struct drm_msm_event_req info;
__u8 data[];
};
#define DRM_MSM_GET_PARAM 0x00
#define DRM_MSM_GEM_NEW 0x02
#define DRM_MSM_GEM_INFO 0x03
#define DRM_MSM_GEM_CPU_PREP 0x04
#define DRM_MSM_GEM_CPU_FINI 0x05
#define DRM_MSM_GEM_SUBMIT 0x06
#define DRM_MSM_WAIT_FENCE 0x07
#define DRM_MSM_GEM_MADVISE 0x08
#define DRM_SDE_WB_CONFIG 0x40
#define DRM_MSM_REGISTER_EVENT 0x41
#define DRM_MSM_DEREGISTER_EVENT 0x42
#define DRM_MSM_RMFB2 0x43
#define DRM_EVENT_HISTOGRAM 0x80000000
#define DRM_EVENT_AD_BACKLIGHT 0x80000001
#define DRM_EVENT_CRTC_POWER 0x80000002
#define DRM_EVENT_SYS_BACKLIGHT 0x80000003
#define DRM_EVENT_SDE_POWER 0x80000004
#define DRM_EVENT_IDLE_NOTIFY 0x80000005
#define DRM_EVENT_PANEL_DEAD 0x80000006
#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
#define DRM_IOCTL_SDE_WB_CONFIG DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg)
#define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req)
#define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req)
#define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_RMFB2), unsigned int)
#ifdef __cplusplus
#endif
#endif

297
sdm710/kernel-headers/drm/msm_drm_pp.h
View File

@@ -1,297 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _MSM_DRM_PP_H_
#define _MSM_DRM_PP_H_
#include <linux/types.h>
struct drm_msm_pcc_coeff {
__u32 c;
__u32 r;
__u32 g;
__u32 b;
__u32 rg;
__u32 gb;
__u32 rb;
__u32 rgb;
};
#define DRM_MSM_PCC3
struct drm_msm_pcc {
__u64 flags;
struct drm_msm_pcc_coeff r;
struct drm_msm_pcc_coeff g;
struct drm_msm_pcc_coeff b;
__u32 r_rr;
__u32 r_gg;
__u32 r_bb;
__u32 g_rr;
__u32 g_gg;
__u32 g_bb;
__u32 b_rr;
__u32 b_gg;
__u32 b_bb;
};
#define PA_VLUT_SIZE 256
struct drm_msm_pa_vlut {
__u64 flags;
__u32 val[PA_VLUT_SIZE];
};
#define PA_HSIC_HUE_ENABLE (1 << 0)
#define PA_HSIC_SAT_ENABLE (1 << 1)
#define PA_HSIC_VAL_ENABLE (1 << 2)
#define PA_HSIC_CONT_ENABLE (1 << 3)
#define DRM_MSM_PA_HSIC
struct drm_msm_pa_hsic {
__u64 flags;
__u32 hue;
__u32 saturation;
__u32 value;
__u32 contrast;
};
#define MEMCOL_PROT_HUE (1 << 0)
#define MEMCOL_PROT_SAT (1 << 1)
#define MEMCOL_PROT_VAL (1 << 2)
#define MEMCOL_PROT_CONT (1 << 3)
#define MEMCOL_PROT_SIXZONE (1 << 4)
#define MEMCOL_PROT_BLEND (1 << 5)
#define DRM_MSM_MEMCOL
struct drm_msm_memcol {
__u64 prot_flags;
__u32 color_adjust_p0;
__u32 color_adjust_p1;
__u32 color_adjust_p2;
__u32 blend_gain;
__u32 sat_hold;
__u32 val_hold;
__u32 hue_region;
__u32 sat_region;
__u32 val_region;
};
#define DRM_MSM_SIXZONE
#define SIXZONE_LUT_SIZE 384
#define SIXZONE_HUE_ENABLE (1 << 0)
#define SIXZONE_SAT_ENABLE (1 << 1)
#define SIXZONE_VAL_ENABLE (1 << 2)
struct drm_msm_sixzone_curve {
__u32 p1;
__u32 p0;
};
struct drm_msm_sixzone {
__u64 flags;
__u32 threshold;
__u32 adjust_p0;
__u32 adjust_p1;
__u32 sat_hold;
__u32 val_hold;
struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE];
};
#define GAMUT_3D_MODE_17 1
#define GAMUT_3D_MODE_5 2
#define GAMUT_3D_MODE_13 3
#define GAMUT_3D_MODE17_TBL_SZ 1229
#define GAMUT_3D_MODE5_TBL_SZ 32
#define GAMUT_3D_MODE13_TBL_SZ 550
#define GAMUT_3D_SCALE_OFF_SZ 16
#define GAMUT_3D_SCALEB_OFF_SZ 12
#define GAMUT_3D_TBL_NUM 4
#define GAMUT_3D_SCALE_OFF_TBL_NUM 3
#define GAMUT_3D_MAP_EN (1 << 0)
struct drm_msm_3d_col {
__u32 c2_c1;
__u32 c0;
};
struct drm_msm_3d_gamut {
__u64 flags;
__u32 mode;
__u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ];
struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ];
};
#define PGC_TBL_LEN 512
#define PGC_8B_ROUND (1 << 0)
struct drm_msm_pgc_lut {
__u64 flags;
__u32 c0[PGC_TBL_LEN];
__u32 c1[PGC_TBL_LEN];
__u32 c2[PGC_TBL_LEN];
};
#define IGC_TBL_LEN 256
#define IGC_DITHER_ENABLE (1 << 0)
struct drm_msm_igc_lut {
__u64 flags;
__u32 c0[IGC_TBL_LEN];
__u32 c1[IGC_TBL_LEN];
__u32 c2[IGC_TBL_LEN];
__u32 strength;
};
#define HIST_V_SIZE 256
struct drm_msm_hist {
__u64 flags;
__u32 data[HIST_V_SIZE];
};
#define AD4_LUT_GRP0_SIZE 33
#define AD4_LUT_GRP1_SIZE 32
struct drm_msm_ad4_init {
__u32 init_param_001[AD4_LUT_GRP0_SIZE];
__u32 init_param_002[AD4_LUT_GRP0_SIZE];
__u32 init_param_003[AD4_LUT_GRP0_SIZE];
__u32 init_param_004[AD4_LUT_GRP0_SIZE];
__u32 init_param_005[AD4_LUT_GRP1_SIZE];
__u32 init_param_006[AD4_LUT_GRP1_SIZE];
__u32 init_param_007[AD4_LUT_GRP0_SIZE];
__u32 init_param_008[AD4_LUT_GRP0_SIZE];
__u32 init_param_009;
__u32 init_param_010;
__u32 init_param_011;
__u32 init_param_012;
__u32 init_param_013;
__u32 init_param_014;
__u32 init_param_015;
__u32 init_param_016;
__u32 init_param_017;
__u32 init_param_018;
__u32 init_param_019;
__u32 init_param_020;
__u32 init_param_021;
__u32 init_param_022;
__u32 init_param_023;
__u32 init_param_024;
__u32 init_param_025;
__u32 init_param_026;
__u32 init_param_027;
__u32 init_param_028;
__u32 init_param_029;
__u32 init_param_030;
__u32 init_param_031;
__u32 init_param_032;
__u32 init_param_033;
__u32 init_param_034;
__u32 init_param_035;
__u32 init_param_036;
__u32 init_param_037;
__u32 init_param_038;
__u32 init_param_039;
__u32 init_param_040;
__u32 init_param_041;
__u32 init_param_042;
__u32 init_param_043;
__u32 init_param_044;
__u32 init_param_045;
__u32 init_param_046;
__u32 init_param_047;
__u32 init_param_048;
__u32 init_param_049;
__u32 init_param_050;
__u32 init_param_051;
__u32 init_param_052;
__u32 init_param_053;
__u32 init_param_054;
__u32 init_param_055;
__u32 init_param_056;
__u32 init_param_057;
__u32 init_param_058;
__u32 init_param_059;
__u32 init_param_060;
__u32 init_param_061;
__u32 init_param_062;
__u32 init_param_063;
__u32 init_param_064;
__u32 init_param_065;
__u32 init_param_066;
__u32 init_param_067;
__u32 init_param_068;
__u32 init_param_069;
__u32 init_param_070;
__u32 init_param_071;
__u32 init_param_072;
__u32 init_param_073;
__u32 init_param_074;
__u32 init_param_075;
};
struct drm_msm_ad4_cfg {
__u32 cfg_param_001;
__u32 cfg_param_002;
__u32 cfg_param_003;
__u32 cfg_param_004;
__u32 cfg_param_005;
__u32 cfg_param_006;
__u32 cfg_param_007;
__u32 cfg_param_008;
__u32 cfg_param_009;
__u32 cfg_param_010;
__u32 cfg_param_011;
__u32 cfg_param_012;
__u32 cfg_param_013;
__u32 cfg_param_014;
__u32 cfg_param_015;
__u32 cfg_param_016;
__u32 cfg_param_017;
__u32 cfg_param_018;
__u32 cfg_param_019;
__u32 cfg_param_020;
__u32 cfg_param_021;
__u32 cfg_param_022;
__u32 cfg_param_023;
__u32 cfg_param_024;
__u32 cfg_param_025;
__u32 cfg_param_026;
__u32 cfg_param_027;
__u32 cfg_param_028;
__u32 cfg_param_029;
__u32 cfg_param_030;
__u32 cfg_param_031;
__u32 cfg_param_032;
__u32 cfg_param_033;
__u32 cfg_param_034;
__u32 cfg_param_035;
__u32 cfg_param_036;
__u32 cfg_param_037;
__u32 cfg_param_038;
__u32 cfg_param_039;
__u32 cfg_param_040;
__u32 cfg_param_041;
__u32 cfg_param_042;
__u32 cfg_param_043;
__u32 cfg_param_044;
__u32 cfg_param_045;
__u32 cfg_param_046;
__u32 cfg_param_047;
__u32 cfg_param_048;
__u32 cfg_param_049;
__u32 cfg_param_050;
__u32 cfg_param_051;
__u32 cfg_param_052;
__u32 cfg_param_053;
};
#define DITHER_MATRIX_SZ 16
struct drm_msm_dither {
__u64 flags;
__u32 temporal_en;
__u32 c0_bitdepth;
__u32 c1_bitdepth;
__u32 c2_bitdepth;
__u32 c3_bitdepth;
__u32 matrix[DITHER_MATRIX_SZ];
};
#define DRM_MSM_PA_DITHER
struct drm_msm_pa_dither {
__u64 flags;
__u32 strength;
__u32 offset_en;
__u32 matrix[DITHER_MATRIX_SZ];
};
#endif

181
sdm710/kernel-headers/drm/sde_drm.h
View File

@@ -1,181 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _SDE_DRM_H_
#define _SDE_DRM_H_
#include "drm.h"
#define SDE_MAX_PLANES 4
#define SDE_MAX_DE_CURVES 3
#define FILTER_EDGE_DIRECTED_2D 0x0
#define FILTER_CIRCULAR_2D 0x1
#define FILTER_SEPARABLE_1D 0x2
#define FILTER_BILINEAR 0x3
#define FILTER_ALPHA_DROP_REPEAT 0x0
#define FILTER_ALPHA_BILINEAR 0x1
#define FILTER_ALPHA_2D 0x3
#define FILTER_BLEND_CIRCULAR_2D 0x0
#define FILTER_BLEND_SEPARABLE_1D 0x1
#define SCALER_LUT_SWAP 0x1
#define SCALER_LUT_DIR_WR 0x2
#define SCALER_LUT_Y_CIR_WR 0x4
#define SCALER_LUT_UV_CIR_WR 0x8
#define SCALER_LUT_Y_SEP_WR 0x10
#define SCALER_LUT_UV_SEP_WR 0x20
#define SDE_DRM_BLEND_OP_NOT_DEFINED 0
#define SDE_DRM_BLEND_OP_OPAQUE 1
#define SDE_DRM_BLEND_OP_PREMULTIPLIED 2
#define SDE_DRM_BLEND_OP_COVERAGE 3
#define SDE_DRM_BLEND_OP_MAX 4
#define SDE_DRM_DEINTERLACE 0
#define SDE_DRM_BITMASK_COUNT 64
#define SDE_DRM_FB_NON_SEC 0
#define SDE_DRM_FB_SEC 1
#define SDE_DRM_FB_NON_SEC_DIR_TRANS 2
#define SDE_DRM_FB_SEC_DIR_TRANS 3
#define SDE_DRM_SEC_NON_SEC 0
#define SDE_DRM_SEC_ONLY 1
struct sde_drm_pix_ext_v1 {
int32_t num_ext_pxls_lr[SDE_MAX_PLANES];
int32_t num_ext_pxls_tb[SDE_MAX_PLANES];
int32_t left_ftch[SDE_MAX_PLANES];
int32_t right_ftch[SDE_MAX_PLANES];
int32_t top_ftch[SDE_MAX_PLANES];
int32_t btm_ftch[SDE_MAX_PLANES];
int32_t left_rpt[SDE_MAX_PLANES];
int32_t right_rpt[SDE_MAX_PLANES];
int32_t top_rpt[SDE_MAX_PLANES];
int32_t btm_rpt[SDE_MAX_PLANES];
};
struct sde_drm_scaler_v1 {
struct sde_drm_pix_ext_v1 pe;
int32_t init_phase_x[SDE_MAX_PLANES];
int32_t phase_step_x[SDE_MAX_PLANES];
int32_t init_phase_y[SDE_MAX_PLANES];
int32_t phase_step_y[SDE_MAX_PLANES];
uint32_t horz_filter[SDE_MAX_PLANES];
uint32_t vert_filter[SDE_MAX_PLANES];
};
struct sde_drm_de_v1 {
uint32_t enable;
int16_t sharpen_level1;
int16_t sharpen_level2;
uint16_t clip;
uint16_t limit;
uint16_t thr_quiet;
uint16_t thr_dieout;
uint16_t thr_low;
uint16_t thr_high;
uint16_t prec_shift;
int16_t adjust_a[SDE_MAX_DE_CURVES];
int16_t adjust_b[SDE_MAX_DE_CURVES];
int16_t adjust_c[SDE_MAX_DE_CURVES];
};
struct sde_drm_scaler_v2 {
uint32_t enable;
uint32_t dir_en;
struct sde_drm_pix_ext_v1 pe;
uint32_t horz_decimate;
uint32_t vert_decimate;
int32_t init_phase_x[SDE_MAX_PLANES];
int32_t phase_step_x[SDE_MAX_PLANES];
int32_t init_phase_y[SDE_MAX_PLANES];
int32_t phase_step_y[SDE_MAX_PLANES];
uint32_t preload_x[SDE_MAX_PLANES];
uint32_t preload_y[SDE_MAX_PLANES];
uint32_t src_width[SDE_MAX_PLANES];
uint32_t src_height[SDE_MAX_PLANES];
uint32_t dst_width;
uint32_t dst_height;
uint32_t y_rgb_filter_cfg;
uint32_t uv_filter_cfg;
uint32_t alpha_filter_cfg;
uint32_t blend_cfg;
uint32_t lut_flag;
uint32_t dir_lut_idx;
uint32_t y_rgb_cir_lut_idx;
uint32_t uv_cir_lut_idx;
uint32_t y_rgb_sep_lut_idx;
uint32_t uv_sep_lut_idx;
struct sde_drm_de_v1 de;
};
#define SDE_MAX_DS_COUNT 2
#define SDE_DRM_DESTSCALER_ENABLE 0x1
#define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2
#define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4
#define SDE_DRM_DESTSCALER_PU_ENABLE 0x8
struct sde_drm_dest_scaler_cfg {
uint32_t flags;
uint32_t index;
uint32_t lm_width;
uint32_t lm_height;
uint64_t scaler_cfg;
};
struct sde_drm_dest_scaler_data {
uint32_t num_dest_scaler;
struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT];
};
#define SDE_CSC_MATRIX_COEFF_SIZE 9
#define SDE_CSC_CLAMP_SIZE 6
#define SDE_CSC_BIAS_SIZE 3
struct sde_drm_csc_v1 {
int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE];
uint32_t pre_bias[SDE_CSC_BIAS_SIZE];
uint32_t post_bias[SDE_CSC_BIAS_SIZE];
uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE];
uint32_t post_clamp[SDE_CSC_CLAMP_SIZE];
};
struct sde_drm_color {
uint32_t color_0;
uint32_t color_1;
uint32_t color_2;
uint32_t color_3;
};
#define SDE_MAX_DIM_LAYERS 7
#define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1
#define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2
struct sde_drm_dim_layer_cfg {
uint32_t flags;
uint32_t stage;
struct sde_drm_color color_fill;
struct drm_clip_rect rect;
};
struct sde_drm_dim_layer_v1 {
uint32_t num_layers;
struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS];
};
#define SDE_DRM_WB_CFG 0x1
#define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1 << 0)
struct sde_drm_wb_cfg {
uint32_t flags;
uint32_t connector_id;
uint32_t count_modes;
uint64_t modes;
};
#define SDE_MAX_ROI_V1 4
struct sde_drm_roi_v1 {
uint32_t num_rects;
struct drm_clip_rect roi[SDE_MAX_ROI_V1];
};
#define SDE_MODE_DPMS_ON 0
#define SDE_MODE_DPMS_LP1 1
#define SDE_MODE_DPMS_LP2 2
#define SDE_MODE_DPMS_STANDBY 3
#define SDE_MODE_DPMS_SUSPEND 4
#define SDE_MODE_DPMS_OFF 5
#endif

10
sdm710/kernel-headers/linux/avtimer.h
View File

@@ -1,10 +0,0 @@
#ifndef _AVTIMER_H
#define _AVTIMER_H
#include <linux/ioctl.h>
#define MAJOR_NUM 100
#define IOCTL_GET_AVTIMER_TICK _IOR(MAJOR_NUM, 0, uint64_t)
#endif

67
sdm710/kernel-headers/linux/ion.h
View File

@@ -1,67 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _LINUX_ION_H
#define _LINUX_ION_H
#include <linux/ioctl.h>
#include <linux/types.h>
typedef int ion_user_handle_t;
enum ion_heap_type {
ION_HEAP_TYPE_SYSTEM,
ION_HEAP_TYPE_SYSTEM_CONTIG,
ION_HEAP_TYPE_CARVEOUT,
ION_HEAP_TYPE_CHUNK,
ION_HEAP_TYPE_DMA,
ION_HEAP_TYPE_CUSTOM,
ION_NUM_HEAPS = 16,
};
#define ION_HEAP_SYSTEM_MASK ((1 << ION_HEAP_TYPE_SYSTEM))
#define ION_HEAP_SYSTEM_CONTIG_MASK ((1 << ION_HEAP_TYPE_SYSTEM_CONTIG))
#define ION_HEAP_CARVEOUT_MASK ((1 << ION_HEAP_TYPE_CARVEOUT))
#define ION_HEAP_TYPE_DMA_MASK ((1 << ION_HEAP_TYPE_DMA))
#define ION_NUM_HEAP_IDS (sizeof(unsigned int) * 8)
#define ION_FLAG_CACHED 1
#define ION_FLAG_CACHED_NEEDS_SYNC 2
struct ion_allocation_data {
size_t len;
size_t align;
unsigned int heap_id_mask;
unsigned int flags;
ion_user_handle_t handle;
};
struct ion_fd_data {
ion_user_handle_t handle;
int fd;
};
struct ion_handle_data {
ion_user_handle_t handle;
};
struct ion_custom_data {
unsigned int cmd;
unsigned long arg;
};
#define ION_IOC_MAGIC 'I'
#define ION_IOC_ALLOC _IOWR(ION_IOC_MAGIC, 0, struct ion_allocation_data)
#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data)
#define ION_IOC_MAP _IOWR(ION_IOC_MAGIC, 2, struct ion_fd_data)
#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data)
#define ION_IOC_IMPORT _IOWR(ION_IOC_MAGIC, 5, struct ion_fd_data)
#define ION_IOC_SYNC _IOWR(ION_IOC_MAGIC, 7, struct ion_fd_data)
#define ION_IOC_CUSTOM _IOWR(ION_IOC_MAGIC, 6, struct ion_custom_data)
#endif

610
sdm710/kernel-headers/linux/ipa_qmi_service_v01.h
View File

@@ -1,610 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef IPA_QMI_SERVICE_V01_H
#define IPA_QMI_SERVICE_V01_H
#define QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01 2
#define QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01 2
#define QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01 2
#define QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01 2
#define QMI_IPA_MAX_FILTERS_V01 64
#define QMI_IPA_MAX_FILTERS_EX_V01 128
#define QMI_IPA_MAX_PIPES_V01 20
#define QMI_IPA_MAX_APN_V01 8
#define QMI_IPA_MAX_PER_CLIENTS_V01 64
#define QMI_IPA_MAX_CLIENT_DST_PIPES_V01 8
#define QMI_IPA_MAX_UL_FIREWALL_RULES_V01 64
#define IPA_QMI_SUPPORTS_STATS
#define IPA_INT_MAX ((int) (~0U >> 1))
#define IPA_INT_MIN (- IPA_INT_MAX - 1)
enum ipa_qmi_result_type_v01 {
IPA_QMI_RESULT_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN,
IPA_QMI_RESULT_SUCCESS_V01 = 0,
IPA_QMI_RESULT_FAILURE_V01 = 1,
IPA_QMI_RESULT_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX,
};
enum ipa_qmi_error_type_v01 {
IPA_QMI_ERROR_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN,
IPA_QMI_ERR_NONE_V01 = 0x0000,
IPA_QMI_ERR_MALFORMED_MSG_V01 = 0x0001,
IPA_QMI_ERR_NO_MEMORY_V01 = 0x0002,
IPA_QMI_ERR_INTERNAL_V01 = 0x0003,
IPA_QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 = 0x0005,
IPA_QMI_ERR_INVALID_ID_V01 = 0x0029,
IPA_QMI_ERR_ENCODING_V01 = 0x003A,
IPA_QMI_ERR_INCOMPATIBLE_STATE_V01 = 0x005A,
IPA_QMI_ERR_NOT_SUPPORTED_V01 = 0x005E,
IPA_QMI_ERROR_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX,
};
struct ipa_qmi_response_type_v01 {
enum ipa_qmi_result_type_v01 result;
enum ipa_qmi_error_type_v01 error;
};
enum ipa_platform_type_enum_v01 {
IPA_PLATFORM_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647,
QMI_IPA_PLATFORM_TYPE_INVALID_V01 = 0,
QMI_IPA_PLATFORM_TYPE_TN_V01 = 1,
QMI_IPA_PLATFORM_TYPE_LE_V01 = 2,
QMI_IPA_PLATFORM_TYPE_MSM_ANDROID_V01 = 3,
QMI_IPA_PLATFORM_TYPE_MSM_WINDOWS_V01 = 4,
QMI_IPA_PLATFORM_TYPE_MSM_QNX_V01 = 5,
IPA_PLATFORM_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647
};
struct ipa_hdr_tbl_info_type_v01 {
uint32_t modem_offset_start;
uint32_t modem_offset_end;
};
struct ipa_route_tbl_info_type_v01 {
uint32_t route_tbl_start_addr;
uint32_t num_indices;
};
struct ipa_modem_mem_info_type_v01 {
uint32_t block_start_addr;
uint32_t size;
};
struct ipa_hdr_proc_ctx_tbl_info_type_v01 {
uint32_t modem_offset_start;
uint32_t modem_offset_end;
};
struct ipa_zip_tbl_info_type_v01 {
uint32_t modem_offset_start;
uint32_t modem_offset_end;
};
struct ipa_init_modem_driver_req_msg_v01 {
uint8_t platform_type_valid;
enum ipa_platform_type_enum_v01 platform_type;
uint8_t hdr_tbl_info_valid;
struct ipa_hdr_tbl_info_type_v01 hdr_tbl_info;
uint8_t v4_route_tbl_info_valid;
struct ipa_route_tbl_info_type_v01 v4_route_tbl_info;
uint8_t v6_route_tbl_info_valid;
struct ipa_route_tbl_info_type_v01 v6_route_tbl_info;
uint8_t v4_filter_tbl_start_addr_valid;
uint32_t v4_filter_tbl_start_addr;
uint8_t v6_filter_tbl_start_addr_valid;
uint32_t v6_filter_tbl_start_addr;
uint8_t modem_mem_info_valid;
struct ipa_modem_mem_info_type_v01 modem_mem_info;
uint8_t ctrl_comm_dest_end_pt_valid;
uint32_t ctrl_comm_dest_end_pt;
uint8_t is_ssr_bootup_valid;
uint8_t is_ssr_bootup;
uint8_t hdr_proc_ctx_tbl_info_valid;
struct ipa_hdr_proc_ctx_tbl_info_type_v01 hdr_proc_ctx_tbl_info;
uint8_t zip_tbl_info_valid;
struct ipa_zip_tbl_info_type_v01 zip_tbl_info;
uint8_t v4_hash_route_tbl_info_valid;
struct ipa_route_tbl_info_type_v01 v4_hash_route_tbl_info;
uint8_t v6_hash_route_tbl_info_valid;
struct ipa_route_tbl_info_type_v01 v6_hash_route_tbl_info;
uint8_t v4_hash_filter_tbl_start_addr_valid;
uint32_t v4_hash_filter_tbl_start_addr;
uint8_t v6_hash_filter_tbl_start_addr_valid;
uint32_t v6_hash_filter_tbl_start_addr;
uint8_t hw_stats_quota_base_addr_valid;
uint32_t hw_stats_quota_base_addr;
uint8_t hw_stats_quota_size_valid;
uint32_t hw_stats_quota_size;
uint8_t hw_drop_stats_base_addr_valid;
uint32_t hw_drop_stats_base_addr;
uint8_t hw_drop_stats_table_size_valid;
uint32_t hw_drop_stats_table_size;
};
struct ipa_init_modem_driver_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
uint8_t ctrl_comm_dest_end_pt_valid;
uint32_t ctrl_comm_dest_end_pt;
uint8_t default_end_pt_valid;
uint32_t default_end_pt;
uint8_t modem_driver_init_pending_valid;
uint8_t modem_driver_init_pending;
};
struct ipa_init_modem_driver_cmplt_req_msg_v01 {
uint8_t status;
};
struct ipa_init_modem_driver_cmplt_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
};
struct ipa_indication_reg_req_msg_v01 {
uint8_t master_driver_init_complete_valid;
uint8_t master_driver_init_complete;
uint8_t data_usage_quota_reached_valid;
uint8_t data_usage_quota_reached;
};
struct ipa_indication_reg_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
};
struct ipa_master_driver_init_complt_ind_msg_v01 {
struct ipa_qmi_response_type_v01 master_driver_init_status;
};
struct ipa_ipfltr_range_eq_16_type_v01 {
uint8_t offset;
uint16_t range_low;
uint16_t range_high;
};
struct ipa_ipfltr_mask_eq_32_type_v01 {
uint8_t offset;
uint32_t mask;
uint32_t value;
};
struct ipa_ipfltr_eq_16_type_v01 {
uint8_t offset;
uint16_t value;
};
struct ipa_ipfltr_eq_32_type_v01 {
uint8_t offset;
uint32_t value;
};
struct ipa_ipfltr_mask_eq_128_type_v01 {
uint8_t offset;
uint8_t mask[16];
uint8_t value[16];
};
struct ipa_filter_rule_type_v01 {
uint16_t rule_eq_bitmap;
uint8_t tos_eq_present;
uint8_t tos_eq;
uint8_t protocol_eq_present;
uint8_t protocol_eq;
uint8_t num_ihl_offset_range_16;
struct ipa_ipfltr_range_eq_16_type_v01 ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01];
uint8_t num_offset_meq_32;
struct ipa_ipfltr_mask_eq_32_type_v01 offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01];
uint8_t tc_eq_present;
uint8_t tc_eq;
uint8_t flow_eq_present;
uint32_t flow_eq;
uint8_t ihl_offset_eq_16_present;
struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16;
uint8_t ihl_offset_eq_32_present;
struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32;
uint8_t num_ihl_offset_meq_32;
struct ipa_ipfltr_mask_eq_32_type_v01 ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01];
uint8_t num_offset_meq_128;
struct ipa_ipfltr_mask_eq_128_type_v01 offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01];
uint8_t metadata_meq32_present;
struct ipa_ipfltr_mask_eq_32_type_v01 metadata_meq32;
uint8_t ipv4_frag_eq_present;
};
enum ipa_ip_type_enum_v01 {
IPA_IP_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647,
QMI_IPA_IP_TYPE_INVALID_V01 = 0,
QMI_IPA_IP_TYPE_V4_V01 = 1,
QMI_IPA_IP_TYPE_V6_V01 = 2,
QMI_IPA_IP_TYPE_V4V6_V01 = 3,
IPA_IP_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647
};
enum ipa_filter_action_enum_v01 {
IPA_FILTER_ACTION_ENUM_MIN_ENUM_VAL_V01 = - 2147483647,
QMI_IPA_FILTER_ACTION_INVALID_V01 = 0,
QMI_IPA_FILTER_ACTION_SRC_NAT_V01 = 1,
QMI_IPA_FILTER_ACTION_DST_NAT_V01 = 2,
QMI_IPA_FILTER_ACTION_ROUTING_V01 = 3,
QMI_IPA_FILTER_ACTION_EXCEPTION_V01 = 4,
IPA_FILTER_ACTION_ENUM_MAX_ENUM_VAL_V01 = 2147483647
};
struct ipa_filter_spec_type_v01 {
uint32_t filter_spec_identifier;
enum ipa_ip_type_enum_v01 ip_type;
struct ipa_filter_rule_type_v01 filter_rule;
enum ipa_filter_action_enum_v01 filter_action;
uint8_t is_routing_table_index_valid;
uint32_t route_table_index;
uint8_t is_mux_id_valid;
uint32_t mux_id;
};
struct ipa_filter_spec_ex_type_v01 {
enum ipa_ip_type_enum_v01 ip_type;
struct ipa_filter_rule_type_v01 filter_rule;
enum ipa_filter_action_enum_v01 filter_action;
uint8_t is_routing_table_index_valid;
uint32_t route_table_index;
uint8_t is_mux_id_valid;
uint32_t mux_id;
uint32_t rule_id;
uint8_t is_rule_hashable;
};
struct ipa_install_fltr_rule_req_msg_v01 {
uint8_t filter_spec_list_valid;
uint32_t filter_spec_list_len;
struct ipa_filter_spec_type_v01 filter_spec_list[QMI_IPA_MAX_FILTERS_V01];
uint8_t source_pipe_index_valid;
uint32_t source_pipe_index;
uint8_t num_ipv4_filters_valid;
uint32_t num_ipv4_filters;
uint8_t num_ipv6_filters_valid;
uint32_t num_ipv6_filters;
uint8_t xlat_filter_indices_list_valid;
uint32_t xlat_filter_indices_list_len;
uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01];
uint8_t filter_spec_ex_list_valid;
uint32_t filter_spec_ex_list_len;
struct ipa_filter_spec_ex_type_v01 filter_spec_ex_list[QMI_IPA_MAX_FILTERS_V01];
};
struct ipa_filter_rule_identifier_to_handle_map_v01 {
uint32_t filter_spec_identifier;
uint32_t filter_handle;
};
struct ipa_install_fltr_rule_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
uint8_t filter_handle_list_valid;
uint32_t filter_handle_list_len;
struct ipa_filter_rule_identifier_to_handle_map_v01 filter_handle_list[QMI_IPA_MAX_FILTERS_V01];
uint8_t rule_id_valid;
uint32_t rule_id_len;
uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01];
};
struct ipa_filter_handle_to_index_map_v01 {
uint32_t filter_handle;
uint32_t filter_index;
};
struct ipa_fltr_installed_notif_req_msg_v01 {
uint32_t source_pipe_index;
enum ipa_qmi_result_type_v01 install_status;
uint32_t filter_index_list_len;
struct ipa_filter_handle_to_index_map_v01 filter_index_list[QMI_IPA_MAX_FILTERS_V01];
uint8_t embedded_pipe_index_valid;
uint32_t embedded_pipe_index;
uint8_t retain_header_valid;
uint8_t retain_header;
uint8_t embedded_call_mux_id_valid;
uint32_t embedded_call_mux_id;
uint8_t num_ipv4_filters_valid;
uint32_t num_ipv4_filters;
uint8_t num_ipv6_filters_valid;
uint32_t num_ipv6_filters;
uint8_t start_ipv4_filter_idx_valid;
uint32_t start_ipv4_filter_idx;
uint8_t start_ipv6_filter_idx_valid;
uint32_t start_ipv6_filter_idx;
uint8_t rule_id_valid;
uint32_t rule_id_len;
uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01];
uint8_t dst_pipe_id_valid;
uint32_t dst_pipe_id_len;
uint32_t dst_pipe_id[QMI_IPA_MAX_CLIENT_DST_PIPES_V01];
};
struct ipa_fltr_installed_notif_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
};
struct ipa_enable_force_clear_datapath_req_msg_v01 {
uint32_t source_pipe_bitmask;
uint32_t request_id;
uint8_t throttle_source_valid;
uint8_t throttle_source;
};
struct ipa_enable_force_clear_datapath_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
};
struct ipa_disable_force_clear_datapath_req_msg_v01 {
uint32_t request_id;
};
struct ipa_disable_force_clear_datapath_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
};
enum ipa_peripheral_speed_enum_v01 {
IPA_PERIPHERAL_SPEED_ENUM_MIN_ENUM_VAL_V01 = - 2147483647,
QMI_IPA_PER_USB_FS_V01 = 1,
QMI_IPA_PER_USB_HS_V01 = 2,
QMI_IPA_PER_USB_SS_V01 = 3,
QMI_IPA_PER_WLAN_V01 = 4,
IPA_PERIPHERAL_SPEED_ENUM_MAX_ENUM_VAL_V01 = 2147483647
};
enum ipa_pipe_mode_enum_v01 {
IPA_PIPE_MODE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647,
QMI_IPA_PIPE_MODE_HW_V01 = 1,
QMI_IPA_PIPE_MODE_SW_V01 = 2,
IPA_PIPE_MODE_ENUM_MAX_ENUM_VAL_V01 = 2147483647
};
enum ipa_peripheral_type_enum_v01 {
IPA_PERIPHERAL_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647,
QMI_IPA_PERIPHERAL_USB_V01 = 1,
QMI_IPA_PERIPHERAL_HSIC_V01 = 2,
QMI_IPA_PERIPHERAL_PCIE_V01 = 3,
IPA_PERIPHERAL_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647
};
struct ipa_config_req_msg_v01 {
uint8_t peripheral_type_valid;
enum ipa_peripheral_type_enum_v01 peripheral_type;
uint8_t hw_deaggr_supported_valid;
uint8_t hw_deaggr_supported;
uint8_t max_aggr_frame_size_valid;
uint32_t max_aggr_frame_size;
uint8_t ipa_ingress_pipe_mode_valid;
enum ipa_pipe_mode_enum_v01 ipa_ingress_pipe_mode;
uint8_t peripheral_speed_info_valid;
enum ipa_peripheral_speed_enum_v01 peripheral_speed_info;
uint8_t dl_accumulation_time_limit_valid;
uint32_t dl_accumulation_time_limit;
uint8_t dl_accumulation_pkt_limit_valid;
uint32_t dl_accumulation_pkt_limit;
uint8_t dl_accumulation_byte_limit_valid;
uint32_t dl_accumulation_byte_limit;
uint8_t ul_accumulation_time_limit_valid;
uint32_t ul_accumulation_time_limit;
uint8_t hw_control_flags_valid;
uint32_t hw_control_flags;
uint8_t ul_msi_event_threshold_valid;
uint32_t ul_msi_event_threshold;
uint8_t dl_msi_event_threshold_valid;
uint32_t dl_msi_event_threshold;
uint8_t ul_fifo_size_valid;
uint32_t ul_fifo_size;
uint8_t dl_fifo_size_valid;
uint32_t dl_fifo_size;
uint8_t dl_buf_size_valid;
uint32_t dl_buf_size;
};
struct ipa_config_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
};
enum ipa_stats_type_enum_v01 {
IPA_STATS_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647,
QMI_IPA_STATS_TYPE_INVALID_V01 = 0,
QMI_IPA_STATS_TYPE_PIPE_V01 = 1,
QMI_IPA_STATS_TYPE_FILTER_RULES_V01 = 2,
IPA_STATS_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647
};
struct ipa_pipe_stats_info_type_v01 {
uint32_t pipe_index;
uint64_t num_ipv4_packets;
uint64_t num_ipv4_bytes;
uint64_t num_ipv6_packets;
uint64_t num_ipv6_bytes;
};
struct ipa_stats_type_filter_rule_v01 {
uint32_t filter_rule_index;
uint64_t num_packets;
};
struct ipa_get_data_stats_req_msg_v01 {
enum ipa_stats_type_enum_v01 ipa_stats_type;
uint8_t reset_stats_valid;
uint8_t reset_stats;
};
struct ipa_get_data_stats_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
uint8_t ipa_stats_type_valid;
enum ipa_stats_type_enum_v01 ipa_stats_type;
uint8_t ul_src_pipe_stats_list_valid;
uint32_t ul_src_pipe_stats_list_len;
struct ipa_pipe_stats_info_type_v01 ul_src_pipe_stats_list[QMI_IPA_MAX_PIPES_V01];
uint8_t dl_dst_pipe_stats_list_valid;
uint32_t dl_dst_pipe_stats_list_len;
struct ipa_pipe_stats_info_type_v01 dl_dst_pipe_stats_list[QMI_IPA_MAX_PIPES_V01];
uint8_t dl_filter_rule_stats_list_valid;
uint32_t dl_filter_rule_stats_list_len;
struct ipa_stats_type_filter_rule_v01 dl_filter_rule_stats_list[QMI_IPA_MAX_FILTERS_V01];
};
struct ipa_apn_data_stats_info_type_v01 {
uint32_t mux_id;
uint64_t num_ul_packets;
uint64_t num_ul_bytes;
uint64_t num_dl_packets;
uint64_t num_dl_bytes;
};
struct ipa_get_apn_data_stats_req_msg_v01 {
uint8_t mux_id_list_valid;
uint32_t mux_id_list_len;
uint32_t mux_id_list[QMI_IPA_MAX_APN_V01];
};
struct ipa_get_apn_data_stats_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
uint8_t apn_data_stats_list_valid;
uint32_t apn_data_stats_list_len;
struct ipa_apn_data_stats_info_type_v01 apn_data_stats_list[QMI_IPA_MAX_APN_V01];
};
struct ipa_data_usage_quota_info_type_v01 {
uint32_t mux_id;
uint64_t num_Mbytes;
};
struct ipa_set_data_usage_quota_req_msg_v01 {
uint8_t apn_quota_list_valid;
uint32_t apn_quota_list_len;
struct ipa_data_usage_quota_info_type_v01 apn_quota_list[QMI_IPA_MAX_APN_V01];
};
struct ipa_set_data_usage_quota_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
};
struct ipa_data_usage_quota_reached_ind_msg_v01 {
struct ipa_data_usage_quota_info_type_v01 apn;
};
struct ipa_stop_data_usage_quota_req_msg_v01 {
char __placeholder;
};
struct ipa_stop_data_usage_quota_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
};
struct ipa_install_fltr_rule_req_ex_msg_v01 {
uint8_t filter_spec_ex_list_valid;
uint32_t filter_spec_ex_list_len;
struct ipa_filter_spec_ex_type_v01 filter_spec_ex_list[QMI_IPA_MAX_FILTERS_EX_V01];
uint8_t source_pipe_index_valid;
uint32_t source_pipe_index;
uint8_t num_ipv4_filters_valid;
uint32_t num_ipv4_filters;
uint8_t num_ipv6_filters_valid;
uint32_t num_ipv6_filters;
uint8_t xlat_filter_indices_list_valid;
uint32_t xlat_filter_indices_list_len;
uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_EX_V01];
};
struct ipa_install_fltr_rule_resp_ex_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
uint8_t rule_id_valid;
uint32_t rule_id_len;
uint32_t rule_id[QMI_IPA_MAX_FILTERS_EX_V01];
};
struct ipa_enable_per_client_stats_req_msg_v01 {
uint8_t enable_per_client_stats;
};
struct ipa_enable_per_client_stats_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
};
struct ipa_per_client_stats_info_type_v01 {
uint32_t client_id;
uint32_t src_pipe_id;
uint64_t num_ul_ipv4_bytes;
uint64_t num_ul_ipv6_bytes;
uint64_t num_dl_ipv4_bytes;
uint64_t num_dl_ipv6_bytes;
uint32_t num_ul_ipv4_pkts;
uint32_t num_ul_ipv6_pkts;
uint32_t num_dl_ipv4_pkts;
uint32_t num_dl_ipv6_pkts;
};
struct ipa_get_stats_per_client_req_msg_v01 {
uint32_t client_id;
uint32_t src_pipe_id;
uint8_t reset_stats_valid;
uint8_t reset_stats;
};
struct ipa_get_stats_per_client_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
uint8_t per_client_stats_list_valid;
uint32_t per_client_stats_list_len;
struct ipa_per_client_stats_info_type_v01 per_client_stats_list[QMI_IPA_MAX_PER_CLIENTS_V01];
};
struct ipa_ul_firewall_rule_type_v01 {
enum ipa_ip_type_enum_v01 ip_type;
struct ipa_filter_rule_type_v01 filter_rule;
};
struct ipa_configure_ul_firewall_rules_req_msg_v01 {
uint32_t firewall_rules_list_len;
struct ipa_ul_firewall_rule_type_v01 firewall_rules_list[QMI_IPA_MAX_UL_FIREWALL_RULES_V01];
uint32_t mux_id;
uint8_t disable_valid;
uint8_t disable;
uint8_t are_blacklist_filters_valid;
uint8_t are_blacklist_filters;
};
struct ipa_configure_ul_firewall_rules_resp_msg_v01 {
struct ipa_qmi_response_type_v01 resp;
};
enum ipa_ul_firewall_status_enum_v01 {
IPA_UL_FIREWALL_STATUS_ENUM_MIN_ENUM_VAL_V01 = - 2147483647,
QMI_IPA_UL_FIREWALL_STATUS_SUCCESS_V01 = 0,
QMI_IPA_UL_FIREWALL_STATUS_FAILURE_V01 = 1,
IPA_UL_FIREWALL_STATUS_ENUM_MAX_ENUM_VAL_V01 = 2147483647
};
struct ipa_ul_firewall_config_result_type_v01 {
enum ipa_ul_firewall_status_enum_v01 is_success;
uint32_t mux_id;
};
struct ipa_configure_ul_firewall_rules_ind_msg_v01 {
struct ipa_ul_firewall_config_result_type_v01 result;
};
#define QMI_IPA_INDICATION_REGISTER_REQ_V01 0x0020
#define QMI_IPA_INDICATION_REGISTER_RESP_V01 0x0020
#define QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 0x0021
#define QMI_IPA_INIT_MODEM_DRIVER_RESP_V01 0x0021
#define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_V01 0x0022
#define QMI_IPA_INSTALL_FILTER_RULE_REQ_V01 0x0023
#define QMI_IPA_INSTALL_FILTER_RULE_RESP_V01 0x0023
#define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01 0x0024
#define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01 0x0024
#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0025
#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0025
#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0026
#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0026
#define QMI_IPA_CONFIG_REQ_V01 0x0027
#define QMI_IPA_CONFIG_RESP_V01 0x0027
#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0028
#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0028
#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0029
#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0029
#define QMI_IPA_GET_DATA_STATS_REQ_V01 0x0030
#define QMI_IPA_GET_DATA_STATS_RESP_V01 0x0030
#define QMI_IPA_GET_APN_DATA_STATS_REQ_V01 0x0031
#define QMI_IPA_GET_APN_DATA_STATS_RESP_V01 0x0031
#define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01 0x0032
#define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01 0x0032
#define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_V01 0x0033
#define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01 0x0034
#define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01 0x0034
#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_V01 0x0035
#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01 0x0035
#define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_V01 0x0037
#define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_V01 0x0037
#define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01 0x0038
#define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_V01 0x0038
#define QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01 0x0039
#define QMI_IPA_GET_STATS_PER_CLIENT_RESP_V01 0x0039
#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_V01 0x003A
#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_V01 0x003A
#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_V01 0x003A
#define QMI_IPA_INIT_MODEM_DRIVER_REQ_MAX_MSG_LEN_V01 162
#define QMI_IPA_INIT_MODEM_DRIVER_RESP_MAX_MSG_LEN_V01 25
#define QMI_IPA_INDICATION_REGISTER_REQ_MAX_MSG_LEN_V01 8
#define QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_INSTALL_FILTER_RULE_REQ_MAX_MSG_LEN_V01 22369
#define QMI_IPA_INSTALL_FILTER_RULE_RESP_MAX_MSG_LEN_V01 783
#define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_MAX_MSG_LEN_V01 870
#define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_MAX_MSG_LEN_V01 7
#define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_MAX_MSG_LEN_V01 15
#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 18
#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 7
#define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_CONFIG_REQ_MAX_MSG_LEN_V01 102
#define QMI_IPA_CONFIG_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 18
#define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 7
#define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_GET_DATA_STATS_REQ_MAX_MSG_LEN_V01 11
#define QMI_IPA_GET_DATA_STATS_RESP_MAX_MSG_LEN_V01 2234
#define QMI_IPA_GET_APN_DATA_STATS_REQ_MAX_MSG_LEN_V01 36
#define QMI_IPA_GET_APN_DATA_STATS_RESP_MAX_MSG_LEN_V01 299
#define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 100
#define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 0
#define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_MAX_MSG_LEN_V01 4
#define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_MAX_MSG_LEN_V01 22685
#define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_MAX_MSG_LEN_V01 523
#define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_MAX_MSG_LEN_V01 4
#define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_GET_STATS_PER_CLIENT_REQ_MAX_MSG_LEN_V01 18
#define QMI_IPA_GET_STATS_PER_CLIENT_RESP_MAX_MSG_LEN_V01 3595
#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_MAX_MSG_LEN_V01 9875
#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_MAX_MSG_LEN_V01 7
#define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_MAX_MSG_LEN_V01 11
#endif

73
sdm710/kernel-headers/linux/mdss_rotator.h
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@@ -1,73 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _MDSS_ROTATOR_H_
#define _MDSS_ROTATOR_H_
#include <linux/msm_mdp_ext.h>
#define MDSS_ROTATOR_IOCTL_MAGIC 'w'
#define MDSS_ROTATION_OPEN _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 1, struct mdp_rotation_config *)
#define MDSS_ROTATION_CONFIG _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 2, struct mdp_rotation_config *)
#define MDSS_ROTATION_REQUEST _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 3, struct mdp_rotation_request *)
#define MDSS_ROTATION_CLOSE _IOW(MDSS_ROTATOR_IOCTL_MAGIC, 4, unsigned int)
#define MDP_ROTATION_NOP 0x01
#define MDP_ROTATION_FLIP_LR 0x02
#define MDP_ROTATION_FLIP_UD 0x04
#define MDP_ROTATION_90 0x08
#define MDP_ROTATION_180 (MDP_ROTATION_FLIP_LR | MDP_ROTATION_FLIP_UD)
#define MDP_ROTATION_270 (MDP_ROTATION_90 | MDP_ROTATION_180)
#define MDP_ROTATION_DEINTERLACE 0x10
#define MDP_ROTATION_BWC_EN 0x40
#define MDP_ROTATION_SECURE 0x80
#define MDSS_ROTATION_REQUEST_VALIDATE 0x01
#define MDP_ROTATION_REQUEST_VERSION_1_0 0x00010000
#define MDSS_ROTATION_HW_ANY 0xFFFFFFFF
struct mdp_rotation_buf_info {
uint32_t width;
uint32_t height;
uint32_t format;
struct mult_factor comp_ratio;
};
struct mdp_rotation_config {
uint32_t version;
uint32_t session_id;
struct mdp_rotation_buf_info input;
struct mdp_rotation_buf_info output;
uint32_t frame_rate;
uint32_t flags;
uint32_t reserved[6];
};
struct mdp_rotation_item {
uint32_t flags;
struct mdp_rect src_rect;
struct mdp_rect dst_rect;
struct mdp_layer_buffer input;
struct mdp_layer_buffer output;
uint32_t pipe_idx;
uint32_t wb_idx;
uint32_t session_id;
uint32_t reserved[6];
};
struct mdp_rotation_request {
uint32_t version;
uint32_t flags;
uint32_t count;
struct mdp_rotation_item * list;
uint32_t reserved[6];
};
#endif

80
sdm710/kernel-headers/linux/mfd/msm-adie-codec.h
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@@ -1,80 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MFD_MSM_ADIE_CODEC_H
#define __UAPI_MFD_MSM_ADIE_CODEC_H
#include <linux/types.h>
#define ADIE_CODEC_ACTION_ENTRY 0x1
#define ADIE_CODEC_ACTION_DELAY_WAIT 0x2
#define ADIE_CODEC_ACTION_STAGE_REACHED 0x3
#define ADIE_CODEC_PATH_OFF 0x0050
#define ADIE_CODEC_DIGITAL_READY 0x0100
#define ADIE_CODEC_DIGITAL_ANALOG_READY 0x1000
#define ADIE_CODEC_ANALOG_OFF 0x0750
#define ADIE_CODEC_DIGITAL_OFF 0x0600
#define ADIE_CODEC_FLASH_IMAGE 0x0001
#define ADIE_CODEC_RX 0
#define ADIE_CODEC_TX 1
#define ADIE_CODEC_LB 3
#define ADIE_CODEC_MAX 4
#define ADIE_CODEC_PACK_ENTRY(reg,mask,val) ((val) | (mask << 8) | (reg << 16))
#define ADIE_CODEC_UNPACK_ENTRY(packed,reg,mask,val) do { ((reg) = ((packed >> 16) & (0xff))); ((mask) = ((packed >> 8) & (0xff))); ((val) = ((packed) & (0xff))); } while(0);
struct adie_codec_action_unit {
u32 type;
u32 action;
};
struct adie_codec_hwsetting_entry {
struct adie_codec_action_unit * actions;
u32 action_sz;
u32 freq_plan;
u32 osr;
};
struct adie_codec_dev_profile {
u32 path_type;
u32 setting_sz;
struct adie_codec_hwsetting_entry * settings;
};
struct adie_codec_register {
u8 reg;
u8 mask;
u8 val;
};
struct adie_codec_register_image {
struct adie_codec_register * regs;
u32 img_sz;
};
struct adie_codec_path;
struct adie_codec_anc_data {
u32 size;
u32 writes[];
};
struct adie_codec_operations {
int codec_id;
int(* codec_open) (struct adie_codec_dev_profile * profile, struct adie_codec_path * * path_pptr);
int(* codec_close) (struct adie_codec_path * path_ptr);
int(* codec_setpath) (struct adie_codec_path * path_ptr, u32 freq_plan, u32 osr);
int(* codec_proceed_stage) (struct adie_codec_path * path_ptr, u32 state);
u32(* codec_freq_supported) (struct adie_codec_dev_profile * profile, u32 requested_freq);
int(* codec_enable_sidetone) (struct adie_codec_path * rx_path_ptr, u32 enable);
int(* codec_enable_anc) (struct adie_codec_path * rx_path_ptr, u32 enable, struct adie_codec_anc_data * calibration_writes);
int(* codec_set_device_digital_volume) (struct adie_codec_path * path_ptr, u32 num_channels, u32 vol_percentage);
int(* codec_set_device_analog_volume) (struct adie_codec_path * path_ptr, u32 num_channels, u32 volume);
int(* codec_set_master_mode) (struct adie_codec_path * path_ptr, u8 master);
};
#endif

1401
sdm710/kernel-headers/linux/mfd/wcd9xxx/wcd9320_registers.h
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File diff suppressed because it is too large Load Diff

364
sdm710/kernel-headers/linux/mfd/wcd9xxx/wcd9xxx_registers.h
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@@ -1,364 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef WCD9XXX_CODEC_DIGITAL_H
#define WCD9XXX_CODEC_DIGITAL_H
#define WCD9XXX_A_CHIP_CTL (0x00)
#define WCD9XXX_A_CHIP_CTL__POR (0x00000000)
#define WCD9XXX_A_CHIP_STATUS (0x01)
#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04)
#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05)
#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06)
#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07)
#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001)
#define WCD9XXX_A_CHIP_VERSION (0x08)
#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020)
#define WCD9XXX_A_SB_VERSION (0x09)
#define WCD9XXX_A_SB_VERSION__POR (0x00000010)
#define WCD9XXX_A_SLAVE_ID_1 (0x0C)
#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077)
#define WCD9XXX_A_SLAVE_ID_2 (0x0D)
#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066)
#define WCD9XXX_A_SLAVE_ID_3 (0x0E)
#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055)
#define WCD9XXX_A_CDC_CTL (0x80)
#define WCD9XXX_A_CDC_CTL__POR (0x00000000)
#define WCD9XXX_A_LEAKAGE_CTL (0x88)
#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004)
#define WCD9XXX_A_INTR_MODE (0x90)
#define WCD9XXX_A_INTR_MASK0 (0x94)
#define WCD9XXX_A_INTR_STATUS0 (0x98)
#define WCD9XXX_A_INTR_CLEAR0 (0x9C)
#define WCD9XXX_A_INTR_LEVEL0 (0xA0)
#define WCD9XXX_A_INTR_LEVEL1 (0xA1)
#define WCD9XXX_A_INTR_LEVEL2 (0xA2)
#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB)
#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80)
#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB)
#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80)
#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL (0x101)
#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL__POR (0x50)
#define WCD9XXX_A_CLK_BUFF_EN1 (0x108)
#define WCD9XXX_A_CLK_BUFF_EN1__POR (0x04)
#define WCD9XXX_A_CLK_BUFF_EN2 (0x109)
#define WCD9XXX_A_CLK_BUFF_EN2__POR (0x02)
#define WCD9XXX_A_RX_COM_BIAS (0x1A2)
#define WCD9XXX_A_RX_COM_BIAS__POR (0x00)
#define WCD9XXX_A_RC_OSC_FREQ (0x1FA)
#define WCD9XXX_A_RC_OSC_FREQ__POR (0x46)
#define WCD9XXX_A_BIAS_OSC_BG_CTL (0x105)
#define WCD9XXX_A_BIAS_OSC_BG_CTL__POR (0x16)
#define WCD9XXX_A_RC_OSC_TEST (0x1FB)
#define WCD9XXX_A_RC_OSC_TEST__POR (0x0A)
#define WCD9XXX_A_CDC_CLK_MCLK_CTL (0x311)
#define WCD9XXX_A_CDC_CLK_MCLK_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_EN_CTL (0x3C0)
#define WCD9XXX_A_CDC_MBHC_EN_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG (0x3C1)
#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG (0x3C2)
#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG__POR (0x06)
#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL (0x3C3)
#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03)
#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL (0x3C4)
#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09)
#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL (0x3C5)
#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E)
#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL (0x3C6)
#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45)
#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL (0x3C7)
#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04)
#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL (0x3C8)
#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78)
#define WCD9XXX_A_CDC_MBHC_B1_STATUS (0x3C9)
#define WCD9XXX_A_CDC_MBHC_B1_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B2_STATUS (0x3CA)
#define WCD9XXX_A_CDC_MBHC_B2_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B3_STATUS (0x3CB)
#define WCD9XXX_A_CDC_MBHC_B3_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B4_STATUS (0x3CC)
#define WCD9XXX_A_CDC_MBHC_B4_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B5_STATUS (0x3CD)
#define WCD9XXX_A_CDC_MBHC_B5_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B1_CTL (0x3CE)
#define WCD9XXX_A_CDC_MBHC_B1_CTL__POR (0xC0)
#define WCD9XXX_A_CDC_MBHC_B2_CTL (0x3CF)
#define WCD9XXX_A_CDC_MBHC_B2_CTL__POR (0x5D)
#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL (0x3D0)
#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL (0x3D1)
#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL (0x3D2)
#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL (0x3D3)
#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL (0x3D4)
#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL (0x3D5)
#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL (0x3D6)
#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF)
#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL (0x3D7)
#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07)
#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL (0x3D8)
#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF)
#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL (0x3D9)
#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F)
#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL (0x3DA)
#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL (0x3DB)
#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80)
#define WCD9XXX_A_CDC_MBHC_CLK_CTL (0x3DC)
#define WCD9XXX_A_CDC_MBHC_CLK_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_INT_CTL (0x3DD)
#define WCD9XXX_A_CDC_MBHC_INT_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL (0x3DE)
#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_SPARE (0x3DF)
#define WCD9XXX_A_CDC_MBHC_SPARE__POR (0x00)
#define WCD9XXX_A_MBHC_SCALING_MUX_1 (0x14E)
#define WCD9XXX_A_MBHC_SCALING_MUX_1__POR (0x00)
#define WCD9XXX_A_RX_HPH_OCP_CTL (0x1AA)
#define WCD9XXX_A_RX_HPH_OCP_CTL__POR (0x68)
#define WCD9XXX_A_MICB_1_CTL (0x12B)
#define WCD9XXX_A_MICB_1_CTL__POR (0x16)
#define WCD9XXX_A_MICB_1_INT_RBIAS (0x12C)
#define WCD9XXX_A_MICB_1_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_1_MBHC (0x12D)
#define WCD9XXX_A_MICB_1_MBHC__POR (0x01)
#define WCD9XXX_A_MICB_CFILT_2_CTL (0x12E)
#define WCD9XXX_A_MICB_CFILT_2_CTL__POR (0x40)
#define WCD9XXX_A_MICB_CFILT_2_VAL (0x12F)
#define WCD9XXX_A_MICB_CFILT_2_VAL__POR (0x80)
#define WCD9XXX_A_MICB_CFILT_2_PRECHRG (0x130)
#define WCD9XXX_A_MICB_CFILT_2_PRECHRG__POR (0x38)
#define WCD9XXX_A_MICB_2_CTL (0x131)
#define WCD9XXX_A_MICB_2_CTL__POR (0x16)
#define WCD9XXX_A_MICB_2_INT_RBIAS (0x132)
#define WCD9XXX_A_MICB_2_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_2_MBHC (0x133)
#define WCD9XXX_A_MICB_2_MBHC__POR (0x02)
#define WCD9XXX_A_MICB_CFILT_3_CTL (0x134)
#define WCD9XXX_A_MICB_CFILT_3_CTL__POR (0x40)
#define WCD9XXX_A_MICB_CFILT_3_VAL (0x135)
#define WCD9XXX_A_MICB_CFILT_3_VAL__POR (0x80)
#define WCD9XXX_A_MICB_CFILT_3_PRECHRG (0x136)
#define WCD9XXX_A_MICB_CFILT_3_PRECHRG__POR (0x38)
#define WCD9XXX_A_MICB_3_CTL (0x137)
#define WCD9XXX_A_MICB_3_CTL__POR (0x16)
#define WCD9XXX_A_MICB_3_INT_RBIAS (0x138)
#define WCD9XXX_A_MICB_3_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_3_MBHC (0x139)
#define WCD9XXX_A_MICB_3_MBHC__POR (0x00)
#define WCD9XXX_A_MICB_4_CTL (0x13D)
#define WCD9XXX_A_MICB_4_CTL__POR (0x16)
#define WCD9XXX_A_MICB_4_INT_RBIAS (0x13E)
#define WCD9XXX_A_MICB_4_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_4_MBHC (0x13F)
#define WCD9XXX_A_MICB_4_MBHC__POR (0x01)
#define WCD9XXX_A_MICB_CFILT_1_VAL (0x129)
#define WCD9XXX_A_MICB_CFILT_1_VAL__POR (0x80)
#define WCD9XXX_A_RX_HPH_L_STATUS (0x1B3)
#define WCD9XXX_A_RX_HPH_L_STATUS__POR (0x00)
#define WCD9XXX_A_MBHC_HPH (0x1FE)
#define WCD9XXX_A_MBHC_HPH__POR (0x44)
#define WCD9XXX_A_RX_HPH_CNP_WG_TIME (0x1AD)
#define WCD9XXX_A_RX_HPH_CNP_WG_TIME__POR (0x2A)
#define WCD9XXX_A_RX_HPH_R_DAC_CTL (0x1B7)
#define WCD9XXX_A_RX_HPH_R_DAC_CTL__POR (0x00)
#define WCD9XXX_A_RX_HPH_L_DAC_CTL (0x1B1)
#define WCD9XXX_A_RX_HPH_L_DAC_CTL__POR (0x00)
#define WCD9XXX_A_TX_7_MBHC_EN (0x171)
#define WCD9XXX_A_TX_7_MBHC_EN__POR (0x0C)
#define WCD9XXX_A_PIN_CTL_OE0 (0x010)
#define WCD9XXX_A_PIN_CTL_OE0__POR (0x00)
#define WCD9XXX_A_PIN_CTL_OE1 (0x011)
#define WCD9XXX_A_PIN_CTL_OE1__POR (0x00)
#define WCD9XXX_A_MICB_CFILT_1_CTL (0x128)
#define WCD9XXX_A_LDO_H_MODE_1 (0x110)
#define WCD9XXX_A_LDO_H_MODE_1__POR (0x65)
#define WCD9XXX_A_MICB_CFILT_1_CTL__POR (0x40)
#define WCD9XXX_A_TX_7_MBHC_TEST_CTL (0x174)
#define WCD9XXX_A_TX_7_MBHC_TEST_CTL__POR (0x38)
#define WCD9XXX_A_MBHC_SCALING_MUX_2 (0x14F)
#define WCD9XXX_A_MBHC_SCALING_MUX_2__POR (0x80)
#define WCD9XXX_A_TX_COM_BIAS (0x14C)
#define WCD9XXX_A_TX_COM_BIAS__POR (0xF0)
#define WCD9XXX_A_MBHC_INSERT_DETECT (0x14A)
#define WCD9XXX_A_MBHC_INSERT_DETECT__POR (0x00)
#define WCD9XXX_A_MBHC_INSERT_DET_STATUS (0x14B)
#define WCD9XXX_A_MBHC_INSERT_DET_STATUS__POR (0x00)
#define WCD9XXX_A_MAD_ANA_CTRL (0x150)
#define WCD9XXX_A_MAD_ANA_CTRL__POR (0xF1)
#define WCD9XXX_A_CDC_CLK_OTHR_CTL (0x30C)
#define WCD9XXX_A_CDC_CLK_OTHR_CTL__POR (0x00)
#define WCD9XXX_A_BUCK_MODE_1 (0x181)
#define WCD9XXX_A_BUCK_MODE_1__POR (0x21)
#define WCD9XXX_A_BUCK_MODE_2 (0x182)
#define WCD9XXX_A_BUCK_MODE_2__POR (0xFF)
#define WCD9XXX_A_BUCK_MODE_3 (0x183)
#define WCD9XXX_A_BUCK_MODE_3__POR (0xCC)
#define WCD9XXX_A_BUCK_MODE_4 (0x184)
#define WCD9XXX_A_BUCK_MODE_4__POR (0x3A)
#define WCD9XXX_A_BUCK_MODE_5 (0x185)
#define WCD9XXX_A_BUCK_MODE_5__POR (0x00)
#define WCD9XXX_A_BUCK_CTRL_VCL_1 (0x186)
#define WCD9XXX_A_BUCK_CTRL_VCL_1__POR (0x48)
#define WCD9XXX_A_BUCK_CTRL_VCL_2 (0x187)
#define WCD9XXX_A_BUCK_CTRL_VCL_2__POR (0xA3)
#define WCD9XXX_A_BUCK_CTRL_VCL_3 (0x188)
#define WCD9XXX_A_BUCK_CTRL_VCL_3__POR (0x82)
#define WCD9XXX_A_BUCK_CTRL_CCL_1 (0x189)
#define WCD9XXX_A_BUCK_CTRL_CCL_1__POR (0xAB)
#define WCD9XXX_A_BUCK_CTRL_CCL_2 (0x18A)
#define WCD9XXX_A_BUCK_CTRL_CCL_2__POR (0xDC)
#define WCD9XXX_A_BUCK_CTRL_CCL_3 (0x18B)
#define WCD9XXX_A_BUCK_CTRL_CCL_3__POR (0x6A)
#define WCD9XXX_A_BUCK_CTRL_CCL_4 (0x18C)
#define WCD9XXX_A_BUCK_CTRL_CCL_4__POR (0x58)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1 (0x18D)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2 (0x18E)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3 (0x18F)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77)
#define WCD9XXX_A_BUCK_TMUX_A_D (0x190)
#define WCD9XXX_A_BUCK_TMUX_A_D__POR (0x00)
#define WCD9XXX_A_NCP_EN (0x192)
#define WCD9XXX_A_NCP_EN__POR (0xFE)
#define WCD9XXX_A_NCP_STATIC (0x194)
#define WCD9XXX_A_NCP_STATIC__POR (0x28)
#define WCD9XXX_A_NCP_BUCKREF (0x191)
#define WCD9XXX_A_NCP_BUCKREF__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_B1_CTL (0x320)
#define WCD9XXX_A_CDC_CLSH_B1_CTL__POR (0xE4)
#define WCD9XXX_A_CDC_CLSH_B2_CTL (0x321)
#define WCD9XXX_A_CDC_CLSH_B2_CTL__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_B3_CTL (0x322)
#define WCD9XXX_A_CDC_CLSH_B3_CTL__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS (0x323)
#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD (0x324)
#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12)
#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD (0x325)
#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23)
#define WCD9XXX_A_CDC_CLSH_K_ADDR (0x328)
#define WCD9XXX_A_CDC_CLSH_K_ADDR__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_K_DATA (0x329)
#define WCD9XXX_A_CDC_CLSH_K_DATA__POR (0xA4)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR (0x32E)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH (0x32F)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR (0x330)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH (0x331)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00)
#define WCD9XXX_A_CDC_RX1_B6_CTL (0x2B5)
#define WCD9XXX_A_CDC_RX1_B6_CTL__POR (0x80)
#define WCD9XXX_A_CDC_RX2_B6_CTL (0x2BD)
#define WCD9XXX_A_CDC_RX2_B6_CTL__POR (0x80)
#define WCD9XXX_A_RX_HPH_L_GAIN (0x1AE)
#define WCD9XXX_A_RX_HPH_L_GAIN__POR (0x00)
#define WCD9XXX_A_RX_HPH_R_GAIN (0x1B4)
#define WCD9XXX_A_RX_HPH_R_GAIN__POR (0x00)
#define WCD9XXX_A_RX_HPH_CHOP_CTL (0x1A5)
#define WCD9XXX_A_RX_HPH_CHOP_CTL__POR (0xB4)
#define WCD9XXX_A_RX_HPH_BIAS_PA (0x1A6)
#define WCD9XXX_A_RX_HPH_BIAS_PA__POR (0x7A)
#define WCD9XXX_A_RX_HPH_L_TEST (0x1AF)
#define WCD9XXX_A_RX_HPH_L_TEST__POR (0x00)
#define WCD9XXX_A_RX_HPH_R_TEST (0x1B5)
#define WCD9XXX_A_RX_HPH_R_TEST__POR (0x00)
#define WCD9XXX_A_CDC_CLK_RX_B1_CTL (0x30F)
#define WCD9XXX_A_CDC_CLK_RX_B1_CTL__POR (0x00)
#define WCD9XXX_A_NCP_CLK (0x193)
#define WCD9XXX_A_NCP_CLK__POR (0x94)
#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP (0x1A9)
#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP__POR (0x2A)
#define WCD9XXX_A_RX_HPH_CNP_WG_CTL (0x1AC)
#define WCD9XXX_A_RX_HPH_CNP_WG_CTL__POR (0xDE)
#define WCD9XXX_A_RX_HPH_L_PA_CTL (0x1B0)
#define WCD9XXX_A_RX_HPH_L_PA_CTL__POR (0x42)
#define WCD9XXX_A_RX_HPH_R_PA_CTL (0x1B6)
#define WCD9XXX_A_RX_HPH_R_PA_CTL__POR (0x42)
#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL (0x383)
#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL (0x361)
#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL (0x362)
#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL (0x363)
#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL (0x364)
#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL__POR (0x00)
#define WCD9330_A_LEAKAGE_CTL (0x03C)
#define WCD9330_A_LEAKAGE_CTL__POR (0x04)
#define WCD9330_A_CDC_CTL (0x034)
#define WCD9330_A_CDC_CTL__POR (0x00)
#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 (0xB42)
#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 (0xB56)
#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 (0xB6A)
#define WCD9XXX_A_CDC_CLSH_K1_MSB (0xC08)
#define WCD9XXX_A_CDC_CLSH_K1_LSB (0xC09)
#define WCD9XXX_A_ANA_RX_SUPPLIES (0x608)
#define WCD9XXX_A_ANA_HPH (0x609)
#define WCD9XXX_A_CDC_CLSH_CRC (0xC01)
#define WCD9XXX_FLYBACK_EN (0x6A4)
#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (0x6A5)
#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (0x6AF)
#define WCD9XXX_RX_BIAS_FLYB_BUFF (0x6C7)
#define WCD9XXX_HPH_L_EN (0x6D3)
#define WCD9XXX_HPH_R_EN (0x6D6)
#define WCD9XXX_HPH_REFBUFF_UHQA_CTL (0x6DD)
#define WCD9XXX_CLASSH_CTRL_VCL_2 (0x69B)
#define WCD9XXX_CDC_CLSH_HPH_V_PA (0xC04)
#define WCD9XXX_CDC_RX0_RX_PATH_SEC0 (0xB49)
#define WCD9XXX_CDC_RX1_RX_PATH_CTL (0xB55)
#define WCD9XXX_CDC_RX2_RX_PATH_CTL (0xB69)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL (0xD41)
#define WCD9XXX_CLASSH_CTRL_CCL_1 (0x69C)
#define WCD9XXX_CDC_RX1_RX_VOL_CTL (0xB59)
#define WCD9XXX_CDC_RX1_RX_VOL_MIX_CTL (0xB5C)
#define WCD9XXX_CDC_RX1_RX_PATH_SEC1 (0xB5E)
#define WCD9XXX_CDC_RX2_RX_VOL_CTL (0xB6D)
#define WCD9XXX_CDC_RX2_RX_VOL_MIX_CTL (0xB70)
#define WCD9XXX_CDC_RX2_RX_PATH_SEC1 (0xB72)
#define WCD9XXX_HPH_CNP_WG_CTL (0x06cc)
#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (0x06a8)
#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (0x0738)
#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (0x06bf)
#define WCD9XXX_HPH_PA_CTL1 (0x06d1)
#endif

39
sdm710/kernel-headers/linux/msm-core-interface.h
View File

@@ -1,39 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __MSM_CORE_LIB_H__
#define __MSM_CORE_LIB_H__
#include <linux/ioctl.h>
#define TEMP_DATA_POINTS 13
#define MAX_NUM_FREQ 200
enum msm_core_ioctl_params {
MSM_CORE_LEAKAGE,
MSM_CORE_VOLTAGE,
};
#define MSM_CORE_MAGIC 0x9D
struct sched_params {
uint32_t cpumask;
uint32_t cluster;
uint32_t power[TEMP_DATA_POINTS][MAX_NUM_FREQ];
uint32_t voltage[MAX_NUM_FREQ];
uint32_t freq[MAX_NUM_FREQ];
};
#define EA_LEAKAGE _IOWR(MSM_CORE_MAGIC, MSM_CORE_LEAKAGE, struct sched_params)
#define EA_VOLT _IOWR(MSM_CORE_MAGIC, MSM_CORE_VOLTAGE, struct sched_params)
#endif

49
sdm710/kernel-headers/linux/msm_adsp.h
View File

@@ -1,49 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _LINUX_MSM_ADSP_H
#define _LINUX_MSM_ADSP_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define ADSP_IOCTL_MAGIC 'q'
struct adsp_command_t {
uint16_t queue;
uint32_t len;
uint8_t * data;
};
struct adsp_event_t {
uint16_t type;
uint32_t timeout_ms;
uint16_t msg_id;
uint16_t flags;
uint32_t len;
uint8_t * data;
};
#define ADSP_IOCTL_ENABLE _IOR(ADSP_IOCTL_MAGIC, 1, unsigned)
#define ADSP_IOCTL_DISABLE _IOR(ADSP_IOCTL_MAGIC, 2, unsigned)
#define ADSP_IOCTL_DISABLE_ACK _IOR(ADSP_IOCTL_MAGIC, 3, unsigned)
#define ADSP_IOCTL_WRITE_COMMAND _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *)
#define ADSP_IOCTL_GET_EVENT _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *)
#define ADSP_IOCTL_SET_CLKRATE _IOR(ADSP_IOCTL_MAGIC, 6, unsigned)
#define ADSP_IOCTL_DISABLE_EVENT_RSP _IOR(ADSP_IOCTL_MAGIC, 10, unsigned)
#define ADSP_IOCTL_REGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 13, unsigned)
#define ADSP_IOCTL_UNREGISTER_PMEM _IOW(ADSP_IOCTL_MAGIC, 14, unsigned)
#define ADSP_IOCTL_ABORT_EVENT_READ _IOW(ADSP_IOCTL_MAGIC, 15, unsigned)
#define ADSP_IOCTL_LINK_TASK _IOW(ADSP_IOCTL_MAGIC, 16, unsigned)
#endif

353
sdm710/kernel-headers/linux/msm_audio.h
View File

@@ -1,353 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _LINUX_MSM_AUDIO_H
#define _LINUX_MSM_AUDIO_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define AUDIO_IOCTL_MAGIC 'a'
#define AUDIO_START _IOW(AUDIO_IOCTL_MAGIC, 0, unsigned int)
#define AUDIO_STOP _IOW(AUDIO_IOCTL_MAGIC, 1, unsigned int)
#define AUDIO_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 2, unsigned int)
#define AUDIO_GET_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 3, struct msm_audio_config)
#define AUDIO_SET_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 4, struct msm_audio_config)
#define AUDIO_GET_STATS _IOR(AUDIO_IOCTL_MAGIC, 5, struct msm_audio_stats)
#define AUDIO_ENABLE_AUDPP _IOW(AUDIO_IOCTL_MAGIC, 6, unsigned int)
#define AUDIO_SET_ADRC _IOW(AUDIO_IOCTL_MAGIC, 7, unsigned int)
#define AUDIO_SET_EQ _IOW(AUDIO_IOCTL_MAGIC, 8, unsigned int)
#define AUDIO_SET_RX_IIR _IOW(AUDIO_IOCTL_MAGIC, 9, unsigned int)
#define AUDIO_SET_VOLUME _IOW(AUDIO_IOCTL_MAGIC, 10, unsigned int)
#define AUDIO_PAUSE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned int)
#define AUDIO_PLAY_DTMF _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned int)
#define AUDIO_GET_EVENT _IOR(AUDIO_IOCTL_MAGIC, 13, struct msm_audio_event)
#define AUDIO_ABORT_GET_EVENT _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned int)
#define AUDIO_REGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 15, unsigned int)
#define AUDIO_DEREGISTER_PMEM _IOW(AUDIO_IOCTL_MAGIC, 16, unsigned int)
#define AUDIO_ASYNC_WRITE _IOW(AUDIO_IOCTL_MAGIC, 17, struct msm_audio_aio_buf)
#define AUDIO_ASYNC_READ _IOW(AUDIO_IOCTL_MAGIC, 18, struct msm_audio_aio_buf)
#define AUDIO_SET_INCALL _IOW(AUDIO_IOCTL_MAGIC, 19, struct msm_voicerec_mode)
#define AUDIO_GET_NUM_SND_DEVICE _IOR(AUDIO_IOCTL_MAGIC, 20, unsigned int)
#define AUDIO_GET_SND_DEVICES _IOWR(AUDIO_IOCTL_MAGIC, 21, struct msm_snd_device_list)
#define AUDIO_ENABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 22, unsigned int)
#define AUDIO_DISABLE_SND_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 23, unsigned int)
#define AUDIO_ROUTE_STREAM _IOW(AUDIO_IOCTL_MAGIC, 24, struct msm_audio_route_config)
#define AUDIO_GET_PCM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 30, unsigned int)
#define AUDIO_SET_PCM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 31, unsigned int)
#define AUDIO_SWITCH_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 32, unsigned int)
#define AUDIO_SET_MUTE _IOW(AUDIO_IOCTL_MAGIC, 33, unsigned int)
#define AUDIO_UPDATE_ACDB _IOW(AUDIO_IOCTL_MAGIC, 34, unsigned int)
#define AUDIO_START_VOICE _IOW(AUDIO_IOCTL_MAGIC, 35, unsigned int)
#define AUDIO_STOP_VOICE _IOW(AUDIO_IOCTL_MAGIC, 36, unsigned int)
#define AUDIO_REINIT_ACDB _IOW(AUDIO_IOCTL_MAGIC, 39, unsigned int)
#define AUDIO_OUTPORT_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 40, unsigned short)
#define AUDIO_SET_ERR_THRESHOLD_VALUE _IOW(AUDIO_IOCTL_MAGIC, 41, unsigned short)
#define AUDIO_GET_BITSTREAM_ERROR_INFO _IOR(AUDIO_IOCTL_MAGIC, 42, struct msm_audio_bitstream_error_info)
#define AUDIO_SET_SRS_TRUMEDIA_PARAM _IOW(AUDIO_IOCTL_MAGIC, 43, unsigned int)
#define AUDIO_SET_STREAM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 80, struct msm_audio_stream_config)
#define AUDIO_GET_STREAM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 81, struct msm_audio_stream_config)
#define AUDIO_GET_SESSION_ID _IOR(AUDIO_IOCTL_MAGIC, 82, unsigned short)
#define AUDIO_GET_STREAM_INFO _IOR(AUDIO_IOCTL_MAGIC, 83, struct msm_audio_bitstream_info)
#define AUDIO_SET_PAN _IOW(AUDIO_IOCTL_MAGIC, 84, unsigned int)
#define AUDIO_SET_QCONCERT_PLUS _IOW(AUDIO_IOCTL_MAGIC, 85, unsigned int)
#define AUDIO_SET_MBADRC _IOW(AUDIO_IOCTL_MAGIC, 86, unsigned int)
#define AUDIO_SET_VOLUME_PATH _IOW(AUDIO_IOCTL_MAGIC, 87, struct msm_vol_info)
#define AUDIO_SET_MAX_VOL_ALL _IOW(AUDIO_IOCTL_MAGIC, 88, unsigned int)
#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 89, unsigned int)
#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 90, unsigned int)
#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 91, unsigned int)
#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 92, unsigned int)
#define AUDIO_GET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 93, struct msm_audio_buf_cfg)
#define AUDIO_SET_BUF_CFG _IOW(AUDIO_IOCTL_MAGIC, 94, struct msm_audio_buf_cfg)
#define AUDIO_SET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 95, struct msm_acdb_cmd_device)
#define AUDIO_GET_ACDB_BLK _IOW(AUDIO_IOCTL_MAGIC, 96, struct msm_acdb_cmd_device)
#define AUDIO_REGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 97, struct msm_audio_ion_info)
#define AUDIO_DEREGISTER_ION _IOW(AUDIO_IOCTL_MAGIC, 98, struct msm_audio_ion_info)
#define AUDIO_SET_EFFECTS_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 99, struct msm_hwacc_effects_config)
#define AUDIO_EFFECTS_SET_BUF_LEN _IOW(AUDIO_IOCTL_MAGIC, 100, struct msm_hwacc_buf_cfg)
#define AUDIO_EFFECTS_GET_BUF_AVAIL _IOW(AUDIO_IOCTL_MAGIC, 101, struct msm_hwacc_buf_avail)
#define AUDIO_EFFECTS_WRITE _IOW(AUDIO_IOCTL_MAGIC, 102, void *)
#define AUDIO_EFFECTS_READ _IOWR(AUDIO_IOCTL_MAGIC, 103, void *)
#define AUDIO_EFFECTS_SET_PP_PARAMS _IOW(AUDIO_IOCTL_MAGIC, 104, void *)
#define AUDIO_PM_AWAKE _IOW(AUDIO_IOCTL_MAGIC, 105, unsigned int)
#define AUDIO_PM_RELAX _IOW(AUDIO_IOCTL_MAGIC, 106, unsigned int)
#define AUDIO_MAX_COMMON_IOCTL_NUM 107
#define HANDSET_MIC 0x01
#define HANDSET_SPKR 0x02
#define HEADSET_MIC 0x03
#define HEADSET_SPKR_MONO 0x04
#define HEADSET_SPKR_STEREO 0x05
#define SPKR_PHONE_MIC 0x06
#define SPKR_PHONE_MONO 0x07
#define SPKR_PHONE_STEREO 0x08
#define BT_SCO_MIC 0x09
#define BT_SCO_SPKR 0x0A
#define BT_A2DP_SPKR 0x0B
#define TTY_HEADSET_MIC 0x0C
#define TTY_HEADSET_SPKR 0x0D
#define DEFAULT_TX 0x0E
#define DEFAULT_RX 0x0F
#define BT_A2DP_TX 0x10
#define HEADSET_MONO_PLUS_SPKR_MONO_RX 0x11
#define HEADSET_MONO_PLUS_SPKR_STEREO_RX 0x12
#define HEADSET_STEREO_PLUS_SPKR_MONO_RX 0x13
#define HEADSET_STEREO_PLUS_SPKR_STEREO_RX 0x14
#define I2S_RX 0x20
#define I2S_TX 0x21
#define ADRC_ENABLE 0x0001
#define EQUALIZER_ENABLE 0x0002
#define IIR_ENABLE 0x0004
#define QCONCERT_PLUS_ENABLE 0x0008
#define MBADRC_ENABLE 0x0010
#define SRS_ENABLE 0x0020
#define SRS_DISABLE 0x0040
#define AGC_ENABLE 0x0001
#define NS_ENABLE 0x0002
#define TX_IIR_ENABLE 0x0004
#define FLUENCE_ENABLE 0x0008
#define VOC_REC_UPLINK 0x00
#define VOC_REC_DOWNLINK 0x01
#define VOC_REC_BOTH 0x02
struct msm_audio_config {
uint32_t buffer_size;
uint32_t buffer_count;
uint32_t channel_count;
uint32_t sample_rate;
uint32_t type;
uint32_t meta_field;
uint32_t bits;
uint32_t unused[3];
};
struct msm_audio_stream_config {
uint32_t buffer_size;
uint32_t buffer_count;
};
struct msm_audio_buf_cfg {
uint32_t meta_info_enable;
uint32_t frames_per_buf;
};
struct msm_audio_stats {
uint32_t byte_count;
uint32_t sample_count;
uint32_t unused[2];
};
struct msm_audio_ion_info {
int fd;
void * vaddr;
};
struct msm_audio_pmem_info {
int fd;
void * vaddr;
};
struct msm_audio_aio_buf {
void * buf_addr;
uint32_t buf_len;
uint32_t data_len;
void * private_data;
unsigned short mfield_sz;
};
#define SND_IOCTL_MAGIC 's'
#define SND_MUTE_UNMUTED 0
#define SND_MUTE_MUTED 1
struct msm_mute_info {
uint32_t mute;
uint32_t path;
};
struct msm_vol_info {
uint32_t vol;
uint32_t path;
};
struct msm_voicerec_mode {
uint32_t rec_mode;
};
struct msm_snd_device_config {
uint32_t device;
uint32_t ear_mute;
uint32_t mic_mute;
};
#define SND_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_device_config *)
enum cad_device_path_type {
CAD_DEVICE_PATH_RX,
CAD_DEVICE_PATH_TX,
CAD_DEVICE_PATH_RX_TX,
CAD_DEVICE_PATH_LB,
CAD_DEVICE_PATH_MAX
};
struct cad_devices_type {
uint32_t rx_device;
uint32_t tx_device;
enum cad_device_path_type pathtype;
};
struct msm_cad_device_config {
struct cad_devices_type device;
uint32_t ear_mute;
uint32_t mic_mute;
};
#define CAD_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_cad_device_config *)
#define SND_METHOD_VOICE 0
#define SND_METHOD_MIDI 4
struct msm_snd_volume_config {
uint32_t device;
uint32_t method;
uint32_t volume;
};
#define SND_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_snd_volume_config *)
struct msm_cad_volume_config {
struct cad_devices_type device;
uint32_t method;
uint32_t volume;
};
#define CAD_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_cad_volume_config *)
#define SND_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned int *)
struct msm_snd_endpoint {
int id;
char name[64];
};
#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *)
#define SND_AVC_CTL _IOW(SND_IOCTL_MAGIC, 6, unsigned int *)
#define SND_AGC_CTL _IOW(SND_IOCTL_MAGIC, 7, unsigned int *)
#define CAD_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned int *)
struct msm_cad_endpoint {
int id;
char name[64];
};
#define CAD_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_cad_endpoint *)
struct msm_audio_pcm_config {
uint32_t pcm_feedback;
uint32_t buffer_count;
uint32_t buffer_size;
};
#define AUDIO_EVENT_SUSPEND 0
#define AUDIO_EVENT_RESUME 1
#define AUDIO_EVENT_WRITE_DONE 2
#define AUDIO_EVENT_READ_DONE 3
#define AUDIO_EVENT_STREAM_INFO 4
#define AUDIO_EVENT_BITSTREAM_ERROR_INFO 5
#define AUDIO_CODEC_TYPE_MP3 0
#define AUDIO_CODEC_TYPE_AAC 1
struct msm_audio_bitstream_info {
uint32_t codec_type;
uint32_t chan_info;
uint32_t sample_rate;
uint32_t bit_stream_info;
uint32_t bit_rate;
uint32_t unused[3];
};
struct msm_audio_bitstream_error_info {
uint32_t dec_id;
uint32_t err_msg_indicator;
uint32_t err_type;
};
union msm_audio_event_payload {
struct msm_audio_aio_buf aio_buf;
struct msm_audio_bitstream_info stream_info;
struct msm_audio_bitstream_error_info error_info;
int reserved;
};
struct msm_audio_event {
int event_type;
int timeout_ms;
union msm_audio_event_payload event_payload;
};
#define MSM_SNDDEV_CAP_RX 0x1
#define MSM_SNDDEV_CAP_TX 0x2
#define MSM_SNDDEV_CAP_VOICE 0x4
struct msm_snd_device_info {
uint32_t dev_id;
uint32_t dev_cap;
char dev_name[64];
};
struct msm_snd_device_list {
uint32_t num_dev;
struct msm_snd_device_info * list;
};
struct msm_dtmf_config {
uint16_t path;
uint16_t dtmf_hi;
uint16_t dtmf_low;
uint16_t duration;
uint16_t tx_gain;
uint16_t rx_gain;
uint16_t mixing;
};
#define AUDIO_ROUTE_STREAM_VOICE_RX 0
#define AUDIO_ROUTE_STREAM_VOICE_TX 1
#define AUDIO_ROUTE_STREAM_PLAYBACK 2
#define AUDIO_ROUTE_STREAM_REC 3
struct msm_audio_route_config {
uint32_t stream_type;
uint32_t stream_id;
uint32_t dev_id;
};
#define AUDIO_MAX_EQ_BANDS 12
struct msm_audio_eq_band {
uint16_t band_idx;
uint32_t filter_type;
uint32_t center_freq_hz;
uint32_t filter_gain;
uint32_t q_factor;
} __attribute__((packed));
struct msm_audio_eq_stream_config {
uint32_t enable;
uint32_t num_bands;
struct msm_audio_eq_band eq_bands[AUDIO_MAX_EQ_BANDS];
} __attribute__((packed));
struct msm_acdb_cmd_device {
uint32_t command_id;
uint32_t device_id;
uint32_t network_id;
uint32_t sample_rate_id;
uint32_t interface_id;
uint32_t algorithm_block_id;
uint32_t total_bytes;
uint32_t * phys_buf;
};
struct msm_hwacc_data_config {
__u32 buf_size;
__u32 num_buf;
__u32 num_channels;
__u8 channel_map[8];
__u32 sample_rate;
__u32 bits_per_sample;
};
struct msm_hwacc_buf_cfg {
__u32 input_len;
__u32 output_len;
};
struct msm_hwacc_buf_avail {
__u32 input_num_avail;
__u32 output_num_avail;
};
struct msm_hwacc_effects_config {
struct msm_hwacc_data_config input;
struct msm_hwacc_data_config output;
struct msm_hwacc_buf_cfg buf_cfg;
__u32 meta_mode_enabled;
__u32 overwrite_topology;
__s32 topology;
};
#define ADSP_STREAM_PP_EVENT 0
#define ADSP_STREAM_ENCDEC_EVENT 1
#define ADSP_STREAM_IEC_61937_FMT_UPDATE_EVENT 2
#define ADSP_STREAM_EVENT_MAX 3
struct msm_adsp_event_data {
__u32 event_type;
__u32 payload_len;
__u8 payload[0];
};
#endif

76
sdm710/kernel-headers/linux/msm_audio_aac.h
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@@ -1,76 +0,0 @@
#ifndef _MSM_AUDIO_AAC_H
#define _MSM_AUDIO_AAC_H
#include <linux/msm_audio.h>
#define AUDIO_SET_AAC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_aac_config)
#define AUDIO_GET_AAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_aac_config)
#define AUDIO_SET_AAC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_aac_enc_config)
#define AUDIO_GET_AAC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+4), struct msm_audio_aac_enc_config)
#define AUDIO_SET_AAC_MIX_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+5), uint32_t)
#define AUDIO_AAC_FORMAT_ADTS -1
#define AUDIO_AAC_FORMAT_RAW 0x0000
#define AUDIO_AAC_FORMAT_PSUEDO_RAW 0x0001
#define AUDIO_AAC_FORMAT_LOAS 0x0002
#define AUDIO_AAC_FORMAT_ADIF 0x0003
#define AUDIO_AAC_OBJECT_LC 0x0002
#define AUDIO_AAC_OBJECT_LTP 0x0004
#define AUDIO_AAC_OBJECT_ERLC 0x0011
#define AUDIO_AAC_OBJECT_BSAC 0x0016
#define AUDIO_AAC_SEC_DATA_RES_ON 0x0001
#define AUDIO_AAC_SEC_DATA_RES_OFF 0x0000
#define AUDIO_AAC_SCA_DATA_RES_ON 0x0001
#define AUDIO_AAC_SCA_DATA_RES_OFF 0x0000
#define AUDIO_AAC_SPEC_DATA_RES_ON 0x0001
#define AUDIO_AAC_SPEC_DATA_RES_OFF 0x0000
#define AUDIO_AAC_SBR_ON_FLAG_ON 0x0001
#define AUDIO_AAC_SBR_ON_FLAG_OFF 0x0000
#define AUDIO_AAC_SBR_PS_ON_FLAG_ON 0x0001
#define AUDIO_AAC_SBR_PS_ON_FLAG_OFF 0x0000
/* Primary channel on both left and right channels */
#define AUDIO_AAC_DUAL_MONO_PL_PR 0
/* Secondary channel on both left and right channels */
#define AUDIO_AAC_DUAL_MONO_SL_SR 1
/* Primary channel on right channel and 2nd on left channel */
#define AUDIO_AAC_DUAL_MONO_SL_PR 2
/* 2nd channel on right channel and primary on left channel */
#define AUDIO_AAC_DUAL_MONO_PL_SR 3
struct msm_audio_aac_config {
signed short format;
unsigned short audio_object;
unsigned short ep_config; /* 0 ~ 3 useful only obj = ERLC */
unsigned short aac_section_data_resilience_flag;
unsigned short aac_scalefactor_data_resilience_flag;
unsigned short aac_spectral_data_resilience_flag;
unsigned short sbr_on_flag;
unsigned short sbr_ps_on_flag;
unsigned short dual_mono_mode;
unsigned short channel_configuration;
unsigned short sample_rate;
};
struct msm_audio_aac_enc_config {
uint32_t channels;
uint32_t sample_rate;
uint32_t bit_rate;
uint32_t stream_format;
};
#endif /* _MSM_AUDIO_AAC_H */

41
sdm710/kernel-headers/linux/msm_audio_ac3.h
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@@ -1,41 +0,0 @@
#ifndef _MSM_AUDIO_AC3_H
#define _MSM_AUDIO_AC3_H
#include <linux/msm_audio.h>
#define AUDIO_SET_AC3_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int)
#define AUDIO_GET_AC3_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int)
#define AUDAC3_DEF_WORDSIZE 0
#define AUDAC3_DEF_USER_DOWNMIX_FLAG 0x0
#define AUDAC3_DEF_USER_KARAOKE_FLAG 0x0
#define AUDAC3_DEF_ERROR_CONCEALMENT 0
#define AUDAC3_DEF_MAX_REPEAT_COUNT 0
struct msm_audio_ac3_config {
unsigned short numChans;
unsigned short wordSize;
unsigned short kCapableMode;
unsigned short compMode;
unsigned short outLfeOn;
unsigned short outputMode;
unsigned short stereoMode;
unsigned short dualMonoMode;
unsigned short fsCod;
unsigned short pcmScaleFac;
unsigned short dynRngScaleHi;
unsigned short dynRngScaleLow;
unsigned short user_downmix_flag;
unsigned short user_karaoke_flag;
unsigned short dm_address_high;
unsigned short dm_address_low;
unsigned short ko_address_high;
unsigned short ko_address_low;
unsigned short error_concealment;
unsigned short max_rep_count;
unsigned short channel_routing_mode[6];
};
#endif /* _MSM_AUDIO_AC3_H */

24
sdm710/kernel-headers/linux/msm_audio_alac.h
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@@ -1,24 +0,0 @@
#ifndef _MSM_AUDIO_ALAC_H
#define _MSM_AUDIO_ALAC_H
#define AUDIO_GET_ALAC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_alac_config)
#define AUDIO_SET_ALAC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_alac_config)
struct msm_audio_alac_config {
uint32_t frameLength;
uint8_t compatVersion;
uint8_t bitDepth;
uint8_t pb; /* currently unused */
uint8_t mb; /* currently unused */
uint8_t kb; /* currently unused */
uint8_t channelCount;
uint16_t maxRun; /* currently unused */
uint32_t maxSize;
uint32_t averageBitRate;
uint32_t sampleRate;
uint32_t channelLayout;
};
#endif /* _MSM_AUDIO_ALAC_H */

34
sdm710/kernel-headers/linux/msm_audio_amrnb.h
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@@ -1,34 +0,0 @@
#ifndef _MSM_AUDIO_AMRNB_H
#define _MSM_AUDIO_AMRNB_H
#include <linux/msm_audio.h>
#define AUDIO_GET_AMRNB_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int)
#define AUDIO_SET_AMRNB_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int)
#define AUDIO_GET_AMRNB_ENC_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+2), \
struct msm_audio_amrnb_enc_config_v2)
#define AUDIO_SET_AMRNB_ENC_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+3), \
struct msm_audio_amrnb_enc_config_v2)
struct msm_audio_amrnb_enc_config {
unsigned short voicememoencweight1;
unsigned short voicememoencweight2;
unsigned short voicememoencweight3;
unsigned short voicememoencweight4;
unsigned short dtx_mode_enable; /* 0xFFFF - enable, 0- disable */
unsigned short test_mode_enable; /* 0xFFFF - enable, 0- disable */
unsigned short enc_mode; /* 0-MR475,1-MR515,2-MR59,3-MR67,4-MR74
* 5-MR795, 6- MR102, 7- MR122(default)
*/
};
struct msm_audio_amrnb_enc_config_v2 {
uint32_t band_mode;
uint32_t dtx_enable;
uint32_t frame_format;
};
#endif /* _MSM_AUDIO_AMRNB_H */

18
sdm710/kernel-headers/linux/msm_audio_amrwb.h
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@@ -1,18 +0,0 @@
#ifndef _MSM_AUDIO_AMRWB_H
#define _MSM_AUDIO_AMRWB_H
#include <linux/msm_audio.h>
#define AUDIO_GET_AMRWB_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), \
struct msm_audio_amrwb_enc_config)
#define AUDIO_SET_AMRWB_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), \
struct msm_audio_amrwb_enc_config)
struct msm_audio_amrwb_enc_config {
uint32_t band_mode;
uint32_t dtx_enable;
uint32_t frame_format;
};
#endif /* _MSM_AUDIO_AMRWB_H */

18
sdm710/kernel-headers/linux/msm_audio_amrwbplus.h
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@@ -1,18 +0,0 @@
#ifndef _MSM_AUDIO_AMR_WB_PLUS_H
#define _MSM_AUDIO_AMR_WB_PLUS_H
#define AUDIO_GET_AMRWBPLUS_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_amrwbplus_config_v2)
#define AUDIO_SET_AMRWBPLUS_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_amrwbplus_config_v2)
struct msm_audio_amrwbplus_config_v2 {
unsigned int size_bytes;
unsigned int version;
unsigned int num_channels;
unsigned int amr_band_mode;
unsigned int amr_dtx_mode;
unsigned int amr_frame_fmt;
unsigned int amr_lsf_idx;
};
#endif /* _MSM_AUDIO_AMR_WB_PLUS_H */

26
sdm710/kernel-headers/linux/msm_audio_ape.h
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@@ -1,26 +0,0 @@
/* The following structure has been taken
* from Monkey's Audio SDK with permission
*/
#ifndef _MSM_AUDIO_APE_H
#define _MSM_AUDIO_APE_H
#define AUDIO_GET_APE_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_ape_config)
#define AUDIO_SET_APE_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_ape_config)
struct msm_audio_ape_config {
uint16_t compatibleVersion;
uint16_t compressionLevel;
uint32_t formatFlags;
uint32_t blocksPerFrame;
uint32_t finalFrameBlocks;
uint32_t totalFrames;
uint16_t bitsPerSample;
uint16_t numChannels;
uint32_t sampleRate;
uint32_t seekTablePresent;
};
#endif /* _MSM_AUDIO_APE_H */

742
sdm710/kernel-headers/linux/msm_audio_calibration.h
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@@ -1,742 +0,0 @@
#ifndef _MSM_AUDIO_CALIBRATION_H
#define _MSM_AUDIO_CALIBRATION_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define CAL_IOCTL_MAGIC 'a'
#define AUDIO_ALLOCATE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
200, void *)
#define AUDIO_DEALLOCATE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
201, void *)
#define AUDIO_PREPARE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
202, void *)
#define AUDIO_SET_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
203, void *)
#define AUDIO_GET_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
204, void *)
#define AUDIO_POST_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
205, void *)
/* For Real-Time Audio Calibration */
#define AUDIO_GET_RTAC_ADM_INFO _IOR(CAL_IOCTL_MAGIC, \
207, void *)
#define AUDIO_GET_RTAC_VOICE_INFO _IOR(CAL_IOCTL_MAGIC, \
208, void *)
#define AUDIO_GET_RTAC_ADM_CAL _IOWR(CAL_IOCTL_MAGIC, \
209, void *)
#define AUDIO_SET_RTAC_ADM_CAL _IOWR(CAL_IOCTL_MAGIC, \
210, void *)
#define AUDIO_GET_RTAC_ASM_CAL _IOWR(CAL_IOCTL_MAGIC, \
211, void *)
#define AUDIO_SET_RTAC_ASM_CAL _IOWR(CAL_IOCTL_MAGIC, \
212, void *)
#define AUDIO_GET_RTAC_CVS_CAL _IOWR(CAL_IOCTL_MAGIC, \
213, void *)
#define AUDIO_SET_RTAC_CVS_CAL _IOWR(CAL_IOCTL_MAGIC, \
214, void *)
#define AUDIO_GET_RTAC_CVP_CAL _IOWR(CAL_IOCTL_MAGIC, \
215, void *)
#define AUDIO_SET_RTAC_CVP_CAL _IOWR(CAL_IOCTL_MAGIC, \
216, void *)
#define AUDIO_GET_RTAC_AFE_CAL _IOWR(CAL_IOCTL_MAGIC, \
217, void *)
#define AUDIO_SET_RTAC_AFE_CAL _IOWR(CAL_IOCTL_MAGIC, \
218, void *)
enum {
CVP_VOC_RX_TOPOLOGY_CAL_TYPE = 0,
CVP_VOC_TX_TOPOLOGY_CAL_TYPE,
CVP_VOCPROC_STATIC_CAL_TYPE,
CVP_VOCPROC_DYNAMIC_CAL_TYPE,
CVS_VOCSTRM_STATIC_CAL_TYPE,
CVP_VOCDEV_CFG_CAL_TYPE,
CVP_VOCPROC_STATIC_COL_CAL_TYPE,
CVP_VOCPROC_DYNAMIC_COL_CAL_TYPE,
CVS_VOCSTRM_STATIC_COL_CAL_TYPE,
ADM_TOPOLOGY_CAL_TYPE,
ADM_CUST_TOPOLOGY_CAL_TYPE,
ADM_AUDPROC_CAL_TYPE,
ADM_AUDVOL_CAL_TYPE,
ASM_TOPOLOGY_CAL_TYPE,
ASM_CUST_TOPOLOGY_CAL_TYPE,
ASM_AUDSTRM_CAL_TYPE,
AFE_COMMON_RX_CAL_TYPE,
AFE_COMMON_TX_CAL_TYPE,
AFE_ANC_CAL_TYPE,
AFE_AANC_CAL_TYPE,
AFE_FB_SPKR_PROT_CAL_TYPE,
AFE_HW_DELAY_CAL_TYPE,
AFE_SIDETONE_CAL_TYPE,
AFE_TOPOLOGY_CAL_TYPE,
AFE_CUST_TOPOLOGY_CAL_TYPE,
LSM_CUST_TOPOLOGY_CAL_TYPE,
LSM_TOPOLOGY_CAL_TYPE,
LSM_CAL_TYPE,
ADM_RTAC_INFO_CAL_TYPE,
VOICE_RTAC_INFO_CAL_TYPE,
ADM_RTAC_APR_CAL_TYPE,
ASM_RTAC_APR_CAL_TYPE,
VOICE_RTAC_APR_CAL_TYPE,
MAD_CAL_TYPE,
ULP_AFE_CAL_TYPE,
ULP_LSM_CAL_TYPE,
DTS_EAGLE_CAL_TYPE,
AUDIO_CORE_METAINFO_CAL_TYPE,
SRS_TRUMEDIA_CAL_TYPE,
CORE_CUSTOM_TOPOLOGIES_CAL_TYPE,
ADM_RTAC_AUDVOL_CAL_TYPE,
ULP_LSM_TOPOLOGY_ID_CAL_TYPE,
AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE,
AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE,
AFE_SIDETONE_IIR_CAL_TYPE,
AFE_LSM_TOPOLOGY_CAL_TYPE,
AFE_LSM_TX_CAL_TYPE,
ADM_LSM_TOPOLOGY_CAL_TYPE,
ADM_LSM_AUDPROC_CAL_TYPE,
MAX_CAL_TYPES,
};
#define AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE
#define AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE
#define AFE_SIDETONE_IIR_CAL_TYPE AFE_SIDETONE_IIR_CAL_TYPE
#define AFE_LSM_TOPOLOGY_CAL_TYPE AFE_LSM_TOPOLOGY_CAL_TYPE
#define AFE_LSM_TX_CAL_TYPE AFE_LSM_TX_CAL_TYPE
#define ADM_LSM_TOPOLOGY_CAL_TYPE ADM_LSM_TOPOLOGY_CAL_TYPE
#define ADM_LSM_AUDPROC_CAL_TYPE ADM_LSM_AUDPROC_CAL_TYPE
#define LSM_CAL_TYPES
#define TOPOLOGY_SPECIFIC_CHANNEL_INFO
#define MSM_SPKR_PROT_SPV3
enum {
VERSION_0_0,
};
enum {
PER_VOCODER_CAL_BIT_MASK = 0x10000,
};
#define MAX_IOCTL_CMD_SIZE 512
/* common structures */
struct audio_cal_header {
int32_t data_size;
int32_t version;
int32_t cal_type;
int32_t cal_type_size;
};
struct audio_cal_type_header {
int32_t version;
int32_t buffer_number;
};
struct audio_cal_data {
/* Size of cal data at mem_handle allocation or at vaddr */
int32_t cal_size;
/* If mem_handle if shared memory is used*/
int32_t mem_handle;
/* size of virtual memory if shared memory not used */
};
/* AUDIO_ALLOCATE_CALIBRATION */
struct audio_cal_type_alloc {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
};
struct audio_cal_alloc {
struct audio_cal_header hdr;
struct audio_cal_type_alloc cal_type;
};
/* AUDIO_DEALLOCATE_CALIBRATION */
struct audio_cal_type_dealloc {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
};
struct audio_cal_dealloc {
struct audio_cal_header hdr;
struct audio_cal_type_dealloc cal_type;
};
/* AUDIO_PREPARE_CALIBRATION */
struct audio_cal_type_prepare {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
};
struct audio_cal_prepare {
struct audio_cal_header hdr;
struct audio_cal_type_prepare cal_type;
};
/* AUDIO_POST_CALIBRATION */
struct audio_cal_type_post {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
};
struct audio_cal_post {
struct audio_cal_header hdr;
struct audio_cal_type_post cal_type;
};
/*AUDIO_CORE_META_INFO */
struct audio_cal_info_metainfo {
uint32_t nKey;
};
/* Cal info types */
enum {
RX_DEVICE,
TX_DEVICE,
MAX_PATH_TYPE
};
struct audio_cal_info_adm_top {
int32_t topology;
int32_t acdb_id;
/* RX_DEVICE or TX_DEVICE */
int32_t path;
int32_t app_type;
int32_t sample_rate;
};
struct audio_cal_info_audproc {
int32_t acdb_id;
/* RX_DEVICE or TX_DEVICE */
int32_t path;
int32_t app_type;
int32_t sample_rate;
};
struct audio_cal_info_audvol {
int32_t acdb_id;
/* RX_DEVICE or TX_DEVICE */
int32_t path;
int32_t app_type;
int32_t vol_index;
};
struct audio_cal_info_afe {
int32_t acdb_id;
/* RX_DEVICE or TX_DEVICE */
int32_t path;
int32_t sample_rate;
};
struct audio_cal_info_afe_top {
int32_t topology;
int32_t acdb_id;
/* RX_DEVICE or TX_DEVICE */
int32_t path;
int32_t sample_rate;
};
struct audio_cal_info_asm_top {
int32_t topology;
int32_t app_type;
};
struct audio_cal_info_audstrm {
int32_t app_type;
};
struct audio_cal_info_aanc {
int32_t acdb_id;
};
#define MAX_HW_DELAY_ENTRIES 25
struct audio_cal_hw_delay_entry {
uint32_t sample_rate;
uint32_t delay_usec;
};
struct audio_cal_hw_delay_data {
uint32_t num_entries;
struct audio_cal_hw_delay_entry entry[MAX_HW_DELAY_ENTRIES];
};
struct audio_cal_info_hw_delay {
int32_t acdb_id;
/* RX_DEVICE or TX_DEVICE */
int32_t path;
int32_t property_type;
struct audio_cal_hw_delay_data data;
};
enum msm_spkr_prot_states {
MSM_SPKR_PROT_CALIBRATED,
MSM_SPKR_PROT_CALIBRATION_IN_PROGRESS,
MSM_SPKR_PROT_DISABLED,
MSM_SPKR_PROT_NOT_CALIBRATED,
MSM_SPKR_PROT_PRE_CALIBRATED,
MSM_SPKR_PROT_IN_FTM_MODE
};
#define MSM_SPKR_PROT_IN_FTM_MODE MSM_SPKR_PROT_IN_FTM_MODE
enum msm_spkr_count {
SP_V2_SPKR_1,
SP_V2_SPKR_2,
SP_V2_NUM_MAX_SPKRS
};
struct audio_cal_info_spk_prot_cfg {
int32_t r0[SP_V2_NUM_MAX_SPKRS];
int32_t t0[SP_V2_NUM_MAX_SPKRS];
uint32_t quick_calib_flag;
uint32_t mode;
/*
* 0 - Start spk prot
* 1 - Start calib
* 2 - Disable spk prot
*/
#ifdef MSM_SPKR_PROT_SPV3
uint32_t sp_version;
int32_t limiter_th[SP_V2_NUM_MAX_SPKRS];
#endif
};
struct audio_cal_info_sp_th_vi_ftm_cfg {
uint32_t wait_time[SP_V2_NUM_MAX_SPKRS];
uint32_t ftm_time[SP_V2_NUM_MAX_SPKRS];
uint32_t mode;
/*
* 0 - normal running mode
* 1 - Calibration
* 2 - FTM mode
*/
};
struct audio_cal_info_sp_ex_vi_ftm_cfg {
uint32_t wait_time[SP_V2_NUM_MAX_SPKRS];
uint32_t ftm_time[SP_V2_NUM_MAX_SPKRS];
uint32_t mode;
/*
* 0 - normal running mode
* 2 - FTM mode
*/
};
struct audio_cal_info_sp_ex_vi_param {
int32_t freq_q20[SP_V2_NUM_MAX_SPKRS];
int32_t resis_q24[SP_V2_NUM_MAX_SPKRS];
int32_t qmct_q24[SP_V2_NUM_MAX_SPKRS];
int32_t status[SP_V2_NUM_MAX_SPKRS];
};
struct audio_cal_info_sp_th_vi_param {
int32_t r_dc_q24[SP_V2_NUM_MAX_SPKRS];
int32_t temp_q22[SP_V2_NUM_MAX_SPKRS];
int32_t status[SP_V2_NUM_MAX_SPKRS];
};
struct audio_cal_info_msm_spk_prot_status {
int32_t r0[SP_V2_NUM_MAX_SPKRS];
int32_t status;
};
struct audio_cal_info_sidetone {
uint16_t enable;
uint16_t gain;
int32_t tx_acdb_id;
int32_t rx_acdb_id;
int32_t mid;
int32_t pid;
};
#define MAX_SIDETONE_IIR_DATA_SIZE 224
#define MAX_NO_IIR_FILTER_STAGE 10
struct audio_cal_info_sidetone_iir {
uint16_t iir_enable;
uint16_t num_biquad_stages;
uint16_t pregain;
int32_t tx_acdb_id;
int32_t rx_acdb_id;
int32_t mid;
int32_t pid;
uint8_t iir_config[MAX_SIDETONE_IIR_DATA_SIZE];
};
struct audio_cal_info_lsm_top {
int32_t topology;
int32_t acdb_id;
int32_t app_type;
};
struct audio_cal_info_lsm {
int32_t acdb_id;
/* RX_DEVICE or TX_DEVICE */
int32_t path;
int32_t app_type;
};
#define VSS_NUM_CHANNELS_MAX 8
struct audio_cal_info_voc_top {
int32_t topology;
int32_t acdb_id;
#ifdef TOPOLOGY_SPECIFIC_CHANNEL_INFO
uint32_t num_channels;
uint8_t channel_mapping[VSS_NUM_CHANNELS_MAX];
#endif
};
struct audio_cal_info_vocproc {
int32_t tx_acdb_id;
int32_t rx_acdb_id;
int32_t tx_sample_rate;
int32_t rx_sample_rate;
};
enum {
DEFAULT_FEATURE_SET,
VOL_BOOST_FEATURE_SET,
};
struct audio_cal_info_vocvol {
int32_t tx_acdb_id;
int32_t rx_acdb_id;
/* DEFAULT_ or VOL_BOOST_FEATURE_SET */
int32_t feature_set;
};
struct audio_cal_info_vocdev_cfg {
int32_t tx_acdb_id;
int32_t rx_acdb_id;
};
#define MAX_VOICE_COLUMNS 20
union audio_cal_col_na {
uint8_t val8;
uint16_t val16;
uint32_t val32;
uint64_t val64;
} __attribute__((packed));
struct audio_cal_col {
uint32_t id;
uint32_t type;
union audio_cal_col_na na_value;
} __attribute__((packed));
struct audio_cal_col_data {
uint32_t num_columns;
struct audio_cal_col column[MAX_VOICE_COLUMNS];
} __attribute__((packed));
struct audio_cal_info_voc_col {
int32_t table_id;
int32_t tx_acdb_id;
int32_t rx_acdb_id;
struct audio_cal_col_data data;
};
/* AUDIO_SET_CALIBRATION & */
struct audio_cal_type_basic {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
};
struct audio_cal_basic {
struct audio_cal_header hdr;
struct audio_cal_type_basic cal_type;
};
struct audio_cal_type_adm_top {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_adm_top cal_info;
};
struct audio_cal_adm_top {
struct audio_cal_header hdr;
struct audio_cal_type_adm_top cal_type;
};
struct audio_cal_type_metainfo {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_metainfo cal_info;
};
struct audio_core_metainfo {
struct audio_cal_header hdr;
struct audio_cal_type_metainfo cal_type;
};
struct audio_cal_type_audproc {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_audproc cal_info;
};
struct audio_cal_audproc {
struct audio_cal_header hdr;
struct audio_cal_type_audproc cal_type;
};
struct audio_cal_type_audvol {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_audvol cal_info;
};
struct audio_cal_audvol {
struct audio_cal_header hdr;
struct audio_cal_type_audvol cal_type;
};
struct audio_cal_type_asm_top {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_asm_top cal_info;
};
struct audio_cal_asm_top {
struct audio_cal_header hdr;
struct audio_cal_type_asm_top cal_type;
};
struct audio_cal_type_audstrm {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_audstrm cal_info;
};
struct audio_cal_audstrm {
struct audio_cal_header hdr;
struct audio_cal_type_audstrm cal_type;
};
struct audio_cal_type_afe {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_afe cal_info;
};
struct audio_cal_afe {
struct audio_cal_header hdr;
struct audio_cal_type_afe cal_type;
};
struct audio_cal_type_afe_top {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_afe_top cal_info;
};
struct audio_cal_afe_top {
struct audio_cal_header hdr;
struct audio_cal_type_afe_top cal_type;
};
struct audio_cal_type_aanc {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_aanc cal_info;
};
struct audio_cal_aanc {
struct audio_cal_header hdr;
struct audio_cal_type_aanc cal_type;
};
struct audio_cal_type_fb_spk_prot_cfg {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_spk_prot_cfg cal_info;
};
struct audio_cal_fb_spk_prot_cfg {
struct audio_cal_header hdr;
struct audio_cal_type_fb_spk_prot_cfg cal_type;
};
struct audio_cal_type_sp_th_vi_ftm_cfg {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_th_vi_ftm_cfg cal_info;
};
struct audio_cal_sp_th_vi_ftm_cfg {
struct audio_cal_header hdr;
struct audio_cal_type_sp_th_vi_ftm_cfg cal_type;
};
struct audio_cal_type_sp_ex_vi_ftm_cfg {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_ex_vi_ftm_cfg cal_info;
};
struct audio_cal_sp_ex_vi_ftm_cfg {
struct audio_cal_header hdr;
struct audio_cal_type_sp_ex_vi_ftm_cfg cal_type;
};
struct audio_cal_type_hw_delay {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_hw_delay cal_info;
};
struct audio_cal_hw_delay {
struct audio_cal_header hdr;
struct audio_cal_type_hw_delay cal_type;
};
struct audio_cal_type_sidetone {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sidetone cal_info;
};
struct audio_cal_sidetone {
struct audio_cal_header hdr;
struct audio_cal_type_sidetone cal_type;
};
struct audio_cal_type_sidetone_iir {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sidetone_iir cal_info;
};
struct audio_cal_sidetone_iir {
struct audio_cal_header hdr;
struct audio_cal_type_sidetone_iir cal_type;
};
struct audio_cal_type_lsm_top {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_lsm_top cal_info;
};
struct audio_cal_lsm_top {
struct audio_cal_header hdr;
struct audio_cal_type_lsm_top cal_type;
};
struct audio_cal_type_lsm {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_lsm cal_info;
};
struct audio_cal_lsm {
struct audio_cal_header hdr;
struct audio_cal_type_lsm cal_type;
};
struct audio_cal_type_voc_top {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_voc_top cal_info;
};
struct audio_cal_voc_top {
struct audio_cal_header hdr;
struct audio_cal_type_voc_top cal_type;
};
struct audio_cal_type_vocproc {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_vocproc cal_info;
};
struct audio_cal_vocproc {
struct audio_cal_header hdr;
struct audio_cal_type_vocproc cal_type;
};
struct audio_cal_type_vocvol {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_vocvol cal_info;
};
struct audio_cal_vocvol {
struct audio_cal_header hdr;
struct audio_cal_type_vocvol cal_type;
};
struct audio_cal_type_vocdev_cfg {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_vocdev_cfg cal_info;
};
struct audio_cal_vocdev_cfg {
struct audio_cal_header hdr;
struct audio_cal_type_vocdev_cfg cal_type;
};
struct audio_cal_type_voc_col {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_voc_col cal_info;
};
struct audio_cal_voc_col {
struct audio_cal_header hdr;
struct audio_cal_type_voc_col cal_type;
};
/* AUDIO_GET_CALIBRATION */
struct audio_cal_type_fb_spk_prot_status {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_msm_spk_prot_status cal_info;
};
struct audio_cal_fb_spk_prot_status {
struct audio_cal_header hdr;
struct audio_cal_type_fb_spk_prot_status cal_type;
};
struct audio_cal_type_sp_th_vi_param {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_th_vi_param cal_info;
};
struct audio_cal_sp_th_vi_param {
struct audio_cal_header hdr;
struct audio_cal_type_sp_th_vi_param cal_type;
};
struct audio_cal_type_sp_ex_vi_param {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_ex_vi_param cal_info;
};
struct audio_cal_sp_ex_vi_param {
struct audio_cal_header hdr;
struct audio_cal_type_sp_ex_vi_param cal_type;
};
#endif /* _MSM_AUDIO_CALIBRATION_H */

17
sdm710/kernel-headers/linux/msm_audio_g711.h
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@@ -1,17 +0,0 @@
#ifndef _MSM_AUDIO_G711_H
#define _MSM_AUDIO_G711_H
#include <linux/msm_audio.h>
struct msm_audio_g711_enc_config {
uint32_t sample_rate;
};
#define AUDIO_SET_G711_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_g711_enc_config)
#define AUDIO_GET_G711_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_g711_enc_config)
#endif /* _MSM_AUDIO_G711_H */

16
sdm710/kernel-headers/linux/msm_audio_g711_dec.h
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@@ -1,16 +0,0 @@
#ifndef _MSM_AUDIO_G711_H
#define _MSM_AUDIO_G711_H
#include <linux/msm_audio.h>
struct msm_audio_g711_dec_config {
uint32_t sample_rate;
};
#define AUDIO_SET_G711_DEC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_g711_dec_config)
#define AUDIO_GET_G711_DEC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_g711_dec_config)
#endif /* _MSM_AUDIO_G711_H */

155
sdm710/kernel-headers/linux/msm_audio_mvs.h
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@@ -1,155 +0,0 @@
#ifndef _MSM_AUDIO_MVS_H
#define _MSM_AUDIO_MVS_H
#include <linux/msm_audio.h>
#define AUDIO_GET_MVS_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM + 0), unsigned int)
#define AUDIO_SET_MVS_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM + 1), unsigned int)
/* MVS modes */
#define MVS_MODE_IS733 0x1 /*QCELP 13K*/
#define MVS_MODE_IS127 0x2 /*EVRC-8k*/
#define MVS_MODE_4GV_NB 0x3 /*EVRC-B*/
#define MVS_MODE_4GV_WB 0x4 /*EVRC-WB*/
#define MVS_MODE_AMR 0x5
#define MVS_MODE_EFR 0x6
#define MVS_MODE_FR 0x7
#define MVS_MODE_HR 0x8
#define MVS_MODE_LINEAR_PCM 0x9
#define MVS_MODE_G711 0xA
#define MVS_MODE_PCM 0xC
#define MVS_MODE_AMR_WB 0xD
#define MVS_MODE_G729A 0xE
#define MVS_MODE_G711A 0xF
#define MVS_MODE_G722 0x10
#define MVS_MODE_PCM_WB 0x12
enum msm_audio_amr_mode {
MVS_AMR_MODE_0475, /* AMR 4.75 kbps */
MVS_AMR_MODE_0515, /* AMR 5.15 kbps */
MVS_AMR_MODE_0590, /* AMR 5.90 kbps */
MVS_AMR_MODE_0670, /* AMR 6.70 kbps */
MVS_AMR_MODE_0740, /* AMR 7.40 kbps */
MVS_AMR_MODE_0795, /* AMR 7.95 kbps */
MVS_AMR_MODE_1020, /* AMR 10.20 kbps */
MVS_AMR_MODE_1220, /* AMR 12.20 kbps */
MVS_AMR_MODE_0660, /* AMR-WB 6.60 kbps */
MVS_AMR_MODE_0885, /* AMR-WB 8.85 kbps */
MVS_AMR_MODE_1265, /* AMR-WB 12.65 kbps */
MVS_AMR_MODE_1425, /* AMR-WB 14.25 kbps */
MVS_AMR_MODE_1585, /* AMR-WB 15.85 kbps */
MVS_AMR_MODE_1825, /* AMR-WB 18.25 kbps */
MVS_AMR_MODE_1985, /* AMR-WB 19.85 kbps */
MVS_AMR_MODE_2305, /* AMR-WB 23.05 kbps */
MVS_AMR_MODE_2385, /* AMR-WB 23.85 kbps */
MVS_AMR_MODE_UNDEF
};
/* The MVS VOC rate type is used to identify the rate of QCELP 13K(IS733),
* EVRC(IS127), 4GV, or 4GV-WB frame.
*/
enum msm_audio_voc_rate {
MVS_VOC_0_RATE, /* Blank frame */
MVS_VOC_8_RATE, /* 1/8 rate */
MVS_VOC_4_RATE, /* 1/4 rate */
MVS_VOC_2_RATE, /* 1/2 rate */
MVS_VOC_1_RATE, /* Full rate */
MVS_VOC_ERASURE, /* erasure frame */
MVS_VOC_RATE_MAX,
MVS_VOC_RATE_UNDEF = MVS_VOC_RATE_MAX
};
enum msm_audio_amr_frame_type {
MVS_AMR_SPEECH_GOOD, /* Good speech frame */
MVS_AMR_SPEECH_DEGRADED, /* Speech degraded */
MVS_AMR_ONSET, /* Onset */
MVS_AMR_SPEECH_BAD, /* Corrupt speech frame (bad CRC) */
MVS_AMR_SID_FIRST, /* First silence descriptor */
MVS_AMR_SID_UPDATE, /* Comfort noise frame */
MVS_AMR_SID_BAD, /* Corrupt SID frame (bad CRC) */
MVS_AMR_NO_DATA, /* Nothing to transmit */
MVS_AMR_SPEECH_LOST /* Downlink speech lost */
};
enum msm_audio_g711a_mode {
MVS_G711A_MODE_MULAW,
MVS_G711A_MODE_ALAW
};
enum msm_audio_g711_mode {
MVS_G711_MODE_MULAW,
MVS_G711_MODE_ALAW
};
enum mvs_g722_mode_type {
MVS_G722_MODE_01,
MVS_G722_MODE_02,
MVS_G722_MODE_03,
MVS_G722_MODE_MAX,
MVS_G722_MODE_UNDEF
};
enum msm_audio_g711a_frame_type {
MVS_G711A_SPEECH_GOOD,
MVS_G711A_SID,
MVS_G711A_NO_DATA,
MVS_G711A_ERASURE
};
enum msm_audio_g729a_frame_type {
MVS_G729A_NO_DATA,
MVS_G729A_SPEECH_GOOD,
MVS_G729A_SID,
MVS_G729A_ERASURE
};
struct min_max_rate {
uint32_t min_rate;
uint32_t max_rate;
};
struct msm_audio_mvs_config {
uint32_t mvs_mode;
uint32_t rate_type;
struct min_max_rate min_max_rate;
uint32_t dtx_mode;
};
#define MVS_MAX_VOC_PKT_SIZE 640
struct gsm_header {
uint8_t bfi;
uint8_t sid;
uint8_t taf;
uint8_t ufi;
};
struct q6_msm_audio_mvs_frame {
union {
uint32_t frame_type;
uint32_t packet_rate;
struct gsm_header gsm_frame_type;
} header;
uint32_t len;
uint8_t voc_pkt[MVS_MAX_VOC_PKT_SIZE];
};
struct msm_audio_mvs_frame {
uint32_t frame_type;
uint32_t len;
uint8_t voc_pkt[MVS_MAX_VOC_PKT_SIZE];
};
#define Q5V2_MVS_MAX_VOC_PKT_SIZE 320
struct q5v2_msm_audio_mvs_frame {
uint32_t frame_type;
uint32_t len;
uint8_t voc_pkt[Q5V2_MVS_MAX_VOC_PKT_SIZE];
};
#endif /* _MSM_AUDIO_MVS_H */

37
sdm710/kernel-headers/linux/msm_audio_qcp.h
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@@ -1,37 +0,0 @@
#ifndef _MSM_AUDIO_QCP_H
#define _MSM_AUDIO_QCP_H
#include <linux/msm_audio.h>
#define AUDIO_SET_QCELP_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
0, struct msm_audio_qcelp_enc_config)
#define AUDIO_GET_QCELP_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
1, struct msm_audio_qcelp_enc_config)
#define AUDIO_SET_EVRC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
2, struct msm_audio_evrc_enc_config)
#define AUDIO_GET_EVRC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
3, struct msm_audio_evrc_enc_config)
#define CDMA_RATE_BLANK 0x00
#define CDMA_RATE_EIGHTH 0x01
#define CDMA_RATE_QUARTER 0x02
#define CDMA_RATE_HALF 0x03
#define CDMA_RATE_FULL 0x04
#define CDMA_RATE_ERASURE 0x05
struct msm_audio_qcelp_enc_config {
uint32_t cdma_rate;
uint32_t min_bit_rate;
uint32_t max_bit_rate;
};
struct msm_audio_evrc_enc_config {
uint32_t cdma_rate;
uint32_t min_bit_rate;
uint32_t max_bit_rate;
};
#endif /* _MSM_AUDIO_QCP_H */

36
sdm710/kernel-headers/linux/msm_audio_sbc.h
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@@ -1,36 +0,0 @@
#ifndef _MSM_AUDIO_SBC_H
#define _MSM_AUDIO_SBC_H
#include <linux/msm_audio.h>
#define AUDIO_SET_SBC_ENC_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_sbc_enc_config)
#define AUDIO_GET_SBC_ENC_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_sbc_enc_config)
#define AUDIO_SBC_BA_LOUDNESS 0x0
#define AUDIO_SBC_BA_SNR 0x1
#define AUDIO_SBC_MODE_MONO 0x0
#define AUDIO_SBC_MODE_DUAL 0x1
#define AUDIO_SBC_MODE_STEREO 0x2
#define AUDIO_SBC_MODE_JSTEREO 0x3
#define AUDIO_SBC_BANDS_8 0x1
#define AUDIO_SBC_BLOCKS_4 0x0
#define AUDIO_SBC_BLOCKS_8 0x1
#define AUDIO_SBC_BLOCKS_12 0x2
#define AUDIO_SBC_BLOCKS_16 0x3
struct msm_audio_sbc_enc_config {
uint32_t channels;
uint32_t sample_rate;
uint32_t bit_allocation;
uint32_t number_of_subbands;
uint32_t number_of_blocks;
uint32_t bit_rate;
uint32_t mode;
};
#endif /* _MSM_AUDIO_SBC_H */

66
sdm710/kernel-headers/linux/msm_audio_voicememo.h
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@@ -1,66 +0,0 @@
#ifndef _MSM_AUDIO_VOICEMEMO_H
#define _MSM_AUDIO_VOICEMEMO_H
#include <linux/msm_audio.h>
#define AUDIO_GET_VOICEMEMO_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int)
#define AUDIO_SET_VOICEMEMO_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int)
/* rec_type */
enum rpc_voc_rec_dir_type {
RPC_VOC_REC_NONE,
RPC_VOC_REC_FORWARD,
RPC_VOC_REC_REVERSE,
RPC_VOC_REC_BOTH,
RPC_VOC_MAX_REC_TYPE
};
/* capability */
enum rpc_voc_capability_type {
RPC_VOC_CAP_IS733 = 4,
RPC_VOC_CAP_IS127 = 8,
RPC_VOC_CAP_AMR = 64,
RPC_VOC_CAP_32BIT_DUMMY = 2147483647
};
/* Rate */
enum rpc_voc_rate_type {
RPC_VOC_0_RATE = 0,
RPC_VOC_8_RATE,
RPC_VOC_4_RATE,
RPC_VOC_2_RATE,
RPC_VOC_1_RATE,
RPC_VOC_ERASURE,
RPC_VOC_ERR_RATE,
RPC_VOC_AMR_RATE_475 = 0,
RPC_VOC_AMR_RATE_515 = 1,
RPC_VOC_AMR_RATE_590 = 2,
RPC_VOC_AMR_RATE_670 = 3,
RPC_VOC_AMR_RATE_740 = 4,
RPC_VOC_AMR_RATE_795 = 5,
RPC_VOC_AMR_RATE_1020 = 6,
RPC_VOC_AMR_RATE_1220 = 7,
};
/* frame_format */
enum rpc_voc_pb_len_rate_var_type {
RPC_VOC_PB_NATIVE_QCP = 3,
RPC_VOC_PB_AMR,
RPC_VOC_PB_EVB
};
struct msm_audio_voicememo_config {
uint32_t rec_type;
uint32_t rec_interval_ms;
uint32_t auto_stop_ms;
uint32_t capability;
uint32_t max_rate;
uint32_t min_rate;
uint32_t frame_format;
uint32_t dtx_enable;
uint32_t data_req_ms;
};
#endif /* _MSM_AUDIO_VOICEMEMO_H */

33
sdm710/kernel-headers/linux/msm_audio_wma.h
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@@ -1,33 +0,0 @@
#ifndef _MSM_AUDIO_WMA_H
#define _MSM_AUDIO_WMA_H
#define AUDIO_GET_WMA_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), unsigned int)
#define AUDIO_SET_WMA_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), unsigned int)
#define AUDIO_GET_WMA_CONFIG_V2 _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+2), struct msm_audio_wma_config_v2)
#define AUDIO_SET_WMA_CONFIG_V2 _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+3), struct msm_audio_wma_config_v2)
struct msm_audio_wma_config {
unsigned short armdatareqthr;
unsigned short channelsdecoded;
unsigned short wmabytespersec;
unsigned short wmasamplingfreq;
unsigned short wmaencoderopts;
};
struct msm_audio_wma_config_v2 {
unsigned short format_tag;
unsigned short numchannels;
uint32_t samplingrate;
uint32_t avgbytespersecond;
unsigned short block_align;
unsigned short validbitspersample;
uint32_t channelmask;
unsigned short encodeopt;
};
#endif /* _MSM_AUDIO_WMA_H */

22
sdm710/kernel-headers/linux/msm_audio_wmapro.h
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@@ -1,22 +0,0 @@
#ifndef _MSM_AUDIO_WMAPRO_H
#define _MSM_AUDIO_WMAPRO_H
#define AUDIO_GET_WMAPRO_CONFIG _IOR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+0), struct msm_audio_wmapro_config)
#define AUDIO_SET_WMAPRO_CONFIG _IOW(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_COMMON_IOCTL_NUM+1), struct msm_audio_wmapro_config)
struct msm_audio_wmapro_config {
unsigned short armdatareqthr;
uint8_t validbitspersample;
uint8_t numchannels;
unsigned short formattag;
uint32_t samplingrate;
uint32_t avgbytespersecond;
unsigned short asfpacketlength;
uint32_t channelmask;
unsigned short encodeopt;
unsigned short advancedencodeopt;
uint32_t advancedencodeopt2;
};
#endif /* _MSM_AUDIO_WMAPRO_H */

29
sdm710/kernel-headers/linux/msm_dsps.h
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@@ -1,29 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _DSPS_H_
#define _DSPS_H_
#include <linux/ioctl.h>
#define DSPS_IOCTL_MAGIC 'd'
#define DSPS_IOCTL_ON _IO(DSPS_IOCTL_MAGIC, 1)
#define DSPS_IOCTL_OFF _IO(DSPS_IOCTL_MAGIC, 2)
#define DSPS_IOCTL_READ_SLOW_TIMER _IOR(DSPS_IOCTL_MAGIC, 3, unsigned int *)
#define DSPS_IOCTL_READ_FAST_TIMER _IOR(DSPS_IOCTL_MAGIC, 4, unsigned int *)
#define DSPS_IOCTL_RESET _IO(DSPS_IOCTL_MAGIC, 5)
#endif

138
sdm710/kernel-headers/linux/msm_ion.h
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@@ -1,138 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _MSM_ION_H
#define _MSM_ION_H
#include "ion.h"
#define ION_BIT(nr) (1UL << (nr))
enum msm_ion_heap_types {
ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1,
ION_HEAP_TYPE_SECURE_DMA = ION_HEAP_TYPE_MSM_START,
ION_HEAP_TYPE_SYSTEM_SECURE,
ION_HEAP_TYPE_HYP_CMA,
ION_HEAP_TYPE_SECURE_CARVEOUT,
};
enum ion_heap_ids {
INVALID_HEAP_ID = - 1,
ION_CP_MM_HEAP_ID = 8,
ION_SECURE_HEAP_ID = 9,
ION_SECURE_DISPLAY_HEAP_ID = 10,
ION_CP_MFC_HEAP_ID = 12,
ION_SPSS_HEAP_ID = 13,
ION_SECURE_CARVEOUT_HEAP_ID = 14,
ION_CP_WB_HEAP_ID = 16,
ION_QSECOM_TA_HEAP_ID = 19,
ION_CAMERA_HEAP_ID = 20,
ION_SYSTEM_CONTIG_HEAP_ID = 21,
ION_ADSP_HEAP_ID = 22,
ION_PIL1_HEAP_ID = 23,
ION_SF_HEAP_ID = 24,
ION_SYSTEM_HEAP_ID = 25,
ION_PIL2_HEAP_ID = 26,
ION_QSECOM_HEAP_ID = 27,
ION_AUDIO_HEAP_ID = 28,
ION_MM_FIRMWARE_HEAP_ID = 29,
ION_GOOGLE_HEAP_ID = 30,
ION_HEAP_ID_RESERVED = 31
};
#define ION_IOMMU_HEAP_ID ION_SYSTEM_HEAP_ID
#define ION_HEAP_TYPE_IOMMU ION_HEAP_TYPE_SYSTEM
#define ION_SPSS_HEAP_ID ION_SPSS_HEAP_ID
enum ion_fixed_position {
NOT_FIXED,
FIXED_LOW,
FIXED_MIDDLE,
FIXED_HIGH,
};
enum cp_mem_usage {
VIDEO_BITSTREAM = 0x1,
VIDEO_PIXEL = 0x2,
VIDEO_NONPIXEL = 0x3,
DISPLAY_SECURE_CP_USAGE = 0x4,
CAMERA_SECURE_CP_USAGE = 0x5,
MAX_USAGE = 0x6,
UNKNOWN = 0x7FFFFFFF,
};
#define ION_FLAG_CP_TOUCH ION_BIT(17)
#define ION_FLAG_CP_BITSTREAM ION_BIT(18)
#define ION_FLAG_CP_PIXEL ION_BIT(19)
#define ION_FLAG_CP_NON_PIXEL ION_BIT(20)
#define ION_FLAG_CP_CAMERA ION_BIT(21)
#define ION_FLAG_CP_HLOS ION_BIT(22)
#define ION_FLAG_CP_SPSS_SP ION_BIT(23)
#define ION_FLAG_CP_SPSS_SP_SHARED ION_BIT(24)
#define ION_FLAG_CP_SEC_DISPLAY ION_BIT(25)
#define ION_FLAG_CP_APP ION_BIT(26)
#define ION_FLAG_CP_CAMERA_PREVIEW ION_BIT(27)
#define ION_FLAG_CP_CDSP ION_BIT(29)
#define ION_FLAG_CP_SPSS_HLOS_SHARED ION_BIT(30)
#define ION_FLAG_ALLOW_NON_CONTIG ION_BIT(28)
#define ION_FLAG_SECURE ION_BIT(ION_HEAP_ID_RESERVED)
#define ION_FLAG_POOL_FORCE_ALLOC ION_BIT(16)
#define ION_SECURE ION_FLAG_SECURE
#define ION_HEAP(bit) ION_BIT(bit)
#define ION_ADSP_HEAP_NAME "adsp"
#define ION_SYSTEM_HEAP_NAME "system"
#define ION_VMALLOC_HEAP_NAME ION_SYSTEM_HEAP_NAME
#define ION_KMALLOC_HEAP_NAME "kmalloc"
#define ION_AUDIO_HEAP_NAME "audio"
#define ION_SF_HEAP_NAME "sf"
#define ION_MM_HEAP_NAME "mm"
#define ION_CAMERA_HEAP_NAME "camera_preview"
#define ION_IOMMU_HEAP_NAME "iommu"
#define ION_MFC_HEAP_NAME "mfc"
#define ION_SPSS_HEAP_NAME "spss"
#define ION_SECURE_CARVEOUT_HEAP_NAME "secure_carveout"
#define ION_WB_HEAP_NAME "wb"
#define ION_MM_FIRMWARE_HEAP_NAME "mm_fw"
#define ION_GOOGLE_HEAP_NAME "easel_mem"
#define ION_PIL1_HEAP_NAME "pil_1"
#define ION_PIL2_HEAP_NAME "pil_2"
#define ION_QSECOM_HEAP_NAME "qsecom"
#define ION_QSECOM_TA_HEAP_NAME "qsecom_ta"
#define ION_SECURE_HEAP_NAME "secure_heap"
#define ION_SECURE_DISPLAY_HEAP_NAME "secure_display"
#define ION_SET_CACHED(__cache) ((__cache) | ION_FLAG_CACHED)
#define ION_SET_UNCACHED(__cache) ((__cache) & ~ION_FLAG_CACHED)
#define ION_IS_CACHED(__flags) ((__flags) & ION_FLAG_CACHED)
struct ion_flush_data {
ion_user_handle_t handle;
int fd;
void * vaddr;
unsigned int offset;
unsigned int length;
};
struct ion_prefetch_regions {
unsigned int vmid;
size_t * sizes;
unsigned int nr_sizes;
};
struct ion_prefetch_data {
int heap_id;
unsigned long len;
struct ion_prefetch_regions * regions;
unsigned int nr_regions;
};
#define ION_IOC_MSM_MAGIC 'M'
#define ION_IOC_CLEAN_CACHES _IOWR(ION_IOC_MSM_MAGIC, 0, struct ion_flush_data)
#define ION_IOC_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 1, struct ion_flush_data)
#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, struct ion_flush_data)
#define ION_IOC_PREFETCH _IOWR(ION_IOC_MSM_MAGIC, 3, struct ion_prefetch_data)
#define ION_IOC_DRAIN _IOWR(ION_IOC_MSM_MAGIC, 4, struct ion_prefetch_data)
#endif

969
sdm710/kernel-headers/linux/msm_ipa.h
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@@ -1,969 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _MSM_IPA_H_
#define _MSM_IPA_H_
#include <stdint.h>
#include <stddef.h>
#include <sys/stat.h>
#include <linux/ioctl.h>
#include <linux/types.h>
#include <linux/if_ether.h>
#define IPA_IOC_MAGIC 0xCF
#define IPA_DEV_NAME "/dev/ipa"
#define IPA_NAT_DEV_NAME "ipaNatTable"
#define IPA_IPV6CT_DEV_NAME "ipaIpv6CTTable"
#define IPA_DFLT_RT_TBL_NAME "ipa_dflt_rt"
#define IPA_IOCTL_ADD_HDR 0
#define IPA_IOCTL_DEL_HDR 1
#define IPA_IOCTL_ADD_RT_RULE 2
#define IPA_IOCTL_DEL_RT_RULE 3
#define IPA_IOCTL_ADD_FLT_RULE 4
#define IPA_IOCTL_DEL_FLT_RULE 5
#define IPA_IOCTL_COMMIT_HDR 6
#define IPA_IOCTL_RESET_HDR 7
#define IPA_IOCTL_COMMIT_RT 8
#define IPA_IOCTL_RESET_RT 9
#define IPA_IOCTL_COMMIT_FLT 10
#define IPA_IOCTL_RESET_FLT 11
#define IPA_IOCTL_DUMP 12
#define IPA_IOCTL_GET_RT_TBL 13
#define IPA_IOCTL_PUT_RT_TBL 14
#define IPA_IOCTL_COPY_HDR 15
#define IPA_IOCTL_QUERY_INTF 16
#define IPA_IOCTL_QUERY_INTF_TX_PROPS 17
#define IPA_IOCTL_QUERY_INTF_RX_PROPS 18
#define IPA_IOCTL_GET_HDR 19
#define IPA_IOCTL_PUT_HDR 20
#define IPA_IOCTL_SET_FLT 21
#define IPA_IOCTL_ALLOC_NAT_MEM 22
#define IPA_IOCTL_V4_INIT_NAT 23
#define IPA_IOCTL_TABLE_DMA_CMD 24
#define IPA_IOCTL_NAT_DMA IPA_IOCTL_TABLE_DMA_CMD
#define IPA_IOCTL_INIT_IPV6CT_TABLE 25
#define IPA_IOCTL_V4_DEL_NAT 26
#define IPA_IOCTL_PULL_MSG 27
#define IPA_IOCTL_GET_NAT_OFFSET 28
#define IPA_IOCTL_RM_ADD_DEPENDENCY 29
#define IPA_IOCTL_RM_DEL_DEPENDENCY 30
#define IPA_IOCTL_GENERATE_FLT_EQ 31
#define IPA_IOCTL_QUERY_INTF_EXT_PROPS 32
#define IPA_IOCTL_QUERY_EP_MAPPING 33
#define IPA_IOCTL_QUERY_RT_TBL_INDEX 34
#define IPA_IOCTL_WRITE_QMAPID 35
#define IPA_IOCTL_MDFY_FLT_RULE 36
#define IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_ADD 37
#define IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_DEL 38
#define IPA_IOCTL_NOTIFY_WAN_EMBMS_CONNECTED 39
#define IPA_IOCTL_ADD_HDR_PROC_CTX 40
#define IPA_IOCTL_DEL_HDR_PROC_CTX 41
#define IPA_IOCTL_MDFY_RT_RULE 42
#define IPA_IOCTL_ADD_RT_RULE_AFTER 43
#define IPA_IOCTL_ADD_FLT_RULE_AFTER 44
#define IPA_IOCTL_GET_HW_VERSION 45
#define IPA_IOCTL_ADD_RT_RULE_EXT 46
#define IPA_IOCTL_ADD_VLAN_IFACE 47
#define IPA_IOCTL_DEL_VLAN_IFACE 48
#define IPA_IOCTL_ADD_L2TP_VLAN_MAPPING 49
#define IPA_IOCTL_DEL_L2TP_VLAN_MAPPING 50
#define IPA_IOCTL_NAT_MODIFY_PDN 51
#define IPA_IOCTL_ALLOC_NAT_TABLE 52
#define IPA_IOCTL_ALLOC_IPV6CT_TABLE 53
#define IPA_IOCTL_DEL_NAT_TABLE 54
#define IPA_IOCTL_DEL_IPV6CT_TABLE 55
#define IPA_IOCTL_CLEANUP 56
#define IPA_IOCTL_QUERY_WLAN_CLIENT 57
#define IPA_IOCTL_GET_VLAN_MODE 58
#define IPA_HDR_MAX_SIZE 64
#define IPA_RESOURCE_NAME_MAX 32
#define IPA_NUM_PROPS_MAX 35
#define IPA_MAC_ADDR_SIZE 6
#define IPA_MBIM_MAX_STREAM_NUM 8
#define IPA_WAN_MSG_IPv6_ADDR_GW_LEN 4
#define IPA_MAX_NUM_HW_PATH_CLIENTS 16
#define QMI_IPA_MAX_CLIENT_DST_PIPES 4
#define IPA_FLT_TOS (1ul << 0)
#define IPA_FLT_PROTOCOL (1ul << 1)
#define IPA_FLT_SRC_ADDR (1ul << 2)
#define IPA_FLT_DST_ADDR (1ul << 3)
#define IPA_FLT_SRC_PORT_RANGE (1ul << 4)
#define IPA_FLT_DST_PORT_RANGE (1ul << 5)
#define IPA_FLT_TYPE (1ul << 6)
#define IPA_FLT_CODE (1ul << 7)
#define IPA_FLT_SPI (1ul << 8)
#define IPA_FLT_SRC_PORT (1ul << 9)
#define IPA_FLT_DST_PORT (1ul << 10)
#define IPA_FLT_TC (1ul << 11)
#define IPA_FLT_FLOW_LABEL (1ul << 12)
#define IPA_FLT_NEXT_HDR (1ul << 13)
#define IPA_FLT_META_DATA (1ul << 14)
#define IPA_FLT_FRAGMENT (1ul << 15)
#define IPA_FLT_TOS_MASKED (1ul << 16)
#define IPA_FLT_MAC_SRC_ADDR_ETHER_II (1ul << 17)
#define IPA_FLT_MAC_DST_ADDR_ETHER_II (1ul << 18)
#define IPA_FLT_MAC_SRC_ADDR_802_3 (1ul << 19)
#define IPA_FLT_MAC_DST_ADDR_802_3 (1ul << 20)
#define IPA_FLT_MAC_ETHER_TYPE (1ul << 21)
#define IPA_FLT_MAC_DST_ADDR_L2TP (1ul << 22)
#define IPA_FLT_TCP_SYN (1ul << 23)
#define IPA_FLT_TCP_SYN_L2TP (1ul << 24)
#define IPA_FLT_L2TP_INNER_IP_TYPE (1ul << 25)
#define IPA_FLT_L2TP_INNER_IPV4_DST_ADDR (1ul << 26)
#define IPA_MAX_PDN_NUM 5
enum ipa_client_type {
IPA_CLIENT_HSIC1_PROD = 0,
IPA_CLIENT_HSIC1_CONS = 1,
IPA_CLIENT_HSIC2_PROD = 2,
IPA_CLIENT_HSIC2_CONS = 3,
IPA_CLIENT_HSIC3_PROD = 4,
IPA_CLIENT_HSIC3_CONS = 5,
IPA_CLIENT_HSIC4_PROD = 6,
IPA_CLIENT_HSIC4_CONS = 7,
IPA_CLIENT_HSIC5_PROD = 8,
IPA_CLIENT_HSIC5_CONS = 9,
IPA_CLIENT_WLAN1_PROD = 10,
IPA_CLIENT_WLAN1_CONS = 11,
IPA_CLIENT_A5_WLAN_AMPDU_PROD = 12,
IPA_CLIENT_WLAN2_CONS = 13,
IPA_CLIENT_WLAN3_CONS = 15,
IPA_CLIENT_WLAN4_CONS = 17,
IPA_CLIENT_USB_PROD = 18,
IPA_CLIENT_USB_CONS = 19,
IPA_CLIENT_USB2_PROD = 20,
IPA_CLIENT_USB2_CONS = 21,
IPA_CLIENT_USB3_PROD = 22,
IPA_CLIENT_USB3_CONS = 23,
IPA_CLIENT_USB4_PROD = 24,
IPA_CLIENT_USB4_CONS = 25,
IPA_CLIENT_UC_USB_PROD = 26,
IPA_CLIENT_USB_DPL_CONS = 27,
IPA_CLIENT_A2_EMBEDDED_PROD = 28,
IPA_CLIENT_A2_EMBEDDED_CONS = 29,
IPA_CLIENT_A2_TETHERED_PROD = 30,
IPA_CLIENT_A2_TETHERED_CONS = 31,
IPA_CLIENT_APPS_LAN_PROD = 32,
IPA_CLIENT_APPS_LAN_CONS = 33,
IPA_CLIENT_APPS_WAN_PROD = 34,
IPA_CLIENT_APPS_LAN_WAN_PROD = IPA_CLIENT_APPS_WAN_PROD,
IPA_CLIENT_APPS_WAN_CONS = 35,
IPA_CLIENT_APPS_CMD_PROD = 36,
IPA_CLIENT_A5_LAN_WAN_CONS = 37,
IPA_CLIENT_ODU_PROD = 38,
IPA_CLIENT_ODU_EMB_CONS = 39,
IPA_CLIENT_ODU_TETH_CONS = 41,
IPA_CLIENT_MHI_PROD = 42,
IPA_CLIENT_MHI_CONS = 43,
IPA_CLIENT_MEMCPY_DMA_SYNC_PROD = 44,
IPA_CLIENT_MEMCPY_DMA_SYNC_CONS = 45,
IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD = 46,
IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS = 47,
IPA_CLIENT_ETHERNET_PROD = 48,
IPA_CLIENT_ETHERNET_CONS = 49,
IPA_CLIENT_Q6_LAN_PROD = 50,
IPA_CLIENT_Q6_LAN_CONS = 51,
IPA_CLIENT_Q6_WAN_PROD = 52,
IPA_CLIENT_Q6_WAN_CONS = 53,
IPA_CLIENT_Q6_CMD_PROD = 54,
IPA_CLIENT_Q6_DUN_CONS = 55,
IPA_CLIENT_Q6_DECOMP_PROD = 56,
IPA_CLIENT_Q6_DECOMP_CONS = 57,
IPA_CLIENT_Q6_DECOMP2_PROD = 58,
IPA_CLIENT_Q6_DECOMP2_CONS = 59,
IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS = 61,
IPA_CLIENT_TEST_PROD = 62,
IPA_CLIENT_TEST_CONS = 63,
IPA_CLIENT_TEST1_PROD = 64,
IPA_CLIENT_TEST1_CONS = 65,
IPA_CLIENT_TEST2_PROD = 66,
IPA_CLIENT_TEST2_CONS = 67,
IPA_CLIENT_TEST3_PROD = 68,
IPA_CLIENT_TEST3_CONS = 69,
IPA_CLIENT_TEST4_PROD = 70,
IPA_CLIENT_TEST4_CONS = 71,
IPA_CLIENT_DUMMY_CONS = 73
};
#define IPA_CLIENT_MAX (IPA_CLIENT_DUMMY_CONS + 1)
#define IPA_CLIENT_IS_APPS_CONS(client) ((client) == IPA_CLIENT_APPS_LAN_CONS || (client) == IPA_CLIENT_APPS_WAN_CONS)
#define IPA_CLIENT_IS_USB_CONS(client) ((client) == IPA_CLIENT_USB_CONS || (client) == IPA_CLIENT_USB2_CONS || (client) == IPA_CLIENT_USB3_CONS || (client) == IPA_CLIENT_USB_DPL_CONS || (client) == IPA_CLIENT_USB4_CONS)
#define IPA_CLIENT_IS_WLAN_CONS(client) ((client) == IPA_CLIENT_WLAN1_CONS || (client) == IPA_CLIENT_WLAN2_CONS || (client) == IPA_CLIENT_WLAN3_CONS || (client) == IPA_CLIENT_WLAN4_CONS)
#define IPA_CLIENT_IS_ODU_CONS(client) ((client) == IPA_CLIENT_ODU_EMB_CONS || (client) == IPA_CLIENT_ODU_TETH_CONS)
#define IPA_CLIENT_IS_Q6_CONS(client) ((client) == IPA_CLIENT_Q6_LAN_CONS || (client) == IPA_CLIENT_Q6_WAN_CONS || (client) == IPA_CLIENT_Q6_DUN_CONS || (client) == IPA_CLIENT_Q6_DECOMP_CONS || (client) == IPA_CLIENT_Q6_DECOMP2_CONS || (client) == IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS)
#define IPA_CLIENT_IS_Q6_PROD(client) ((client) == IPA_CLIENT_Q6_LAN_PROD || (client) == IPA_CLIENT_Q6_WAN_PROD || (client) == IPA_CLIENT_Q6_CMD_PROD || (client) == IPA_CLIENT_Q6_DECOMP_PROD || (client) == IPA_CLIENT_Q6_DECOMP2_PROD)
#define IPA_CLIENT_IS_Q6_NON_ZIP_CONS(client) ((client) == IPA_CLIENT_Q6_LAN_CONS || (client) == IPA_CLIENT_Q6_WAN_CONS || (client) == IPA_CLIENT_Q6_DUN_CONS || (client) == IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS)
#define IPA_CLIENT_IS_Q6_ZIP_CONS(client) ((client) == IPA_CLIENT_Q6_DECOMP_CONS || (client) == IPA_CLIENT_Q6_DECOMP2_CONS)
#define IPA_CLIENT_IS_Q6_NON_ZIP_PROD(client) ((client) == IPA_CLIENT_Q6_LAN_PROD || (client) == IPA_CLIENT_Q6_WAN_PROD || (client) == IPA_CLIENT_Q6_CMD_PROD)
#define IPA_CLIENT_IS_Q6_ZIP_PROD(client) ((client) == IPA_CLIENT_Q6_DECOMP_PROD || (client) == IPA_CLIENT_Q6_DECOMP2_PROD)
#define IPA_CLIENT_IS_MEMCPY_DMA_CONS(client) ((client) == IPA_CLIENT_MEMCPY_DMA_SYNC_CONS || (client) == IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS)
#define IPA_CLIENT_IS_MEMCPY_DMA_PROD(client) ((client) == IPA_CLIENT_MEMCPY_DMA_SYNC_PROD || (client) == IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD)
#define IPA_CLIENT_IS_MHI_CONS(client) ((client) == IPA_CLIENT_MHI_CONS)
#define IPA_CLIENT_IS_MHI(client) ((client) == IPA_CLIENT_MHI_CONS || (client) == IPA_CLIENT_MHI_PROD)
#define IPA_CLIENT_IS_TEST_PROD(client) ((client) == IPA_CLIENT_TEST_PROD || (client) == IPA_CLIENT_TEST1_PROD || (client) == IPA_CLIENT_TEST2_PROD || (client) == IPA_CLIENT_TEST3_PROD || (client) == IPA_CLIENT_TEST4_PROD)
#define IPA_CLIENT_IS_TEST_CONS(client) ((client) == IPA_CLIENT_TEST_CONS || (client) == IPA_CLIENT_TEST1_CONS || (client) == IPA_CLIENT_TEST2_CONS || (client) == IPA_CLIENT_TEST3_CONS || (client) == IPA_CLIENT_TEST4_CONS)
#define IPA_CLIENT_IS_TEST(client) (IPA_CLIENT_IS_TEST_PROD(client) || IPA_CLIENT_IS_TEST_CONS(client))
enum ipa_ip_type {
IPA_IP_v4,
IPA_IP_v6,
IPA_IP_MAX
};
enum ipa_rule_type {
IPA_RULE_HASHABLE,
IPA_RULE_NON_HASHABLE,
};
#define IPA_RULE_TYPE_MAX (IPA_RULE_NON_HASHABLE + 1)
enum ipa_flt_action {
IPA_PASS_TO_ROUTING,
IPA_PASS_TO_SRC_NAT,
IPA_PASS_TO_DST_NAT,
IPA_PASS_TO_EXCEPTION
};
enum ipa_wlan_event {
WLAN_CLIENT_CONNECT,
WLAN_CLIENT_DISCONNECT,
WLAN_CLIENT_POWER_SAVE_MODE,
WLAN_CLIENT_NORMAL_MODE,
SW_ROUTING_ENABLE,
SW_ROUTING_DISABLE,
WLAN_AP_CONNECT,
WLAN_AP_DISCONNECT,
WLAN_STA_CONNECT,
WLAN_STA_DISCONNECT,
WLAN_CLIENT_CONNECT_EX,
WLAN_SWITCH_TO_SCC,
WLAN_SWITCH_TO_MCC,
WLAN_WDI_ENABLE,
WLAN_WDI_DISABLE,
IPA_WLAN_EVENT_MAX
};
enum ipa_wan_event {
WAN_UPSTREAM_ROUTE_ADD = IPA_WLAN_EVENT_MAX,
WAN_UPSTREAM_ROUTE_DEL,
WAN_EMBMS_CONNECT,
WAN_XLAT_CONNECT,
IPA_WAN_EVENT_MAX
};
enum ipa_ecm_event {
ECM_CONNECT = IPA_WAN_EVENT_MAX,
ECM_DISCONNECT,
IPA_ECM_EVENT_MAX,
};
enum ipa_tethering_stats_event {
IPA_TETHERING_STATS_UPDATE_STATS = IPA_ECM_EVENT_MAX,
IPA_TETHERING_STATS_UPDATE_NETWORK_STATS,
IPA_TETHERING_STATS_EVENT_MAX,
};
enum ipa_quota_event {
IPA_QUOTA_REACH = IPA_TETHERING_STATS_EVENT_MAX,
IPA_QUOTA_EVENT_MAX,
};
enum ipa_ssr_event {
IPA_SSR_BEFORE_SHUTDOWN = IPA_QUOTA_EVENT_MAX,
IPA_SSR_AFTER_POWERUP,
IPA_SSR_EVENT_MAX
};
enum ipa_vlan_l2tp_event {
ADD_VLAN_IFACE = IPA_SSR_EVENT_MAX,
DEL_VLAN_IFACE,
ADD_L2TP_VLAN_MAPPING,
DEL_L2TP_VLAN_MAPPING,
IPA_VLAN_L2TP_EVENT_MAX,
};
enum ipa_per_client_stats_event {
IPA_PER_CLIENT_STATS_CONNECT_EVENT = IPA_VLAN_L2TP_EVENT_MAX,
IPA_PER_CLIENT_STATS_DISCONNECT_EVENT,
IPA_PER_CLIENT_STATS_EVENT_MAX
};
enum ipa_wlan_fw_ssr_event {
WLAN_FWR_SSR_BEFORE_SHUTDOWN = IPA_PER_CLIENT_STATS_EVENT_MAX,
IPA_WLAN_FW_SSR_EVENT_MAX,
#define IPA_WLAN_FW_SSR_EVENT_MAX IPA_WLAN_FW_SSR_EVENT_MAX
};
#define IPA_EVENT_MAX_NUM (IPA_WLAN_FW_SSR_EVENT_MAX)
#define IPA_EVENT_MAX ((int) IPA_EVENT_MAX_NUM)
enum ipa_rm_resource_name {
IPA_RM_RESOURCE_Q6_PROD = 0,
IPA_RM_RESOURCE_Q6_CONS = 1,
IPA_RM_RESOURCE_USB_PROD = 2,
IPA_RM_RESOURCE_USB_CONS = 3,
IPA_RM_RESOURCE_USB_DPL_DUMMY_PROD = 4,
IPA_RM_RESOURCE_USB_DPL_CONS = 5,
IPA_RM_RESOURCE_HSIC_PROD = 6,
IPA_RM_RESOURCE_HSIC_CONS = 7,
IPA_RM_RESOURCE_STD_ECM_PROD = 8,
IPA_RM_RESOURCE_APPS_CONS = 9,
IPA_RM_RESOURCE_RNDIS_PROD = 10,
IPA_RM_RESOURCE_WWAN_0_PROD = 12,
IPA_RM_RESOURCE_WLAN_PROD = 14,
IPA_RM_RESOURCE_WLAN_CONS = 15,
IPA_RM_RESOURCE_ODU_ADAPT_PROD = 16,
IPA_RM_RESOURCE_ODU_ADAPT_CONS = 17,
IPA_RM_RESOURCE_MHI_PROD = 18,
IPA_RM_RESOURCE_MHI_CONS = 19,
IPA_RM_RESOURCE_ETHERNET_PROD = 20,
IPA_RM_RESOURCE_ETHERNET_CONS = 21,
};
#define IPA_RM_RESOURCE_MAX (IPA_RM_RESOURCE_ETHERNET_CONS + 1)
enum ipa_hw_type {
IPA_HW_None = 0,
IPA_HW_v1_0 = 1,
IPA_HW_v1_1 = 2,
IPA_HW_v2_0 = 3,
IPA_HW_v2_1 = 4,
IPA_HW_v2_5 = 5,
IPA_HW_v2_6 = IPA_HW_v2_5,
IPA_HW_v2_6L = 6,
IPA_HW_v3_0 = 10,
IPA_HW_v3_1 = 11,
IPA_HW_v3_5 = 12,
IPA_HW_v3_5_1 = 13,
IPA_HW_v4_0 = 14,
};
#define IPA_HW_MAX (IPA_HW_v4_0 + 1)
#define IPA_HW_v4_0 IPA_HW_v4_0
struct ipa_rule_attrib {
uint32_t attrib_mask;
uint16_t src_port_lo;
uint16_t src_port_hi;
uint16_t dst_port_lo;
uint16_t dst_port_hi;
uint8_t type;
uint8_t code;
uint8_t tos_value;
uint8_t tos_mask;
uint32_t spi;
uint16_t src_port;
uint16_t dst_port;
uint32_t meta_data;
uint32_t meta_data_mask;
uint8_t src_mac_addr[ETH_ALEN];
uint8_t src_mac_addr_mask[ETH_ALEN];
uint8_t dst_mac_addr[ETH_ALEN];
uint8_t dst_mac_addr_mask[ETH_ALEN];
uint16_t ether_type;
union {
struct {
uint8_t tos;
uint8_t protocol;
uint32_t src_addr;
uint32_t src_addr_mask;
uint32_t dst_addr;
uint32_t dst_addr_mask;
} v4;
struct {
uint8_t tc;
uint32_t flow_label;
uint8_t next_hdr;
uint32_t src_addr[4];
uint32_t src_addr_mask[4];
uint32_t dst_addr[4];
uint32_t dst_addr_mask[4];
} v6;
} u;
};
#define IPA_IPFLTR_NUM_MEQ_32_EQNS 2
#define IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS 2
#define IPA_IPFLTR_NUM_MEQ_128_EQNS 2
#define IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS 2
struct ipa_ipfltr_eq_16 {
int8_t offset;
uint16_t value;
};
struct ipa_ipfltr_eq_32 {
int8_t offset;
uint32_t value;
};
struct ipa_ipfltr_mask_eq_128 {
int8_t offset;
uint8_t mask[16];
uint8_t value[16];
};
struct ipa_ipfltr_mask_eq_32 {
int8_t offset;
uint32_t mask;
uint32_t value;
};
struct ipa_ipfltr_range_eq_16 {
int8_t offset;
uint16_t range_low;
uint16_t range_high;
};
struct ipa_ipfltri_rule_eq {
uint16_t rule_eq_bitmap;
uint8_t tos_eq_present;
uint8_t tos_eq;
uint8_t protocol_eq_present;
uint8_t protocol_eq;
uint8_t num_ihl_offset_range_16;
struct ipa_ipfltr_range_eq_16 ihl_offset_range_16[IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS];
uint8_t num_offset_meq_32;
struct ipa_ipfltr_mask_eq_32 offset_meq_32[IPA_IPFLTR_NUM_MEQ_32_EQNS];
uint8_t tc_eq_present;
uint8_t tc_eq;
uint8_t fl_eq_present;
uint32_t fl_eq;
uint8_t ihl_offset_eq_16_present;
struct ipa_ipfltr_eq_16 ihl_offset_eq_16;
uint8_t ihl_offset_eq_32_present;
struct ipa_ipfltr_eq_32 ihl_offset_eq_32;
uint8_t num_ihl_offset_meq_32;
struct ipa_ipfltr_mask_eq_32 ihl_offset_meq_32[IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS];
uint8_t num_offset_meq_128;
struct ipa_ipfltr_mask_eq_128 offset_meq_128[IPA_IPFLTR_NUM_MEQ_128_EQNS];
uint8_t metadata_meq32_present;
struct ipa_ipfltr_mask_eq_32 metadata_meq32;
uint8_t ipv4_frag_eq_present;
};
struct ipa_flt_rule {
uint8_t retain_hdr;
uint8_t to_uc;
enum ipa_flt_action action;
uint32_t rt_tbl_hdl;
struct ipa_rule_attrib attrib;
struct ipa_ipfltri_rule_eq eq_attrib;
uint32_t rt_tbl_idx;
uint8_t eq_attrib_type;
uint8_t max_prio;
uint8_t hashable;
uint16_t rule_id;
uint8_t set_metadata;
uint8_t pdn_idx;
};
enum ipa_hdr_l2_type {
IPA_HDR_L2_NONE,
IPA_HDR_L2_ETHERNET_II,
IPA_HDR_L2_802_3,
IPA_HDR_L2_802_1Q,
};
#define IPA_HDR_L2_MAX (IPA_HDR_L2_802_1Q + 1)
#define IPA_HDR_L2_802_1Q IPA_HDR_L2_802_1Q
enum ipa_hdr_proc_type {
IPA_HDR_PROC_NONE,
IPA_HDR_PROC_ETHII_TO_ETHII,
IPA_HDR_PROC_ETHII_TO_802_3,
IPA_HDR_PROC_802_3_TO_ETHII,
IPA_HDR_PROC_802_3_TO_802_3,
IPA_HDR_PROC_L2TP_HEADER_ADD,
IPA_HDR_PROC_L2TP_HEADER_REMOVE
};
#define IPA_HDR_PROC_MAX (IPA_HDR_PROC_L2TP_HEADER_REMOVE + 1)
struct ipa_rt_rule {
enum ipa_client_type dst;
uint32_t hdr_hdl;
uint32_t hdr_proc_ctx_hdl;
struct ipa_rule_attrib attrib;
uint8_t max_prio;
uint8_t hashable;
uint8_t retain_hdr;
};
struct ipa_hdr_add {
char name[IPA_RESOURCE_NAME_MAX];
uint8_t hdr[IPA_HDR_MAX_SIZE];
uint8_t hdr_len;
enum ipa_hdr_l2_type type;
uint8_t is_partial;
uint32_t hdr_hdl;
int status;
uint8_t is_eth2_ofst_valid;
uint16_t eth2_ofst;
};
struct ipa_ioc_add_hdr {
uint8_t commit;
uint8_t num_hdrs;
struct ipa_hdr_add hdr[0];
};
struct ipa_l2tp_header_add_procparams {
uint32_t eth_hdr_retained : 1;
uint32_t input_ip_version : 1;
uint32_t output_ip_version : 1;
uint32_t reserved : 29;
};
struct ipa_l2tp_header_remove_procparams {
uint32_t hdr_len_remove : 8;
uint32_t eth_hdr_retained : 1;
uint32_t hdr_ofst_pkt_size_valid : 1;
uint32_t hdr_ofst_pkt_size : 6;
uint32_t hdr_endianness : 1;
uint32_t reserved : 15;
};
struct ipa_l2tp_hdr_proc_ctx_params {
struct ipa_l2tp_header_add_procparams hdr_add_param;
struct ipa_l2tp_header_remove_procparams hdr_remove_param;
uint8_t is_dst_pipe_valid;
enum ipa_client_type dst_pipe;
};
#define L2TP_USER_SPACE_SPECIFY_DST_PIPE
struct ipa_hdr_proc_ctx_add {
enum ipa_hdr_proc_type type;
uint32_t hdr_hdl;
uint32_t proc_ctx_hdl;
int status;
struct ipa_l2tp_hdr_proc_ctx_params l2tp_params;
};
#define IPA_L2TP_HDR_PROC_SUPPORT
struct ipa_ioc_add_hdr_proc_ctx {
uint8_t commit;
uint8_t num_proc_ctxs;
struct ipa_hdr_proc_ctx_add proc_ctx[0];
};
struct ipa_ioc_copy_hdr {
char name[IPA_RESOURCE_NAME_MAX];
uint8_t hdr[IPA_HDR_MAX_SIZE];
uint8_t hdr_len;
enum ipa_hdr_l2_type type;
uint8_t is_partial;
uint8_t is_eth2_ofst_valid;
uint16_t eth2_ofst;
};
struct ipa_ioc_get_hdr {
char name[IPA_RESOURCE_NAME_MAX];
uint32_t hdl;
};
struct ipa_hdr_del {
uint32_t hdl;
int status;
};
struct ipa_ioc_del_hdr {
uint8_t commit;
uint8_t num_hdls;
struct ipa_hdr_del hdl[0];
};
struct ipa_hdr_proc_ctx_del {
uint32_t hdl;
int status;
};
struct ipa_ioc_del_hdr_proc_ctx {
uint8_t commit;
uint8_t num_hdls;
struct ipa_hdr_proc_ctx_del hdl[0];
};
struct ipa_rt_rule_add {
struct ipa_rt_rule rule;
uint8_t at_rear;
uint32_t rt_rule_hdl;
int status;
};
struct ipa_ioc_add_rt_rule {
uint8_t commit;
enum ipa_ip_type ip;
char rt_tbl_name[IPA_RESOURCE_NAME_MAX];
uint8_t num_rules;
struct ipa_rt_rule_add rules[0];
};
struct ipa_ioc_add_rt_rule_after {
uint8_t commit;
enum ipa_ip_type ip;
char rt_tbl_name[IPA_RESOURCE_NAME_MAX];
uint8_t num_rules;
uint32_t add_after_hdl;
struct ipa_rt_rule_add rules[0];
};
struct ipa_rt_rule_mdfy {
struct ipa_rt_rule rule;
uint32_t rt_rule_hdl;
int status;
};
struct ipa_ioc_mdfy_rt_rule {
uint8_t commit;
enum ipa_ip_type ip;
uint8_t num_rules;
struct ipa_rt_rule_mdfy rules[0];
};
struct ipa_rt_rule_del {
uint32_t hdl;
int status;
};
struct ipa_rt_rule_add_ext {
struct ipa_rt_rule rule;
uint8_t at_rear;
uint32_t rt_rule_hdl;
int status;
uint16_t rule_id;
};
struct ipa_ioc_add_rt_rule_ext {
uint8_t commit;
enum ipa_ip_type ip;
char rt_tbl_name[IPA_RESOURCE_NAME_MAX];
uint8_t num_rules;
struct ipa_rt_rule_add_ext rules[0];
};
struct ipa_ioc_del_rt_rule {
uint8_t commit;
enum ipa_ip_type ip;
uint8_t num_hdls;
struct ipa_rt_rule_del hdl[0];
};
struct ipa_ioc_get_rt_tbl_indx {
enum ipa_ip_type ip;
char name[IPA_RESOURCE_NAME_MAX];
uint32_t idx;
};
struct ipa_flt_rule_add {
struct ipa_flt_rule rule;
uint8_t at_rear;
uint32_t flt_rule_hdl;
int status;
};
struct ipa_ioc_add_flt_rule {
uint8_t commit;
enum ipa_ip_type ip;
enum ipa_client_type ep;
uint8_t global;
uint8_t num_rules;
struct ipa_flt_rule_add rules[0];
};
struct ipa_ioc_add_flt_rule_after {
uint8_t commit;
enum ipa_ip_type ip;
enum ipa_client_type ep;
uint8_t num_rules;
uint32_t add_after_hdl;
struct ipa_flt_rule_add rules[0];
};
struct ipa_flt_rule_mdfy {
struct ipa_flt_rule rule;
uint32_t rule_hdl;
int status;
};
struct ipa_ioc_mdfy_flt_rule {
uint8_t commit;
enum ipa_ip_type ip;
uint8_t num_rules;
struct ipa_flt_rule_mdfy rules[0];
};
struct ipa_flt_rule_del {
uint32_t hdl;
int status;
};
struct ipa_ioc_del_flt_rule {
uint8_t commit;
enum ipa_ip_type ip;
uint8_t num_hdls;
struct ipa_flt_rule_del hdl[0];
};
struct ipa_ioc_get_rt_tbl {
enum ipa_ip_type ip;
char name[IPA_RESOURCE_NAME_MAX];
uint32_t hdl;
};
struct ipa_ioc_query_intf {
char name[IPA_RESOURCE_NAME_MAX];
uint32_t num_tx_props;
uint32_t num_rx_props;
uint32_t num_ext_props;
enum ipa_client_type excp_pipe;
};
struct ipa_ioc_tx_intf_prop {
enum ipa_ip_type ip;
struct ipa_rule_attrib attrib;
enum ipa_client_type dst_pipe;
enum ipa_client_type alt_dst_pipe;
char hdr_name[IPA_RESOURCE_NAME_MAX];
enum ipa_hdr_l2_type hdr_l2_type;
};
struct ipa_ioc_query_intf_tx_props {
char name[IPA_RESOURCE_NAME_MAX];
uint32_t num_tx_props;
struct ipa_ioc_tx_intf_prop tx[0];
};
struct ipa_ioc_ext_intf_prop {
enum ipa_ip_type ip;
struct ipa_ipfltri_rule_eq eq_attrib;
enum ipa_flt_action action;
uint32_t rt_tbl_idx;
uint8_t mux_id;
uint32_t filter_hdl;
uint8_t is_xlat_rule;
uint32_t rule_id;
uint8_t is_rule_hashable;
};
struct ipa_ioc_query_intf_ext_props {
char name[IPA_RESOURCE_NAME_MAX];
uint32_t num_ext_props;
struct ipa_ioc_ext_intf_prop ext[0];
};
struct ipa_ioc_rx_intf_prop {
enum ipa_ip_type ip;
struct ipa_rule_attrib attrib;
enum ipa_client_type src_pipe;
enum ipa_hdr_l2_type hdr_l2_type;
};
struct ipa_ioc_query_intf_rx_props {
char name[IPA_RESOURCE_NAME_MAX];
uint32_t num_rx_props;
struct ipa_ioc_rx_intf_prop rx[0];
};
struct ipa_ioc_nat_alloc_mem {
char dev_name[IPA_RESOURCE_NAME_MAX];
size_t size;
off_t offset;
};
struct ipa_ioc_nat_ipv6ct_table_alloc {
size_t size;
off_t offset;
};
struct ipa_ioc_v4_nat_init {
uint8_t tbl_index;
uint32_t ipv4_rules_offset;
uint32_t expn_rules_offset;
uint32_t index_offset;
uint32_t index_expn_offset;
uint16_t table_entries;
uint16_t expn_table_entries;
uint32_t ip_addr;
};
struct ipa_ioc_ipv6ct_init {
uint32_t base_table_offset;
uint32_t expn_table_offset;
uint16_t table_entries;
uint16_t expn_table_entries;
uint8_t tbl_index;
};
struct ipa_ioc_v4_nat_del {
uint8_t table_index;
uint32_t public_ip_addr;
};
struct ipa_ioc_nat_ipv6ct_table_del {
uint8_t table_index;
};
struct ipa_ioc_nat_dma_one {
uint8_t table_index;
uint8_t base_addr;
uint32_t offset;
uint16_t data;
};
struct ipa_ioc_nat_dma_cmd {
uint8_t entries;
struct ipa_ioc_nat_dma_one dma[0];
};
struct ipa_ioc_nat_pdn_entry {
uint8_t pdn_index;
uint32_t public_ip;
uint32_t src_metadata;
uint32_t dst_metadata;
};
struct ipa_ioc_vlan_iface_info {
char name[IPA_RESOURCE_NAME_MAX];
uint8_t vlan_id;
};
struct ipa_ioc_l2tp_vlan_mapping_info {
enum ipa_ip_type iptype;
char l2tp_iface_name[IPA_RESOURCE_NAME_MAX];
uint8_t l2tp_session_id;
char vlan_iface_name[IPA_RESOURCE_NAME_MAX];
};
struct ipa_msg_meta {
uint8_t msg_type;
uint8_t rsvd;
uint16_t msg_len;
};
struct ipa_wlan_msg {
char name[IPA_RESOURCE_NAME_MAX];
uint8_t mac_addr[IPA_MAC_ADDR_SIZE];
};
enum ipa_wlan_hdr_attrib_type {
WLAN_HDR_ATTRIB_MAC_ADDR,
WLAN_HDR_ATTRIB_STA_ID
};
struct ipa_wlan_hdr_attrib_val {
enum ipa_wlan_hdr_attrib_type attrib_type;
uint8_t offset;
union {
uint8_t mac_addr[IPA_MAC_ADDR_SIZE];
uint8_t sta_id;
} u;
};
struct ipa_wlan_msg_ex {
char name[IPA_RESOURCE_NAME_MAX];
uint8_t num_of_attribs;
struct ipa_wlan_hdr_attrib_val attribs[0];
};
struct ipa_ecm_msg {
char name[IPA_RESOURCE_NAME_MAX];
int ifindex;
};
struct ipa_wan_msg {
char upstream_ifname[IPA_RESOURCE_NAME_MAX];
char tethered_ifname[IPA_RESOURCE_NAME_MAX];
enum ipa_ip_type ip;
uint32_t ipv4_addr_gw;
uint32_t ipv6_addr_gw[IPA_WAN_MSG_IPv6_ADDR_GW_LEN];
};
struct ipa_ioc_rm_dependency {
enum ipa_rm_resource_name resource_name;
enum ipa_rm_resource_name depends_on_name;
};
struct ipa_ioc_generate_flt_eq {
enum ipa_ip_type ip;
struct ipa_rule_attrib attrib;
struct ipa_ipfltri_rule_eq eq_attrib;
};
struct ipa_ioc_write_qmapid {
enum ipa_client_type client;
uint8_t qmap_id;
};
enum ipacm_client_enum {
IPACM_CLIENT_USB = 1,
IPACM_CLIENT_WLAN,
IPACM_CLIENT_MAX
};
enum ipacm_per_client_device_type {
IPACM_CLIENT_DEVICE_TYPE_USB = 0,
IPACM_CLIENT_DEVICE_TYPE_WLAN = 1,
IPACM_CLIENT_DEVICE_TYPE_ETH = 2
};
#define IPACM_MAX_CLIENT_DEVICE_TYPES 3
struct ipa_lan_client_msg {
char lanIface[IPA_RESOURCE_NAME_MAX];
uint8_t mac[IPA_MAC_ADDR_SIZE];
};
struct ipa_lan_client {
uint8_t mac[IPA_MAC_ADDR_SIZE];
int8_t client_idx;
uint8_t inited;
};
struct ipa_tether_device_info {
int32_t ul_src_pipe;
uint8_t hdr_len;
uint32_t num_clients;
struct ipa_lan_client lan_client[IPA_MAX_NUM_HW_PATH_CLIENTS];
};
enum ipa_vlan_ifaces {
IPA_VLAN_IF_ETH,
IPA_VLAN_IF_RNDIS,
IPA_VLAN_IF_ECM
};
#define IPA_VLAN_IF_EMAC IPA_VLAN_IF_ETH
#define IPA_VLAN_IF_MAX (IPA_VLAN_IF_ECM + 1)
struct ipa_ioc_get_vlan_mode {
enum ipa_vlan_ifaces iface;
uint32_t is_vlan_mode;
};
#define IPA_IOC_ADD_HDR _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_HDR, struct ipa_ioc_add_hdr *)
#define IPA_IOC_DEL_HDR _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_HDR, struct ipa_ioc_del_hdr *)
#define IPA_IOC_ADD_RT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_RT_RULE, struct ipa_ioc_add_rt_rule *)
#define IPA_IOC_ADD_RT_RULE_EXT _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_RT_RULE_EXT, struct ipa_ioc_add_rt_rule_ext *)
#define IPA_IOC_ADD_RT_RULE_AFTER _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_RT_RULE_AFTER, struct ipa_ioc_add_rt_rule_after *)
#define IPA_IOC_DEL_RT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_RT_RULE, struct ipa_ioc_del_rt_rule *)
#define IPA_IOC_ADD_FLT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_FLT_RULE, struct ipa_ioc_add_flt_rule *)
#define IPA_IOC_ADD_FLT_RULE_AFTER _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_FLT_RULE_AFTER, struct ipa_ioc_add_flt_rule_after *)
#define IPA_IOC_DEL_FLT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_FLT_RULE, struct ipa_ioc_del_flt_rule *)
#define IPA_IOC_COMMIT_HDR _IO(IPA_IOC_MAGIC, IPA_IOCTL_COMMIT_HDR)
#define IPA_IOC_RESET_HDR _IO(IPA_IOC_MAGIC, IPA_IOCTL_RESET_HDR)
#define IPA_IOC_COMMIT_RT _IOW(IPA_IOC_MAGIC, IPA_IOCTL_COMMIT_RT, enum ipa_ip_type)
#define IPA_IOC_RESET_RT _IOW(IPA_IOC_MAGIC, IPA_IOCTL_RESET_RT, enum ipa_ip_type)
#define IPA_IOC_COMMIT_FLT _IOW(IPA_IOC_MAGIC, IPA_IOCTL_COMMIT_FLT, enum ipa_ip_type)
#define IPA_IOC_RESET_FLT _IOW(IPA_IOC_MAGIC, IPA_IOCTL_RESET_FLT, enum ipa_ip_type)
#define IPA_IOC_DUMP _IO(IPA_IOC_MAGIC, IPA_IOCTL_DUMP)
#define IPA_IOC_GET_RT_TBL _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GET_RT_TBL, struct ipa_ioc_get_rt_tbl *)
#define IPA_IOC_PUT_RT_TBL _IOW(IPA_IOC_MAGIC, IPA_IOCTL_PUT_RT_TBL, uint32_t)
#define IPA_IOC_COPY_HDR _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_COPY_HDR, struct ipa_ioc_copy_hdr *)
#define IPA_IOC_QUERY_INTF _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_INTF, struct ipa_ioc_query_intf *)
#define IPA_IOC_QUERY_INTF_TX_PROPS _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_INTF_TX_PROPS, struct ipa_ioc_query_intf_tx_props *)
#define IPA_IOC_QUERY_INTF_RX_PROPS _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_INTF_RX_PROPS, struct ipa_ioc_query_intf_rx_props *)
#define IPA_IOC_QUERY_INTF_EXT_PROPS _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_INTF_EXT_PROPS, struct ipa_ioc_query_intf_ext_props *)
#define IPA_IOC_GET_HDR _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GET_HDR, struct ipa_ioc_get_hdr *)
#define IPA_IOC_PUT_HDR _IOW(IPA_IOC_MAGIC, IPA_IOCTL_PUT_HDR, uint32_t)
#define IPA_IOC_ALLOC_NAT_MEM _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ALLOC_NAT_MEM, struct ipa_ioc_nat_alloc_mem *)
#define IPA_IOC_ALLOC_NAT_TABLE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ALLOC_NAT_TABLE, struct ipa_ioc_nat_ipv6ct_table_alloc *)
#define IPA_IOC_ALLOC_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ALLOC_IPV6CT_TABLE, struct ipa_ioc_nat_ipv6ct_table_alloc *)
#define IPA_IOC_V4_INIT_NAT _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_V4_INIT_NAT, struct ipa_ioc_v4_nat_init *)
#define IPA_IOC_INIT_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_INIT_IPV6CT_TABLE, struct ipa_ioc_ipv6ct_init *)
#define IPA_IOC_NAT_DMA _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_NAT_DMA, struct ipa_ioc_nat_dma_cmd *)
#define IPA_IOC_TABLE_DMA_CMD _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_TABLE_DMA_CMD, struct ipa_ioc_nat_dma_cmd *)
#define IPA_IOC_V4_DEL_NAT _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_V4_DEL_NAT, struct ipa_ioc_v4_nat_del *)
#define IPA_IOC_DEL_NAT_TABLE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_NAT_TABLE, struct ipa_ioc_nat_ipv6ct_table_del *)
#define IPA_IOC_DEL_IPV6CT_TABLE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_IPV6CT_TABLE, struct ipa_ioc_nat_ipv6ct_table_del *)
#define IPA_IOC_GET_NAT_OFFSET _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GET_NAT_OFFSET, uint32_t *)
#define IPA_IOC_NAT_MODIFY_PDN _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_NAT_MODIFY_PDN, struct ipa_ioc_nat_pdn_entry *)
#define IPA_IOC_SET_FLT _IOW(IPA_IOC_MAGIC, IPA_IOCTL_SET_FLT, uint32_t)
#define IPA_IOC_PULL_MSG _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_PULL_MSG, struct ipa_msg_meta *)
#define IPA_IOC_RM_ADD_DEPENDENCY _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_RM_ADD_DEPENDENCY, struct ipa_ioc_rm_dependency *)
#define IPA_IOC_RM_DEL_DEPENDENCY _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_RM_DEL_DEPENDENCY, struct ipa_ioc_rm_dependency *)
#define IPA_IOC_GENERATE_FLT_EQ _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GENERATE_FLT_EQ, struct ipa_ioc_generate_flt_eq *)
#define IPA_IOC_QUERY_EP_MAPPING _IOR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_EP_MAPPING, uint32_t)
#define IPA_IOC_QUERY_RT_TBL_INDEX _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_RT_TBL_INDEX, struct ipa_ioc_get_rt_tbl_indx *)
#define IPA_IOC_WRITE_QMAPID _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_WRITE_QMAPID, struct ipa_ioc_write_qmapid *)
#define IPA_IOC_MDFY_FLT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_MDFY_FLT_RULE, struct ipa_ioc_mdfy_flt_rule *)
#define IPA_IOC_MDFY_RT_RULE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_MDFY_RT_RULE, struct ipa_ioc_mdfy_rt_rule *)
#define IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_ADD _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_ADD, struct ipa_wan_msg *)
#define IPA_IOC_NOTIFY_WAN_UPSTREAM_ROUTE_DEL _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_NOTIFY_WAN_UPSTREAM_ROUTE_DEL, struct ipa_wan_msg *)
#define IPA_IOC_NOTIFY_WAN_EMBMS_CONNECTED _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_NOTIFY_WAN_EMBMS_CONNECTED, struct ipa_wan_msg *)
#define IPA_IOC_ADD_HDR_PROC_CTX _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_HDR_PROC_CTX, struct ipa_ioc_add_hdr_proc_ctx *)
#define IPA_IOC_DEL_HDR_PROC_CTX _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_HDR_PROC_CTX, struct ipa_ioc_del_hdr_proc_ctx *)
#define IPA_IOC_GET_HW_VERSION _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GET_HW_VERSION, enum ipa_hw_type *)
#define IPA_IOC_ADD_VLAN_IFACE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_VLAN_IFACE, struct ipa_ioc_vlan_iface_info *)
#define IPA_IOC_DEL_VLAN_IFACE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_VLAN_IFACE, struct ipa_ioc_vlan_iface_info *)
#define IPA_IOC_ADD_L2TP_VLAN_MAPPING _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_ADD_L2TP_VLAN_MAPPING, struct ipa_ioc_l2tp_vlan_mapping_info *)
#define IPA_IOC_DEL_L2TP_VLAN_MAPPING _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_DEL_L2TP_VLAN_MAPPING, struct ipa_ioc_l2tp_vlan_mapping_info *)
#define IPA_IOC_CLEANUP _IO(IPA_IOC_MAGIC, IPA_IOCTL_CLEANUP)
#define IPA_IOC_QUERY_WLAN_CLIENT _IO(IPA_IOC_MAGIC, IPA_IOCTL_QUERY_WLAN_CLIENT)
#define IPA_IOC_GET_VLAN_MODE _IOWR(IPA_IOC_MAGIC, IPA_IOCTL_GET_VLAN_MODE, struct ipa_ioc_get_vlan_mode *)
#define TETH_BRIDGE_IOC_MAGIC 0xCE
#define TETH_BRIDGE_IOCTL_SET_BRIDGE_MODE 0
#define TETH_BRIDGE_IOCTL_SET_AGGR_PARAMS 1
#define TETH_BRIDGE_IOCTL_GET_AGGR_PARAMS 2
#define TETH_BRIDGE_IOCTL_GET_AGGR_CAPABILITIES 3
#define TETH_BRIDGE_IOCTL_MAX 4
enum teth_link_protocol_type {
TETH_LINK_PROTOCOL_IP,
TETH_LINK_PROTOCOL_ETHERNET,
TETH_LINK_PROTOCOL_MAX,
};
enum teth_aggr_protocol_type {
TETH_AGGR_PROTOCOL_NONE,
TETH_AGGR_PROTOCOL_MBIM,
TETH_AGGR_PROTOCOL_TLP,
TETH_AGGR_PROTOCOL_MAX,
};
struct teth_aggr_params_link {
enum teth_aggr_protocol_type aggr_prot;
uint32_t max_transfer_size_byte;
uint32_t max_datagrams;
};
struct teth_aggr_params {
struct teth_aggr_params_link ul;
struct teth_aggr_params_link dl;
};
struct teth_aggr_capabilities {
uint16_t num_protocols;
struct teth_aggr_params_link prot_caps[0];
};
struct teth_ioc_set_bridge_mode {
enum teth_link_protocol_type link_protocol;
uint16_t lcid;
};
struct teth_ioc_aggr_params {
struct teth_aggr_params aggr_params;
uint16_t lcid;
};
#define TETH_BRIDGE_IOC_SET_BRIDGE_MODE _IOW(TETH_BRIDGE_IOC_MAGIC, TETH_BRIDGE_IOCTL_SET_BRIDGE_MODE, struct teth_ioc_set_bridge_mode *)
#define TETH_BRIDGE_IOC_SET_AGGR_PARAMS _IOW(TETH_BRIDGE_IOC_MAGIC, TETH_BRIDGE_IOCTL_SET_AGGR_PARAMS, struct teth_ioc_aggr_params *)
#define TETH_BRIDGE_IOC_GET_AGGR_PARAMS _IOR(TETH_BRIDGE_IOC_MAGIC, TETH_BRIDGE_IOCTL_GET_AGGR_PARAMS, struct teth_ioc_aggr_params *)
#define TETH_BRIDGE_IOC_GET_AGGR_CAPABILITIES _IOWR(TETH_BRIDGE_IOC_MAGIC, TETH_BRIDGE_IOCTL_GET_AGGR_CAPABILITIES, struct teth_aggr_capabilities *)
#define ODU_BRIDGE_IOC_MAGIC 0xCD
#define ODU_BRIDGE_IOCTL_SET_MODE 0
#define ODU_BRIDGE_IOCTL_SET_LLV6_ADDR 1
#define ODU_BRIDGE_IOCTL_MAX 2
enum odu_bridge_mode {
ODU_BRIDGE_MODE_ROUTER,
ODU_BRIDGE_MODE_BRIDGE,
ODU_BRIDGE_MODE_MAX,
};
#define ODU_BRIDGE_IOC_SET_MODE _IOW(ODU_BRIDGE_IOC_MAGIC, ODU_BRIDGE_IOCTL_SET_MODE, enum odu_bridge_mode)
#define ODU_BRIDGE_IOC_SET_LLV6_ADDR _IOW(ODU_BRIDGE_IOC_MAGIC, ODU_BRIDGE_IOCTL_SET_LLV6_ADDR, struct in6_addr *)
#endif

773
sdm710/kernel-headers/linux/msm_kgsl.h
View File

@@ -1,773 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _MSM_KGSL_H
#define _MSM_KGSL_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define KGSL_VERSION_MAJOR 3
#define KGSL_VERSION_MINOR 14
#define KGSL_CONTEXT_SAVE_GMEM 0x00000001
#define KGSL_CONTEXT_NO_GMEM_ALLOC 0x00000002
#define KGSL_CONTEXT_SUBMIT_IB_LIST 0x00000004
#define KGSL_CONTEXT_CTX_SWITCH 0x00000008
#define KGSL_CONTEXT_PREAMBLE 0x00000010
#define KGSL_CONTEXT_TRASH_STATE 0x00000020
#define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040
#define KGSL_CONTEXT_USER_GENERATED_TS 0x00000080
#define KGSL_CONTEXT_END_OF_FRAME 0x00000100
#define KGSL_CONTEXT_NO_FAULT_TOLERANCE 0x00000200
#define KGSL_CONTEXT_SYNC 0x00000400
#define KGSL_CONTEXT_PWR_CONSTRAINT 0x00000800
#define KGSL_CONTEXT_PRIORITY_MASK 0x0000F000
#define KGSL_CONTEXT_PRIORITY_SHIFT 12
#define KGSL_CONTEXT_PRIORITY_UNDEF 0
#define KGSL_CONTEXT_IFH_NOP 0x00010000
#define KGSL_CONTEXT_SECURE 0x00020000
#define KGSL_CONTEXT_NO_SNAPSHOT 0x00040000
#define KGSL_CONTEXT_SPARSE 0x00080000
#define KGSL_CONTEXT_PREEMPT_STYLE_MASK 0x0E000000
#define KGSL_CONTEXT_PREEMPT_STYLE_SHIFT 25
#define KGSL_CONTEXT_PREEMPT_STYLE_DEFAULT 0x0
#define KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER 0x1
#define KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN 0x2
#define KGSL_CONTEXT_TYPE_MASK 0x01F00000
#define KGSL_CONTEXT_TYPE_SHIFT 20
#define KGSL_CONTEXT_TYPE_ANY 0
#define KGSL_CONTEXT_TYPE_GL 1
#define KGSL_CONTEXT_TYPE_CL 2
#define KGSL_CONTEXT_TYPE_C2D 3
#define KGSL_CONTEXT_TYPE_RS 4
#define KGSL_CONTEXT_TYPE_UNKNOWN 0x1E
#define KGSL_CONTEXT_INVALIDATE_ON_FAULT 0x10000000
#define KGSL_CONTEXT_INVALID 0xffffffff
#define KGSL_CMDBATCH_MEMLIST 0x00000001
#define KGSL_CMDBATCH_MARKER 0x00000002
#define KGSL_CMDBATCH_SUBMIT_IB_LIST KGSL_CONTEXT_SUBMIT_IB_LIST
#define KGSL_CMDBATCH_CTX_SWITCH KGSL_CONTEXT_CTX_SWITCH
#define KGSL_CMDBATCH_PROFILING 0x00000010
#define KGSL_CMDBATCH_PROFILING_KTIME 0x00000020
#define KGSL_CMDBATCH_END_OF_FRAME KGSL_CONTEXT_END_OF_FRAME
#define KGSL_CMDBATCH_SYNC KGSL_CONTEXT_SYNC
#define KGSL_CMDBATCH_PWR_CONSTRAINT KGSL_CONTEXT_PWR_CONSTRAINT
#define KGSL_CMDBATCH_SPARSE 0x1000
#define KGSL_CMDLIST_IB 0x00000001U
#define KGSL_CMDLIST_CTXTSWITCH_PREAMBLE 0x00000002U
#define KGSL_CMDLIST_IB_PREAMBLE 0x00000004U
#define KGSL_OBJLIST_MEMOBJ 0x00000008U
#define KGSL_OBJLIST_PROFILE 0x00000010U
#define KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP 0
#define KGSL_CMD_SYNCPOINT_TYPE_FENCE 1
#define KGSL_MEMFLAGS_SECURE 0x00000008ULL
#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000U
#define KGSL_MEMFLAGS_GPUWRITEONLY 0x02000000U
#define KGSL_MEMFLAGS_FORCE_32BIT 0x100000000ULL
#define KGSL_SPARSE_BIND_MULTIPLE_TO_PHYS 0x400000000ULL
#define KGSL_SPARSE_BIND 0x1ULL
#define KGSL_SPARSE_UNBIND 0x2ULL
#define KGSL_CACHEMODE_MASK 0x0C000000U
#define KGSL_CACHEMODE_SHIFT 26
#define KGSL_CACHEMODE_WRITECOMBINE 0
#define KGSL_CACHEMODE_UNCACHED 1
#define KGSL_CACHEMODE_WRITETHROUGH 2
#define KGSL_CACHEMODE_WRITEBACK 3
#define KGSL_MEMFLAGS_USE_CPU_MAP 0x10000000ULL
#define KGSL_MEMFLAGS_SPARSE_PHYS 0x20000000ULL
#define KGSL_MEMFLAGS_SPARSE_VIRT 0x40000000ULL
#define KGSL_MEMFLAGS_IOCOHERENT 0x80000000ULL
#define KGSL_MEMTYPE_MASK 0x0000FF00
#define KGSL_MEMTYPE_SHIFT 8
#define KGSL_MEMTYPE_OBJECTANY 0
#define KGSL_MEMTYPE_FRAMEBUFFER 1
#define KGSL_MEMTYPE_RENDERBUFFER 2
#define KGSL_MEMTYPE_ARRAYBUFFER 3
#define KGSL_MEMTYPE_ELEMENTARRAYBUFFER 4
#define KGSL_MEMTYPE_VERTEXARRAYBUFFER 5
#define KGSL_MEMTYPE_TEXTURE 6
#define KGSL_MEMTYPE_SURFACE 7
#define KGSL_MEMTYPE_EGL_SURFACE 8
#define KGSL_MEMTYPE_GL 9
#define KGSL_MEMTYPE_CL 10
#define KGSL_MEMTYPE_CL_BUFFER_MAP 11
#define KGSL_MEMTYPE_CL_BUFFER_NOMAP 12
#define KGSL_MEMTYPE_CL_IMAGE_MAP 13
#define KGSL_MEMTYPE_CL_IMAGE_NOMAP 14
#define KGSL_MEMTYPE_CL_KERNEL_STACK 15
#define KGSL_MEMTYPE_COMMAND 16
#define KGSL_MEMTYPE_2D 17
#define KGSL_MEMTYPE_EGL_IMAGE 18
#define KGSL_MEMTYPE_EGL_SHADOW 19
#define KGSL_MEMTYPE_MULTISAMPLE 20
#define KGSL_MEMTYPE_KERNEL 255
#define KGSL_MEMALIGN_MASK 0x00FF0000
#define KGSL_MEMALIGN_SHIFT 16
enum kgsl_user_mem_type {
KGSL_USER_MEM_TYPE_PMEM = 0x00000000,
KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001,
KGSL_USER_MEM_TYPE_ADDR = 0x00000002,
KGSL_USER_MEM_TYPE_ION = 0x00000003,
KGSL_USER_MEM_TYPE_DMABUF = 0x00000003,
KGSL_USER_MEM_TYPE_MAX = 0x00000007,
};
#define KGSL_MEMFLAGS_USERMEM_MASK 0x000000e0
#define KGSL_MEMFLAGS_USERMEM_SHIFT 5
#define KGSL_USERMEM_FLAG(x) (((x) + 1) << KGSL_MEMFLAGS_USERMEM_SHIFT)
#define KGSL_MEMFLAGS_NOT_USERMEM 0
#define KGSL_MEMFLAGS_USERMEM_PMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_PMEM)
#define KGSL_MEMFLAGS_USERMEM_ASHMEM KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ASHMEM)
#define KGSL_MEMFLAGS_USERMEM_ADDR KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ADDR)
#define KGSL_MEMFLAGS_USERMEM_ION KGSL_USERMEM_FLAG(KGSL_USER_MEM_TYPE_ION)
#define KGSL_FLAGS_NORMALMODE 0x00000000
#define KGSL_FLAGS_SAFEMODE 0x00000001
#define KGSL_FLAGS_INITIALIZED0 0x00000002
#define KGSL_FLAGS_INITIALIZED 0x00000004
#define KGSL_FLAGS_STARTED 0x00000008
#define KGSL_FLAGS_ACTIVE 0x00000010
#define KGSL_FLAGS_RESERVED0 0x00000020
#define KGSL_FLAGS_RESERVED1 0x00000040
#define KGSL_FLAGS_RESERVED2 0x00000080
#define KGSL_FLAGS_SOFT_RESET 0x00000100
#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200
#define KGSL_SYNCOBJ_SERVER_TIMEOUT 2000
#define KGSL_UBWC_NONE 0
#define KGSL_UBWC_1_0 1
#define KGSL_UBWC_2_0 2
#define KGSL_UBWC_3_0 3
enum kgsl_ctx_reset_stat {
KGSL_CTX_STAT_NO_ERROR = 0x00000000,
KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001,
KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002,
KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003
};
#define KGSL_CONVERT_TO_MBPS(val) (val * 1000 * 1000U)
enum kgsl_deviceid {
KGSL_DEVICE_3D0 = 0x00000000,
KGSL_DEVICE_MAX
};
struct kgsl_devinfo {
unsigned int device_id;
unsigned int chip_id;
unsigned int mmu_enabled;
unsigned long gmem_gpubaseaddr;
unsigned int gpu_id;
size_t gmem_sizebytes;
};
struct kgsl_devmemstore {
__volatile__ unsigned int soptimestamp;
unsigned int sbz;
__volatile__ unsigned int eoptimestamp;
unsigned int sbz2;
__volatile__ unsigned int preempted;
unsigned int sbz3;
__volatile__ unsigned int ref_wait_ts;
unsigned int sbz4;
unsigned int current_context;
unsigned int sbz5;
};
#define KGSL_MEMSTORE_OFFSET(ctxt_id,field) ((ctxt_id) * sizeof(struct kgsl_devmemstore) + offsetof(struct kgsl_devmemstore, field))
enum kgsl_timestamp_type {
KGSL_TIMESTAMP_CONSUMED = 0x00000001,
KGSL_TIMESTAMP_RETIRED = 0x00000002,
KGSL_TIMESTAMP_QUEUED = 0x00000003,
};
#define KGSL_PROP_DEVICE_INFO 0x1
#define KGSL_PROP_DEVICE_SHADOW 0x2
#define KGSL_PROP_DEVICE_POWER 0x3
#define KGSL_PROP_SHMEM 0x4
#define KGSL_PROP_SHMEM_APERTURES 0x5
#define KGSL_PROP_MMU_ENABLE 0x6
#define KGSL_PROP_INTERRUPT_WAITS 0x7
#define KGSL_PROP_VERSION 0x8
#define KGSL_PROP_GPU_RESET_STAT 0x9
#define KGSL_PROP_PWRCTRL 0xE
#define KGSL_PROP_PWR_CONSTRAINT 0x12
#define KGSL_PROP_UCHE_GMEM_VADDR 0x13
#define KGSL_PROP_SP_GENERIC_MEM 0x14
#define KGSL_PROP_UCODE_VERSION 0x15
#define KGSL_PROP_GPMU_VERSION 0x16
#define KGSL_PROP_HIGHEST_BANK_BIT 0x17
#define KGSL_PROP_DEVICE_BITNESS 0x18
#define KGSL_PROP_DEVICE_QDSS_STM 0x19
#define KGSL_PROP_MIN_ACCESS_LENGTH 0x1A
#define KGSL_PROP_UBWC_MODE 0x1B
#define KGSL_PROP_DEVICE_QTIMER 0x20
#define KGSL_PROP_L3_PWR_CONSTRAINT 0x22
struct kgsl_shadowprop {
unsigned long gpuaddr;
size_t size;
unsigned int flags;
};
struct kgsl_qdss_stm_prop {
uint64_t gpuaddr;
uint64_t size;
};
struct kgsl_qtimer_prop {
uint64_t gpuaddr;
uint64_t size;
};
struct kgsl_version {
unsigned int drv_major;
unsigned int drv_minor;
unsigned int dev_major;
unsigned int dev_minor;
};
struct kgsl_sp_generic_mem {
uint64_t local;
uint64_t pvt;
};
struct kgsl_ucode_version {
unsigned int pfp;
unsigned int pm4;
};
struct kgsl_gpmu_version {
unsigned int major;
unsigned int minor;
unsigned int features;
};
#define KGSL_PERFCOUNTER_GROUP_CP 0x0
#define KGSL_PERFCOUNTER_GROUP_RBBM 0x1
#define KGSL_PERFCOUNTER_GROUP_PC 0x2
#define KGSL_PERFCOUNTER_GROUP_VFD 0x3
#define KGSL_PERFCOUNTER_GROUP_HLSQ 0x4
#define KGSL_PERFCOUNTER_GROUP_VPC 0x5
#define KGSL_PERFCOUNTER_GROUP_TSE 0x6
#define KGSL_PERFCOUNTER_GROUP_RAS 0x7
#define KGSL_PERFCOUNTER_GROUP_UCHE 0x8
#define KGSL_PERFCOUNTER_GROUP_TP 0x9
#define KGSL_PERFCOUNTER_GROUP_SP 0xA
#define KGSL_PERFCOUNTER_GROUP_RB 0xB
#define KGSL_PERFCOUNTER_GROUP_PWR 0xC
#define KGSL_PERFCOUNTER_GROUP_VBIF 0xD
#define KGSL_PERFCOUNTER_GROUP_VBIF_PWR 0xE
#define KGSL_PERFCOUNTER_GROUP_MH 0xF
#define KGSL_PERFCOUNTER_GROUP_PA_SU 0x10
#define KGSL_PERFCOUNTER_GROUP_SQ 0x11
#define KGSL_PERFCOUNTER_GROUP_SX 0x12
#define KGSL_PERFCOUNTER_GROUP_TCF 0x13
#define KGSL_PERFCOUNTER_GROUP_TCM 0x14
#define KGSL_PERFCOUNTER_GROUP_TCR 0x15
#define KGSL_PERFCOUNTER_GROUP_L2 0x16
#define KGSL_PERFCOUNTER_GROUP_VSC 0x17
#define KGSL_PERFCOUNTER_GROUP_CCU 0x18
#define KGSL_PERFCOUNTER_GROUP_LRZ 0x19
#define KGSL_PERFCOUNTER_GROUP_CMP 0x1A
#define KGSL_PERFCOUNTER_GROUP_ALWAYSON 0x1B
#define KGSL_PERFCOUNTER_GROUP_SP_PWR 0x1C
#define KGSL_PERFCOUNTER_GROUP_TP_PWR 0x1D
#define KGSL_PERFCOUNTER_GROUP_RB_PWR 0x1E
#define KGSL_PERFCOUNTER_GROUP_CCU_PWR 0x1F
#define KGSL_PERFCOUNTER_GROUP_UCHE_PWR 0x20
#define KGSL_PERFCOUNTER_GROUP_CP_PWR 0x21
#define KGSL_PERFCOUNTER_GROUP_GPMU_PWR 0x22
#define KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR 0x23
#define KGSL_PERFCOUNTER_GROUP_MAX 0x24
#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF
#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE
struct kgsl_ibdesc {
unsigned long gpuaddr;
unsigned long __pad;
size_t sizedwords;
unsigned int ctrl;
};
struct kgsl_cmdbatch_profiling_buffer {
uint64_t wall_clock_s;
uint64_t wall_clock_ns;
uint64_t gpu_ticks_queued;
uint64_t gpu_ticks_submitted;
uint64_t gpu_ticks_retired;
};
#define KGSL_IOC_TYPE 0x09
struct kgsl_device_getproperty {
unsigned int type;
void * value;
size_t sizebytes;
};
#define IOCTL_KGSL_DEVICE_GETPROPERTY _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty)
struct kgsl_device_waittimestamp {
unsigned int timestamp;
unsigned int timeout;
};
#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp)
struct kgsl_device_waittimestamp_ctxtid {
unsigned int context_id;
unsigned int timestamp;
unsigned int timeout;
};
#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid)
struct kgsl_ringbuffer_issueibcmds {
unsigned int drawctxt_id;
unsigned long ibdesc_addr;
unsigned int numibs;
unsigned int timestamp;
unsigned int flags;
};
#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds)
struct kgsl_cmdstream_readtimestamp {
unsigned int type;
unsigned int timestamp;
};
#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp)
struct kgsl_cmdstream_freememontimestamp {
unsigned long gpuaddr;
unsigned int type;
unsigned int timestamp;
};
#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp)
struct kgsl_drawctxt_create {
unsigned int flags;
unsigned int drawctxt_id;
};
#define IOCTL_KGSL_DRAWCTXT_CREATE _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create)
struct kgsl_drawctxt_destroy {
unsigned int drawctxt_id;
};
#define IOCTL_KGSL_DRAWCTXT_DESTROY _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy)
struct kgsl_map_user_mem {
int fd;
unsigned long gpuaddr;
size_t len;
size_t offset;
unsigned long hostptr;
enum kgsl_user_mem_type memtype;
unsigned int flags;
};
#define IOCTL_KGSL_MAP_USER_MEM _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem)
struct kgsl_cmdstream_readtimestamp_ctxtid {
unsigned int context_id;
unsigned int type;
unsigned int timestamp;
};
#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid)
struct kgsl_cmdstream_freememontimestamp_ctxtid {
unsigned int context_id;
unsigned long gpuaddr;
unsigned int type;
unsigned int timestamp;
};
#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID _IOW(KGSL_IOC_TYPE, 0x17, struct kgsl_cmdstream_freememontimestamp_ctxtid)
struct kgsl_sharedmem_from_pmem {
int pmem_fd;
unsigned long gpuaddr;
unsigned int len;
unsigned int offset;
};
#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem)
struct kgsl_sharedmem_free {
unsigned long gpuaddr;
};
#define IOCTL_KGSL_SHAREDMEM_FREE _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free)
struct kgsl_cff_user_event {
unsigned char cff_opcode;
unsigned int op1;
unsigned int op2;
unsigned int op3;
unsigned int op4;
unsigned int op5;
unsigned int __pad[2];
};
#define IOCTL_KGSL_CFF_USER_EVENT _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event)
struct kgsl_gmem_desc {
unsigned int x;
unsigned int y;
unsigned int width;
unsigned int height;
unsigned int pitch;
};
struct kgsl_buffer_desc {
void * hostptr;
unsigned long gpuaddr;
int size;
unsigned int format;
unsigned int pitch;
unsigned int enabled;
};
struct kgsl_bind_gmem_shadow {
unsigned int drawctxt_id;
struct kgsl_gmem_desc gmem_desc;
unsigned int shadow_x;
unsigned int shadow_y;
struct kgsl_buffer_desc shadow_buffer;
unsigned int buffer_id;
};
#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow)
struct kgsl_sharedmem_from_vmalloc {
unsigned long gpuaddr;
unsigned int hostptr;
unsigned int flags;
};
#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc)
#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free)
struct kgsl_drawctxt_set_bin_base_offset {
unsigned int drawctxt_id;
unsigned int offset;
};
#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset)
enum kgsl_cmdwindow_type {
KGSL_CMDWINDOW_MIN = 0x00000000,
KGSL_CMDWINDOW_2D = 0x00000000,
KGSL_CMDWINDOW_3D = 0x00000001,
KGSL_CMDWINDOW_MMU = 0x00000002,
KGSL_CMDWINDOW_ARBITER = 0x000000FF,
KGSL_CMDWINDOW_MAX = 0x000000FF,
};
struct kgsl_cmdwindow_write {
enum kgsl_cmdwindow_type target;
unsigned int addr;
unsigned int data;
};
#define IOCTL_KGSL_CMDWINDOW_WRITE _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write)
struct kgsl_gpumem_alloc {
unsigned long gpuaddr;
size_t size;
unsigned int flags;
};
#define IOCTL_KGSL_GPUMEM_ALLOC _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc)
struct kgsl_cff_syncmem {
unsigned long gpuaddr;
size_t len;
unsigned int __pad[2];
};
#define IOCTL_KGSL_CFF_SYNCMEM _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem)
struct kgsl_timestamp_event {
int type;
unsigned int timestamp;
unsigned int context_id;
void * priv;
size_t len;
};
#define IOCTL_KGSL_TIMESTAMP_EVENT_OLD _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event)
#define KGSL_TIMESTAMP_EVENT_GENLOCK 1
struct kgsl_timestamp_event_genlock {
int handle;
};
#define KGSL_TIMESTAMP_EVENT_FENCE 2
struct kgsl_timestamp_event_fence {
int fence_fd;
};
#define IOCTL_KGSL_SETPROPERTY _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty)
#define IOCTL_KGSL_TIMESTAMP_EVENT _IOWR(KGSL_IOC_TYPE, 0x33, struct kgsl_timestamp_event)
struct kgsl_gpumem_alloc_id {
unsigned int id;
unsigned int flags;
size_t size;
size_t mmapsize;
unsigned long gpuaddr;
unsigned long __pad[2];
};
#define IOCTL_KGSL_GPUMEM_ALLOC_ID _IOWR(KGSL_IOC_TYPE, 0x34, struct kgsl_gpumem_alloc_id)
struct kgsl_gpumem_free_id {
unsigned int id;
unsigned int __pad;
};
#define IOCTL_KGSL_GPUMEM_FREE_ID _IOWR(KGSL_IOC_TYPE, 0x35, struct kgsl_gpumem_free_id)
struct kgsl_gpumem_get_info {
unsigned long gpuaddr;
unsigned int id;
unsigned int flags;
size_t size;
size_t mmapsize;
unsigned long useraddr;
unsigned long __pad[4];
};
#define IOCTL_KGSL_GPUMEM_GET_INFO _IOWR(KGSL_IOC_TYPE, 0x36, struct kgsl_gpumem_get_info)
struct kgsl_gpumem_sync_cache {
unsigned long gpuaddr;
unsigned int id;
unsigned int op;
size_t offset;
size_t length;
};
#define KGSL_GPUMEM_CACHE_CLEAN (1 << 0)
#define KGSL_GPUMEM_CACHE_TO_GPU KGSL_GPUMEM_CACHE_CLEAN
#define KGSL_GPUMEM_CACHE_INV (1 << 1)
#define KGSL_GPUMEM_CACHE_FROM_GPU KGSL_GPUMEM_CACHE_INV
#define KGSL_GPUMEM_CACHE_FLUSH (KGSL_GPUMEM_CACHE_CLEAN | KGSL_GPUMEM_CACHE_INV)
#define KGSL_GPUMEM_CACHE_RANGE (1 << 31U)
#define IOCTL_KGSL_GPUMEM_SYNC_CACHE _IOW(KGSL_IOC_TYPE, 0x37, struct kgsl_gpumem_sync_cache)
struct kgsl_perfcounter_get {
unsigned int groupid;
unsigned int countable;
unsigned int offset;
unsigned int offset_hi;
unsigned int __pad;
};
#define IOCTL_KGSL_PERFCOUNTER_GET _IOWR(KGSL_IOC_TYPE, 0x38, struct kgsl_perfcounter_get)
struct kgsl_perfcounter_put {
unsigned int groupid;
unsigned int countable;
unsigned int __pad[2];
};
#define IOCTL_KGSL_PERFCOUNTER_PUT _IOW(KGSL_IOC_TYPE, 0x39, struct kgsl_perfcounter_put)
struct kgsl_perfcounter_query {
unsigned int groupid;
unsigned int * countables;
unsigned int count;
unsigned int max_counters;
unsigned int __pad[2];
};
#define IOCTL_KGSL_PERFCOUNTER_QUERY _IOWR(KGSL_IOC_TYPE, 0x3A, struct kgsl_perfcounter_query)
struct kgsl_perfcounter_read_group {
unsigned int groupid;
unsigned int countable;
unsigned long long value;
};
struct kgsl_perfcounter_read {
struct kgsl_perfcounter_read_group * reads;
unsigned int count;
unsigned int __pad[2];
};
#define IOCTL_KGSL_PERFCOUNTER_READ _IOWR(KGSL_IOC_TYPE, 0x3B, struct kgsl_perfcounter_read)
struct kgsl_gpumem_sync_cache_bulk {
unsigned int * id_list;
unsigned int count;
unsigned int op;
unsigned int __pad[2];
};
#define IOCTL_KGSL_GPUMEM_SYNC_CACHE_BULK _IOWR(KGSL_IOC_TYPE, 0x3C, struct kgsl_gpumem_sync_cache_bulk)
struct kgsl_cmd_syncpoint_timestamp {
unsigned int context_id;
unsigned int timestamp;
};
struct kgsl_cmd_syncpoint_fence {
int fd;
};
struct kgsl_cmd_syncpoint {
int type;
void * priv;
size_t size;
};
#define KGSL_IBDESC_MEMLIST 0x1
#define KGSL_IBDESC_PROFILING_BUFFER 0x2
struct kgsl_submit_commands {
unsigned int context_id;
unsigned int flags;
struct kgsl_ibdesc * cmdlist;
unsigned int numcmds;
struct kgsl_cmd_syncpoint * synclist;
unsigned int numsyncs;
unsigned int timestamp;
unsigned int __pad[4];
};
#define IOCTL_KGSL_SUBMIT_COMMANDS _IOWR(KGSL_IOC_TYPE, 0x3D, struct kgsl_submit_commands)
struct kgsl_device_constraint {
unsigned int type;
unsigned int context_id;
void * data;
size_t size;
};
#define KGSL_CONSTRAINT_NONE 0
#define KGSL_CONSTRAINT_PWRLEVEL 1
#define KGSL_CONSTRAINT_L3_NONE 2
#define KGSL_CONSTRAINT_L3_PWRLEVEL 3
#define KGSL_CONSTRAINT_PWR_MIN 0
#define KGSL_CONSTRAINT_PWR_MAX 1
#define KGSL_CONSTRAINT_L3_PWR_MED 0
#define KGSL_CONSTRAINT_L3_PWR_MAX 1
struct kgsl_device_constraint_pwrlevel {
unsigned int level;
};
struct kgsl_syncsource_create {
unsigned int id;
unsigned int __pad[3];
};
#define IOCTL_KGSL_SYNCSOURCE_CREATE _IOWR(KGSL_IOC_TYPE, 0x40, struct kgsl_syncsource_create)
struct kgsl_syncsource_destroy {
unsigned int id;
unsigned int __pad[3];
};
#define IOCTL_KGSL_SYNCSOURCE_DESTROY _IOWR(KGSL_IOC_TYPE, 0x41, struct kgsl_syncsource_destroy)
struct kgsl_syncsource_create_fence {
unsigned int id;
int fence_fd;
unsigned int __pad[4];
};
#define IOCTL_KGSL_SYNCSOURCE_CREATE_FENCE _IOWR(KGSL_IOC_TYPE, 0x42, struct kgsl_syncsource_create_fence)
struct kgsl_syncsource_signal_fence {
unsigned int id;
int fence_fd;
unsigned int __pad[4];
};
#define IOCTL_KGSL_SYNCSOURCE_SIGNAL_FENCE _IOWR(KGSL_IOC_TYPE, 0x43, struct kgsl_syncsource_signal_fence)
struct kgsl_cff_sync_gpuobj {
uint64_t offset;
uint64_t length;
unsigned int id;
};
#define IOCTL_KGSL_CFF_SYNC_GPUOBJ _IOW(KGSL_IOC_TYPE, 0x44, struct kgsl_cff_sync_gpuobj)
struct kgsl_gpuobj_alloc {
uint64_t size;
uint64_t flags;
uint64_t va_len;
uint64_t mmapsize;
unsigned int id;
unsigned int metadata_len;
uint64_t metadata;
};
#define KGSL_GPUOBJ_ALLOC_METADATA_MAX 64
#define IOCTL_KGSL_GPUOBJ_ALLOC _IOWR(KGSL_IOC_TYPE, 0x45, struct kgsl_gpuobj_alloc)
struct kgsl_gpuobj_free {
uint64_t flags;
uint64_t priv;
unsigned int id;
unsigned int type;
unsigned int len;
};
#define KGSL_GPUOBJ_FREE_ON_EVENT 1
#define KGSL_GPU_EVENT_TIMESTAMP 1
#define KGSL_GPU_EVENT_FENCE 2
struct kgsl_gpu_event_timestamp {
unsigned int context_id;
unsigned int timestamp;
};
struct kgsl_gpu_event_fence {
int fd;
};
#define IOCTL_KGSL_GPUOBJ_FREE _IOW(KGSL_IOC_TYPE, 0x46, struct kgsl_gpuobj_free)
struct kgsl_gpuobj_info {
uint64_t gpuaddr;
uint64_t flags;
uint64_t size;
uint64_t va_len;
uint64_t va_addr;
unsigned int id;
};
#define IOCTL_KGSL_GPUOBJ_INFO _IOWR(KGSL_IOC_TYPE, 0x47, struct kgsl_gpuobj_info)
struct kgsl_gpuobj_import {
uint64_t priv;
uint64_t priv_len;
uint64_t flags;
unsigned int type;
unsigned int id;
};
struct kgsl_gpuobj_import_dma_buf {
int fd;
};
struct kgsl_gpuobj_import_useraddr {
uint64_t virtaddr;
};
#define IOCTL_KGSL_GPUOBJ_IMPORT _IOWR(KGSL_IOC_TYPE, 0x48, struct kgsl_gpuobj_import)
struct kgsl_gpuobj_sync_obj {
uint64_t offset;
uint64_t length;
unsigned int id;
unsigned int op;
};
struct kgsl_gpuobj_sync {
uint64_t objs;
unsigned int obj_len;
unsigned int count;
};
#define IOCTL_KGSL_GPUOBJ_SYNC _IOW(KGSL_IOC_TYPE, 0x49, struct kgsl_gpuobj_sync)
struct kgsl_command_object {
uint64_t offset;
uint64_t gpuaddr;
uint64_t size;
unsigned int flags;
unsigned int id;
};
struct kgsl_command_syncpoint {
uint64_t priv;
uint64_t size;
unsigned int type;
};
struct kgsl_gpu_command {
uint64_t flags;
uint64_t cmdlist;
unsigned int cmdsize;
unsigned int numcmds;
uint64_t objlist;
unsigned int objsize;
unsigned int numobjs;
uint64_t synclist;
unsigned int syncsize;
unsigned int numsyncs;
unsigned int context_id;
unsigned int timestamp;
};
#define IOCTL_KGSL_GPU_COMMAND _IOWR(KGSL_IOC_TYPE, 0x4A, struct kgsl_gpu_command)
struct kgsl_preemption_counters_query {
uint64_t counters;
unsigned int size_user;
unsigned int size_priority_level;
unsigned int max_priority_level;
};
#define IOCTL_KGSL_PREEMPTIONCOUNTER_QUERY _IOWR(KGSL_IOC_TYPE, 0x4B, struct kgsl_preemption_counters_query)
#define KGSL_GPUOBJ_SET_INFO_METADATA (1 << 0)
#define KGSL_GPUOBJ_SET_INFO_TYPE (1 << 1)
struct kgsl_gpuobj_set_info {
uint64_t flags;
uint64_t metadata;
unsigned int id;
unsigned int metadata_len;
unsigned int type;
};
#define IOCTL_KGSL_GPUOBJ_SET_INFO _IOW(KGSL_IOC_TYPE, 0x4C, struct kgsl_gpuobj_set_info)
struct kgsl_sparse_phys_alloc {
uint64_t size;
uint64_t pagesize;
uint64_t flags;
unsigned int id;
};
#define IOCTL_KGSL_SPARSE_PHYS_ALLOC _IOWR(KGSL_IOC_TYPE, 0x50, struct kgsl_sparse_phys_alloc)
struct kgsl_sparse_phys_free {
unsigned int id;
};
#define IOCTL_KGSL_SPARSE_PHYS_FREE _IOW(KGSL_IOC_TYPE, 0x51, struct kgsl_sparse_phys_free)
struct kgsl_sparse_virt_alloc {
uint64_t size;
uint64_t pagesize;
uint64_t flags;
uint64_t gpuaddr;
unsigned int id;
};
#define IOCTL_KGSL_SPARSE_VIRT_ALLOC _IOWR(KGSL_IOC_TYPE, 0x52, struct kgsl_sparse_virt_alloc)
struct kgsl_sparse_virt_free {
unsigned int id;
};
#define IOCTL_KGSL_SPARSE_VIRT_FREE _IOW(KGSL_IOC_TYPE, 0x53, struct kgsl_sparse_virt_free)
struct kgsl_sparse_binding_object {
uint64_t virtoffset;
uint64_t physoffset;
uint64_t size;
uint64_t flags;
unsigned int id;
};
struct kgsl_sparse_bind {
uint64_t list;
unsigned int id;
unsigned int size;
unsigned int count;
};
#define IOCTL_KGSL_SPARSE_BIND _IOW(KGSL_IOC_TYPE, 0x54, struct kgsl_sparse_bind)
struct kgsl_gpu_sparse_command {
uint64_t flags;
uint64_t sparselist;
uint64_t synclist;
unsigned int sparsesize;
unsigned int numsparse;
unsigned int syncsize;
unsigned int numsyncs;
unsigned int context_id;
unsigned int timestamp;
unsigned int id;
};
#define IOCTL_KGSL_GPU_SPARSE_COMMAND _IOWR(KGSL_IOC_TYPE, 0x55, struct kgsl_gpu_sparse_command)
#endif

1150
sdm710/kernel-headers/linux/msm_mdp.h
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File diff suppressed because it is too large Load Diff

230
sdm710/kernel-headers/linux/msm_mdp_ext.h
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@@ -1,230 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _MSM_MDP_EXT_H_
#define _MSM_MDP_EXT_H_
#include <linux/msm_mdp.h>
#define MDP_IOCTL_MAGIC 'S'
#define MSMFB_ATOMIC_COMMIT _IOWR(MDP_IOCTL_MAGIC, 128, void *)
#define MSMFB_ASYNC_POSITION_UPDATE _IOWR(MDP_IOCTL_MAGIC, 129, struct mdp_position_update)
#define MSMFB_MDP_SET_CFG _IOW(MDP_IOCTL_MAGIC, 130, struct mdp_set_cfg)
#ifdef __LP64
#define MDP_LAYER_COMMIT_V1_PAD 2
#else
#define MDP_LAYER_COMMIT_V1_PAD 3
#endif
#define MDP_LAYER_FLIP_LR 0x1
#define MDP_LAYER_FLIP_UD 0x2
#define MDP_LAYER_ENABLE_PIXEL_EXT 0x4
#define MDP_LAYER_FORGROUND 0x8
#define MDP_LAYER_SECURE_SESSION 0x10
#define MDP_LAYER_SOLID_FILL 0x20
#define MDP_LAYER_DEINTERLACE 0x40
#define MDP_LAYER_BWC 0x80
#define MDP_LAYER_ASYNC 0x100
#define MDP_LAYER_PP 0x200
#define MDP_LAYER_SECURE_DISPLAY_SESSION 0x400
#define MDP_LAYER_ENABLE_QSEED3_SCALE 0x800
#define MDP_LAYER_MULTIRECT_ENABLE 0x1000
#define MDP_LAYER_MULTIRECT_PARALLEL_MODE 0x2000
#define MDP_DESTSCALER_ENABLE 0x1
#define MDP_DESTSCALER_SCALE_UPDATE 0x2
#define MDP_DESTSCALER_ENHANCER_UPDATE 0x4
#define MDP_VALIDATE_LAYER 0x01
#define MDP_COMMIT_WAIT_FOR_FINISH 0x02
#define MDP_COMMIT_SYNC_FENCE_WAIT 0x04
#define MDP_COMMIT_AVR_EN 0x08
#define MDP_COMMIT_AVR_ONE_SHOT_MODE 0x10
#define MDP_COMMIT_CWB_EN 0x800
#define MDP_COMMIT_CWB_DSPP 0x1000
#define MDP_COMMIT_VERSION_1_0 0x00010000
struct mdp_layer_plane {
int fd;
uint32_t offset;
uint32_t stride;
};
struct mdp_layer_buffer {
uint32_t width;
uint32_t height;
uint32_t format;
struct mdp_layer_plane planes[MAX_PLANES];
uint32_t plane_count;
struct mult_factor comp_ratio;
int fence;
uint32_t reserved;
};
struct mdp_input_layer {
uint32_t flags;
uint32_t pipe_ndx;
uint8_t horz_deci;
uint8_t vert_deci;
uint8_t alpha;
uint16_t z_order;
uint32_t transp_mask;
uint32_t bg_color;
enum mdss_mdp_blend_op blend_op;
enum mdp_color_space color_space;
struct mdp_rect src_rect;
struct mdp_rect dst_rect;
void * scale;
struct mdp_layer_buffer buffer;
void * pp_info;
int error_code;
uint32_t reserved[6];
};
struct mdp_output_layer {
uint32_t flags;
uint32_t writeback_ndx;
struct mdp_layer_buffer buffer;
enum mdp_color_space color_space;
uint32_t reserved[5];
};
struct mdp_destination_scaler_data {
uint32_t flags;
uint32_t dest_scaler_ndx;
uint32_t lm_width;
uint32_t lm_height;
uint64_t scale;
};
#define MDP_VIDEO_FRC_ENABLE (1 << 0)
struct mdp_frc_info {
uint32_t flags;
uint32_t frame_cnt;
int64_t timestamp;
};
struct mdp_layer_commit_v1 {
uint32_t flags;
int release_fence;
struct mdp_rect left_roi;
struct mdp_rect right_roi;
struct mdp_input_layer * input_layers;
uint32_t input_layer_cnt;
struct mdp_output_layer * output_layer;
int retire_fence;
void * dest_scaler;
uint32_t dest_scaler_cnt;
struct mdp_frc_info * frc_info;
uint32_t reserved[MDP_LAYER_COMMIT_V1_PAD];
};
struct mdp_layer_commit {
uint32_t version;
union {
struct mdp_layer_commit_v1 commit_v1;
};
};
struct mdp_point {
uint32_t x;
uint32_t y;
};
struct mdp_async_layer {
uint32_t flags;
uint32_t pipe_ndx;
struct mdp_point src;
struct mdp_point dst;
int error_code;
uint32_t reserved[3];
};
struct mdp_position_update {
struct mdp_async_layer * input_layers;
uint32_t input_layer_cnt;
};
#define MAX_DET_CURVES 3
struct mdp_det_enhance_data {
uint32_t enable;
int16_t sharpen_level1;
int16_t sharpen_level2;
uint16_t clip;
uint16_t limit;
uint16_t thr_quiet;
uint16_t thr_dieout;
uint16_t thr_low;
uint16_t thr_high;
uint16_t prec_shift;
int16_t adjust_a[MAX_DET_CURVES];
int16_t adjust_b[MAX_DET_CURVES];
int16_t adjust_c[MAX_DET_CURVES];
};
#define ENABLE_SCALE 0x1
#define ENABLE_DETAIL_ENHANCE 0x2
#define ENABLE_DIRECTION_DETECTION 0x4
#define SCALER_LUT_SWAP 0x1
#define SCALER_LUT_DIR_WR 0x2
#define SCALER_LUT_Y_CIR_WR 0x4
#define SCALER_LUT_UV_CIR_WR 0x8
#define SCALER_LUT_Y_SEP_WR 0x10
#define SCALER_LUT_UV_SEP_WR 0x20
#define FILTER_EDGE_DIRECTED_2D 0x0
#define FILTER_CIRCULAR_2D 0x1
#define FILTER_SEPARABLE_1D 0x2
#define FILTER_BILINEAR 0x3
#define FILTER_ALPHA_DROP_REPEAT 0x0
#define FILTER_ALPHA_BILINEAR 0x1
struct mdp_scale_data_v2 {
uint32_t enable;
int32_t init_phase_x[MAX_PLANES];
int32_t phase_step_x[MAX_PLANES];
int32_t init_phase_y[MAX_PLANES];
int32_t phase_step_y[MAX_PLANES];
uint32_t num_ext_pxls_left[MAX_PLANES];
uint32_t num_ext_pxls_right[MAX_PLANES];
uint32_t num_ext_pxls_top[MAX_PLANES];
uint32_t num_ext_pxls_btm[MAX_PLANES];
int32_t left_ftch[MAX_PLANES];
int32_t left_rpt[MAX_PLANES];
int32_t right_ftch[MAX_PLANES];
int32_t right_rpt[MAX_PLANES];
uint32_t top_rpt[MAX_PLANES];
uint32_t btm_rpt[MAX_PLANES];
uint32_t top_ftch[MAX_PLANES];
uint32_t btm_ftch[MAX_PLANES];
uint32_t roi_w[MAX_PLANES];
uint32_t preload_x[MAX_PLANES];
uint32_t preload_y[MAX_PLANES];
uint32_t src_width[MAX_PLANES];
uint32_t src_height[MAX_PLANES];
uint32_t dst_width;
uint32_t dst_height;
uint32_t y_rgb_filter_cfg;
uint32_t uv_filter_cfg;
uint32_t alpha_filter_cfg;
uint32_t blend_cfg;
uint32_t lut_flag;
uint32_t dir_lut_idx;
uint32_t y_rgb_cir_lut_idx;
uint32_t uv_cir_lut_idx;
uint32_t y_rgb_sep_lut_idx;
uint32_t uv_sep_lut_idx;
struct mdp_det_enhance_data detail_enhance;
uint64_t reserved[8];
};
struct mdp_scale_luts_info {
uint64_t dir_lut;
uint64_t cir_lut;
uint64_t sep_lut;
uint32_t dir_lut_size;
uint32_t cir_lut_size;
uint32_t sep_lut_size;
};
#define MDP_QSEED3_LUT_CFG 0x1
struct mdp_set_cfg {
uint64_t flags;
uint32_t len;
uint64_t payload;
};
#endif

67
sdm710/kernel-headers/linux/msm_pft.h
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@@ -1,67 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef MSM_PFT_H_
#define MSM_PFT_H_
#include <linux/types.h>
enum pft_command_opcode {
PFT_CMD_OPCODE_SET_STATE,
PFT_CMD_OPCODE_UPDATE_REG_APP_UID,
PFT_CMD_OPCODE_PERFORM_IN_PLACE_FILE_ENC,
PFT_CMD_OPCODE_MAX_COMMAND_INDEX
};
enum pft_state {
PFT_STATE_DEACTIVATED,
PFT_STATE_DEACTIVATING,
PFT_STATE_KEY_REMOVED,
PFT_STATE_REMOVING_KEY,
PFT_STATE_KEY_LOADED,
PFT_STATE_MAX_INDEX
};
enum pft_command_response_code {
PFT_CMD_RESP_SUCCESS,
PFT_CMD_RESP_GENERAL_ERROR,
PFT_CMD_RESP_INVALID_COMMAND,
PFT_CMD_RESP_INVALID_CMD_PARAMS,
PFT_CMD_RESP_INVALID_STATE,
PFT_CMD_RESP_ALREADY_IN_STATE,
PFT_CMD_RESP_INPLACE_FILE_IS_OPEN,
PFT_CMD_RESP_ENT_FILES_CLOSING_FAILURE,
PFT_CMD_RESP_MAX_INDEX
};
struct pft_command_response {
__u32 command_id;
__u32 error_code;
};
struct pft_command {
__u32 opcode;
union {
struct {
__u32 state;
} set_state;
struct {
__u32 items_count;
uid_t table[0];
} update_app_list;
struct {
__u32 file_descriptor;
} preform_in_place_file_enc;
};
};
#endif

129
sdm710/kernel-headers/linux/msm_rmnet.h
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@@ -1,129 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _MSM_RMNET_H_
#define _MSM_RMNET_H_
#define RMNET_MODE_NONE (0x00)
#define RMNET_MODE_LLP_ETH (0x01)
#define RMNET_MODE_LLP_IP (0x02)
#define RMNET_MODE_QOS (0x04)
#define RMNET_MODE_MASK (RMNET_MODE_LLP_ETH | RMNET_MODE_LLP_IP | RMNET_MODE_QOS)
#define RMNET_IS_MODE_QOS(mode) ((mode & RMNET_MODE_QOS) == RMNET_MODE_QOS)
#define RMNET_IS_MODE_IP(mode) ((mode & RMNET_MODE_LLP_IP) == RMNET_MODE_LLP_IP)
#define RMNET_IOCTL_SET_LLP_ETHERNET 0x000089F1
#define RMNET_IOCTL_SET_LLP_IP 0x000089F2
#define RMNET_IOCTL_GET_LLP 0x000089F3
#define RMNET_IOCTL_SET_QOS_ENABLE 0x000089F4
#define RMNET_IOCTL_SET_QOS_DISABLE 0x000089F5
#define RMNET_IOCTL_GET_QOS 0x000089F6
#define RMNET_IOCTL_GET_OPMODE 0x000089F7
#define RMNET_IOCTL_OPEN 0x000089F8
#define RMNET_IOCTL_CLOSE 0x000089F9
#define RMNET_IOCTL_FLOW_ENABLE 0x000089FA
#define RMNET_IOCTL_FLOW_DISABLE 0x000089FB
#define RMNET_IOCTL_FLOW_SET_HNDL 0x000089FC
#define RMNET_IOCTL_EXTENDED 0x000089FD
#define RMNET_IOCTL_GET_SUPPORTED_FEATURES 0x0000
#define RMNET_IOCTL_SET_MRU 0x0001
#define RMNET_IOCTL_GET_MRU 0x0002
#define RMNET_IOCTL_GET_EPID 0x0003
#define RMNET_IOCTL_GET_DRIVER_NAME 0x0004
#define RMNET_IOCTL_ADD_MUX_CHANNEL 0x0005
#define RMNET_IOCTL_SET_EGRESS_DATA_FORMAT 0x0006
#define RMNET_IOCTL_SET_INGRESS_DATA_FORMAT 0x0007
#define RMNET_IOCTL_SET_AGGREGATION_COUNT 0x0008
#define RMNET_IOCTL_GET_AGGREGATION_COUNT 0x0009
#define RMNET_IOCTL_SET_AGGREGATION_SIZE 0x000A
#define RMNET_IOCTL_GET_AGGREGATION_SIZE 0x000B
#define RMNET_IOCTL_FLOW_CONTROL 0x000C
#define RMNET_IOCTL_GET_DFLT_CONTROL_CHANNEL 0x000D
#define RMNET_IOCTL_GET_HWSW_MAP 0x000E
#define RMNET_IOCTL_SET_RX_HEADROOM 0x000F
#define RMNET_IOCTL_GET_EP_PAIR 0x0010
#define RMNET_IOCTL_SET_QOS_VERSION 0x0011
#define RMNET_IOCTL_GET_QOS_VERSION 0x0012
#define RMNET_IOCTL_GET_SUPPORTED_QOS_MODES 0x0013
#define RMNET_IOCTL_SET_SLEEP_STATE 0x0014
#define RMNET_IOCTL_SET_XLAT_DEV_INFO 0x0015
#define RMNET_IOCTL_DEREGISTER_DEV 0x0016
#define RMNET_IOCTL_GET_SG_SUPPORT 0x0017
#define RMNET_IOCTL_FEAT_NOTIFY_MUX_CHANNEL (1 << 0)
#define RMNET_IOCTL_FEAT_SET_EGRESS_DATA_FORMAT (1 << 1)
#define RMNET_IOCTL_FEAT_SET_INGRESS_DATA_FORMAT (1 << 2)
#define RMNET_IOCTL_FEAT_SET_AGGREGATION_COUNT (1 << 3)
#define RMNET_IOCTL_FEAT_GET_AGGREGATION_COUNT (1 << 4)
#define RMNET_IOCTL_FEAT_SET_AGGREGATION_SIZE (1 << 5)
#define RMNET_IOCTL_FEAT_GET_AGGREGATION_SIZE (1 << 6)
#define RMNET_IOCTL_FEAT_FLOW_CONTROL (1 << 7)
#define RMNET_IOCTL_FEAT_GET_DFLT_CONTROL_CHANNEL (1 << 8)
#define RMNET_IOCTL_FEAT_GET_HWSW_MAP (1 << 9)
#define RMNET_IOCTL_EGRESS_FORMAT_MAP (1 << 1)
#define RMNET_IOCTL_EGRESS_FORMAT_AGGREGATION (1 << 2)
#define RMNET_IOCTL_EGRESS_FORMAT_MUXING (1 << 3)
#define RMNET_IOCTL_EGRESS_FORMAT_CHECKSUM (1 << 4)
#define RMNET_IOCTL_INGRESS_FORMAT_MAP (1 << 1)
#define RMNET_IOCTL_INGRESS_FORMAT_DEAGGREGATION (1 << 2)
#define RMNET_IOCTL_INGRESS_FORMAT_DEMUXING (1 << 3)
#define RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM (1 << 4)
#define RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA (1 << 5)
#ifndef IFNAMSIZ
#define IFNAMSIZ 16
#endif
struct rmnet_ioctl_extended_s {
uint32_t extended_ioctl;
union {
uint32_t data;
int8_t if_name[IFNAMSIZ];
struct {
uint32_t mux_id;
int8_t vchannel_name[IFNAMSIZ];
} rmnet_mux_val;
struct {
uint8_t flow_mode;
uint8_t mux_id;
} flow_control_prop;
struct {
uint32_t consumer_pipe_num;
uint32_t producer_pipe_num;
} ipa_ep_pair;
struct {
uint32_t __data;
uint32_t agg_size;
uint32_t agg_count;
} ingress_format;
} u;
};
struct rmnet_ioctl_data_s {
union {
uint32_t operation_mode;
uint32_t tcm_handle;
} u;
};
#define RMNET_IOCTL_QOS_MODE_6 (1 << 0)
#define RMNET_IOCTL_QOS_MODE_8 (1 << 1)
struct QMI_QOS_HDR_S {
unsigned char version;
unsigned char flags;
uint32_t flow_id;
} __attribute((__packed__));
struct qmi_qos_hdr8_s {
struct QMI_QOS_HDR_S hdr;
uint8_t reserved[2];
} __attribute((__packed__));
#endif

66
sdm710/kernel-headers/linux/msm_rotator.h
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@@ -1,66 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __MSM_ROTATOR_H__
#define __MSM_ROTATOR_H__
#include <linux/types.h>
#include <linux/msm_mdp.h>
#define MSM_ROTATOR_IOCTL_MAGIC 'R'
#define MSM_ROTATOR_IOCTL_START _IOWR(MSM_ROTATOR_IOCTL_MAGIC, 1, struct msm_rotator_img_info)
#define MSM_ROTATOR_IOCTL_ROTATE _IOW(MSM_ROTATOR_IOCTL_MAGIC, 2, struct msm_rotator_data_info)
#define MSM_ROTATOR_IOCTL_FINISH _IOW(MSM_ROTATOR_IOCTL_MAGIC, 3, int)
#define ROTATOR_VERSION_01 0xA5B4C301
enum rotator_clk_type {
ROTATOR_CORE_CLK,
ROTATOR_PCLK,
ROTATOR_IMEM_CLK
};
struct msm_rotator_img_info {
unsigned int session_id;
struct msmfb_img src;
struct msmfb_img dst;
struct mdp_rect src_rect;
unsigned int dst_x;
unsigned int dst_y;
unsigned char rotations;
int enable;
unsigned int downscale_ratio;
unsigned int secure;
};
struct msm_rotator_data_info {
int session_id;
struct msmfb_data src;
struct msmfb_data dst;
unsigned int version_key;
struct msmfb_data src_chroma;
struct msmfb_data dst_chroma;
};
struct msm_rot_clocks {
const char * clk_name;
enum rotator_clk_type clk_type;
unsigned int clk_rate;
};
struct msm_rotator_platform_data {
unsigned int number_of_clocks;
unsigned int hardware_version_number;
struct msm_rot_clocks * rotator_clks;
struct msm_bus_scale_pdata * bus_scale_table;
char rot_iommu_split_domain;
};
#endif

65
sdm710/kernel-headers/linux/msm_thermal_ioctl.h
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@@ -1,65 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _MSM_THERMAL_IOCTL_H
#define _MSM_THERMAL_IOCTL_H
#include <linux/ioctl.h>
#define MSM_THERMAL_IOCTL_NAME "msm_thermal_query"
#define MSM_IOCTL_FREQ_SIZE 16
struct __attribute__((__packed__)) cpu_freq_arg {
uint32_t cpu_num;
uint32_t freq_req;
};
struct __attribute__((__packed__)) clock_plan_arg {
uint32_t cluster_num;
uint32_t freq_table_len;
uint32_t set_idx;
unsigned int freq_table[MSM_IOCTL_FREQ_SIZE];
};
struct __attribute__((__packed__)) voltage_plan_arg {
uint32_t cluster_num;
uint32_t voltage_table_len;
uint32_t set_idx;
uint32_t voltage_table[MSM_IOCTL_FREQ_SIZE];
};
struct __attribute__((__packed__)) msm_thermal_ioctl {
uint32_t size;
union {
struct cpu_freq_arg cpu_freq;
struct clock_plan_arg clock_freq;
struct voltage_plan_arg voltage;
};
};
enum {
MSM_SET_CPU_MAX_FREQ = 0x00,
MSM_SET_CPU_MIN_FREQ = 0x01,
MSM_SET_CLUSTER_MAX_FREQ = 0x02,
MSM_SET_CLUSTER_MIN_FREQ = 0x03,
MSM_GET_CLUSTER_FREQ_PLAN = 0x04,
MSM_GET_CLUSTER_VOLTAGE_PLAN = 0x05,
MSM_CMD_MAX_NR,
};
#define MSM_THERMAL_MAGIC_NUM 0xCA
#define MSM_THERMAL_SET_CPU_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CPU_MAX_FREQ, struct msm_thermal_ioctl)
#define MSM_THERMAL_SET_CPU_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CPU_MIN_FREQ, struct msm_thermal_ioctl)
#define MSM_THERMAL_SET_CLUSTER_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CLUSTER_MAX_FREQ, struct msm_thermal_ioctl)
#define MSM_THERMAL_SET_CLUSTER_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM, MSM_SET_CLUSTER_MIN_FREQ, struct msm_thermal_ioctl)
#define MSM_THERMAL_GET_CLUSTER_FREQUENCY_PLAN _IOR(MSM_THERMAL_MAGIC_NUM, MSM_GET_CLUSTER_FREQ_PLAN, struct msm_thermal_ioctl)
#define MSM_THERMAL_GET_CLUSTER_VOLTAGE_PLAN _IOR(MSM_THERMAL_MAGIC_NUM, MSM_GET_CLUSTER_VOLTAGE_PLAN, struct msm_thermal_ioctl)
#endif

469
sdm710/kernel-headers/linux/msm_vidc_dec.h
View File

@@ -1,469 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _MSM_VIDC_DEC_H_
#define _MSM_VIDC_DEC_H_
#include <linux/types.h>
#include <linux/ioctl.h>
#define VDEC_S_BASE 0x40000000
#define VDEC_S_SUCCESS (VDEC_S_BASE)
#define VDEC_S_EFAIL (VDEC_S_BASE + 1)
#define VDEC_S_EFATAL (VDEC_S_BASE + 2)
#define VDEC_S_EBADPARAM (VDEC_S_BASE + 3)
#define VDEC_S_EINVALSTATE (VDEC_S_BASE + 4)
#define VDEC_S_ENOSWRES (VDEC_S_BASE + 5)
#define VDEC_S_ENOHWRES (VDEC_S_BASE + 6)
#define VDEC_S_EINVALCMD (VDEC_S_BASE + 7)
#define VDEC_S_ETIMEOUT (VDEC_S_BASE + 8)
#define VDEC_S_ENOPREREQ (VDEC_S_BASE + 9)
#define VDEC_S_ECMDQFULL (VDEC_S_BASE + 10)
#define VDEC_S_ENOTSUPP (VDEC_S_BASE + 11)
#define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12)
#define VDEC_S_BUSY (VDEC_S_BASE + 13)
#define VDEC_S_INPUT_BITSTREAM_ERR (VDEC_S_BASE + 14)
#define VDEC_INTF_VER 1
#define VDEC_MSG_BASE 0x0000000
#define VDEC_MSG_INVALID (VDEC_MSG_BASE + 0)
#define VDEC_MSG_RESP_INPUT_BUFFER_DONE (VDEC_MSG_BASE + 1)
#define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2)
#define VDEC_MSG_RESP_INPUT_FLUSHED (VDEC_MSG_BASE + 3)
#define VDEC_MSG_RESP_OUTPUT_FLUSHED (VDEC_MSG_BASE + 4)
#define VDEC_MSG_RESP_FLUSH_INPUT_DONE (VDEC_MSG_BASE + 5)
#define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6)
#define VDEC_MSG_RESP_START_DONE (VDEC_MSG_BASE + 7)
#define VDEC_MSG_RESP_STOP_DONE (VDEC_MSG_BASE + 8)
#define VDEC_MSG_RESP_PAUSE_DONE (VDEC_MSG_BASE + 9)
#define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10)
#define VDEC_MSG_RESP_RESOURCE_LOADED (VDEC_MSG_BASE + 11)
#define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12)
#define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13)
#define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14)
#define VDEC_MSG_EVT_INFO_CONFIG_CHANGED (VDEC_MSG_BASE + 15)
#define VDEC_MSG_EVT_INFO_FIELD_DROPPED (VDEC_MSG_BASE + 16)
#define VDEC_MSG_EVT_HW_OVERLOAD (VDEC_MSG_BASE + 17)
#define VDEC_MSG_EVT_MAX_CLIENTS (VDEC_MSG_BASE + 18)
#define VDEC_MSG_EVT_HW_UNSUPPORTED (VDEC_MSG_BASE + 19)
#define VDEC_BUFFERFLAG_EOS 0x00000001
#define VDEC_BUFFERFLAG_DECODEONLY 0x00000004
#define VDEC_BUFFERFLAG_DATACORRUPT 0x00000008
#define VDEC_BUFFERFLAG_ENDOFFRAME 0x00000010
#define VDEC_BUFFERFLAG_SYNCFRAME 0x00000020
#define VDEC_BUFFERFLAG_EXTRADATA 0x00000040
#define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080
#define VDEC_EXTRADATA_NONE 0x001
#define VDEC_EXTRADATA_QP 0x004
#define VDEC_EXTRADATA_MB_ERROR_MAP 0x008
#define VDEC_EXTRADATA_SEI 0x010
#define VDEC_EXTRADATA_VUI 0x020
#define VDEC_EXTRADATA_VC1 0x040
#define VDEC_EXTRADATA_EXT_DATA 0x0800
#define VDEC_EXTRADATA_USER_DATA 0x1000
#define VDEC_EXTRADATA_EXT_BUFFER 0x2000
#define VDEC_CMDBASE 0x800
#define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE)
#define VDEC_IOCTL_MAGIC 'v'
struct vdec_ioctl_msg {
void * in;
void * out;
};
#define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_INTERLACE_FORMAT _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_OUTPUT_FORMAT _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_OUTPUT_FORMAT _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_CODEC _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_CODEC _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_PICRES _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_PICRES _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_EXTRADATA _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_EXTRADATA _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_SEQUENCE_HEADER _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_BUFFER_REQ _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_BUFFER_REQ _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg)
#define VDEC_IOCTL_ALLOCATE_BUFFER _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg)
#define VDEC_IOCTL_FREE_BUFFER _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_BUFFER _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg)
#define VDEC_IOCTL_FILL_OUTPUT_BUFFER _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg)
#define VDEC_IOCTL_DECODE_FRAME _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg)
#define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19)
#define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20)
#define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21)
#define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22)
#define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23)
#define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_NEXT_MSG _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg)
#define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26)
#define VDEC_IOCTL_GET_NUMBER_INSTANCES _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_PICTURE_ORDER _IOW(VDEC_IOCTL_MAGIC, 28, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_FRAME_RATE _IOW(VDEC_IOCTL_MAGIC, 29, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_H264_MV_BUFFER _IOW(VDEC_IOCTL_MAGIC, 30, struct vdec_ioctl_msg)
#define VDEC_IOCTL_FREE_H264_MV_BUFFER _IOW(VDEC_IOCTL_MAGIC, 31, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_MV_BUFFER_SIZE _IOR(VDEC_IOCTL_MAGIC, 32, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_IDR_ONLY_DECODING _IO(VDEC_IOCTL_MAGIC, 33)
#define VDEC_IOCTL_SET_CONT_ON_RECONFIG _IO(VDEC_IOCTL_MAGIC, 34)
#define VDEC_IOCTL_SET_DISABLE_DMX _IOW(VDEC_IOCTL_MAGIC, 35, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_DISABLE_DMX _IOR(VDEC_IOCTL_MAGIC, 36, struct vdec_ioctl_msg)
#define VDEC_IOCTL_GET_DISABLE_DMX_SUPPORT _IOR(VDEC_IOCTL_MAGIC, 37, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_PERF_CLK _IOR(VDEC_IOCTL_MAGIC, 38, struct vdec_ioctl_msg)
#define VDEC_IOCTL_SET_META_BUFFERS _IOW(VDEC_IOCTL_MAGIC, 39, struct vdec_ioctl_msg)
#define VDEC_IOCTL_FREE_META_BUFFERS _IO(VDEC_IOCTL_MAGIC, 40)
enum vdec_picture {
PICTURE_TYPE_I,
PICTURE_TYPE_P,
PICTURE_TYPE_B,
PICTURE_TYPE_BI,
PICTURE_TYPE_SKIP,
PICTURE_TYPE_IDR,
PICTURE_TYPE_UNKNOWN
};
enum vdec_buffer {
VDEC_BUFFER_TYPE_INPUT,
VDEC_BUFFER_TYPE_OUTPUT
};
struct vdec_allocatorproperty {
enum vdec_buffer buffer_type;
uint32_t mincount;
uint32_t maxcount;
uint32_t actualcount;
size_t buffer_size;
uint32_t alignment;
uint32_t buf_poolid;
size_t meta_buffer_size;
};
struct vdec_bufferpayload {
void * bufferaddr;
size_t buffer_len;
int pmem_fd;
size_t offset;
size_t mmaped_size;
};
struct vdec_setbuffer_cmd {
enum vdec_buffer buffer_type;
struct vdec_bufferpayload buffer;
};
struct vdec_fillbuffer_cmd {
struct vdec_bufferpayload buffer;
void * client_data;
};
enum vdec_bufferflush {
VDEC_FLUSH_TYPE_INPUT,
VDEC_FLUSH_TYPE_OUTPUT,
VDEC_FLUSH_TYPE_ALL
};
enum vdec_codec {
VDEC_CODECTYPE_H264 = 0x1,
VDEC_CODECTYPE_H263 = 0x2,
VDEC_CODECTYPE_MPEG4 = 0x3,
VDEC_CODECTYPE_DIVX_3 = 0x4,
VDEC_CODECTYPE_DIVX_4 = 0x5,
VDEC_CODECTYPE_DIVX_5 = 0x6,
VDEC_CODECTYPE_DIVX_6 = 0x7,
VDEC_CODECTYPE_XVID = 0x8,
VDEC_CODECTYPE_MPEG1 = 0x9,
VDEC_CODECTYPE_MPEG2 = 0xa,
VDEC_CODECTYPE_VC1 = 0xb,
VDEC_CODECTYPE_VC1_RCV = 0xc,
VDEC_CODECTYPE_HEVC = 0xd,
VDEC_CODECTYPE_MVC = 0xe,
VDEC_CODECTYPE_VP8 = 0xf,
VDEC_CODECTYPE_VP9 = 0x10,
};
enum vdec_mpeg2_profile {
VDEC_MPEG2ProfileSimple = 0x1,
VDEC_MPEG2ProfileMain = 0x2,
VDEC_MPEG2Profile422 = 0x4,
VDEC_MPEG2ProfileSNR = 0x8,
VDEC_MPEG2ProfileSpatial = 0x10,
VDEC_MPEG2ProfileHigh = 0x20,
VDEC_MPEG2ProfileKhronosExtensions = 0x6F000000,
VDEC_MPEG2ProfileVendorStartUnused = 0x7F000000,
VDEC_MPEG2ProfileMax = 0x7FFFFFFF
};
enum vdec_mpeg2_level {
VDEC_MPEG2LevelLL = 0x1,
VDEC_MPEG2LevelML = 0x2,
VDEC_MPEG2LevelH14 = 0x4,
VDEC_MPEG2LevelHL = 0x8,
VDEC_MPEG2LevelKhronosExtensions = 0x6F000000,
VDEC_MPEG2LevelVendorStartUnused = 0x7F000000,
VDEC_MPEG2LevelMax = 0x7FFFFFFF
};
enum vdec_mpeg4_profile {
VDEC_MPEG4ProfileSimple = 0x01,
VDEC_MPEG4ProfileSimpleScalable = 0x02,
VDEC_MPEG4ProfileCore = 0x04,
VDEC_MPEG4ProfileMain = 0x08,
VDEC_MPEG4ProfileNbit = 0x10,
VDEC_MPEG4ProfileScalableTexture = 0x20,
VDEC_MPEG4ProfileSimpleFace = 0x40,
VDEC_MPEG4ProfileSimpleFBA = 0x80,
VDEC_MPEG4ProfileBasicAnimated = 0x100,
VDEC_MPEG4ProfileHybrid = 0x200,
VDEC_MPEG4ProfileAdvancedRealTime = 0x400,
VDEC_MPEG4ProfileCoreScalable = 0x800,
VDEC_MPEG4ProfileAdvancedCoding = 0x1000,
VDEC_MPEG4ProfileAdvancedCore = 0x2000,
VDEC_MPEG4ProfileAdvancedScalable = 0x4000,
VDEC_MPEG4ProfileAdvancedSimple = 0x8000,
VDEC_MPEG4ProfileKhronosExtensions = 0x6F000000,
VDEC_MPEG4ProfileVendorStartUnused = 0x7F000000,
VDEC_MPEG4ProfileMax = 0x7FFFFFFF
};
enum vdec_mpeg4_level {
VDEC_MPEG4Level0 = 0x01,
VDEC_MPEG4Level0b = 0x02,
VDEC_MPEG4Level1 = 0x04,
VDEC_MPEG4Level2 = 0x08,
VDEC_MPEG4Level3 = 0x10,
VDEC_MPEG4Level4 = 0x20,
VDEC_MPEG4Level4a = 0x40,
VDEC_MPEG4Level5 = 0x80,
VDEC_MPEG4LevelKhronosExtensions = 0x6F000000,
VDEC_MPEG4LevelVendorStartUnused = 0x7F000000,
VDEC_MPEG4LevelMax = 0x7FFFFFFF
};
enum vdec_avc_profile {
VDEC_AVCProfileBaseline = 0x01,
VDEC_AVCProfileMain = 0x02,
VDEC_AVCProfileExtended = 0x04,
VDEC_AVCProfileHigh = 0x08,
VDEC_AVCProfileHigh10 = 0x10,
VDEC_AVCProfileHigh422 = 0x20,
VDEC_AVCProfileHigh444 = 0x40,
VDEC_AVCProfileKhronosExtensions = 0x6F000000,
VDEC_AVCProfileVendorStartUnused = 0x7F000000,
VDEC_AVCProfileMax = 0x7FFFFFFF
};
enum vdec_avc_level {
VDEC_AVCLevel1 = 0x01,
VDEC_AVCLevel1b = 0x02,
VDEC_AVCLevel11 = 0x04,
VDEC_AVCLevel12 = 0x08,
VDEC_AVCLevel13 = 0x10,
VDEC_AVCLevel2 = 0x20,
VDEC_AVCLevel21 = 0x40,
VDEC_AVCLevel22 = 0x80,
VDEC_AVCLevel3 = 0x100,
VDEC_AVCLevel31 = 0x200,
VDEC_AVCLevel32 = 0x400,
VDEC_AVCLevel4 = 0x800,
VDEC_AVCLevel41 = 0x1000,
VDEC_AVCLevel42 = 0x2000,
VDEC_AVCLevel5 = 0x4000,
VDEC_AVCLevel51 = 0x8000,
VDEC_AVCLevelKhronosExtensions = 0x6F000000,
VDEC_AVCLevelVendorStartUnused = 0x7F000000,
VDEC_AVCLevelMax = 0x7FFFFFFF
};
enum vdec_divx_profile {
VDEC_DIVXProfile_qMobile = 0x01,
VDEC_DIVXProfile_Mobile = 0x02,
VDEC_DIVXProfile_HD = 0x04,
VDEC_DIVXProfile_Handheld = 0x08,
VDEC_DIVXProfile_Portable = 0x10,
VDEC_DIVXProfile_HomeTheater = 0x20
};
enum vdec_xvid_profile {
VDEC_XVIDProfile_Simple = 0x1,
VDEC_XVIDProfile_Advanced_Realtime_Simple = 0x2,
VDEC_XVIDProfile_Advanced_Simple = 0x4
};
enum vdec_xvid_level {
VDEC_XVID_LEVEL_S_L0 = 0x1,
VDEC_XVID_LEVEL_S_L1 = 0x2,
VDEC_XVID_LEVEL_S_L2 = 0x4,
VDEC_XVID_LEVEL_S_L3 = 0x8,
VDEC_XVID_LEVEL_ARTS_L1 = 0x10,
VDEC_XVID_LEVEL_ARTS_L2 = 0x20,
VDEC_XVID_LEVEL_ARTS_L3 = 0x40,
VDEC_XVID_LEVEL_ARTS_L4 = 0x80,
VDEC_XVID_LEVEL_AS_L0 = 0x100,
VDEC_XVID_LEVEL_AS_L1 = 0x200,
VDEC_XVID_LEVEL_AS_L2 = 0x400,
VDEC_XVID_LEVEL_AS_L3 = 0x800,
VDEC_XVID_LEVEL_AS_L4 = 0x1000
};
enum vdec_h263profile {
VDEC_H263ProfileBaseline = 0x01,
VDEC_H263ProfileH320Coding = 0x02,
VDEC_H263ProfileBackwardCompatible = 0x04,
VDEC_H263ProfileISWV2 = 0x08,
VDEC_H263ProfileISWV3 = 0x10,
VDEC_H263ProfileHighCompression = 0x20,
VDEC_H263ProfileInternet = 0x40,
VDEC_H263ProfileInterlace = 0x80,
VDEC_H263ProfileHighLatency = 0x100,
VDEC_H263ProfileKhronosExtensions = 0x6F000000,
VDEC_H263ProfileVendorStartUnused = 0x7F000000,
VDEC_H263ProfileMax = 0x7FFFFFFF
};
enum vdec_h263level {
VDEC_H263Level10 = 0x01,
VDEC_H263Level20 = 0x02,
VDEC_H263Level30 = 0x04,
VDEC_H263Level40 = 0x08,
VDEC_H263Level45 = 0x10,
VDEC_H263Level50 = 0x20,
VDEC_H263Level60 = 0x40,
VDEC_H263Level70 = 0x80,
VDEC_H263LevelKhronosExtensions = 0x6F000000,
VDEC_H263LevelVendorStartUnused = 0x7F000000,
VDEC_H263LevelMax = 0x7FFFFFFF
};
enum vdec_wmv_format {
VDEC_WMVFormatUnused = 0x01,
VDEC_WMVFormat7 = 0x02,
VDEC_WMVFormat8 = 0x04,
VDEC_WMVFormat9 = 0x08,
VDEC_WMFFormatKhronosExtensions = 0x6F000000,
VDEC_WMFFormatVendorStartUnused = 0x7F000000,
VDEC_WMVFormatMax = 0x7FFFFFFF
};
enum vdec_vc1_profile {
VDEC_VC1ProfileSimple = 0x1,
VDEC_VC1ProfileMain = 0x2,
VDEC_VC1ProfileAdvanced = 0x4
};
enum vdec_vc1_level {
VDEC_VC1_LEVEL_S_Low = 0x1,
VDEC_VC1_LEVEL_S_Medium = 0x2,
VDEC_VC1_LEVEL_M_Low = 0x4,
VDEC_VC1_LEVEL_M_Medium = 0x8,
VDEC_VC1_LEVEL_M_High = 0x10,
VDEC_VC1_LEVEL_A_L0 = 0x20,
VDEC_VC1_LEVEL_A_L1 = 0x40,
VDEC_VC1_LEVEL_A_L2 = 0x80,
VDEC_VC1_LEVEL_A_L3 = 0x100,
VDEC_VC1_LEVEL_A_L4 = 0x200
};
struct vdec_profile_level {
uint32_t profiles;
uint32_t levels;
};
enum vdec_interlaced_format {
VDEC_InterlaceFrameProgressive = 0x1,
VDEC_InterlaceInterleaveFrameTopFieldFirst = 0x2,
VDEC_InterlaceInterleaveFrameBottomFieldFirst = 0x4
};
#define VDEC_YUV_FORMAT_NV12_TP10_UBWC VDEC_YUV_FORMAT_NV12_TP10_UBWC
enum vdec_output_fromat {
VDEC_YUV_FORMAT_NV12 = 0x1,
VDEC_YUV_FORMAT_TILE_4x2 = 0x2,
VDEC_YUV_FORMAT_NV12_UBWC = 0x3,
VDEC_YUV_FORMAT_NV12_TP10_UBWC = 0x4
};
enum vdec_output_order {
VDEC_ORDER_DISPLAY = 0x1,
VDEC_ORDER_DECODE = 0x2
};
struct vdec_picsize {
uint32_t frame_width;
uint32_t frame_height;
uint32_t stride;
uint32_t scan_lines;
};
struct vdec_seqheader {
void * ptr_seqheader;
size_t seq_header_len;
int pmem_fd;
size_t pmem_offset;
};
struct vdec_mberror {
void * ptr_errormap;
size_t err_mapsize;
};
struct vdec_input_frameinfo {
void * bufferaddr;
size_t offset;
size_t datalen;
uint32_t flags;
int64_t timestamp;
void * client_data;
int pmem_fd;
size_t pmem_offset;
void * desc_addr;
uint32_t desc_size;
};
struct vdec_framesize {
uint32_t left;
uint32_t top;
uint32_t right;
uint32_t bottom;
};
struct vdec_aspectratioinfo {
uint32_t aspect_ratio;
uint32_t par_width;
uint32_t par_height;
};
struct vdec_sep_metadatainfo {
void * metabufaddr;
uint32_t size;
int fd;
int offset;
uint32_t buffer_size;
};
struct vdec_output_frameinfo {
void * bufferaddr;
size_t offset;
size_t len;
uint32_t flags;
int64_t time_stamp;
enum vdec_picture pic_type;
void * client_data;
void * input_frame_clientdata;
struct vdec_picsize picsize;
struct vdec_framesize framesize;
enum vdec_interlaced_format interlaced_format;
struct vdec_aspectratioinfo aspect_ratio_info;
struct vdec_sep_metadatainfo metadata_info;
};
union vdec_msgdata {
struct vdec_output_frameinfo output_frame;
void * input_frame_clientdata;
};
struct vdec_msginfo {
uint32_t status_code;
uint32_t msgcode;
union vdec_msgdata msgdata;
size_t msgdatasize;
};
struct vdec_framerate {
unsigned long fps_denominator;
unsigned long fps_numerator;
};
struct vdec_h264_mv {
size_t size;
int count;
int pmem_fd;
int offset;
};
struct vdec_mv_buff_size {
int width;
int height;
int size;
int alignment;
};
struct vdec_meta_buffers {
size_t size;
int count;
int pmem_fd;
int pmem_fd_iommu;
int offset;
};
#endif

387
sdm710/kernel-headers/linux/msm_vidc_enc.h
View File

@@ -1,387 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _MSM_VIDC_ENC_H_
#define _MSM_VIDC_ENC_H_
#include <linux/types.h>
#include <linux/ioctl.h>
#define VEN_S_BASE 0x00000000
#define VEN_S_SUCCESS (VEN_S_BASE)
#define VEN_S_EFAIL (VEN_S_BASE + 1)
#define VEN_S_EFATAL (VEN_S_BASE + 2)
#define VEN_S_EBADPARAM (VEN_S_BASE + 3)
#define VEN_S_EINVALSTATE (VEN_S_BASE + 4)
#define VEN_S_ENOSWRES (VEN_S_BASE + 5)
#define VEN_S_ENOHWRES (VEN_S_BASE + 6)
#define VEN_S_EBUFFREQ (VEN_S_BASE + 7)
#define VEN_S_EINVALCMD (VEN_S_BASE + 8)
#define VEN_S_ETIMEOUT (VEN_S_BASE + 9)
#define VEN_S_ENOREATMPT (VEN_S_BASE + 10)
#define VEN_S_ENOPREREQ (VEN_S_BASE + 11)
#define VEN_S_ECMDQFULL (VEN_S_BASE + 12)
#define VEN_S_ENOTSUPP (VEN_S_BASE + 13)
#define VEN_S_ENOTIMPL (VEN_S_BASE + 14)
#define VEN_S_ENOTPMEM (VEN_S_BASE + 15)
#define VEN_S_EFLUSHED (VEN_S_BASE + 16)
#define VEN_S_EINSUFBUF (VEN_S_BASE + 17)
#define VEN_S_ESAMESTATE (VEN_S_BASE + 18)
#define VEN_S_EINVALTRANS (VEN_S_BASE + 19)
#define VEN_INTF_VER 1
#define VEN_MSG_INDICATION 0
#define VEN_MSG_INPUT_BUFFER_DONE 1
#define VEN_MSG_OUTPUT_BUFFER_DONE 2
#define VEN_MSG_NEED_OUTPUT_BUFFER 3
#define VEN_MSG_FLUSH_INPUT_DONE 4
#define VEN_MSG_FLUSH_OUTPUT_DONE 5
#define VEN_MSG_START 6
#define VEN_MSG_STOP 7
#define VEN_MSG_PAUSE 8
#define VEN_MSG_RESUME 9
#define VEN_MSG_STOP_READING_MSG 10
#define VEN_MSG_LTRUSE_FAILED 11
#define VEN_MSG_HW_OVERLOAD 12
#define VEN_MSG_MAX_CLIENTS 13
#define VEN_BUFFLAG_EOS 0x00000001
#define VEN_BUFFLAG_ENDOFFRAME 0x00000010
#define VEN_BUFFLAG_SYNCFRAME 0x00000020
#define VEN_BUFFLAG_EXTRADATA 0x00000040
#define VEN_BUFFLAG_CODECCONFIG 0x00000080
#define VEN_EXTRADATA_NONE 0x001
#define VEN_EXTRADATA_QCOMFILLER 0x002
#define VEN_EXTRADATA_SLICEINFO 0x100
#define VEN_EXTRADATA_LTRINFO 0x200
#define VEN_EXTRADATA_MBINFO 0x400
#define VEN_FRAME_TYPE_I 1
#define VEN_FRAME_TYPE_P 2
#define VEN_FRAME_TYPE_B 3
#define VEN_CODEC_MPEG4 1
#define VEN_CODEC_H264 2
#define VEN_CODEC_H263 3
#define VEN_PROFILE_MPEG4_SP 1
#define VEN_PROFILE_MPEG4_ASP 2
#define VEN_PROFILE_H264_BASELINE 3
#define VEN_PROFILE_H264_MAIN 4
#define VEN_PROFILE_H264_HIGH 5
#define VEN_PROFILE_H263_BASELINE 6
#define VEN_LEVEL_MPEG4_0 0x1
#define VEN_LEVEL_MPEG4_1 0x2
#define VEN_LEVEL_MPEG4_2 0x3
#define VEN_LEVEL_MPEG4_3 0x4
#define VEN_LEVEL_MPEG4_4 0x5
#define VEN_LEVEL_MPEG4_5 0x6
#define VEN_LEVEL_MPEG4_3b 0x7
#define VEN_LEVEL_MPEG4_6 0x8
#define VEN_LEVEL_H264_1 0x9
#define VEN_LEVEL_H264_1b 0xA
#define VEN_LEVEL_H264_1p1 0xB
#define VEN_LEVEL_H264_1p2 0xC
#define VEN_LEVEL_H264_1p3 0xD
#define VEN_LEVEL_H264_2 0xE
#define VEN_LEVEL_H264_2p1 0xF
#define VEN_LEVEL_H264_2p2 0x10
#define VEN_LEVEL_H264_3 0x11
#define VEN_LEVEL_H264_3p1 0x12
#define VEN_LEVEL_H264_3p2 0x13
#define VEN_LEVEL_H264_4 0x14
#define VEN_LEVEL_H263_10 0x15
#define VEN_LEVEL_H263_20 0x16
#define VEN_LEVEL_H263_30 0x17
#define VEN_LEVEL_H263_40 0x18
#define VEN_LEVEL_H263_45 0x19
#define VEN_LEVEL_H263_50 0x1A
#define VEN_LEVEL_H263_60 0x1B
#define VEN_LEVEL_H263_70 0x1C
#define VEN_ENTROPY_MODEL_CAVLC 1
#define VEN_ENTROPY_MODEL_CABAC 2
#define VEN_CABAC_MODEL_0 1
#define VEN_CABAC_MODEL_1 2
#define VEN_CABAC_MODEL_2 3
#define VEN_DB_DISABLE 1
#define VEN_DB_ALL_BLKG_BNDRY 2
#define VEN_DB_SKIP_SLICE_BNDRY 3
#define VEN_MSLICE_OFF 1
#define VEN_MSLICE_CNT_MB 2
#define VEN_MSLICE_CNT_BYTE 3
#define VEN_MSLICE_GOB 4
#define VEN_RC_OFF 1
#define VEN_RC_VBR_VFR 2
#define VEN_RC_VBR_CFR 3
#define VEN_RC_CBR_VFR 4
#define VEN_RC_CBR_CFR 5
#define VEN_FLUSH_INPUT 1
#define VEN_FLUSH_OUTPUT 2
#define VEN_FLUSH_ALL 3
#define VEN_INPUTFMT_NV12 1
#define VEN_INPUTFMT_NV21 2
#define VEN_INPUTFMT_NV12_16M2KA 3
#define VEN_ROTATION_0 1
#define VEN_ROTATION_90 2
#define VEN_ROTATION_180 3
#define VEN_ROTATION_270 4
#define VEN_TIMEOUT_INFINITE 0xffffffff
#define VEN_IR_OFF 1
#define VEN_IR_CYCLIC 2
#define VEN_IR_RANDOM 3
#define VEN_IOCTLBASE_NENC 0x800
#define VEN_IOCTLBASE_ENC 0x850
struct venc_ioctl_msg {
void * in;
void * out;
};
#define VEN_IOCTL_SET_INTF_VERSION _IOW(VEN_IOCTLBASE_NENC, 0, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_READ_NEXT_MSG _IOWR(VEN_IOCTLBASE_NENC, 1, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_STOP_READ_MSG _IO(VEN_IOCTLBASE_NENC, 2)
#define VEN_IOCTL_SET_INPUT_BUFFER_REQ _IOW(VEN_IOCTLBASE_NENC, 3, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_INPUT_BUFFER_REQ _IOR(VEN_IOCTLBASE_NENC, 4, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_ALLOC_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 5, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 6, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_FREE_INPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 7, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_OUTPUT_BUFFER_REQ _IOW(VEN_IOCTLBASE_NENC, 8, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_OUTPUT_BUFFER_REQ _IOR(VEN_IOCTLBASE_NENC, 9, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_ALLOC_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 10, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 11, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_FREE_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 12, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_START _IO(VEN_IOCTLBASE_NENC, 13)
#define VEN_IOCTL_CMD_ENCODE_FRAME _IOW(VEN_IOCTLBASE_NENC, 14, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_FILL_OUTPUT_BUFFER _IOW(VEN_IOCTLBASE_NENC, 15, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_FLUSH _IOW(VEN_IOCTLBASE_NENC, 16, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_PAUSE _IO(VEN_IOCTLBASE_NENC, 17)
#define VEN_IOCTL_CMD_RESUME _IO(VEN_IOCTLBASE_NENC, 18)
#define VEN_IOCTL_CMD_STOP _IO(VEN_IOCTLBASE_NENC, 19)
#define VEN_IOCTL_SET_RECON_BUFFER _IOW(VEN_IOCTLBASE_NENC, 20, struct venc_ioctl_msg)
#define VEN_IOCTL_FREE_RECON_BUFFER _IOW(VEN_IOCTLBASE_NENC, 21, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_RECON_BUFFER_SIZE _IOW(VEN_IOCTLBASE_NENC, 22, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_BASE_CFG _IOW(VEN_IOCTLBASE_ENC, 1, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_BASE_CFG _IOR(VEN_IOCTLBASE_ENC, 2, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_LIVE_MODE _IOW(VEN_IOCTLBASE_ENC, 3, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_LIVE_MODE _IOR(VEN_IOCTLBASE_ENC, 4, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_CODEC_PROFILE _IOW(VEN_IOCTLBASE_ENC, 5, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_CODEC_PROFILE _IOR(VEN_IOCTLBASE_ENC, 6, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_PROFILE_LEVEL _IOW(VEN_IOCTLBASE_ENC, 7, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_PROFILE_LEVEL _IOR(VEN_IOCTLBASE_ENC, 8, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_SHORT_HDR _IOW(VEN_IOCTLBASE_ENC, 9, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_SHORT_HDR _IOR(VEN_IOCTLBASE_ENC, 10, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_SESSION_QP _IOW(VEN_IOCTLBASE_ENC, 11, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_SESSION_QP _IOR(VEN_IOCTLBASE_ENC, 12, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_INTRA_PERIOD _IOW(VEN_IOCTLBASE_ENC, 13, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_INTRA_PERIOD _IOR(VEN_IOCTLBASE_ENC, 14, struct venc_ioctl_msg)
#define VEN_IOCTL_CMD_REQUEST_IFRAME _IO(VEN_IOCTLBASE_ENC, 15)
#define VEN_IOCTL_GET_CAPABILITY _IOR(VEN_IOCTLBASE_ENC, 16, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_SEQUENCE_HDR _IOR(VEN_IOCTLBASE_ENC, 17, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_ENTROPY_CFG _IOW(VEN_IOCTLBASE_ENC, 18, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_ENTROPY_CFG _IOR(VEN_IOCTLBASE_ENC, 19, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_DEBLOCKING_CFG _IOW(VEN_IOCTLBASE_ENC, 20, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_DEBLOCKING_CFG _IOR(VEN_IOCTLBASE_ENC, 21, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_INTRA_REFRESH _IOW(VEN_IOCTLBASE_ENC, 22, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_INTRA_REFRESH _IOR(VEN_IOCTLBASE_ENC, 23, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_MULTI_SLICE_CFG _IOW(VEN_IOCTLBASE_ENC, 24, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_MULTI_SLICE_CFG _IOR(VEN_IOCTLBASE_ENC, 25, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_RATE_CTRL_CFG _IOW(VEN_IOCTLBASE_ENC, 26, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_RATE_CTRL_CFG _IOR(VEN_IOCTLBASE_ENC, 27, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_VOP_TIMING_CFG _IOW(VEN_IOCTLBASE_ENC, 28, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_VOP_TIMING_CFG _IOR(VEN_IOCTLBASE_ENC, 29, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_FRAME_RATE _IOW(VEN_IOCTLBASE_ENC, 30, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_FRAME_RATE _IOR(VEN_IOCTLBASE_ENC, 31, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_TARGET_BITRATE _IOW(VEN_IOCTLBASE_ENC, 32, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_TARGET_BITRATE _IOR(VEN_IOCTLBASE_ENC, 33, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_ROTATION _IOW(VEN_IOCTLBASE_ENC, 34, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_ROTATION _IOR(VEN_IOCTLBASE_ENC, 35, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_HEC _IOW(VEN_IOCTLBASE_ENC, 36, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_HEC _IOR(VEN_IOCTLBASE_ENC, 37, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_DATA_PARTITION _IOW(VEN_IOCTLBASE_ENC, 38, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_DATA_PARTITION _IOR(VEN_IOCTLBASE_ENC, 39, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_RVLC _IOW(VEN_IOCTLBASE_ENC, 40, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_RVLC _IOR(VEN_IOCTLBASE_ENC, 41, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_AC_PREDICTION _IOW(VEN_IOCTLBASE_ENC, 42, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_AC_PREDICTION _IOR(VEN_IOCTLBASE_ENC, 43, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_QP_RANGE _IOW(VEN_IOCTLBASE_ENC, 44, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_QP_RANGE _IOR(VEN_IOCTLBASE_ENC, 45, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_NUMBER_INSTANCES _IOR(VEN_IOCTLBASE_ENC, 46, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_METABUFFER_MODE _IOW(VEN_IOCTLBASE_ENC, 47, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_EXTRADATA _IOW(VEN_IOCTLBASE_ENC, 48, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_EXTRADATA _IOR(VEN_IOCTLBASE_ENC, 49, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_SLICE_DELIVERY_MODE _IO(VEN_IOCTLBASE_ENC, 50)
#define VEN_IOCTL_SET_H263_PLUSPTYPE _IOW(VEN_IOCTLBASE_ENC, 51, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_CAPABILITY_LTRCOUNT _IOW(VEN_IOCTLBASE_ENC, 52, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_CAPABILITY_LTRCOUNT _IOR(VEN_IOCTLBASE_ENC, 53, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_LTRMODE _IOW(VEN_IOCTLBASE_ENC, 54, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_LTRMODE _IOR(VEN_IOCTLBASE_ENC, 55, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_LTRCOUNT _IOW(VEN_IOCTLBASE_ENC, 56, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_LTRCOUNT _IOR(VEN_IOCTLBASE_ENC, 57, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_LTRPERIOD _IOW(VEN_IOCTLBASE_ENC, 58, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_LTRPERIOD _IOR(VEN_IOCTLBASE_ENC, 59, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_LTRUSE _IOW(VEN_IOCTLBASE_ENC, 60, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_LTRUSE _IOR(VEN_IOCTLBASE_ENC, 61, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_LTRMARK _IOW(VEN_IOCTLBASE_ENC, 62, struct venc_ioctl_msg)
#define VEN_IOCTL_GET_LTRMARK _IOR(VEN_IOCTLBASE_ENC, 63, struct venc_ioctl_msg)
#define VEN_IOCTL_SET_SPS_PPS_FOR_IDR _IOW(VEN_IOCTLBASE_ENC, 64, struct venc_ioctl_msg)
struct venc_range {
unsigned long max;
unsigned long min;
unsigned long step_size;
};
struct venc_switch {
unsigned char status;
};
struct venc_allocatorproperty {
unsigned long mincount;
unsigned long maxcount;
unsigned long actualcount;
unsigned long datasize;
unsigned long suffixsize;
unsigned long alignment;
unsigned long bufpoolid;
};
struct venc_bufferpayload {
unsigned char * pbuffer;
size_t sz;
int fd;
unsigned int offset;
unsigned int maped_size;
unsigned long filled_len;
};
struct venc_buffer {
unsigned char * ptrbuffer;
unsigned long sz;
unsigned long len;
unsigned long offset;
long long timestamp;
unsigned long flags;
void * clientdata;
};
struct venc_basecfg {
unsigned long input_width;
unsigned long input_height;
unsigned long dvs_width;
unsigned long dvs_height;
unsigned long codectype;
unsigned long fps_num;
unsigned long fps_den;
unsigned long targetbitrate;
unsigned long inputformat;
};
struct venc_profile {
unsigned long profile;
};
struct ven_profilelevel {
unsigned long level;
};
struct venc_sessionqp {
unsigned long iframeqp;
unsigned long pframqp;
};
struct venc_qprange {
unsigned long maxqp;
unsigned long minqp;
};
struct venc_plusptype {
unsigned long plusptype_enable;
};
struct venc_intraperiod {
unsigned long num_pframes;
unsigned long num_bframes;
};
struct venc_seqheader {
unsigned char * hdrbufptr;
unsigned long bufsize;
unsigned long hdrlen;
};
struct venc_capability {
unsigned long codec_types;
unsigned long maxframe_width;
unsigned long maxframe_height;
unsigned long maxtarget_bitrate;
unsigned long maxframe_rate;
unsigned long input_formats;
unsigned char dvs;
};
struct venc_entropycfg {
unsigned int longentropysel;
unsigned long cabacmodel;
};
struct venc_dbcfg {
unsigned long db_mode;
unsigned long slicealpha_offset;
unsigned long slicebeta_offset;
};
struct venc_intrarefresh {
unsigned long irmode;
unsigned long mbcount;
};
struct venc_multiclicecfg {
unsigned long mslice_mode;
unsigned long mslice_size;
};
struct venc_bufferflush {
unsigned long flush_mode;
};
struct venc_ratectrlcfg {
unsigned long rcmode;
};
struct venc_voptimingcfg {
unsigned long voptime_resolution;
};
struct venc_framerate {
unsigned long fps_denominator;
unsigned long fps_numerator;
};
struct venc_targetbitrate {
unsigned long target_bitrate;
};
struct venc_rotation {
unsigned long rotation;
};
struct venc_timeout {
unsigned long millisec;
};
struct venc_headerextension {
unsigned long header_extension;
};
struct venc_msg {
unsigned long statuscode;
unsigned long msgcode;
struct venc_buffer buf;
unsigned long msgdata_size;
};
struct venc_recon_addr {
unsigned char * pbuffer;
unsigned long buffer_size;
unsigned long pmem_fd;
unsigned long offset;
};
struct venc_recon_buff_size {
int width;
int height;
int size;
int alignment;
};
struct venc_ltrmode {
unsigned long ltr_mode;
};
struct venc_ltrcount {
unsigned long ltr_count;
};
struct venc_ltrperiod {
unsigned long ltr_period;
};
struct venc_ltruse {
unsigned long ltr_id;
unsigned long ltr_frames;
};
#endif

214
sdm710/kernel-headers/linux/qseecom.h
View File

@@ -1,214 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _QSEECOM_H_
#define _QSEECOM_H_
#include <linux/types.h>
#include <linux/ioctl.h>
#define MAX_ION_FD 4
#define MAX_APP_NAME_SIZE 64
#define QSEECOM_HASH_SIZE 32
#define QSEECOM_TA_ION_ALLOCATE_DELAY 50
#define QSEECOM_TA_ION_ALLOCATE_MAX_ATTEMP 20
struct qseecom_register_listener_req {
uint32_t listener_id;
int32_t ifd_data_fd;
void * virt_sb_base;
uint32_t sb_size;
};
struct qseecom_send_cmd_req {
void * cmd_req_buf;
unsigned int cmd_req_len;
void * resp_buf;
unsigned int resp_len;
};
struct qseecom_ion_fd_info {
int32_t fd;
uint32_t cmd_buf_offset;
};
struct qseecom_send_modfd_cmd_req {
void * cmd_req_buf;
unsigned int cmd_req_len;
void * resp_buf;
unsigned int resp_len;
struct qseecom_ion_fd_info ifd_data[MAX_ION_FD];
};
struct qseecom_send_resp_req {
void * resp_buf;
unsigned int resp_len;
};
struct qseecom_load_img_req {
uint32_t mdt_len;
uint32_t img_len;
int32_t ifd_data_fd;
char img_name[MAX_APP_NAME_SIZE];
uint32_t app_arch;
uint32_t app_id;
};
struct qseecom_set_sb_mem_param_req {
int32_t ifd_data_fd;
void * virt_sb_base;
uint32_t sb_len;
};
struct qseecom_qseos_version_req {
unsigned int qseos_version;
};
struct qseecom_qseos_app_load_query {
char app_name[MAX_APP_NAME_SIZE];
uint32_t app_id;
uint32_t app_arch;
};
struct qseecom_send_svc_cmd_req {
uint32_t cmd_id;
void * cmd_req_buf;
unsigned int cmd_req_len;
void * resp_buf;
unsigned int resp_len;
};
enum qseecom_key_management_usage_type {
QSEOS_KM_USAGE_DISK_ENCRYPTION = 0x01,
QSEOS_KM_USAGE_FILE_ENCRYPTION = 0x02,
QSEOS_KM_USAGE_UFS_ICE_DISK_ENCRYPTION = 0x03,
QSEOS_KM_USAGE_SDCC_ICE_DISK_ENCRYPTION = 0x04,
QSEOS_KM_USAGE_MAX
};
struct qseecom_create_key_req {
unsigned char hash32[QSEECOM_HASH_SIZE];
enum qseecom_key_management_usage_type usage;
};
struct qseecom_wipe_key_req {
enum qseecom_key_management_usage_type usage;
int wipe_key_flag;
};
struct qseecom_update_key_userinfo_req {
unsigned char current_hash32[QSEECOM_HASH_SIZE];
unsigned char new_hash32[QSEECOM_HASH_SIZE];
enum qseecom_key_management_usage_type usage;
};
#define SHA256_DIGEST_LENGTH (256 / 8)
struct qseecom_save_partition_hash_req {
int partition_id;
char digest[SHA256_DIGEST_LENGTH];
};
struct qseecom_is_es_activated_req {
int is_activated;
};
struct qseecom_mdtp_cipher_dip_req {
uint8_t * in_buf;
uint32_t in_buf_size;
uint8_t * out_buf;
uint32_t out_buf_size;
uint32_t direction;
};
enum qseecom_bandwidth_request_mode {
INACTIVE = 0,
LOW,
MEDIUM,
HIGH,
};
struct qseecom_send_modfd_listener_resp {
void * resp_buf_ptr;
unsigned int resp_len;
struct qseecom_ion_fd_info ifd_data[MAX_ION_FD];
};
struct qseecom_qteec_req {
void * req_ptr;
uint32_t req_len;
void * resp_ptr;
uint32_t resp_len;
};
struct qseecom_qteec_modfd_req {
void * req_ptr;
uint32_t req_len;
void * resp_ptr;
uint32_t resp_len;
struct qseecom_ion_fd_info ifd_data[MAX_ION_FD];
};
struct qseecom_sg_entry {
uint32_t phys_addr;
uint32_t len;
};
struct qseecom_sg_entry_64bit {
uint64_t phys_addr;
uint32_t len;
} __attribute__((packed));
#define QSEECOM_SG_LIST_BUF_FORMAT_VERSION_1 1
#define QSEECOM_SG_LIST_BUF_FORMAT_VERSION_2 2
struct qseecom_sg_list_buf_hdr_64bit {
struct qseecom_sg_entry_64bit blank_entry;
uint32_t version;
uint64_t new_buf_phys_addr;
uint32_t nents_total;
} __attribute__((packed));
#define QSEECOM_SG_LIST_BUF_HDR_SZ_64BIT sizeof(struct qseecom_sg_list_buf_hdr_64bit)
#define MAX_CE_PIPE_PAIR_PER_UNIT 3
#define INVALID_CE_INFO_UNIT_NUM 0xffffffff
#define CE_PIPE_PAIR_USE_TYPE_FDE 0
#define CE_PIPE_PAIR_USE_TYPE_PFE 1
struct qseecom_ce_pipe_entry {
int valid;
unsigned int ce_num;
unsigned int ce_pipe_pair;
};
#define MAX_CE_INFO_HANDLE_SIZE 32
struct qseecom_ce_info_req {
unsigned char handle[MAX_CE_INFO_HANDLE_SIZE];
unsigned int usage;
unsigned int unit_num;
unsigned int num_ce_pipe_entries;
struct qseecom_ce_pipe_entry ce_pipe_entry[MAX_CE_PIPE_PAIR_PER_UNIT];
};
#define SG_ENTRY_SZ sizeof(struct qseecom_sg_entry)
#define SG_ENTRY_SZ_64BIT sizeof(struct qseecom_sg_entry_64bit)
struct file;
#define QSEECOM_IOC_MAGIC 0x97
#define QSEECOM_IOCTL_REGISTER_LISTENER_REQ _IOWR(QSEECOM_IOC_MAGIC, 1, struct qseecom_register_listener_req)
#define QSEECOM_IOCTL_UNREGISTER_LISTENER_REQ _IO(QSEECOM_IOC_MAGIC, 2)
#define QSEECOM_IOCTL_SEND_CMD_REQ _IOWR(QSEECOM_IOC_MAGIC, 3, struct qseecom_send_cmd_req)
#define QSEECOM_IOCTL_SEND_MODFD_CMD_REQ _IOWR(QSEECOM_IOC_MAGIC, 4, struct qseecom_send_modfd_cmd_req)
#define QSEECOM_IOCTL_RECEIVE_REQ _IO(QSEECOM_IOC_MAGIC, 5)
#define QSEECOM_IOCTL_SEND_RESP_REQ _IO(QSEECOM_IOC_MAGIC, 6)
#define QSEECOM_IOCTL_LOAD_APP_REQ _IOWR(QSEECOM_IOC_MAGIC, 7, struct qseecom_load_img_req)
#define QSEECOM_IOCTL_SET_MEM_PARAM_REQ _IOWR(QSEECOM_IOC_MAGIC, 8, struct qseecom_set_sb_mem_param_req)
#define QSEECOM_IOCTL_UNLOAD_APP_REQ _IO(QSEECOM_IOC_MAGIC, 9)
#define QSEECOM_IOCTL_GET_QSEOS_VERSION_REQ _IOWR(QSEECOM_IOC_MAGIC, 10, struct qseecom_qseos_version_req)
#define QSEECOM_IOCTL_PERF_ENABLE_REQ _IO(QSEECOM_IOC_MAGIC, 11)
#define QSEECOM_IOCTL_PERF_DISABLE_REQ _IO(QSEECOM_IOC_MAGIC, 12)
#define QSEECOM_IOCTL_LOAD_EXTERNAL_ELF_REQ _IOWR(QSEECOM_IOC_MAGIC, 13, struct qseecom_load_img_req)
#define QSEECOM_IOCTL_UNLOAD_EXTERNAL_ELF_REQ _IO(QSEECOM_IOC_MAGIC, 14)
#define QSEECOM_IOCTL_APP_LOADED_QUERY_REQ _IOWR(QSEECOM_IOC_MAGIC, 15, struct qseecom_qseos_app_load_query)
#define QSEECOM_IOCTL_SEND_CMD_SERVICE_REQ _IOWR(QSEECOM_IOC_MAGIC, 16, struct qseecom_send_svc_cmd_req)
#define QSEECOM_IOCTL_CREATE_KEY_REQ _IOWR(QSEECOM_IOC_MAGIC, 17, struct qseecom_create_key_req)
#define QSEECOM_IOCTL_WIPE_KEY_REQ _IOWR(QSEECOM_IOC_MAGIC, 18, struct qseecom_wipe_key_req)
#define QSEECOM_IOCTL_SAVE_PARTITION_HASH_REQ _IOWR(QSEECOM_IOC_MAGIC, 19, struct qseecom_save_partition_hash_req)
#define QSEECOM_IOCTL_IS_ES_ACTIVATED_REQ _IOWR(QSEECOM_IOC_MAGIC, 20, struct qseecom_is_es_activated_req)
#define QSEECOM_IOCTL_SEND_MODFD_RESP _IOWR(QSEECOM_IOC_MAGIC, 21, struct qseecom_send_modfd_listener_resp)
#define QSEECOM_IOCTL_SET_BUS_SCALING_REQ _IOWR(QSEECOM_IOC_MAGIC, 23, int)
#define QSEECOM_IOCTL_UPDATE_KEY_USER_INFO_REQ _IOWR(QSEECOM_IOC_MAGIC, 24, struct qseecom_update_key_userinfo_req)
#define QSEECOM_QTEEC_IOCTL_OPEN_SESSION_REQ _IOWR(QSEECOM_IOC_MAGIC, 30, struct qseecom_qteec_modfd_req)
#define QSEECOM_QTEEC_IOCTL_CLOSE_SESSION_REQ _IOWR(QSEECOM_IOC_MAGIC, 31, struct qseecom_qteec_req)
#define QSEECOM_QTEEC_IOCTL_INVOKE_MODFD_CMD_REQ _IOWR(QSEECOM_IOC_MAGIC, 32, struct qseecom_qteec_modfd_req)
#define QSEECOM_QTEEC_IOCTL_REQUEST_CANCELLATION_REQ _IOWR(QSEECOM_IOC_MAGIC, 33, struct qseecom_qteec_modfd_req)
#define QSEECOM_IOCTL_MDTP_CIPHER_DIP_REQ _IOWR(QSEECOM_IOC_MAGIC, 34, struct qseecom_mdtp_cipher_dip_req)
#define QSEECOM_IOCTL_SEND_MODFD_CMD_64_REQ _IOWR(QSEECOM_IOC_MAGIC, 35, struct qseecom_send_modfd_cmd_req)
#define QSEECOM_IOCTL_SEND_MODFD_RESP_64 _IOWR(QSEECOM_IOC_MAGIC, 36, struct qseecom_send_modfd_listener_resp)
#define QSEECOM_IOCTL_GET_CE_PIPE_INFO _IOWR(QSEECOM_IOC_MAGIC, 40, struct qseecom_ce_info_req)
#define QSEECOM_IOCTL_FREE_CE_PIPE_INFO _IOWR(QSEECOM_IOC_MAGIC, 41, struct qseecom_ce_info_req)
#define QSEECOM_IOCTL_QUERY_CE_PIPE_INFO _IOWR(QSEECOM_IOC_MAGIC, 42, struct qseecom_ce_info_req)
#endif

115
sdm710/kernel-headers/linux/rmnet_data.h
View File

@@ -1,115 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _RMNET_DATA_H_
#define _RMNET_DATA_H_
#define RMNET_LOCAL_LOGICAL_ENDPOINT - 1
#define RMNET_EGRESS_FORMAT__RESERVED__ (1 << 0)
#define RMNET_EGRESS_FORMAT_MAP (1 << 1)
#define RMNET_EGRESS_FORMAT_AGGREGATION (1 << 2)
#define RMNET_EGRESS_FORMAT_MUXING (1 << 3)
#define RMNET_EGRESS_FORMAT_MAP_CKSUMV3 (1 << 4)
#define RMNET_EGRESS_FORMAT_MAP_CKSUMV4 (1 << 5)
#define RMNET_INGRESS_FIX_ETHERNET (1 << 0)
#define RMNET_INGRESS_FORMAT_MAP (1 << 1)
#define RMNET_INGRESS_FORMAT_DEAGGREGATION (1 << 2)
#define RMNET_INGRESS_FORMAT_DEMUXING (1 << 3)
#define RMNET_INGRESS_FORMAT_MAP_COMMANDS (1 << 4)
#define RMNET_INGRESS_FORMAT_MAP_CKSUMV3 (1 << 5)
#define RMNET_INGRESS_FORMAT_MAP_CKSUMV4 (1 << 6)
#define RMNET_NETLINK_PROTO 31
#define RMNET_MAX_STR_LEN 16
#define RMNET_NL_DATA_MAX_LEN 64
#define RMNET_NETLINK_MSG_COMMAND 0
#define RMNET_NETLINK_MSG_RETURNCODE 1
#define RMNET_NETLINK_MSG_RETURNDATA 2
struct rmnet_nl_msg_s {
uint16_t reserved;
uint16_t message_type;
uint16_t reserved2 : 14;
uint16_t crd : 2;
union {
uint16_t arg_length;
uint16_t return_code;
};
union {
uint8_t data[RMNET_NL_DATA_MAX_LEN];
struct {
uint8_t dev[RMNET_MAX_STR_LEN];
uint32_t flags;
uint16_t agg_size;
uint16_t agg_count;
uint8_t tail_spacing;
} data_format;
struct {
uint8_t dev[RMNET_MAX_STR_LEN];
int32_t ep_id;
uint8_t operating_mode;
uint8_t next_dev[RMNET_MAX_STR_LEN];
} local_ep_config;
struct {
uint32_t id;
uint8_t vnd_name[RMNET_MAX_STR_LEN];
} vnd;
struct {
uint32_t id;
uint32_t map_flow_id;
uint32_t tc_flow_id;
} flow_control;
};
};
enum rmnet_netlink_message_types_e {
RMNET_NETLINK_ASSOCIATE_NETWORK_DEVICE,
RMNET_NETLINK_UNASSOCIATE_NETWORK_DEVICE,
RMNET_NETLINK_GET_NETWORK_DEVICE_ASSOCIATED,
RMNET_NETLINK_SET_LINK_EGRESS_DATA_FORMAT,
RMNET_NETLINK_GET_LINK_EGRESS_DATA_FORMAT,
RMNET_NETLINK_SET_LINK_INGRESS_DATA_FORMAT,
RMNET_NETLINK_GET_LINK_INGRESS_DATA_FORMAT,
RMNET_NETLINK_SET_LOGICAL_EP_CONFIG,
RMNET_NETLINK_UNSET_LOGICAL_EP_CONFIG,
RMNET_NETLINK_GET_LOGICAL_EP_CONFIG,
RMNET_NETLINK_NEW_VND,
RMNET_NETLINK_NEW_VND_WITH_PREFIX,
RMNET_NETLINK_GET_VND_NAME,
RMNET_NETLINK_FREE_VND,
RMNET_NETLINK_ADD_VND_TC_FLOW,
RMNET_NETLINK_DEL_VND_TC_FLOW,
RMNET_NETLINK_NEW_VND_WITH_NAME
};
#define RMNET_NETLINK_NEW_VND_WITH_NAME RMNET_NETLINK_NEW_VND_WITH_NAME
enum rmnet_config_endpoint_modes_e {
RMNET_EPMODE_NONE,
RMNET_EPMODE_VND,
RMNET_EPMODE_BRIDGE,
RMNET_EPMODE_LENGTH
};
enum rmnet_config_return_codes_e {
RMNET_CONFIG_OK,
RMNET_CONFIG_UNKNOWN_MESSAGE,
RMNET_CONFIG_UNKNOWN_ERROR,
RMNET_CONFIG_NOMEM,
RMNET_CONFIG_DEVICE_IN_USE,
RMNET_CONFIG_INVALID_REQUEST,
RMNET_CONFIG_NO_SUCH_DEVICE,
RMNET_CONFIG_BAD_ARGUMENTS,
RMNET_CONFIG_BAD_EGRESS_DEVICE,
RMNET_CONFIG_TC_HANDLE_FULL
};
#endif

140
sdm710/kernel-headers/linux/rmnet_ipa_fd_ioctl.h
View File

@@ -1,140 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _RMNET_IPA_FD_IOCTL_H
#define _RMNET_IPA_FD_IOCTL_H
#include <linux/ioctl.h>
#include <linux/ipa_qmi_service_v01.h>
#include <linux/msm_ipa.h>
#define WAN_IOC_MAGIC 0x69
#define WAN_IOCTL_ADD_FLT_RULE 0
#define WAN_IOCTL_ADD_FLT_INDEX 1
#define WAN_IOCTL_VOTE_FOR_BW_MBPS 2
#define WAN_IOCTL_POLL_TETHERING_STATS 3
#define WAN_IOCTL_SET_DATA_QUOTA 4
#define WAN_IOCTL_SET_TETHER_CLIENT_PIPE 5
#define WAN_IOCTL_QUERY_TETHER_STATS 6
#define WAN_IOCTL_RESET_TETHER_STATS 7
#define WAN_IOCTL_QUERY_DL_FILTER_STATS 8
#define WAN_IOCTL_ADD_FLT_RULE_EX 9
#define WAN_IOCTL_QUERY_TETHER_STATS_ALL 10
#define WAN_IOCTL_NOTIFY_WAN_STATE 11
#define WAN_IOCTL_ADD_UL_FLT_RULE 12
#define WAN_IOCTL_ENABLE_PER_CLIENT_STATS 13
#define WAN_IOCTL_QUERY_PER_CLIENT_STATS 14
#define WAN_IOCTL_SET_LAN_CLIENT_INFO 15
#define WAN_IOCTL_CLEAR_LAN_CLIENT_INFO 16
#define WAN_IOCTL_SEND_LAN_CLIENT_MSG 17
#ifndef IFNAMSIZ
#define IFNAMSIZ 16
#endif
struct wan_ioctl_poll_tethering_stats {
uint64_t polling_interval_secs;
uint8_t reset_stats;
};
struct wan_ioctl_set_data_quota {
char interface_name[IFNAMSIZ];
uint64_t quota_mbytes;
uint8_t set_quota;
};
struct wan_ioctl_set_tether_client_pipe {
enum ipacm_client_enum ipa_client;
uint8_t reset_client;
uint32_t ul_src_pipe_len;
uint32_t ul_src_pipe_list[QMI_IPA_MAX_PIPES_V01];
uint32_t dl_dst_pipe_len;
uint32_t dl_dst_pipe_list[QMI_IPA_MAX_PIPES_V01];
};
struct wan_ioctl_query_tether_stats {
char upstreamIface[IFNAMSIZ];
char tetherIface[IFNAMSIZ];
enum ipacm_client_enum ipa_client;
uint64_t ipv4_tx_packets;
uint64_t ipv4_tx_bytes;
uint64_t ipv4_rx_packets;
uint64_t ipv4_rx_bytes;
uint64_t ipv6_tx_packets;
uint64_t ipv6_tx_bytes;
uint64_t ipv6_rx_packets;
uint64_t ipv6_rx_bytes;
};
struct wan_ioctl_query_tether_stats_all {
char upstreamIface[IFNAMSIZ];
enum ipacm_client_enum ipa_client;
uint8_t reset_stats;
uint64_t tx_bytes;
uint64_t rx_bytes;
};
struct wan_ioctl_reset_tether_stats {
char upstreamIface[IFNAMSIZ];
uint8_t reset_stats;
};
struct wan_ioctl_query_dl_filter_stats {
uint8_t reset_stats;
struct ipa_get_data_stats_resp_msg_v01 stats_resp;
uint32_t index;
};
struct wan_ioctl_notify_wan_state {
uint8_t up;
};
struct wan_ioctl_send_lan_client_msg {
struct ipa_lan_client_msg lan_client;
enum ipa_per_client_stats_event client_event;
};
struct wan_ioctl_lan_client_info {
enum ipacm_per_client_device_type device_type;
uint8_t mac[IPA_MAC_ADDR_SIZE];
uint8_t client_init;
int8_t client_idx;
uint8_t hdr_len;
enum ipa_client_type ul_src_pipe;
};
struct wan_ioctl_per_client_info {
uint8_t mac[IPA_MAC_ADDR_SIZE];
uint64_t ipv4_tx_bytes;
uint64_t ipv4_rx_bytes;
uint64_t ipv6_tx_bytes;
uint64_t ipv6_rx_bytes;
};
struct wan_ioctl_query_per_client_stats {
enum ipacm_per_client_device_type device_type;
uint8_t reset_stats;
uint8_t disconnect_clnt;
uint8_t num_clients;
struct wan_ioctl_per_client_info client_info[IPA_MAX_NUM_HW_PATH_CLIENTS];
};
#define WAN_IOC_ADD_FLT_RULE _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_ADD_FLT_RULE, struct ipa_install_fltr_rule_req_msg_v01 *)
#define WAN_IOC_ADD_FLT_RULE_INDEX _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_ADD_FLT_INDEX, struct ipa_fltr_installed_notif_req_msg_v01 *)
#define WAN_IOC_VOTE_FOR_BW_MBPS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_VOTE_FOR_BW_MBPS, uint32_t *)
#define WAN_IOC_POLL_TETHERING_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_POLL_TETHERING_STATS, struct wan_ioctl_poll_tethering_stats *)
#define WAN_IOC_SET_DATA_QUOTA _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_SET_DATA_QUOTA, struct wan_ioctl_set_data_quota *)
#define WAN_IOC_SET_TETHER_CLIENT_PIPE _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_SET_TETHER_CLIENT_PIPE, struct wan_ioctl_set_tether_client_pipe *)
#define WAN_IOC_QUERY_TETHER_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_QUERY_TETHER_STATS, struct wan_ioctl_query_tether_stats *)
#define WAN_IOC_RESET_TETHER_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_RESET_TETHER_STATS, struct wan_ioctl_reset_tether_stats *)
#define WAN_IOC_QUERY_DL_FILTER_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_QUERY_DL_FILTER_STATS, struct wan_ioctl_query_dl_filter_stats *)
#define WAN_IOC_ADD_FLT_RULE_EX _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_ADD_FLT_RULE_EX, struct ipa_install_fltr_rule_req_ex_msg_v01 *)
#define WAN_IOC_QUERY_TETHER_STATS_ALL _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_QUERY_TETHER_STATS_ALL, struct wan_ioctl_query_tether_stats_all *)
#define WAN_IOC_NOTIFY_WAN_STATE _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_NOTIFY_WAN_STATE, struct wan_ioctl_notify_wan_state *)
#define WAN_IOC_ADD_UL_FLT_RULE _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_ADD_UL_FLT_RULE, struct ipa_configure_ul_firewall_rules_req_msg_v01 *)
#define WAN_IOC_ENABLE_PER_CLIENT_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_ENABLE_PER_CLIENT_STATS, bool *)
#define WAN_IOC_QUERY_PER_CLIENT_STATS _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_QUERY_PER_CLIENT_STATS, struct wan_ioctl_query_per_client_stats *)
#define WAN_IOC_SET_LAN_CLIENT_INFO _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_SET_LAN_CLIENT_INFO, struct wan_ioctl_lan_client_info *)
#define WAN_IOC_SEND_LAN_CLIENT_MSG _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_SEND_LAN_CLIENT_MSG, struct wan_ioctl_send_lan_client_msg *)
#define WAN_IOC_CLEAR_LAN_CLIENT_INFO _IOWR(WAN_IOC_MAGIC, WAN_IOCTL_CLEAR_LAN_CLIENT_INFO, struct wan_ioctl_lan_client_info *)
#endif

99
sdm710/kernel-headers/linux/sockios.h
View File

@@ -1,99 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _LINUX_SOCKIOS_H
#define _LINUX_SOCKIOS_H
#include <asm/sockios.h>
#define SIOCINQ FIONREAD
#define SIOCOUTQ TIOCOUTQ
#define SIOCADDRT 0x890B
#define SIOCDELRT 0x890C
#define SIOCRTMSG 0x890D
#define SIOCGIFNAME 0x8910
#define SIOCSIFLINK 0x8911
#define SIOCGIFCONF 0x8912
#define SIOCGIFFLAGS 0x8913
#define SIOCSIFFLAGS 0x8914
#define SIOCGIFADDR 0x8915
#define SIOCSIFADDR 0x8916
#define SIOCGIFDSTADDR 0x8917
#define SIOCSIFDSTADDR 0x8918
#define SIOCGIFBRDADDR 0x8919
#define SIOCSIFBRDADDR 0x891a
#define SIOCGIFNETMASK 0x891b
#define SIOCSIFNETMASK 0x891c
#define SIOCGIFMETRIC 0x891d
#define SIOCSIFMETRIC 0x891e
#define SIOCGIFMEM 0x891f
#define SIOCSIFMEM 0x8920
#define SIOCGIFMTU 0x8921
#define SIOCSIFMTU 0x8922
#define SIOCSIFNAME 0x8923
#define SIOCSIFHWADDR 0x8924
#define SIOCGIFENCAP 0x8925
#define SIOCSIFENCAP 0x8926
#define SIOCGIFHWADDR 0x8927
#define SIOCGIFSLAVE 0x8929
#define SIOCSIFSLAVE 0x8930
#define SIOCADDMULTI 0x8931
#define SIOCDELMULTI 0x8932
#define SIOCGIFINDEX 0x8933
#define SIOGIFINDEX SIOCGIFINDEX
#define SIOCSIFPFLAGS 0x8934
#define SIOCGIFPFLAGS 0x8935
#define SIOCDIFADDR 0x8936
#define SIOCSIFHWBROADCAST 0x8937
#define SIOCGIFCOUNT 0x8938
#define SIOCGIFBR 0x8940
#define SIOCSIFBR 0x8941
#define SIOCGIFTXQLEN 0x8942
#define SIOCSIFTXQLEN 0x8943
#define SIOCETHTOOL 0x8946
#define SIOCGMIIPHY 0x8947
#define SIOCGMIIREG 0x8948
#define SIOCSMIIREG 0x8949
#define SIOCWANDEV 0x894A
#define SIOCOUTQNSD 0x894B
#define SIOCDARP 0x8953
#define SIOCGARP 0x8954
#define SIOCSARP 0x8955
#define SIOCDRARP 0x8960
#define SIOCGRARP 0x8961
#define SIOCSRARP 0x8962
#define SIOCGIFMAP 0x8970
#define SIOCSIFMAP 0x8971
#define SIOCADDDLCI 0x8980
#define SIOCDELDLCI 0x8981
#define SIOCGIFVLAN 0x8982
#define SIOCSIFVLAN 0x8983
#define SIOCBONDENSLAVE 0x8990
#define SIOCBONDRELEASE 0x8991
#define SIOCBONDSETHWADDR 0x8992
#define SIOCBONDSLAVEINFOQUERY 0x8993
#define SIOCBONDINFOQUERY 0x8994
#define SIOCBONDCHANGEACTIVE 0x8995
#define SIOCBRADDBR 0x89a0
#define SIOCBRDELBR 0x89a1
#define SIOCBRADDIF 0x89a2
#define SIOCBRDELIF 0x89a3
#define SIOCSHWTSTAMP 0x89b0
#define SIOCGHWTSTAMP 0x89b1
#define SIOCDEVPRIVATE 0x89F0
#define SIOCPROTOPRIVATE 0x89E0
#endif

78
sdm710/kernel-headers/linux/spcom.h
View File

@@ -1,78 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _SPCOM_H_
#define _SPCOM_H_
#include <linux/types.h>
#ifndef BIT
#define BIT(x) (1 << x)
#endif
#ifndef PAGE_SIZE
#define PAGE_SIZE 4096
#endif
#define SPCOM_MAX_CHANNELS 0x20
#define SPCOM_CHANNEL_NAME_SIZE 32
#define SPCOM_GET_NEXT_REQUEST_SIZE (PAGE_SIZE - 1)
enum spcom_cmd_id {
SPCOM_CMD_LOAD_APP = 0x4C4F4144,
SPCOM_CMD_RESET_SP = 0x52455354,
SPCOM_CMD_SEND = 0x53454E44,
SPCOM_CMD_SEND_MODIFIED = 0x534E444D,
SPCOM_CMD_LOCK_ION_BUF = 0x4C4F434B,
SPCOM_CMD_UNLOCK_ION_BUF = 0x554C434B,
SPCOM_CMD_FSSR = 0x46535352,
SPCOM_CMD_CREATE_CHANNEL = 0x43524554,
};
enum spcom_poll_events {
SPCOM_POLL_LINK_STATE = BIT(1),
SPCOM_POLL_CH_CONNECT = BIT(2),
SPCOM_POLL_READY_FLAG = BIT(14),
SPCOM_POLL_WAIT_FLAG = BIT(15),
};
struct spcom_user_command {
enum spcom_cmd_id cmd_id;
uint32_t arg;
} __attribute__((packed));
struct spcom_send_command {
enum spcom_cmd_id cmd_id;
uint32_t timeout_msec;
uint32_t buf_size;
char buf[0];
} __attribute__((packed));
struct spcom_user_create_channel_command {
enum spcom_cmd_id cmd_id;
char ch_name[SPCOM_CHANNEL_NAME_SIZE];
} __attribute__((packed));
#define SPCOM_MAX_ION_BUF 4
struct spcom_ion_info {
int32_t fd;
uint32_t buf_offset;
};
#define SPCOM_ION_FD_UNLOCK_ALL 0xFFFF
struct spcom_ion_handle {
int32_t fd;
};
struct spcom_user_send_modified_command {
enum spcom_cmd_id cmd_id;
struct spcom_ion_info ion_info[SPCOM_MAX_ION_BUF];
uint32_t timeout_msec;
uint32_t buf_size;
char buf[0];
} __attribute__((packed));
#endif

1286
sdm710/kernel-headers/linux/v4l2-controls.h
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File diff suppressed because it is too large Load Diff

1400
sdm710/kernel-headers/linux/videodev2.h
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File diff suppressed because it is too large Load Diff

38
sdm710/kernel-headers/linux/wcd-spi-ac-params.h
View File

@@ -1,38 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_WCD_SPI_AC_PARAMS_H__
#define __UAPI_WCD_SPI_AC_PARAMS_H__
#include <linux/types.h>
#define WCD_SPI_AC_CMD_CONC_BEGIN 0x01
#define WCD_SPI_AC_CMD_CONC_END 0x02
#define WCD_SPI_AC_CMD_BUF_DATA 0x03
#define WCD_SPI_AC_MAX_BUFFERS 2
#define WCD_SPI_AC_MAX_CH_PER_BUF 8
#define WCD_SPI_AC_CLIENT_CDEV_NAME "wcd-spi-ac-client"
#define WCD_SPI_AC_PROCFS_DIR_NAME "wcd-spi-ac"
#define WCD_SPI_AC_PROCFS_STATE_NAME "svc-state"
struct wcd_spi_ac_buf_data {
__u32 addr[WCD_SPI_AC_MAX_CH_PER_BUF];
} __attribute__((packed));
struct wcd_spi_ac_write_cmd {
__u32 cmd_type;
__u8 payload[0];
} __attribute__((packed));
#endif

31
sdm710/kernel-headers/media/cam_cpas.h
View File

@@ -1,31 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_CPAS_H__
#define __UAPI_CAM_CPAS_H__
#include "cam_defs.h"
#define CAM_FAMILY_CAMERA_SS 1
#define CAM_FAMILY_CPAS_SS 2
struct cam_cpas_query_cap {
uint32_t camera_family;
uint32_t reserved;
struct cam_hw_version camera_version;
struct cam_hw_version cpas_version;
};
#endif

262
sdm710/kernel-headers/media/cam_defs.h
View File

@@ -1,262 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_DEFS_H__
#define __UAPI_CAM_DEFS_H__
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
#define CAM_COMMON_OPCODE_BASE 0x100
#define CAM_QUERY_CAP (CAM_COMMON_OPCODE_BASE + 0x1)
#define CAM_ACQUIRE_DEV (CAM_COMMON_OPCODE_BASE + 0x2)
#define CAM_START_DEV (CAM_COMMON_OPCODE_BASE + 0x3)
#define CAM_STOP_DEV (CAM_COMMON_OPCODE_BASE + 0x4)
#define CAM_CONFIG_DEV (CAM_COMMON_OPCODE_BASE + 0x5)
#define CAM_RELEASE_DEV (CAM_COMMON_OPCODE_BASE + 0x6)
#define CAM_SD_SHUTDOWN (CAM_COMMON_OPCODE_BASE + 0x7)
#define CAM_FLUSH_REQ (CAM_COMMON_OPCODE_BASE + 0x8)
#define CAM_COMMON_OPCODE_MAX (CAM_COMMON_OPCODE_BASE + 0x9)
#define CAM_EXT_OPCODE_BASE 0x200
#define CAM_CONFIG_DEV_EXTERNAL (CAM_EXT_OPCODE_BASE + 0x1)
#define CAM_HANDLE_USER_POINTER 1
#define CAM_HANDLE_MEM_HANDLE 2
#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK 0xFFFFFF00
#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT 8
#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK 0xFF
#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT 0
#define CAM_CMD_BUF_DMI 0x1
#define CAM_CMD_BUF_DMI16 0x2
#define CAM_CMD_BUF_DMI32 0x3
#define CAM_CMD_BUF_DMI64 0x4
#define CAM_CMD_BUF_DIRECT 0x5
#define CAM_CMD_BUF_INDIRECT 0x6
#define CAM_CMD_BUF_I2C 0x7
#define CAM_CMD_BUF_FW 0x8
#define CAM_CMD_BUF_GENERIC 0x9
#define CAM_CMD_BUF_LEGACY 0xA
enum flush_type_t {
CAM_FLUSH_TYPE_REQ,
CAM_FLUSH_TYPE_ALL,
CAM_FLUSH_TYPE_MAX
};
struct cam_control {
uint32_t op_code;
uint32_t size;
uint32_t handle_type;
uint32_t reserved;
uint64_t handle;
};
#define VIDIOC_CAM_CONTROL _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_control)
struct cam_hw_version {
uint32_t major;
uint32_t minor;
uint32_t incr;
uint32_t reserved;
};
struct cam_iommu_handle {
int32_t non_secure;
int32_t secure;
};
#define CAM_SECURE_MODE_NON_SECURE 0
#define CAM_SECURE_MODE_SECURE 1
#define CAM_FORMAT_BASE 0
#define CAM_FORMAT_MIPI_RAW_6 1
#define CAM_FORMAT_MIPI_RAW_8 2
#define CAM_FORMAT_MIPI_RAW_10 3
#define CAM_FORMAT_MIPI_RAW_12 4
#define CAM_FORMAT_MIPI_RAW_14 5
#define CAM_FORMAT_MIPI_RAW_16 6
#define CAM_FORMAT_MIPI_RAW_20 7
#define CAM_FORMAT_QTI_RAW_8 8
#define CAM_FORMAT_QTI_RAW_10 9
#define CAM_FORMAT_QTI_RAW_12 10
#define CAM_FORMAT_QTI_RAW_14 11
#define CAM_FORMAT_PLAIN8 12
#define CAM_FORMAT_PLAIN16_8 13
#define CAM_FORMAT_PLAIN16_10 14
#define CAM_FORMAT_PLAIN16_12 15
#define CAM_FORMAT_PLAIN16_14 16
#define CAM_FORMAT_PLAIN16_16 17
#define CAM_FORMAT_PLAIN32_20 18
#define CAM_FORMAT_PLAIN64 19
#define CAM_FORMAT_PLAIN128 20
#define CAM_FORMAT_ARGB 21
#define CAM_FORMAT_ARGB_10 22
#define CAM_FORMAT_ARGB_12 23
#define CAM_FORMAT_ARGB_14 24
#define CAM_FORMAT_DPCM_10_6_10 25
#define CAM_FORMAT_DPCM_10_8_10 26
#define CAM_FORMAT_DPCM_12_6_12 27
#define CAM_FORMAT_DPCM_12_8_12 28
#define CAM_FORMAT_DPCM_14_8_14 29
#define CAM_FORMAT_DPCM_14_10_14 30
#define CAM_FORMAT_NV21 31
#define CAM_FORMAT_NV12 32
#define CAM_FORMAT_TP10 33
#define CAM_FORMAT_YUV422 34
#define CAM_FORMAT_PD8 35
#define CAM_FORMAT_PD10 36
#define CAM_FORMAT_UBWC_NV12 37
#define CAM_FORMAT_UBWC_NV12_4R 38
#define CAM_FORMAT_UBWC_TP10 39
#define CAM_FORMAT_UBWC_P010 40
#define CAM_FORMAT_PLAIN8_SWAP 41
#define CAM_FORMAT_PLAIN8_10 42
#define CAM_FORMAT_PLAIN8_10_SWAP 43
#define CAM_FORMAT_YV12 44
#define CAM_FORMAT_Y_ONLY 45
#define CAM_FORMAT_MAX 46
#define CAM_ROTATE_CW_0_DEGREE 0
#define CAM_ROTATE_CW_90_DEGREE 1
#define CAM_RORATE_CW_180_DEGREE 2
#define CAM_ROTATE_CW_270_DEGREE 3
#define CAM_COLOR_SPACE_BASE 0
#define CAM_COLOR_SPACE_BT601_FULL 1
#define CAM_COLOR_SPACE_BT601625 2
#define CAM_COLOR_SPACE_BT601525 3
#define CAM_COLOR_SPACE_BT709 4
#define CAM_COLOR_SPACE_DEPTH 5
#define CAM_COLOR_SPACE_MAX 6
#define CAM_BUF_INPUT 1
#define CAM_BUF_OUTPUT 2
#define CAM_BUF_IN_OUT 3
#define CAM_PACKET_DEV_BASE 0
#define CAM_PACKET_DEV_IMG_SENSOR 1
#define CAM_PACKET_DEV_ACTUATOR 2
#define CAM_PACKET_DEV_COMPANION 3
#define CAM_PACKET_DEV_EEPOM 4
#define CAM_PACKET_DEV_CSIPHY 5
#define CAM_PACKET_DEV_OIS 6
#define CAM_PACKET_DEV_FLASH 7
#define CAM_PACKET_DEV_FD 8
#define CAM_PACKET_DEV_JPEG_ENC 9
#define CAM_PACKET_DEV_JPEG_DEC 10
#define CAM_PACKET_DEV_VFE 11
#define CAM_PACKET_DEV_CPP 12
#define CAM_PACKET_DEV_CSID 13
#define CAM_PACKET_DEV_ISPIF 14
#define CAM_PACKET_DEV_IFE 15
#define CAM_PACKET_DEV_ICP 16
#define CAM_PACKET_DEV_LRME 17
#define CAM_PACKET_DEV_MAX 18
#define CAM_PACKET_MAX_PLANES 3
struct cam_plane_cfg {
uint32_t width;
uint32_t height;
uint32_t plane_stride;
uint32_t slice_height;
uint32_t meta_stride;
uint32_t meta_size;
uint32_t meta_offset;
uint32_t packer_config;
uint32_t mode_config;
uint32_t tile_config;
uint32_t h_init;
uint32_t v_init;
};
struct cam_cmd_buf_desc {
int32_t mem_handle;
uint32_t offset;
uint32_t size;
uint32_t length;
uint32_t type;
uint32_t meta_data;
};
struct cam_buf_io_cfg {
int32_t mem_handle[CAM_PACKET_MAX_PLANES];
uint32_t offsets[CAM_PACKET_MAX_PLANES];
struct cam_plane_cfg planes[CAM_PACKET_MAX_PLANES];
uint32_t format;
uint32_t color_space;
uint32_t color_pattern;
uint32_t bpp;
uint32_t rotation;
uint32_t resource_type;
int32_t fence;
int32_t early_fence;
struct cam_cmd_buf_desc aux_cmd_buf;
uint32_t direction;
uint32_t batch_size;
uint32_t subsample_pattern;
uint32_t subsample_period;
uint32_t framedrop_pattern;
uint32_t framedrop_period;
uint32_t flag;
uint32_t padding;
};
struct cam_packet_header {
uint32_t op_code;
uint32_t size;
uint64_t request_id;
uint32_t flags;
uint32_t padding;
};
struct cam_patch_desc {
int32_t dst_buf_hdl;
uint32_t dst_offset;
int32_t src_buf_hdl;
uint32_t src_offset;
};
struct cam_packet {
struct cam_packet_header header;
uint32_t cmd_buf_offset;
uint32_t num_cmd_buf;
uint32_t io_configs_offset;
uint32_t num_io_configs;
uint32_t patch_offset;
uint32_t num_patches;
uint32_t kmd_cmd_buf_index;
uint32_t kmd_cmd_buf_offset;
uint64_t payload[1];
};
struct cam_release_dev_cmd {
int32_t session_handle;
int32_t dev_handle;
};
struct cam_start_stop_dev_cmd {
int32_t session_handle;
int32_t dev_handle;
};
struct cam_config_dev_cmd {
int32_t session_handle;
int32_t dev_handle;
uint64_t offset;
uint64_t packet_handle;
};
struct cam_query_cap_cmd {
uint32_t size;
uint32_t handle_type;
uint64_t caps_handle;
};
struct cam_acquire_dev_cmd {
int32_t session_handle;
int32_t dev_handle;
uint32_t handle_type;
uint32_t num_resources;
uint64_t resource_hdl;
};
struct cam_flush_dev_cmd {
uint64_t version;
int32_t session_handle;
int32_t dev_handle;
uint32_t flush_type;
uint32_t reserved;
int64_t req_id;
};
#endif

73
sdm710/kernel-headers/media/cam_fd.h
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@@ -1,73 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_FD_H__
#define __UAPI_CAM_FD_H__
#include "cam_defs.h"
#define CAM_FD_MAX_FACES 35
#define CAM_FD_RAW_RESULT_ENTRIES 512
#define CAM_PACKET_OPCODES_FD_FRAME_UPDATE 0x0
#define CAM_FD_CMD_BUFFER_ID_GENERIC 0x0
#define CAM_FD_CMD_BUFFER_ID_CDM 0x1
#define CAM_FD_CMD_BUFFER_ID_MAX 0x2
#define CAM_FD_BLOB_TYPE_SOC_CLOCK_BW_REQUEST 0x0
#define CAM_FD_BLOB_TYPE_RAW_RESULTS_REQUIRED 0x1
#define CAM_FD_INPUT_PORT_ID_IMAGE 0x0
#define CAM_FD_INPUT_PORT_ID_MAX 0x1
#define CAM_FD_OUTPUT_PORT_ID_RESULTS 0x0
#define CAM_FD_OUTPUT_PORT_ID_RAW_RESULTS 0x1
#define CAM_FD_OUTPUT_PORT_ID_WORK_BUFFER 0x2
#define CAM_FD_OUTPUT_PORT_ID_MAX 0x3
struct cam_fd_soc_clock_bw_request {
uint64_t clock_rate;
uint64_t bandwidth;
uint64_t reserved[4];
};
struct cam_fd_face {
uint32_t prop1;
uint32_t prop2;
uint32_t prop3;
uint32_t prop4;
};
struct cam_fd_results {
struct cam_fd_face faces[CAM_FD_MAX_FACES];
uint32_t face_count;
uint32_t reserved[3];
};
struct cam_fd_hw_caps {
struct cam_hw_version core_version;
struct cam_hw_version wrapper_version;
uint32_t raw_results_available;
uint32_t supported_modes;
uint64_t reserved;
};
struct cam_fd_query_cap_cmd {
struct cam_iommu_handle device_iommu;
struct cam_iommu_handle cdm_iommu;
struct cam_fd_hw_caps hw_caps;
uint64_t reserved;
};
struct cam_fd_acquire_dev_info {
struct cam_fd_soc_clock_bw_request clk_bw_request;
uint32_t priority;
uint32_t mode;
uint32_t get_raw_results;
uint32_t reserved[13];
};
#endif

106
sdm710/kernel-headers/media/cam_icp.h
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@@ -1,106 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_ICP_H__
#define __UAPI_CAM_ICP_H__
#include "cam_defs.h"
#define CAM_ICP_DEV_TYPE_A5 1
#define CAM_ICP_DEV_TYPE_IPE 2
#define CAM_ICP_DEV_TYPE_BPS 3
#define CAM_ICP_DEV_TYPE_IPE_CDM 4
#define CAM_ICP_DEV_TYPE_BPS_CDM 5
#define CAM_ICP_DEV_TYPE_MAX 5
#define CAM_ICP_RES_TYPE_BPS 1
#define CAM_ICP_RES_TYPE_IPE_RT 2
#define CAM_ICP_RES_TYPE_IPE 3
#define CAM_ICP_RES_TYPE_MAX 4
#define CAM_ICP_OPCODE_IPE_UPDATE 0
#define CAM_ICP_OPCODE_BPS_UPDATE 1
#define CAM_ICP_IPE_INPUT_IMAGE_FULL 0x0
#define CAM_ICP_IPE_INPUT_IMAGE_DS4 0x1
#define CAM_ICP_IPE_INPUT_IMAGE_DS16 0x2
#define CAM_ICP_IPE_INPUT_IMAGE_DS64 0x3
#define CAM_ICP_IPE_INPUT_IMAGE_FULL_REF 0x4
#define CAM_ICP_IPE_INPUT_IMAGE_DS4_REF 0x5
#define CAM_ICP_IPE_INPUT_IMAGE_DS16_REF 0x6
#define CAM_ICP_IPE_INPUT_IMAGE_DS64_REF 0x7
#define CAM_ICP_IPE_OUTPUT_IMAGE_DISPLAY 0x8
#define CAM_ICP_IPE_OUTPUT_IMAGE_VIDEO 0x9
#define CAM_ICP_IPE_OUTPUT_IMAGE_FULL_REF 0xA
#define CAM_ICP_IPE_OUTPUT_IMAGE_DS4_REF 0xB
#define CAM_ICP_IPE_OUTPUT_IMAGE_DS16_REF 0xC
#define CAM_ICP_IPE_OUTPUT_IMAGE_DS64_REF 0xD
#define CAM_ICP_IPE_IMAGE_MAX 0xE
#define CAM_ICP_BPS_INPUT_IMAGE 0x0
#define CAM_ICP_BPS_OUTPUT_IMAGE_FULL 0x1
#define CAM_ICP_BPS_OUTPUT_IMAGE_DS4 0x2
#define CAM_ICP_BPS_OUTPUT_IMAGE_DS16 0x3
#define CAM_ICP_BPS_OUTPUT_IMAGE_DS64 0x4
#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BG 0x5
#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BHIST 0x6
#define CAM_ICP_BPS_OUTPUT_IMAGE_REG1 0x7
#define CAM_ICP_BPS_OUTPUT_IMAGE_REG2 0x8
#define CAM_ICP_BPS_IO_IMAGES_MAX 0x9
#define CAM_ICP_CMD_META_GENERIC_BLOB 0x1
#define CAM_ICP_CMD_GENERIC_BLOB_CLK 0x1
struct cam_icp_clk_bw_request {
uint64_t budget_ns;
uint32_t frame_cycles;
uint32_t rt_flag;
uint64_t uncompressed_bw;
uint64_t compressed_bw;
};
struct cam_icp_dev_ver {
uint32_t dev_type;
uint32_t reserved;
struct cam_hw_version hw_ver;
};
struct cam_icp_ver {
uint32_t major;
uint32_t minor;
uint32_t revision;
uint32_t reserved;
};
struct cam_icp_query_cap_cmd {
struct cam_iommu_handle dev_iommu_handle;
struct cam_iommu_handle cdm_iommu_handle;
struct cam_icp_ver fw_version;
struct cam_icp_ver api_version;
uint32_t num_ipe;
uint32_t num_bps;
struct cam_icp_dev_ver dev_ver[CAM_ICP_DEV_TYPE_MAX];
};
struct cam_icp_res_info {
uint32_t format;
uint32_t width;
uint32_t height;
uint32_t fps;
};
struct cam_icp_acquire_dev_info {
uint32_t scratch_mem_size;
uint32_t dev_type;
uint32_t io_config_cmd_size;
int32_t io_config_cmd_handle;
uint32_t secure_mode;
int32_t chain_info;
struct cam_icp_res_info in_res;
uint32_t num_out_res;
struct cam_icp_res_info out_res[1];
} __attribute__((__packed__));
#endif

188
sdm710/kernel-headers/media/cam_isp.h
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@@ -1,188 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_ISP_H__
#define __UAPI_CAM_ISP_H__
#include "cam_defs.h"
#include "cam_isp_vfe.h"
#include "cam_isp_ife.h"
#define CAM_ISP_DEV_NAME "cam-isp"
#define CAM_ISP_HW_BASE 0
#define CAM_ISP_HW_CSID 1
#define CAM_ISP_HW_VFE 2
#define CAM_ISP_HW_IFE 3
#define CAM_ISP_HW_ISPIF 4
#define CAM_ISP_HW_MAX 5
#define CAM_ISP_PATTERN_BAYER_RGRGRG 0
#define CAM_ISP_PATTERN_BAYER_GRGRGR 1
#define CAM_ISP_PATTERN_BAYER_BGBGBG 2
#define CAM_ISP_PATTERN_BAYER_GBGBGB 3
#define CAM_ISP_PATTERN_YUV_YCBYCR 4
#define CAM_ISP_PATTERN_YUV_YCRYCB 5
#define CAM_ISP_PATTERN_YUV_CBYCRY 6
#define CAM_ISP_PATTERN_YUV_CRYCBY 7
#define CAM_ISP_PATTERN_MAX 8
#define CAM_ISP_RES_USAGE_SINGLE 0
#define CAM_ISP_RES_USAGE_DUAL 1
#define CAM_ISP_RES_USAGE_MAX 2
#define CAM_ISP_RES_ID_PORT 0
#define CAM_ISP_RES_ID_CLK 1
#define CAM_ISP_RES_ID_MAX 2
#define CAM_ISP_LANE_TYPE_DPHY 0
#define CAM_ISP_LANE_TYPE_CPHY 1
#define CAM_ISP_LANE_TYPE_MAX 2
#define CAM_ISP_RES_COMP_GROUP_NONE 0
#define CAM_ISP_RES_COMP_GROUP_ID_0 1
#define CAM_ISP_RES_COMP_GROUP_ID_1 2
#define CAM_ISP_RES_COMP_GROUP_ID_2 3
#define CAM_ISP_RES_COMP_GROUP_ID_3 4
#define CAM_ISP_RES_COMP_GROUP_ID_4 5
#define CAM_ISP_RES_COMP_GROUP_ID_5 6
#define CAM_ISP_RES_COMP_GROUP_ID_MAX 6
#define CAM_ISP_PACKET_OP_BASE 0
#define CAM_ISP_PACKET_INIT_DEV 1
#define CAM_ISP_PACKET_UPDATE_DEV 2
#define CAM_ISP_PACKET_OP_MAX 3
#define CAM_ISP_PACKET_META_BASE 0
#define CAM_ISP_PACKET_META_LEFT 1
#define CAM_ISP_PACKET_META_RIGHT 2
#define CAM_ISP_PACKET_META_COMMON 3
#define CAM_ISP_PACKET_META_DMI_LEFT 4
#define CAM_ISP_PACKET_META_DMI_RIGHT 5
#define CAM_ISP_PACKET_META_DMI_COMMON 6
#define CAM_ISP_PACKET_META_CLOCK 7
#define CAM_ISP_PACKET_META_CSID 8
#define CAM_ISP_PACKET_META_DUAL_CONFIG 9
#define CAM_ISP_PACKET_META_GENERIC_BLOB_LEFT 10
#define CAM_ISP_PACKET_META_GENERIC_BLOB_RIGHT 11
#define CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON 12
#define CAM_ISP_DSP_MODE_NONE 0
#define CAM_ISP_DSP_MODE_ONE_WAY 1
#define CAM_ISP_DSP_MODE_ROUND 2
#define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0
#define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1
#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2
struct cam_isp_dev_cap_info {
uint32_t hw_type;
uint32_t reserved;
struct cam_hw_version hw_version;
};
struct cam_isp_query_cap_cmd {
struct cam_iommu_handle device_iommu;
struct cam_iommu_handle cdm_iommu;
int32_t num_dev;
uint32_t reserved;
struct cam_isp_dev_cap_info dev_caps[CAM_ISP_HW_MAX];
};
struct cam_isp_out_port_info {
uint32_t res_type;
uint32_t format;
uint32_t width;
uint32_t height;
uint32_t comp_grp_id;
uint32_t split_point;
uint32_t secure_mode;
uint32_t reserved;
};
struct cam_isp_in_port_info {
uint32_t res_type;
uint32_t lane_type;
uint32_t lane_num;
uint32_t lane_cfg;
uint32_t vc;
uint32_t dt;
uint32_t format;
uint32_t test_pattern;
uint32_t usage_type;
uint32_t left_start;
uint32_t left_stop;
uint32_t left_width;
uint32_t right_start;
uint32_t right_stop;
uint32_t right_width;
uint32_t line_start;
uint32_t line_stop;
uint32_t height;
uint32_t pixel_clk;
uint32_t batch_size;
uint32_t dsp_mode;
uint32_t hbi_cnt;
uint32_t reserved;
uint32_t num_out_res;
struct cam_isp_out_port_info data[1];
};
struct cam_isp_resource {
uint32_t resource_id;
uint32_t length;
uint32_t handle_type;
uint32_t reserved;
uint64_t res_hdl;
};
struct cam_isp_port_hfr_config {
uint32_t resource_type;
uint32_t subsample_pattern;
uint32_t subsample_period;
uint32_t framedrop_pattern;
uint32_t framedrop_period;
uint32_t reserved;
} __attribute__((packed));
struct cam_isp_resource_hfr_config {
uint32_t num_ports;
uint32_t reserved;
struct cam_isp_port_hfr_config port_hfr_config[1];
} __attribute__((packed));
struct cam_isp_dual_split_params {
uint32_t split_point;
uint32_t right_padding;
uint32_t left_padding;
uint32_t reserved;
};
struct cam_isp_dual_stripe_config {
uint32_t offset;
uint32_t width;
uint32_t tileconfig;
uint32_t port_id;
};
struct cam_isp_dual_config {
uint32_t num_ports;
uint32_t reserved;
struct cam_isp_dual_split_params split_params;
struct cam_isp_dual_stripe_config stripes[1];
} __attribute__((packed));
struct cam_isp_clock_config {
uint32_t usage_type;
uint32_t num_rdi;
uint64_t left_pix_hz;
uint64_t right_pix_hz;
uint64_t rdi_hz[1];
} __attribute__((packed));
struct cam_isp_bw_vote {
uint32_t resource_id;
uint32_t reserved;
uint64_t cam_bw_bps;
uint64_t ext_bw_bps;
} __attribute__((packed));
struct cam_isp_bw_config {
uint32_t usage_type;
uint32_t num_rdi;
struct cam_isp_bw_vote left_pix_vote;
struct cam_isp_bw_vote right_pix_vote;
struct cam_isp_bw_vote rdi_vote[1];
} __attribute__((packed));
#endif

50
sdm710/kernel-headers/media/cam_isp_ife.h
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@@ -1,50 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_ISP_IFE_H__
#define __UAPI_CAM_ISP_IFE_H__
#define CAM_ISP_IFE_OUT_RES_BASE 0x3000
#define CAM_ISP_IFE_OUT_RES_FULL (CAM_ISP_IFE_OUT_RES_BASE + 0)
#define CAM_ISP_IFE_OUT_RES_DS4 (CAM_ISP_IFE_OUT_RES_BASE + 1)
#define CAM_ISP_IFE_OUT_RES_DS16 (CAM_ISP_IFE_OUT_RES_BASE + 2)
#define CAM_ISP_IFE_OUT_RES_RAW_DUMP (CAM_ISP_IFE_OUT_RES_BASE + 3)
#define CAM_ISP_IFE_OUT_RES_FD (CAM_ISP_IFE_OUT_RES_BASE + 4)
#define CAM_ISP_IFE_OUT_RES_PDAF (CAM_ISP_IFE_OUT_RES_BASE + 5)
#define CAM_ISP_IFE_OUT_RES_RDI_0 (CAM_ISP_IFE_OUT_RES_BASE + 6)
#define CAM_ISP_IFE_OUT_RES_RDI_1 (CAM_ISP_IFE_OUT_RES_BASE + 7)
#define CAM_ISP_IFE_OUT_RES_RDI_2 (CAM_ISP_IFE_OUT_RES_BASE + 8)
#define CAM_ISP_IFE_OUT_RES_RDI_3 (CAM_ISP_IFE_OUT_RES_BASE + 9)
#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BE (CAM_ISP_IFE_OUT_RES_BASE + 10)
#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_IFE_OUT_RES_BASE + 11)
#define CAM_ISP_IFE_OUT_RES_STATS_TL_BG (CAM_ISP_IFE_OUT_RES_BASE + 12)
#define CAM_ISP_IFE_OUT_RES_STATS_BF (CAM_ISP_IFE_OUT_RES_BASE + 13)
#define CAM_ISP_IFE_OUT_RES_STATS_AWB_BG (CAM_ISP_IFE_OUT_RES_BASE + 14)
#define CAM_ISP_IFE_OUT_RES_STATS_BHIST (CAM_ISP_IFE_OUT_RES_BASE + 15)
#define CAM_ISP_IFE_OUT_RES_STATS_RS (CAM_ISP_IFE_OUT_RES_BASE + 16)
#define CAM_ISP_IFE_OUT_RES_STATS_CS (CAM_ISP_IFE_OUT_RES_BASE + 17)
#define CAM_ISP_IFE_OUT_RES_STATS_IHIST (CAM_ISP_IFE_OUT_RES_BASE + 18)
#define CAM_ISP_IFE_OUT_RES_MAX (CAM_ISP_IFE_OUT_RES_BASE + 19)
#define CAM_ISP_IFE_IN_RES_BASE 0x4000
#define CAM_ISP_IFE_IN_RES_TPG (CAM_ISP_IFE_IN_RES_BASE + 0)
#define CAM_ISP_IFE_IN_RES_PHY_0 (CAM_ISP_IFE_IN_RES_BASE + 1)
#define CAM_ISP_IFE_IN_RES_PHY_1 (CAM_ISP_IFE_IN_RES_BASE + 2)
#define CAM_ISP_IFE_IN_RES_PHY_2 (CAM_ISP_IFE_IN_RES_BASE + 3)
#define CAM_ISP_IFE_IN_RES_PHY_3 (CAM_ISP_IFE_IN_RES_BASE + 4)
#define CAM_ISP_IFE_IN_RES_MAX (CAM_ISP_IFE_IN_RES_BASE + 5)
#endif

56
sdm710/kernel-headers/media/cam_isp_vfe.h
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@@ -1,56 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_ISP_VFE_H__
#define __UAPI_CAM_ISP_VFE_H__
#define CAM_ISP_VFE_OUT_RES_BASE 0x1000
#define CAM_ISP_VFE_OUT_RES_ENC (CAM_ISP_VFE_OUT_RES_BASE + 0)
#define CAM_ISP_VFE_OUT_RES_VIEW (CAM_ISP_VFE_OUT_RES_BASE + 1)
#define CAM_ISP_VFE_OUT_RES_VID (CAM_ISP_VFE_OUT_RES_BASE + 2)
#define CAM_ISP_VFE_OUT_RES_RDI_0 (CAM_ISP_VFE_OUT_RES_BASE + 3)
#define CAM_ISP_VFE_OUT_RES_RDI_1 (CAM_ISP_VFE_OUT_RES_BASE + 4)
#define CAM_ISP_VFE_OUT_RES_RDI_2 (CAM_ISP_VFE_OUT_RES_BASE + 5)
#define CAM_ISP_VFE_OUT_RES_RDI_3 (CAM_ISP_VFE_OUT_RES_BASE + 6)
#define CAM_ISP_VFE_OUT_RES_STATS_AEC (CAM_ISP_VFE_OUT_RES_BASE + 7)
#define CAM_ISP_VFE_OUT_RES_STATS_AF (CAM_ISP_VFE_OUT_RES_BASE + 8)
#define CAM_ISP_VFE_OUT_RES_STATS_AWB (CAM_ISP_VFE_OUT_RES_BASE + 9)
#define CAM_ISP_VFE_OUT_RES_STATS_RS (CAM_ISP_VFE_OUT_RES_BASE + 10)
#define CAM_ISP_VFE_OUT_RES_STATS_CS (CAM_ISP_VFE_OUT_RES_BASE + 11)
#define CAM_ISP_VFE_OUT_RES_STATS_IHIST (CAM_ISP_VFE_OUT_RES_BASE + 12)
#define CAM_ISP_VFE_OUT_RES_STATS_SKIN (CAM_ISP_VFE_OUT_RES_BASE + 13)
#define CAM_ISP_VFE_OUT_RES_STATS_BG (CAM_ISP_VFE_OUT_RES_BASE + 14)
#define CAM_ISP_VFE_OUT_RES_STATS_BF (CAM_ISP_VFE_OUT_RES_BASE + 15)
#define CAM_ISP_VFE_OUT_RES_STATS_BE (CAM_ISP_VFE_OUT_RES_BASE + 16)
#define CAM_ISP_VFE_OUT_RES_STATS_BHIST (CAM_ISP_VFE_OUT_RES_BASE + 17)
#define CAM_ISP_VFE_OUT_RES_STATS_BF_SCALE (CAM_ISP_VFE_OUT_RES_BASE + 18)
#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BE (CAM_ISP_VFE_OUT_RES_BASE + 19)
#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_VFE_OUT_RES_BASE + 20)
#define CAM_ISP_VFE_OUT_RES_STATS_AEC_BG (CAM_ISP_VFE_OUT_RES_BASE + 21)
#define CAM_ISP_VFE_OUT_RES_CAMIF_RAW (CAM_ISP_VFE_OUT_RES_BASE + 22)
#define CAM_ISP_VFE_OUT_RES_IDEAL_RAW (CAM_ISP_VFE_OUT_RES_BASE + 23)
#define CAM_ISP_VFE_OUT_RES_MAX (CAM_ISP_VFE_OUT_RES_BASE + 24)
#define CAM_ISP_VFE_IN_RES_BASE 0x2000
#define CAM_ISP_VFE_IN_RES_TPG (CAM_ISP_VFE_IN_RES_BASE + 0)
#define CAM_ISP_VFE_IN_RES_PHY_0 (CAM_ISP_VFE_IN_RES_BASE + 1)
#define CAM_ISP_VFE_IN_RES_PHY_1 (CAM_ISP_VFE_IN_RES_BASE + 2)
#define CAM_ISP_VFE_IN_RES_PHY_2 (CAM_ISP_VFE_IN_RES_BASE + 3)
#define CAM_ISP_VFE_IN_RES_PHY_3 (CAM_ISP_VFE_IN_RES_BASE + 4)
#define CAM_ISP_VFE_IN_RES_FE (CAM_ISP_VFE_IN_RES_BASE + 5)
#define CAM_ISP_VFE_IN_RES_MAX (CAM_ISP_VFE_IN_RES_BASE + 6)
#endif

67
sdm710/kernel-headers/media/cam_jpeg.h
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@@ -1,67 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_JPEG_H__
#define __UAPI_CAM_JPEG_H__
#include "cam_defs.h"
#define CAM_JPEG_DEV_TYPE_ENC 0
#define CAM_JPEG_DEV_TYPE_DMA 1
#define CAM_JPEG_DEV_TYPE_MAX 2
#define CAM_JPEG_NUM_DEV_PER_RES_MAX 1
#define CAM_JPEG_RES_TYPE_ENC 0
#define CAM_JPEG_RES_TYPE_DMA 1
#define CAM_JPEG_RES_TYPE_MAX 2
#define CAM_JPEG_OPCODE_ENC_UPDATE 0
#define CAM_JPEG_OPCODE_DMA_UPDATE 1
#define CAM_JPEG_ENC_INPUT_IMAGE 0x0
#define CAM_JPEG_ENC_OUTPUT_IMAGE 0x1
#define CAM_JPEG_ENC_IO_IMAGES_MAX 0x2
#define CAM_JPEG_DMA_INPUT_IMAGE 0x0
#define CAM_JPEG_DMA_OUTPUT_IMAGE 0x1
#define CAM_JPEG_DMA_IO_IMAGES_MAX 0x2
#define CAM_JPEG_IMAGE_MAX 0x2
struct cam_jpeg_dev_ver {
uint32_t size;
uint32_t dev_type;
struct cam_hw_version hw_ver;
};
struct cam_jpeg_query_cap_cmd {
struct cam_iommu_handle dev_iommu_handle;
struct cam_iommu_handle cdm_iommu_handle;
uint32_t num_enc;
uint32_t num_dma;
struct cam_jpeg_dev_ver dev_ver[CAM_JPEG_DEV_TYPE_MAX];
};
struct cam_jpeg_res_info {
uint32_t format;
uint32_t width;
uint32_t height;
uint32_t fps;
};
struct cam_jpeg_acquire_dev_info {
uint32_t dev_type;
uint32_t reserved;
struct cam_jpeg_res_info in_res;
struct cam_jpeg_res_info out_res;
};
struct cam_jpeg_config_inout_param_info {
int32_t clk_index;
int32_t output_size;
};
#endif

60
sdm710/kernel-headers/media/cam_lrme.h
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@@ -1,60 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_LRME_H__
#define __UAPI_CAM_LRME_H__
#include "cam_defs.h"
enum CAM_LRME_IO_TYPE {
CAM_LRME_IO_TYPE_TAR,
CAM_LRME_IO_TYPE_REF,
CAM_LRME_IO_TYPE_RES,
CAM_LRME_IO_TYPE_DS2,
};
#define CAM_LRME_INPUT_PORT_TYPE_TAR (1 << 0)
#define CAM_LRME_INPUT_PORT_TYPE_REF (1 << 1)
#define CAM_LRME_OUTPUT_PORT_TYPE_DS2 (1 << 0)
#define CAM_LRME_OUTPUT_PORT_TYPE_RES (1 << 1)
#define CAM_LRME_DEV_MAX 1
struct cam_lrme_hw_version {
uint32_t gen;
uint32_t rev;
uint32_t step;
};
struct cam_lrme_dev_cap {
struct cam_lrme_hw_version clc_hw_version;
struct cam_lrme_hw_version bus_rd_hw_version;
struct cam_lrme_hw_version bus_wr_hw_version;
struct cam_lrme_hw_version top_hw_version;
struct cam_lrme_hw_version top_titan_version;
};
struct cam_lrme_query_cap_cmd {
struct cam_iommu_handle device_iommu;
struct cam_iommu_handle cdm_iommu;
uint32_t num_devices;
struct cam_lrme_dev_cap dev_caps[CAM_LRME_DEV_MAX];
};
struct cam_lrme_soc_info {
uint64_t clock_rate;
uint64_t bandwidth;
uint64_t reserved[4];
};
struct cam_lrme_acquire_args {
struct cam_lrme_soc_info lrme_soc_info;
};
#endif

217
sdm710/kernel-headers/media/cam_req_mgr.h
View File

@@ -1,217 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_LINUX_CAM_REQ_MGR_H
#define __UAPI_LINUX_CAM_REQ_MGR_H
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
#include <linux/media.h>
#include <media/cam_defs.h>
#define CAM_REQ_MGR_VNODE_NAME "cam-req-mgr-devnode"
#define CAM_DEVICE_TYPE_BASE (MEDIA_ENT_F_OLD_BASE)
#define CAM_VNODE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE)
#define CAM_SENSOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 1)
#define CAM_IFE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 2)
#define CAM_ICP_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 3)
#define CAM_LRME_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 4)
#define CAM_JPEG_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 5)
#define CAM_FD_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 6)
#define CAM_CPAS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 7)
#define CAM_CSIPHY_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 8)
#define CAM_ACTUATOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 9)
#define CAM_CCI_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 10)
#define CAM_FLASH_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 11)
#define CAM_EEPROM_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 12)
#define CAM_OIS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 13)
#define CAM_REQ_MGR_HDL_IDX_POS 8
#define CAM_REQ_MGR_HDL_IDX_MASK ((1 << CAM_REQ_MGR_HDL_IDX_POS) - 1)
#define CAM_REQ_MGR_GET_HDL_IDX(hdl) (hdl & CAM_REQ_MGR_HDL_IDX_MASK)
#define CAM_REQ_MGR_MAX_HANDLES 64
#define MAX_LINKS_PER_SESSION 2
#define V4L_EVENT_CAM_REQ_MGR_EVENT (V4L2_EVENT_PRIVATE_START + 0)
#define V4L_EVENT_CAM_REQ_MGR_SOF 0
#define V4L_EVENT_CAM_REQ_MGR_ERROR 1
#define V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS 2
#define V4L_EVENT_CAM_REQ_MGR_MAX 3
#define CAM_REQ_MGR_SOF_EVENT_SUCCESS 0
#define CAM_REQ_MGR_SOF_EVENT_ERROR 1
#define CAM_REQ_MGR_LINK_ACTIVATE 0
#define CAM_REQ_MGR_LINK_DEACTIVATE 1
#define CAM_REQ_MGR_FLUSH_TYPE_ALL 0
#define CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ 1
#define CAM_REQ_MGR_FLUSH_TYPE_MAX 2
#define CAM_REQ_MGR_SYNC_MODE_NO_SYNC 0
#define CAM_REQ_MGR_SYNC_MODE_SYNC 1
struct cam_req_mgr_event_data {
int32_t session_hdl;
int32_t link_hdl;
int32_t frame_id;
int32_t reserved;
int64_t req_id;
uint64_t tv_sec;
uint64_t tv_usec;
};
struct cam_req_mgr_session_info {
int32_t session_hdl;
int32_t reserved;
};
struct cam_req_mgr_link_info {
int32_t session_hdl;
uint32_t num_devices;
int32_t dev_hdls[CAM_REQ_MGR_MAX_HANDLES];
int32_t link_hdl;
};
struct cam_req_mgr_unlink_info {
int32_t session_hdl;
int32_t link_hdl;
};
struct cam_req_mgr_flush_info {
int32_t session_hdl;
int32_t link_hdl;
uint32_t flush_type;
uint32_t reserved;
int64_t req_id;
};
struct cam_req_mgr_sched_request {
int32_t session_hdl;
int32_t link_hdl;
int32_t bubble_enable;
int32_t sync_mode;
int64_t req_id;
};
struct cam_req_mgr_sync_mode {
int32_t session_hdl;
int32_t sync_mode;
int32_t num_links;
int32_t link_hdls[MAX_LINKS_PER_SESSION];
int32_t master_link_hdl;
int32_t reserved;
};
struct cam_req_mgr_link_control {
int32_t ops;
int32_t session_hdl;
int32_t num_links;
int32_t reserved;
int32_t link_hdls[MAX_LINKS_PER_SESSION];
};
#define CAM_REQ_MGR_CREATE_DEV_NODES (CAM_COMMON_OPCODE_MAX + 1)
#define CAM_REQ_MGR_CREATE_SESSION (CAM_COMMON_OPCODE_MAX + 2)
#define CAM_REQ_MGR_DESTROY_SESSION (CAM_COMMON_OPCODE_MAX + 3)
#define CAM_REQ_MGR_LINK (CAM_COMMON_OPCODE_MAX + 4)
#define CAM_REQ_MGR_UNLINK (CAM_COMMON_OPCODE_MAX + 5)
#define CAM_REQ_MGR_SCHED_REQ (CAM_COMMON_OPCODE_MAX + 6)
#define CAM_REQ_MGR_FLUSH_REQ (CAM_COMMON_OPCODE_MAX + 7)
#define CAM_REQ_MGR_SYNC_MODE (CAM_COMMON_OPCODE_MAX + 8)
#define CAM_REQ_MGR_ALLOC_BUF (CAM_COMMON_OPCODE_MAX + 9)
#define CAM_REQ_MGR_MAP_BUF (CAM_COMMON_OPCODE_MAX + 10)
#define CAM_REQ_MGR_RELEASE_BUF (CAM_COMMON_OPCODE_MAX + 11)
#define CAM_REQ_MGR_CACHE_OPS (CAM_COMMON_OPCODE_MAX + 12)
#define CAM_REQ_MGR_LINK_CONTROL (CAM_COMMON_OPCODE_MAX + 13)
#define CAM_MEM_FLAG_HW_READ_WRITE (1 << 0)
#define CAM_MEM_FLAG_HW_READ_ONLY (1 << 1)
#define CAM_MEM_FLAG_HW_WRITE_ONLY (1 << 2)
#define CAM_MEM_FLAG_KMD_ACCESS (1 << 3)
#define CAM_MEM_FLAG_UMD_ACCESS (1 << 4)
#define CAM_MEM_FLAG_PROTECTED_MODE (1 << 5)
#define CAM_MEM_FLAG_CMD_BUF_TYPE (1 << 6)
#define CAM_MEM_FLAG_PIXEL_BUF_TYPE (1 << 7)
#define CAM_MEM_FLAG_STATS_BUF_TYPE (1 << 8)
#define CAM_MEM_FLAG_PACKET_BUF_TYPE (1 << 9)
#define CAM_MEM_FLAG_CACHE (1 << 10)
#define CAM_MEM_FLAG_HW_SHARED_ACCESS (1 << 11)
#define CAM_MEM_MMU_MAX_HANDLE 16
#define CAM_MEM_BUFQ_MAX 1024
#define CAM_MEM_MGR_SECURE_BIT_POS 15
#define CAM_MEM_MGR_HDL_IDX_SIZE 15
#define CAM_MEM_MGR_HDL_FD_SIZE 16
#define CAM_MEM_MGR_HDL_IDX_END_POS 16
#define CAM_MEM_MGR_HDL_FD_END_POS 32
#define CAM_MEM_MGR_HDL_IDX_MASK ((1 << CAM_MEM_MGR_HDL_IDX_SIZE) - 1)
#define GET_MEM_HANDLE(idx,fd) ((idx & CAM_MEM_MGR_HDL_IDX_MASK) | (fd << (CAM_MEM_MGR_HDL_FD_END_POS - CAM_MEM_MGR_HDL_FD_SIZE)))
#define CAM_MEM_MGR_GET_HDL_IDX(hdl) (hdl & CAM_MEM_MGR_HDL_IDX_MASK)
#define CAM_MEM_MGR_SET_SECURE_HDL(hdl,flag) ((flag) ? (hdl |= (1 << CAM_MEM_MGR_SECURE_BIT_POS)) : ((hdl) &= ~(1 << CAM_MEM_MGR_SECURE_BIT_POS)))
#define CAM_MEM_MGR_IS_SECURE_HDL(hdl) (((hdl) & (1 << CAM_MEM_MGR_SECURE_BIT_POS)) >> CAM_MEM_MGR_SECURE_BIT_POS)
#define CAM_MEM_DMA_NONE 0
#define CAM_MEM_DMA_BIDIRECTIONAL 1
#define CAM_MEM_DMA_TO_DEVICE 2
#define CAM_MEM_DMA_FROM_DEVICE 3
#define CAM_MEM_CLEAN_CACHE 1
#define CAM_MEM_INV_CACHE 2
#define CAM_MEM_CLEAN_INV_CACHE 3
struct cam_mem_alloc_out_params {
uint32_t buf_handle;
int32_t fd;
uint64_t vaddr;
};
struct cam_mem_map_out_params {
uint32_t buf_handle;
uint32_t reserved;
uint64_t vaddr;
};
struct cam_mem_mgr_alloc_cmd {
uint64_t len;
uint64_t align;
int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE];
uint32_t num_hdl;
uint32_t flags;
struct cam_mem_alloc_out_params out;
};
struct cam_mem_mgr_map_cmd {
int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE];
uint32_t num_hdl;
uint32_t flags;
int32_t fd;
uint32_t reserved;
struct cam_mem_map_out_params out;
};
struct cam_mem_mgr_release_cmd {
int32_t buf_handle;
uint32_t reserved;
};
struct cam_mem_cache_ops_cmd {
int32_t buf_handle;
uint32_t mem_cache_ops;
};
#define CAM_REQ_MGR_ERROR_TYPE_DEVICE 0
#define CAM_REQ_MGR_ERROR_TYPE_REQUEST 1
#define CAM_REQ_MGR_ERROR_TYPE_BUFFER 2
struct cam_req_mgr_error_msg {
uint32_t error_type;
uint32_t request_id;
int32_t device_hdl;
int32_t link_hdl;
uint64_t resource_size;
};
struct cam_req_mgr_frame_msg {
uint64_t request_id;
uint64_t frame_id;
uint64_t timestamp;
int32_t link_hdl;
uint32_t sof_status;
};
struct cam_req_mgr_message {
int32_t session_hdl;
int32_t reserved;
union {
struct cam_req_mgr_error_msg err_msg;
struct cam_req_mgr_frame_msg frame_msg;
} u;
};
#endif

239
sdm710/kernel-headers/media/cam_sensor.h
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@@ -1,239 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_SENSOR_H__
#define __UAPI_CAM_SENSOR_H__
#include <linux/types.h>
#include <linux/ioctl.h>
#include <media/cam_defs.h>
#define CAM_SENSOR_PROBE_CMD (CAM_COMMON_OPCODE_MAX + 1)
#define CAM_FLASH_MAX_LED_TRIGGERS 3
#define MAX_OIS_NAME_SIZE 32
#define CAM_CSIPHY_SECURE_MODE_ENABLED 1
#define MAX_RAINBOW_CONFIG_SIZE 32
enum rainbow_op_type {
RAINBOW_SEQ_READ,
RAINBOW_RANDOM_READ,
RAINBOW_SEQ_WRITE,
RAINBOW_RANDOM_WRITE
};
struct rainbow_config {
enum rainbow_op_type operation;
uint32_t size;
uint32_t reg_addr[MAX_RAINBOW_CONFIG_SIZE];
uint32_t reg_data[MAX_RAINBOW_CONFIG_SIZE];
} __attribute__((packed));
#define RAINBOW_CONFIG _IOWR('R', 1, struct rainbow_config)
struct cam_sensor_query_cap {
uint32_t slot_info;
uint32_t secure_camera;
uint32_t pos_pitch;
uint32_t pos_roll;
uint32_t pos_yaw;
uint32_t actuator_slot_id;
uint32_t eeprom_slot_id;
uint32_t ois_slot_id;
uint32_t flash_slot_id;
uint32_t csiphy_slot_id;
} __attribute__((packed));
struct cam_csiphy_query_cap {
uint32_t slot_info;
uint32_t version;
uint32_t clk_lane;
uint32_t reserved;
} __attribute__((packed));
struct cam_actuator_query_cap {
uint32_t slot_info;
uint32_t reserved;
} __attribute__((packed));
struct cam_eeprom_query_cap_t {
uint32_t slot_info;
uint16_t eeprom_kernel_probe;
uint16_t reserved;
} __attribute__((packed));
struct cam_ois_query_cap_t {
uint32_t slot_info;
uint16_t reserved;
} __attribute__((packed));
struct cam_cmd_i2c_info {
uint16_t slave_addr;
uint8_t i2c_freq_mode;
uint8_t cmd_type;
} __attribute__((packed));
struct cam_cmd_get_ois_data {
uint32_t reg_addr;
uint32_t reg_data;
uint64_t query_size_handle;
uint64_t query_data_handle;
} __attribute__((packed));
struct cam_ois_shift {
int16_t ois_shift_x;
int16_t ois_shift_y;
int64_t time_readout;
} __attribute__((packed));
struct cam_ois_opcode {
uint32_t prog;
uint32_t coeff;
uint32_t pheripheral;
uint32_t memory;
} __attribute__((packed));
struct cam_cmd_ois_info {
uint16_t slave_addr;
uint8_t i2c_freq_mode;
uint8_t cmd_type;
uint8_t ois_fw_flag;
uint8_t is_ois_calib;
char ois_name[MAX_OIS_NAME_SIZE];
struct cam_ois_opcode opcode;
} __attribute__((packed));
struct cam_cmd_probe {
uint8_t data_type;
uint8_t addr_type;
uint8_t op_code;
uint8_t cmd_type;
uint32_t reg_addr;
uint32_t expected_data;
uint32_t data_mask;
uint16_t camera_id;
uint8_t fw_update_flag;
uint16_t reserved;
} __attribute__((packed));
struct cam_power_settings {
uint16_t power_seq_type;
uint16_t reserved;
uint32_t config_val_low;
uint32_t config_val_high;
} __attribute__((packed));
struct cam_cmd_power {
uint16_t count;
uint8_t reserved;
uint8_t cmd_type;
struct cam_power_settings power_settings[1];
} __attribute__((packed));
struct i2c_rdwr_header {
uint16_t count;
uint8_t op_code;
uint8_t cmd_type;
uint8_t data_type;
uint8_t addr_type;
uint16_t slave_addr;
} __attribute__((packed));
struct i2c_random_wr_payload {
uint32_t reg_addr;
uint32_t reg_data;
} __attribute__((packed));
struct cam_cmd_i2c_random_wr {
struct i2c_rdwr_header header;
struct i2c_random_wr_payload random_wr_payload[1];
} __attribute__((packed));
struct cam_cmd_read {
uint32_t reg_data;
uint32_t reserved;
} __attribute__((packed));
struct cam_cmd_i2c_continuous_wr {
struct i2c_rdwr_header header;
uint32_t reg_addr;
struct cam_cmd_read data_read[1];
} __attribute__((packed));
struct cam_cmd_i2c_random_rd {
struct i2c_rdwr_header header;
struct cam_cmd_read data_read[1];
} __attribute__((packed));
struct cam_cmd_i2c_continuous_rd {
struct i2c_rdwr_header header;
uint32_t reg_addr;
} __attribute__((packed));
struct cam_cmd_conditional_wait {
uint8_t data_type;
uint8_t addr_type;
uint8_t op_code;
uint8_t cmd_type;
uint16_t timeout;
uint16_t reserved;
uint32_t reg_addr;
uint32_t reg_data;
uint32_t data_mask;
} __attribute__((packed));
struct cam_cmd_unconditional_wait {
int16_t delay;
uint8_t op_code;
uint8_t cmd_type;
} __attribute__((packed));
struct cam_csiphy_info {
uint16_t lane_mask;
uint16_t lane_assign;
uint8_t csiphy_3phase;
uint8_t combo_mode;
uint8_t lane_cnt;
uint8_t secure_mode;
uint64_t settle_time;
uint64_t data_rate;
} __attribute__((packed));
struct cam_csiphy_acquire_dev_info {
uint32_t combo_mode;
uint32_t reserved;
} __attribute__((packed));
struct cam_sensor_acquire_dev {
uint32_t session_handle;
uint32_t device_handle;
uint32_t handle_type;
uint32_t reserved;
uint64_t info_handle;
} __attribute__((packed));
struct cam_sensor_streamon_dev {
uint32_t session_handle;
uint32_t device_handle;
uint32_t handle_type;
uint32_t reserved;
uint64_t info_handle;
} __attribute__((packed));
struct cam_flash_init {
uint8_t flash_type;
uint16_t reserved;
uint8_t cmd_type;
} __attribute__((packed));
struct cam_flash_set_rer {
uint16_t count;
uint8_t opcode;
uint8_t cmd_type;
uint16_t num_iteration;
uint16_t reserved;
uint32_t led_on_delay_ms;
uint32_t led_off_delay_ms;
uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS];
} __attribute__((packed));
struct cam_flash_set_on_off {
uint16_t count;
uint8_t opcode;
uint8_t cmd_type;
uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS];
} __attribute__((packed));
struct cam_flash_query_curr {
uint16_t reserved;
uint8_t opcode;
uint8_t cmd_type;
uint32_t query_current_ma;
} __attribute__((packed));
struct cam_flash_query_cap_info {
uint32_t slot_info;
uint32_t max_current_flash[CAM_FLASH_MAX_LED_TRIGGERS];
uint32_t max_duration_flash[CAM_FLASH_MAX_LED_TRIGGERS];
uint32_t max_current_torch[CAM_FLASH_MAX_LED_TRIGGERS];
} __attribute__((packed));
#endif

79
sdm710/kernel-headers/media/cam_sync.h
View File

@@ -1,79 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_CAM_SYNC_H__
#define __UAPI_CAM_SYNC_H__
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
#include <linux/media.h>
#define CAM_SYNC_DEVICE_NAME "cam_sync_device"
#define CAM_SYNC_V4L_EVENT (V4L2_EVENT_PRIVATE_START + 0)
#define CAM_SYNC_V4L_EVENT_ID_CB_TRIG 0
#define CAM_SYNC_USER_PAYLOAD_SIZE 2
#define CAM_SYNC_DEVICE_TYPE (MEDIA_ENT_F_OLD_BASE)
#define CAM_SYNC_GET_PAYLOAD_PTR(ev,type) (type *) ((char *) ev.u.data + sizeof(struct cam_sync_ev_header))
#define CAM_SYNC_GET_HEADER_PTR(ev) ((struct cam_sync_ev_header *) ev.u.data)
#define CAM_SYNC_STATE_INVALID 0
#define CAM_SYNC_STATE_ACTIVE 1
#define CAM_SYNC_STATE_SIGNALED_SUCCESS 2
#define CAM_SYNC_STATE_SIGNALED_ERROR 3
struct cam_sync_ev_header {
int32_t sync_obj;
int32_t status;
};
struct cam_sync_info {
char name[64];
int32_t sync_obj;
};
struct cam_sync_signal {
int32_t sync_obj;
uint32_t sync_state;
};
struct cam_sync_merge {
__u64 sync_objs;
uint32_t num_objs;
int32_t merged;
};
struct cam_sync_userpayload_info {
int32_t sync_obj;
uint32_t reserved;
__u64 payload[CAM_SYNC_USER_PAYLOAD_SIZE];
};
struct cam_sync_wait {
int32_t sync_obj;
uint32_t reserved;
uint64_t timeout_ms;
};
struct cam_private_ioctl_arg {
__u32 id;
__u32 size;
__u32 result;
__u32 reserved;
__u64 ioctl_ptr;
};
#define CAM_PRIVATE_IOCTL_CMD _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_private_ioctl_arg)
#define CAM_SYNC_CREATE 0
#define CAM_SYNC_DESTROY 1
#define CAM_SYNC_SIGNAL 2
#define CAM_SYNC_MERGE 3
#define CAM_SYNC_REGISTER_PAYLOAD 4
#define CAM_SYNC_DEREGISTER_PAYLOAD 5
#define CAM_SYNC_WAIT 6
#endif

540
sdm710/kernel-headers/media/msm_cam_sensor.h
View File

@@ -1,540 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_LINUX_MSM_CAM_SENSOR_H
#define __UAPI_LINUX_MSM_CAM_SENSOR_H
#include <linux/v4l2-mediabus.h>
#include <media/msm_camsensor_sdk.h>
#include <linux/types.h>
#include <linux/i2c.h>
#define I2C_SEQ_REG_SETTING_MAX 5
#define MSM_SENSOR_MCLK_8HZ 8000000
#define MSM_SENSOR_MCLK_16HZ 16000000
#define MSM_SENSOR_MCLK_24HZ 24000000
#define MAX_SENSOR_NAME 32
#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024
#define MAX_OIS_MOD_NAME_SIZE 32
#define MAX_OIS_NAME_SIZE 32
#define MAX_OIS_REG_SETTINGS 800
#define MOVE_NEAR 0
#define MOVE_FAR 1
#define MSM_ACTUATOR_MOVE_SIGNED_FAR - 1
#define MSM_ACTUATOR_MOVE_SIGNED_NEAR 1
#define MAX_ACTUATOR_REGION 5
#define MAX_EEPROM_NAME 32
#define MAX_AF_ITERATIONS 3
#define MAX_NUMBER_OF_STEPS 47
#define MAX_REGULATOR 5
#define FLASH_QUERY_CURRENT 1
#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A')
#define MSM_V4L2_PIX_FMT_META10 v4l2_fourcc('M', 'E', '1', '0')
#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4')
#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4')
#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')
#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4')
enum flash_type {
LED_FLASH = 1,
STROBE_FLASH,
GPIO_FLASH
};
enum msm_sensor_resolution_t {
MSM_SENSOR_RES_FULL,
MSM_SENSOR_RES_QTR,
MSM_SENSOR_RES_2,
MSM_SENSOR_RES_3,
MSM_SENSOR_RES_4,
MSM_SENSOR_RES_5,
MSM_SENSOR_RES_6,
MSM_SENSOR_RES_7,
MSM_SENSOR_INVALID_RES,
};
enum msm_camera_stream_type_t {
MSM_CAMERA_STREAM_PREVIEW,
MSM_CAMERA_STREAM_SNAPSHOT,
MSM_CAMERA_STREAM_VIDEO,
MSM_CAMERA_STREAM_INVALID,
};
enum sensor_sub_module_t {
SUB_MODULE_SENSOR,
SUB_MODULE_CHROMATIX,
SUB_MODULE_ACTUATOR,
SUB_MODULE_EEPROM,
SUB_MODULE_LED_FLASH,
SUB_MODULE_STROBE_FLASH,
SUB_MODULE_CSID,
SUB_MODULE_CSID_3D,
SUB_MODULE_CSIPHY,
SUB_MODULE_CSIPHY_3D,
SUB_MODULE_OIS,
SUB_MODULE_EXT,
SUB_MODULE_IR_LED,
SUB_MODULE_IR_CUT,
SUB_MODULE_LASER_LED,
SUB_MODULE_MAX,
};
enum {
MSM_CAMERA_EFFECT_MODE_OFF,
MSM_CAMERA_EFFECT_MODE_MONO,
MSM_CAMERA_EFFECT_MODE_NEGATIVE,
MSM_CAMERA_EFFECT_MODE_SOLARIZE,
MSM_CAMERA_EFFECT_MODE_SEPIA,
MSM_CAMERA_EFFECT_MODE_POSTERIZE,
MSM_CAMERA_EFFECT_MODE_WHITEBOARD,
MSM_CAMERA_EFFECT_MODE_BLACKBOARD,
MSM_CAMERA_EFFECT_MODE_AQUA,
MSM_CAMERA_EFFECT_MODE_EMBOSS,
MSM_CAMERA_EFFECT_MODE_SKETCH,
MSM_CAMERA_EFFECT_MODE_NEON,
MSM_CAMERA_EFFECT_MODE_MAX
};
enum {
MSM_CAMERA_WB_MODE_AUTO,
MSM_CAMERA_WB_MODE_CUSTOM,
MSM_CAMERA_WB_MODE_INCANDESCENT,
MSM_CAMERA_WB_MODE_FLUORESCENT,
MSM_CAMERA_WB_MODE_WARM_FLUORESCENT,
MSM_CAMERA_WB_MODE_DAYLIGHT,
MSM_CAMERA_WB_MODE_CLOUDY_DAYLIGHT,
MSM_CAMERA_WB_MODE_TWILIGHT,
MSM_CAMERA_WB_MODE_SHADE,
MSM_CAMERA_WB_MODE_OFF,
MSM_CAMERA_WB_MODE_MAX
};
enum {
MSM_CAMERA_SCENE_MODE_OFF,
MSM_CAMERA_SCENE_MODE_AUTO,
MSM_CAMERA_SCENE_MODE_LANDSCAPE,
MSM_CAMERA_SCENE_MODE_SNOW,
MSM_CAMERA_SCENE_MODE_BEACH,
MSM_CAMERA_SCENE_MODE_SUNSET,
MSM_CAMERA_SCENE_MODE_NIGHT,
MSM_CAMERA_SCENE_MODE_PORTRAIT,
MSM_CAMERA_SCENE_MODE_BACKLIGHT,
MSM_CAMERA_SCENE_MODE_SPORTS,
MSM_CAMERA_SCENE_MODE_ANTISHAKE,
MSM_CAMERA_SCENE_MODE_FLOWERS,
MSM_CAMERA_SCENE_MODE_CANDLELIGHT,
MSM_CAMERA_SCENE_MODE_FIREWORKS,
MSM_CAMERA_SCENE_MODE_PARTY,
MSM_CAMERA_SCENE_MODE_NIGHT_PORTRAIT,
MSM_CAMERA_SCENE_MODE_THEATRE,
MSM_CAMERA_SCENE_MODE_ACTION,
MSM_CAMERA_SCENE_MODE_AR,
MSM_CAMERA_SCENE_MODE_FACE_PRIORITY,
MSM_CAMERA_SCENE_MODE_BARCODE,
MSM_CAMERA_SCENE_MODE_HDR,
MSM_CAMERA_SCENE_MODE_MAX
};
enum csid_cfg_type_t {
CSID_INIT,
CSID_CFG,
CSID_TESTMODE_CFG,
CSID_RELEASE,
};
enum csiphy_cfg_type_t {
CSIPHY_INIT,
CSIPHY_CFG,
CSIPHY_RELEASE,
};
enum camera_vreg_type {
VREG_TYPE_DEFAULT,
VREG_TYPE_CUSTOM,
};
enum sensor_af_t {
SENSOR_AF_FOCUSSED,
SENSOR_AF_NOT_FOCUSSED,
};
enum cci_i2c_master_t {
MASTER_0,
MASTER_1,
MASTER_MAX,
};
struct msm_camera_i2c_array_write_config {
struct msm_camera_i2c_reg_setting conf_array;
uint16_t slave_addr;
};
struct msm_camera_i2c_read_config {
uint16_t slave_addr;
uint16_t reg_addr;
enum msm_camera_i2c_reg_addr_type addr_type;
enum msm_camera_i2c_data_type data_type;
uint16_t data;
};
struct msm_camera_csi2_params {
struct msm_camera_csid_params csid_params;
struct msm_camera_csiphy_params csiphy_params;
uint8_t csi_clk_scale_enable;
};
struct msm_camera_csi_lane_params {
uint16_t csi_lane_assign;
uint16_t csi_lane_mask;
};
struct csi_lane_params_t {
uint16_t csi_lane_assign;
uint8_t csi_lane_mask;
uint8_t csi_if;
int8_t csid_core[2];
uint8_t csi_phy_sel;
};
struct msm_sensor_info_t {
char sensor_name[MAX_SENSOR_NAME];
uint32_t session_id;
int32_t subdev_id[SUB_MODULE_MAX];
int32_t subdev_intf[SUB_MODULE_MAX];
uint8_t is_mount_angle_valid;
uint32_t sensor_mount_angle;
int modes_supported;
enum camb_position_t position;
};
struct camera_vreg_t {
const char * reg_name;
int min_voltage;
int max_voltage;
int op_mode;
uint32_t delay;
const char * custom_vreg_name;
enum camera_vreg_type type;
};
struct sensorb_cfg_data {
int cfgtype;
union {
struct msm_sensor_info_t sensor_info;
struct msm_sensor_init_params sensor_init_params;
void * setting;
struct msm_sensor_i2c_sync_params sensor_i2c_sync_params;
} cfg;
};
struct csid_cfg_data {
enum csid_cfg_type_t cfgtype;
union {
uint32_t csid_version;
struct msm_camera_csid_params * csid_params;
struct msm_camera_csid_testmode_parms * csid_testmode_params;
} cfg;
};
struct csiphy_cfg_data {
enum csiphy_cfg_type_t cfgtype;
union {
struct msm_camera_csiphy_params * csiphy_params;
struct msm_camera_csi_lane_params * csi_lane_params;
} cfg;
};
enum eeprom_cfg_type_t {
CFG_EEPROM_GET_INFO,
CFG_EEPROM_GET_CAL_DATA,
CFG_EEPROM_READ_CAL_DATA,
CFG_EEPROM_WRITE_DATA,
CFG_EEPROM_GET_MM_INFO,
CFG_EEPROM_INIT,
};
struct eeprom_get_t {
uint32_t num_bytes;
};
struct eeprom_read_t {
uint8_t * dbuffer;
uint32_t num_bytes;
};
struct eeprom_write_t {
uint8_t * dbuffer;
uint32_t num_bytes;
};
struct eeprom_get_cmm_t {
uint32_t cmm_support;
uint32_t cmm_compression;
uint32_t cmm_size;
};
struct msm_eeprom_info_t {
struct msm_sensor_power_setting_array * power_setting_array;
enum i2c_freq_mode_t i2c_freq_mode;
struct msm_eeprom_memory_map_array * mem_map_array;
};
struct msm_ir_led_cfg_data_t {
enum msm_ir_led_cfg_type_t cfg_type;
int32_t pwm_duty_on_ns;
int32_t pwm_period_ns;
};
struct msm_ir_cut_cfg_data_t {
enum msm_ir_cut_cfg_type_t cfg_type;
};
struct msm_laser_led_cfg_data_t {
enum msm_laser_led_cfg_type_t cfg_type;
void * setting;
void * debug_reg;
uint32_t debug_reg_size;
uint16_t i2c_addr;
enum i2c_freq_mode_t i2c_freq_mode;
};
struct msm_eeprom_cfg_data {
enum eeprom_cfg_type_t cfgtype;
uint8_t is_supported;
union {
char eeprom_name[MAX_EEPROM_NAME];
struct eeprom_get_t get_data;
struct eeprom_read_t read_data;
struct eeprom_write_t write_data;
struct eeprom_get_cmm_t get_cmm_data;
struct msm_eeprom_info_t eeprom_info;
} cfg;
};
enum msm_sensor_cfg_type_t {
CFG_SET_SLAVE_INFO,
CFG_SLAVE_READ_I2C,
CFG_WRITE_I2C_ARRAY,
CFG_SLAVE_WRITE_I2C_ARRAY,
CFG_WRITE_I2C_SEQ_ARRAY,
CFG_POWER_UP,
CFG_POWER_DOWN,
CFG_SET_STOP_STREAM_SETTING,
CFG_GET_SENSOR_INFO,
CFG_GET_SENSOR_INIT_PARAMS,
CFG_SET_INIT_SETTING,
CFG_SET_RESOLUTION,
CFG_SET_STOP_STREAM,
CFG_SET_START_STREAM,
CFG_SET_SATURATION,
CFG_SET_CONTRAST,
CFG_SET_SHARPNESS,
CFG_SET_ISO,
CFG_SET_EXPOSURE_COMPENSATION,
CFG_SET_ANTIBANDING,
CFG_SET_BESTSHOT_MODE,
CFG_SET_EFFECT,
CFG_SET_WHITE_BALANCE,
CFG_SET_AUTOFOCUS,
CFG_CANCEL_AUTOFOCUS,
CFG_SET_STREAM_TYPE,
CFG_SET_I2C_SYNC_PARAM,
CFG_WRITE_I2C_ARRAY_ASYNC,
CFG_WRITE_I2C_ARRAY_SYNC,
CFG_WRITE_I2C_ARRAY_SYNC_BLOCK,
};
enum msm_actuator_cfg_type_t {
CFG_GET_ACTUATOR_INFO,
CFG_SET_ACTUATOR_INFO,
CFG_SET_DEFAULT_FOCUS,
CFG_MOVE_FOCUS,
CFG_SET_POSITION,
CFG_ACTUATOR_POWERDOWN,
CFG_ACTUATOR_POWERUP,
CFG_ACTUATOR_INIT,
};
struct msm_ois_opcode {
uint32_t prog;
uint32_t coeff;
uint32_t pheripheral;
uint32_t memory;
};
enum msm_ois_cfg_type_t {
CFG_OIS_INIT,
CFG_OIS_POWERDOWN,
CFG_OIS_POWERUP,
CFG_OIS_CONTROL,
CFG_OIS_I2C_WRITE_SEQ_TABLE,
};
enum msm_ois_cfg_download_type_t {
CFG_OIS_DOWNLOAD,
CFG_OIS_DATA_CONFIG,
};
enum msm_ois_i2c_operation {
MSM_OIS_WRITE = 0,
MSM_OIS_POLL,
MSM_OIS_READ,
};
#define MSM_OIS_READ MSM_OIS_READ
struct reg_settings_ois_t {
uint16_t reg_addr;
enum msm_camera_i2c_reg_addr_type addr_type;
uint32_t reg_data;
enum msm_camera_i2c_data_type data_type;
enum msm_ois_i2c_operation i2c_operation;
uint32_t delay;
};
struct msm_ois_params_t {
uint16_t data_size;
uint16_t setting_size;
uint32_t i2c_addr;
enum i2c_freq_mode_t i2c_freq_mode;
enum msm_camera_i2c_reg_addr_type i2c_addr_type;
enum msm_camera_i2c_data_type i2c_data_type;
struct reg_settings_ois_t * settings;
};
struct msm_ois_set_info_t {
struct msm_ois_params_t ois_params;
};
struct msm_actuator_move_params_t {
int8_t dir;
int8_t sign_dir;
int16_t dest_step_pos;
int32_t num_steps;
uint16_t curr_lens_pos;
struct damping_params_t * ringing_params;
};
struct msm_actuator_tuning_params_t {
int16_t initial_code;
uint16_t pwd_step;
uint16_t region_size;
uint32_t total_steps;
struct region_params_t * region_params;
};
struct park_lens_data_t {
uint32_t damping_step;
uint32_t damping_delay;
uint32_t hw_params;
uint32_t max_step;
};
struct msm_actuator_params_t {
enum actuator_type act_type;
uint8_t reg_tbl_size;
uint16_t data_size;
uint16_t init_setting_size;
uint32_t i2c_addr;
enum i2c_freq_mode_t i2c_freq_mode;
enum msm_camera_i2c_reg_addr_type i2c_addr_type;
enum msm_camera_i2c_data_type i2c_data_type;
struct msm_actuator_reg_params_t * reg_tbl_params;
struct reg_settings_t * init_settings;
struct park_lens_data_t park_lens;
};
struct msm_actuator_set_info_t {
struct msm_actuator_params_t actuator_params;
struct msm_actuator_tuning_params_t af_tuning_params;
};
struct msm_actuator_get_info_t {
uint32_t focal_length_num;
uint32_t focal_length_den;
uint32_t f_number_num;
uint32_t f_number_den;
uint32_t f_pix_num;
uint32_t f_pix_den;
uint32_t total_f_dist_num;
uint32_t total_f_dist_den;
uint32_t hor_view_angle_num;
uint32_t hor_view_angle_den;
uint32_t ver_view_angle_num;
uint32_t ver_view_angle_den;
};
enum af_camera_name {
ACTUATOR_MAIN_CAM_0,
ACTUATOR_MAIN_CAM_1,
ACTUATOR_MAIN_CAM_2,
ACTUATOR_MAIN_CAM_3,
ACTUATOR_MAIN_CAM_4,
ACTUATOR_MAIN_CAM_5,
ACTUATOR_WEB_CAM_0,
ACTUATOR_WEB_CAM_1,
ACTUATOR_WEB_CAM_2,
};
struct msm_ois_slave_info {
char ois_name[MAX_OIS_NAME_SIZE];
uint32_t i2c_addr;
struct msm_ois_opcode opcode;
};
struct msm_ois_cfg_data {
int cfgtype;
union {
struct msm_ois_set_info_t set_info;
struct msm_camera_i2c_seq_reg_setting * settings;
} cfg;
};
struct msm_ois_cfg_download_data {
int cfgtype;
struct msm_ois_slave_info slave_info;
};
struct msm_actuator_set_position_t {
uint16_t number_of_steps;
uint32_t hw_params;
uint16_t pos[MAX_NUMBER_OF_STEPS];
uint16_t delay[MAX_NUMBER_OF_STEPS];
};
struct msm_actuator_cfg_data {
int cfgtype;
uint8_t is_af_supported;
union {
struct msm_actuator_move_params_t move;
struct msm_actuator_set_info_t set_info;
struct msm_actuator_get_info_t get_info;
struct msm_actuator_set_position_t setpos;
enum af_camera_name cam_name;
} cfg;
};
enum msm_camera_led_config_t {
MSM_CAMERA_LED_OFF,
MSM_CAMERA_LED_LOW,
MSM_CAMERA_LED_HIGH,
MSM_CAMERA_LED_INIT,
MSM_CAMERA_LED_RELEASE,
};
struct msm_camera_led_cfg_t {
enum msm_camera_led_config_t cfgtype;
int32_t torch_current[MAX_LED_TRIGGERS];
int32_t flash_current[MAX_LED_TRIGGERS];
int32_t flash_duration[MAX_LED_TRIGGERS];
};
struct msm_flash_init_info_t {
enum msm_flash_driver_type flash_driver_type;
uint32_t slave_addr;
enum i2c_freq_mode_t i2c_freq_mode;
struct msm_sensor_power_setting_array * power_setting_array;
struct msm_camera_i2c_reg_setting_array * settings;
};
struct msm_flash_cfg_data_t {
enum msm_flash_cfg_type_t cfg_type;
int32_t flash_current[MAX_LED_TRIGGERS];
int32_t flash_duration[MAX_LED_TRIGGERS];
union {
struct msm_flash_init_info_t * flash_init_info;
struct msm_camera_i2c_reg_setting_array * settings;
} cfg;
};
struct msm_flash_query_data_t {
int32_t flags;
int32_t query_type;
int32_t max_avail_curr;
};
enum msm_sensor_init_cfg_type_t {
CFG_SINIT_PROBE,
CFG_SINIT_PROBE_DONE,
CFG_SINIT_PROBE_WAIT_DONE,
};
struct sensor_init_cfg_data {
enum msm_sensor_init_cfg_type_t cfgtype;
struct msm_sensor_info_t probed_info;
char entity_name[MAX_SENSOR_NAME];
union {
void * setting;
} cfg;
};
#define VIDIOC_MSM_SENSOR_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data)
#define VIDIOC_MSM_SENSOR_RELEASE _IO('V', BASE_VIDIOC_PRIVATE + 2)
#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID _IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t)
#define VIDIOC_MSM_CSIPHY_IO_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data)
#define VIDIOC_MSM_CSID_IO_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data)
#define VIDIOC_MSM_ACTUATOR_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data)
#define VIDIOC_MSM_FLASH_LED_DATA_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t)
#define VIDIOC_MSM_EEPROM_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data)
#define VIDIOC_MSM_SENSOR_GET_AF_STATUS _IOWR('V', BASE_VIDIOC_PRIVATE + 9, uint32_t)
#define VIDIOC_MSM_SENSOR_INIT_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data)
#define VIDIOC_MSM_OIS_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data)
#define VIDIOC_MSM_FLASH_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t)
#define VIDIOC_MSM_OIS_CFG_DOWNLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_ois_cfg_download_data)
#define VIDIOC_MSM_FLASH_QUERY_DATA _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_flash_query_data_t)
#define VIDIOC_MSM_IR_LED_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_led_cfg_data_t)
#define VIDIOC_MSM_IR_CUT_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_cut_cfg_data_t)
#define VIDIOC_MSM_LASER_LED_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_laser_led_cfg_data_t)
#endif

1707
sdm710/kernel-headers/media/msm_camera.h
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File diff suppressed because it is too large Load Diff

383
sdm710/kernel-headers/media/msm_camsensor_sdk.h
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@@ -1,383 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_LINUX_MSM_CAMSENSOR_SDK_H
#define __UAPI_LINUX_MSM_CAMSENSOR_SDK_H
#include <linux/videodev2.h>
#define KVERSION 0x1
#define MAX_POWER_CONFIG 12
#define GPIO_OUT_LOW (0 << 1)
#define GPIO_OUT_HIGH (1 << 1)
#define CSI_EMBED_DATA 0x12
#define CSI_RESERVED_DATA_0 0x13
#define CSI_YUV422_8 0x1E
#define CSI_RAW8 0x2A
#define CSI_RAW10 0x2B
#define CSI_RAW12 0x2C
#define CSI_DECODE_6BIT 0
#define CSI_DECODE_8BIT 1
#define CSI_DECODE_10BIT 2
#define CSI_DECODE_12BIT 3
#define CSI_DECODE_DPCM_10_6_10 4
#define CSI_DECODE_DPCM_10_8_10 5
#define MAX_CID 16
#define I2C_SEQ_REG_DATA_MAX 1024
#define I2C_REG_DATA_MAX (8 * 1024)
#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A')
#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4')
#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4')
#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')
#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4')
#define MAX_ACTUATOR_REG_TBL_SIZE 8
#define MAX_ACTUATOR_REGION 5
#define NUM_ACTUATOR_DIR 2
#define MAX_ACTUATOR_SCENARIO 8
#define MAX_ACT_MOD_NAME_SIZE 32
#define MAX_ACT_NAME_SIZE 32
#define MAX_ACTUATOR_INIT_SET 120
#define MAX_I2C_REG_SET 12
#define MAX_LED_TRIGGERS 3
#define MSM_EEPROM_MEMORY_MAP_MAX_SIZE 80
#define MSM_EEPROM_MAX_MEM_MAP_CNT 8
#define MSM_SENSOR_BYPASS_VIDEO_NODE 1
enum msm_sensor_camera_id_t {
CAMERA_0,
CAMERA_1,
CAMERA_2,
CAMERA_3,
MAX_CAMERAS,
};
enum i2c_freq_mode_t {
I2C_STANDARD_MODE,
I2C_FAST_MODE,
I2C_CUSTOM_MODE,
I2C_FAST_PLUS_MODE,
I2C_MAX_MODES,
};
enum camb_position_t {
BACK_CAMERA_B,
FRONT_CAMERA_B,
AUX_CAMERA_B = 0x100,
INVALID_CAMERA_B,
};
enum msm_sensor_power_seq_type_t {
SENSOR_CLK,
SENSOR_GPIO,
SENSOR_VREG,
SENSOR_I2C_MUX,
SENSOR_I2C,
};
enum msm_camera_i2c_reg_addr_type {
MSM_CAMERA_I2C_BYTE_ADDR = 1,
MSM_CAMERA_I2C_WORD_ADDR,
MSM_CAMERA_I2C_3B_ADDR,
MSM_CAMERA_I2C_DWORD_ADDR,
MSM_CAMERA_I2C_ADDR_TYPE_MAX,
};
#define MSM_CAMERA_I2C_DWORD_ADDR MSM_CAMERA_I2C_DWORD_ADDR
enum msm_camera_i2c_data_type {
MSM_CAMERA_I2C_BYTE_DATA = 1,
MSM_CAMERA_I2C_WORD_DATA,
MSM_CAMERA_I2C_DWORD_DATA,
MSM_CAMERA_I2C_SET_BYTE_MASK,
MSM_CAMERA_I2C_UNSET_BYTE_MASK,
MSM_CAMERA_I2C_SET_WORD_MASK,
MSM_CAMERA_I2C_UNSET_WORD_MASK,
MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA,
MSM_CAMERA_I2C_DATA_TYPE_MAX,
};
enum msm_sensor_power_seq_gpio_t {
SENSOR_GPIO_RESET,
SENSOR_GPIO_STANDBY,
SENSOR_GPIO_AF_PWDM,
SENSOR_GPIO_VIO,
SENSOR_GPIO_VANA,
SENSOR_GPIO_VDIG,
SENSOR_GPIO_VAF,
SENSOR_GPIO_FL_EN,
SENSOR_GPIO_FL_NOW,
SENSOR_GPIO_FL_RESET,
SENSOR_GPIO_CUSTOM1,
SENSOR_GPIO_CUSTOM2,
SENSOR_GPIO_CUSTOM3,
SENSOR_GPIO_MAX,
};
#define SENSOR_GPIO_CUSTOM3 SENSOR_GPIO_CUSTOM3
enum msm_ir_cut_filter_gpio_t {
IR_CUT_FILTER_GPIO_P = 0,
IR_CUT_FILTER_GPIO_M,
IR_CUT_FILTER_GPIO_MAX,
};
#define IR_CUT_FILTER_GPIO_P IR_CUT_FILTER_GPIO_P
#define IR_CUT_FILTER_GPIO_M IR_CUT_FILTER_GPIO_M
#define R_CUT_FILTER_GPIO_MAX IR_CUT_FILTER_GPIO_MAX
enum msm_camera_vreg_name_t {
CAM_VDIG,
CAM_VIO,
CAM_VANA,
CAM_VAF,
CAM_V_CUSTOM1,
CAM_V_CUSTOM2,
CAM_VREG_MAX,
};
enum msm_sensor_clk_type_t {
SENSOR_CAM_MCLK,
SENSOR_CAM_CLK,
SENSOR_CAM_CLK_MAX,
};
enum camerab_mode_t {
CAMERA_MODE_2D_B = (1 << 0),
CAMERA_MODE_3D_B = (1 << 1),
CAMERA_MODE_INVALID = (1 << 2),
};
enum msm_actuator_data_type {
MSM_ACTUATOR_BYTE_DATA = 1,
MSM_ACTUATOR_WORD_DATA,
};
enum msm_actuator_addr_type {
MSM_ACTUATOR_BYTE_ADDR = 1,
MSM_ACTUATOR_WORD_ADDR,
};
enum msm_actuator_write_type {
MSM_ACTUATOR_WRITE_HW_DAMP,
MSM_ACTUATOR_WRITE_DAC,
MSM_ACTUATOR_WRITE,
MSM_ACTUATOR_WRITE_DIR_REG,
MSM_ACTUATOR_POLL,
MSM_ACTUATOR_READ_WRITE,
};
enum msm_actuator_i2c_operation {
MSM_ACT_WRITE = 0,
MSM_ACT_POLL,
};
enum actuator_type {
ACTUATOR_VCM,
ACTUATOR_PIEZO,
ACTUATOR_HVCM,
ACTUATOR_BIVCM,
};
enum msm_flash_driver_type {
FLASH_DRIVER_PMIC,
FLASH_DRIVER_I2C,
FLASH_DRIVER_GPIO,
FLASH_DRIVER_DEFAULT
};
enum msm_flash_cfg_type_t {
CFG_FLASH_INIT,
CFG_FLASH_RELEASE,
CFG_FLASH_OFF,
CFG_FLASH_LOW,
CFG_FLASH_HIGH,
};
enum msm_ir_led_cfg_type_t {
CFG_IR_LED_INIT = 0,
CFG_IR_LED_RELEASE,
CFG_IR_LED_OFF,
CFG_IR_LED_ON,
};
#define CFG_IR_LED_INIT CFG_IR_LED_INIT
#define CFG_IR_LED_RELEASE CFG_IR_LED_RELEASE
#define CFG_IR_LED_OFF CFG_IR_LED_OFF
#define CFG_IR_LED_ON CFG_IR_LED_ON
enum msm_laser_led_cfg_type_t {
CFG_LASER_LED_INIT,
CFG_LASER_LED_CONTROL,
};
#define CFG_LASER_LED_INIT CFG_LASER_LED_INIT
#define CFG_LASER_LED_CONTROL CFG_LASER_LED_CONTROL
enum msm_ir_cut_cfg_type_t {
CFG_IR_CUT_INIT = 0,
CFG_IR_CUT_RELEASE,
CFG_IR_CUT_OFF,
CFG_IR_CUT_ON,
};
#define CFG_IR_CUT_INIT CFG_IR_CUT_INIT
#define CFG_IR_CUT_RELEASE CFG_IR_CUT_RELEASE
#define CFG_IR_CUT_OFF CFG_IR_CUT_OFF
#define CFG_IR_CUT_ON CFG_IR_CUT_ON
enum msm_sensor_output_format_t {
MSM_SENSOR_BAYER,
MSM_SENSOR_YCBCR,
MSM_SENSOR_META,
};
struct msm_sensor_power_setting {
enum msm_sensor_power_seq_type_t seq_type;
unsigned short seq_val;
long config_val;
unsigned short delay;
void * data[10];
};
struct msm_sensor_power_setting_array {
struct msm_sensor_power_setting power_setting_a[MAX_POWER_CONFIG];
struct msm_sensor_power_setting * power_setting;
unsigned short size;
struct msm_sensor_power_setting power_down_setting_a[MAX_POWER_CONFIG];
struct msm_sensor_power_setting * power_down_setting;
unsigned short size_down;
};
enum msm_camera_i2c_operation {
MSM_CAM_WRITE = 0,
MSM_CAM_POLL,
MSM_CAM_READ,
};
struct msm_sensor_i2c_sync_params {
unsigned int cid;
int csid;
unsigned short line;
unsigned short delay;
};
struct msm_camera_reg_settings_t {
uint16_t reg_addr;
enum msm_camera_i2c_reg_addr_type addr_type;
uint16_t reg_data;
enum msm_camera_i2c_data_type data_type;
enum msm_camera_i2c_operation i2c_operation;
uint16_t delay;
};
struct msm_eeprom_mem_map_t {
int slave_addr;
struct msm_camera_reg_settings_t mem_settings[MSM_EEPROM_MEMORY_MAP_MAX_SIZE];
int memory_map_size;
};
struct msm_eeprom_memory_map_array {
struct msm_eeprom_mem_map_t memory_map[MSM_EEPROM_MAX_MEM_MAP_CNT];
uint32_t msm_size_of_max_mappings;
};
struct msm_sensor_init_params {
int modes_supported;
enum camb_position_t position;
unsigned int sensor_mount_angle;
};
struct msm_sensor_id_info_t {
unsigned short sensor_id_reg_addr;
unsigned short sensor_id;
unsigned short sensor_id_mask;
};
struct msm_camera_sensor_slave_info {
char sensor_name[32];
char eeprom_name[32];
char actuator_name[32];
char ois_name[32];
char flash_name[32];
enum msm_sensor_camera_id_t camera_id;
unsigned short slave_addr;
enum i2c_freq_mode_t i2c_freq_mode;
enum msm_camera_i2c_reg_addr_type addr_type;
struct msm_sensor_id_info_t sensor_id_info;
struct msm_sensor_power_setting_array power_setting_array;
unsigned char is_init_params_valid;
struct msm_sensor_init_params sensor_init_params;
enum msm_sensor_output_format_t output_format;
uint8_t bypass_video_node_creation;
};
struct msm_camera_i2c_reg_array {
unsigned short reg_addr;
unsigned short reg_data;
unsigned int delay;
};
struct msm_camera_i2c_reg_setting {
struct msm_camera_i2c_reg_array * reg_setting;
unsigned short size;
enum msm_camera_i2c_reg_addr_type addr_type;
enum msm_camera_i2c_data_type data_type;
unsigned short delay;
};
struct msm_camera_csid_vc_cfg {
unsigned char cid;
unsigned char dt;
unsigned char decode_format;
};
struct msm_camera_csid_lut_params {
unsigned char num_cid;
struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID];
struct msm_camera_csid_vc_cfg * vc_cfg[MAX_CID];
};
struct msm_camera_csid_params {
unsigned char lane_cnt;
unsigned short lane_assign;
unsigned char phy_sel;
unsigned int csi_clk;
struct msm_camera_csid_lut_params lut_params;
unsigned char csi_3p_sel;
};
struct msm_camera_csid_testmode_parms {
unsigned int num_bytes_per_line;
unsigned int num_lines;
unsigned int h_blanking_count;
unsigned int v_blanking_count;
unsigned int payload_mode;
};
struct msm_camera_csiphy_params {
unsigned char lane_cnt;
unsigned char settle_cnt;
unsigned short lane_mask;
unsigned char combo_mode;
unsigned char csid_core;
unsigned int csiphy_clk;
unsigned char csi_3phase;
uint64_t data_rate;
};
struct msm_camera_i2c_seq_reg_array {
unsigned short reg_addr;
unsigned char reg_data[I2C_SEQ_REG_DATA_MAX];
unsigned short reg_data_size;
};
struct msm_camera_i2c_seq_reg_setting {
struct msm_camera_i2c_seq_reg_array * reg_setting;
unsigned short size;
enum msm_camera_i2c_reg_addr_type addr_type;
unsigned short delay;
};
struct msm_actuator_reg_params_t {
enum msm_actuator_write_type reg_write_type;
unsigned int hw_mask;
unsigned short reg_addr;
unsigned short hw_shift;
unsigned short data_shift;
unsigned short data_type;
unsigned short addr_type;
unsigned short reg_data;
unsigned short delay;
};
struct damping_params_t {
unsigned int damping_step;
unsigned int damping_delay;
unsigned int hw_params;
};
struct region_params_t {
unsigned short step_bound[2];
unsigned short code_per_step;
unsigned int qvalue;
};
struct reg_settings_t {
unsigned short reg_addr;
enum msm_camera_i2c_reg_addr_type addr_type;
unsigned short reg_data;
enum msm_camera_i2c_data_type data_type;
enum msm_actuator_i2c_operation i2c_operation;
unsigned int delay;
};
struct msm_camera_i2c_reg_setting_array {
struct msm_camera_i2c_reg_array reg_setting_a[MAX_I2C_REG_SET];
unsigned short size;
enum msm_camera_i2c_reg_addr_type addr_type;
enum msm_camera_i2c_data_type data_type;
unsigned short delay;
};
#endif

57
sdm710/kernel-headers/media/msm_fd.h
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@@ -1,57 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MSM_FD__
#define __UAPI_MSM_FD__
#include <linux/videodev2.h>
#include <linux/types.h>
struct msm_fd_event {
__u32 buf_index;
__u32 frame_id;
__u32 face_cnt;
};
enum msm_fd_pose {
MSM_FD_POSE_FRONT,
MSM_FD_POSE_RIGHT_DIAGONAL,
MSM_FD_POSE_RIGHT,
MSM_FD_POSE_LEFT_DIAGONAL,
MSM_FD_POSE_LEFT,
};
struct msm_fd_face_data {
__u32 pose;
__u32 angle;
__u32 confidence;
__u32 reserved;
struct v4l2_rect face;
};
struct msm_fd_result {
__u32 frame_id;
__u32 face_cnt;
struct msm_fd_face_data * face_data;
};
#define VIDIOC_MSM_FD_GET_RESULT _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result)
#define MSM_EVENT_FD (V4L2_EVENT_PRIVATE_START)
#define V4L2_CID_FD_SPEED (V4L2_CID_PRIVATE_BASE)
#define V4L2_CID_FD_FACE_ANGLE (V4L2_CID_PRIVATE_BASE + 1)
#define V4L2_CID_FD_MIN_FACE_SIZE (V4L2_CID_PRIVATE_BASE + 2)
#define V4L2_CID_FD_FACE_DIRECTION (V4L2_CID_PRIVATE_BASE + 3)
#define V4L2_CID_FD_DETECTION_THRESHOLD (V4L2_CID_PRIVATE_BASE + 4)
#define V4L2_CID_FD_WORK_MEMORY_SIZE (V4L2_CID_PRIVATE_BASE + 5)
#define V4L2_CID_FD_WORK_MEMORY_FD (V4L2_CID_PRIVATE_BASE + 6)
#endif

90
sdm710/kernel-headers/media/msm_gemini.h
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@@ -1,90 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MSM_GEMINI_H
#define __UAPI_MSM_GEMINI_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define MSM_GMN_IOCTL_MAGIC 'g'
#define MSM_GMN_IOCTL_GET_HW_VERSION _IOW(MSM_GMN_IOCTL_MAGIC, 1, struct msm_gemini_hw_cmd *)
#define MSM_GMN_IOCTL_RESET _IOW(MSM_GMN_IOCTL_MAGIC, 2, struct msm_gemini_ctrl_cmd *)
#define MSM_GMN_IOCTL_STOP _IOW(MSM_GMN_IOCTL_MAGIC, 3, struct msm_gemini_hw_cmds *)
#define MSM_GMN_IOCTL_START _IOW(MSM_GMN_IOCTL_MAGIC, 4, struct msm_gemini_hw_cmds *)
#define MSM_GMN_IOCTL_INPUT_BUF_ENQUEUE _IOW(MSM_GMN_IOCTL_MAGIC, 5, struct msm_gemini_buf *)
#define MSM_GMN_IOCTL_INPUT_GET _IOW(MSM_GMN_IOCTL_MAGIC, 6, struct msm_gemini_buf *)
#define MSM_GMN_IOCTL_INPUT_GET_UNBLOCK _IOW(MSM_GMN_IOCTL_MAGIC, 7, int)
#define MSM_GMN_IOCTL_OUTPUT_BUF_ENQUEUE _IOW(MSM_GMN_IOCTL_MAGIC, 8, struct msm_gemini_buf *)
#define MSM_GMN_IOCTL_OUTPUT_GET _IOW(MSM_GMN_IOCTL_MAGIC, 9, struct msm_gemini_buf *)
#define MSM_GMN_IOCTL_OUTPUT_GET_UNBLOCK _IOW(MSM_GMN_IOCTL_MAGIC, 10, int)
#define MSM_GMN_IOCTL_EVT_GET _IOW(MSM_GMN_IOCTL_MAGIC, 11, struct msm_gemini_ctrl_cmd *)
#define MSM_GMN_IOCTL_EVT_GET_UNBLOCK _IOW(MSM_GMN_IOCTL_MAGIC, 12, int)
#define MSM_GMN_IOCTL_HW_CMD _IOW(MSM_GMN_IOCTL_MAGIC, 13, struct msm_gemini_hw_cmd *)
#define MSM_GMN_IOCTL_HW_CMDS _IOW(MSM_GMN_IOCTL_MAGIC, 14, struct msm_gemini_hw_cmds *)
#define MSM_GMN_IOCTL_TEST_DUMP_REGION _IOW(MSM_GMN_IOCTL_MAGIC, 15, unsigned long)
#define MSM_GMN_IOCTL_SET_MODE _IOW(MSM_GMN_IOCTL_MAGIC, 16, enum msm_gmn_out_mode)
#define MSM_GEMINI_MODE_REALTIME_ENCODE 0
#define MSM_GEMINI_MODE_OFFLINE_ENCODE 1
#define MSM_GEMINI_MODE_REALTIME_ROTATION 2
#define MSM_GEMINI_MODE_OFFLINE_ROTATION 3
enum msm_gmn_out_mode {
MSM_GMN_OUTMODE_FRAGMENTED,
MSM_GMN_OUTMODE_SINGLE
};
struct msm_gemini_ctrl_cmd {
uint32_t type;
uint32_t len;
void * value;
};
#define MSM_GEMINI_EVT_RESET 0
#define MSM_GEMINI_EVT_FRAMEDONE 1
#define MSM_GEMINI_EVT_ERR 2
struct msm_gemini_buf {
uint32_t type;
int fd;
void * vaddr;
uint32_t y_off;
uint32_t y_len;
uint32_t framedone_len;
uint32_t cbcr_off;
uint32_t cbcr_len;
uint32_t num_of_mcu_rows;
uint32_t offset;
};
#define MSM_GEMINI_HW_CMD_TYPE_READ 0
#define MSM_GEMINI_HW_CMD_TYPE_WRITE 1
#define MSM_GEMINI_HW_CMD_TYPE_WRITE_OR 2
#define MSM_GEMINI_HW_CMD_TYPE_UWAIT 3
#define MSM_GEMINI_HW_CMD_TYPE_MWAIT 4
#define MSM_GEMINI_HW_CMD_TYPE_MDELAY 5
#define MSM_GEMINI_HW_CMD_TYPE_UDELAY 6
struct msm_gemini_hw_cmd {
uint32_t type : 4;
uint32_t n : 12;
uint32_t offset : 16;
uint32_t mask;
union {
uint32_t data;
uint32_t * pdata;
};
};
struct msm_gemini_hw_cmds {
uint32_t m;
struct msm_gemini_hw_cmd hw_cmd[1];
};
#endif

54
sdm710/kernel-headers/media/msm_gestures.h
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@@ -1,54 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MSM_GESTURES_H
#define __UAPI_MSM_GESTURES_H
#include <linux/types.h>
#include <linux/ioctl.h>
#include <media/msm_camera.h>
#define MSM_GES_IOCTL_CTRL_COMMAND _IOW('V', BASE_VIDIOC_PRIVATE + 20, struct v4l2_control)
#define VIDIOC_MSM_GESTURE_EVT _IOWR('V', BASE_VIDIOC_PRIVATE + 21, struct v4l2_event)
#define MSM_GES_GET_EVT_PAYLOAD _IOW('V', BASE_VIDIOC_PRIVATE + 22, struct msm_ges_evt)
#define VIDIOC_MSM_GESTURE_CAM_EVT _IOWR('V', BASE_VIDIOC_PRIVATE + 23, int)
#define MSM_GES_RESP_V4L2 MSM_CAM_RESP_MAX
#define MSM_GES_RESP_MAX (MSM_GES_RESP_V4L2 + 1)
#define MSM_SVR_RESP_MAX MSM_GES_RESP_MAX
#define MSM_V4L2_GES_BASE 100
#define MSM_V4L2_GES_OPEN (MSM_V4L2_GES_BASE + 0)
#define MSM_V4L2_GES_CLOSE (MSM_V4L2_GES_BASE + 1)
#define MSM_V4L2_GES_CAM_OPEN (MSM_V4L2_GES_BASE + 2)
#define MSM_V4L2_GES_CAM_CLOSE (MSM_V4L2_GES_BASE + 3)
#define MSM_GES_APP_EVT_MIN (V4L2_EVENT_PRIVATE_START + 0x14)
#define MSM_GES_APP_NOTIFY_EVENT (MSM_GES_APP_EVT_MIN + 0)
#define MSM_GES_APP_NOTIFY_ERROR_EVENT (MSM_GES_APP_EVT_MIN + 1)
#define MSM_GES_APP_EVT_MAX (MSM_GES_APP_EVT_MIN + 2)
#define MSM_GESTURE_CID_CTRL_CMD V4L2_CID_BRIGHTNESS
#define MAX_GES_EVENTS 25
struct msm_ges_ctrl_cmd {
int type;
void * value;
int len;
int fd;
uint32_t cookie;
};
struct msm_ges_evt {
void * evt_data;
int evt_len;
};
#endif

334
sdm710/kernel-headers/media/msm_isp.h
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@@ -1,334 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MSM_ISP_H__
#define __UAPI_MSM_ISP_H__
#define BIT(nr) (1UL << (nr))
#define MSG_ID_RESET_ACK 0
#define MSG_ID_START_ACK 1
#define MSG_ID_STOP_ACK 2
#define MSG_ID_UPDATE_ACK 3
#define MSG_ID_OUTPUT_P 4
#define MSG_ID_OUTPUT_T 5
#define MSG_ID_OUTPUT_S 6
#define MSG_ID_OUTPUT_V 7
#define MSG_ID_SNAPSHOT_DONE 8
#define MSG_ID_STATS_AEC 9
#define MSG_ID_STATS_AF 10
#define MSG_ID_STATS_AWB 11
#define MSG_ID_STATS_RS 12
#define MSG_ID_STATS_CS 13
#define MSG_ID_STATS_IHIST 14
#define MSG_ID_STATS_SKIN 15
#define MSG_ID_EPOCH1 16
#define MSG_ID_EPOCH2 17
#define MSG_ID_SYNC_TIMER0_DONE 18
#define MSG_ID_SYNC_TIMER1_DONE 19
#define MSG_ID_SYNC_TIMER2_DONE 20
#define MSG_ID_ASYNC_TIMER0_DONE 21
#define MSG_ID_ASYNC_TIMER1_DONE 22
#define MSG_ID_ASYNC_TIMER2_DONE 23
#define MSG_ID_ASYNC_TIMER3_DONE 24
#define MSG_ID_AE_OVERFLOW 25
#define MSG_ID_AF_OVERFLOW 26
#define MSG_ID_AWB_OVERFLOW 27
#define MSG_ID_RS_OVERFLOW 28
#define MSG_ID_CS_OVERFLOW 29
#define MSG_ID_IHIST_OVERFLOW 30
#define MSG_ID_SKIN_OVERFLOW 31
#define MSG_ID_AXI_ERROR 32
#define MSG_ID_CAMIF_OVERFLOW 33
#define MSG_ID_VIOLATION 34
#define MSG_ID_CAMIF_ERROR 35
#define MSG_ID_BUS_OVERFLOW 36
#define MSG_ID_SOF_ACK 37
#define MSG_ID_STOP_REC_ACK 38
#define MSG_ID_STATS_AWB_AEC 39
#define MSG_ID_OUTPUT_PRIMARY 40
#define MSG_ID_OUTPUT_SECONDARY 41
#define MSG_ID_STATS_COMPOSITE 42
#define MSG_ID_OUTPUT_TERTIARY1 43
#define MSG_ID_STOP_LS_ACK 44
#define MSG_ID_OUTPUT_TERTIARY2 45
#define MSG_ID_STATS_BG 46
#define MSG_ID_STATS_BF 47
#define MSG_ID_STATS_BHIST 48
#define MSG_ID_RDI0_UPDATE_ACK 49
#define MSG_ID_RDI1_UPDATE_ACK 50
#define MSG_ID_RDI2_UPDATE_ACK 51
#define MSG_ID_PIX0_UPDATE_ACK 52
#define MSG_ID_PREV_STOP_ACK 53
#define MSG_ID_STATS_BE 54
#define VFE_CMD_DUMMY_0 0
#define VFE_CMD_SET_CLK 1
#define VFE_CMD_RESET 2
#define VFE_CMD_START 3
#define VFE_CMD_TEST_GEN_START 4
#define VFE_CMD_OPERATION_CFG 5
#define VFE_CMD_AXI_OUT_CFG 6
#define VFE_CMD_CAMIF_CFG 7
#define VFE_CMD_AXI_INPUT_CFG 8
#define VFE_CMD_BLACK_LEVEL_CFG 9
#define VFE_CMD_MESH_ROLL_OFF_CFG 10
#define VFE_CMD_DEMUX_CFG 11
#define VFE_CMD_FOV_CFG 12
#define VFE_CMD_MAIN_SCALER_CFG 13
#define VFE_CMD_WB_CFG 14
#define VFE_CMD_COLOR_COR_CFG 15
#define VFE_CMD_RGB_G_CFG 16
#define VFE_CMD_LA_CFG 17
#define VFE_CMD_CHROMA_EN_CFG 18
#define VFE_CMD_CHROMA_SUP_CFG 19
#define VFE_CMD_MCE_CFG 20
#define VFE_CMD_SK_ENHAN_CFG 21
#define VFE_CMD_ASF_CFG 22
#define VFE_CMD_S2Y_CFG 23
#define VFE_CMD_S2CbCr_CFG 24
#define VFE_CMD_CHROMA_SUBS_CFG 25
#define VFE_CMD_OUT_CLAMP_CFG 26
#define VFE_CMD_FRAME_SKIP_CFG 27
#define VFE_CMD_DUMMY_1 28
#define VFE_CMD_DUMMY_2 29
#define VFE_CMD_DUMMY_3 30
#define VFE_CMD_UPDATE 31
#define VFE_CMD_BL_LVL_UPDATE 32
#define VFE_CMD_DEMUX_UPDATE 33
#define VFE_CMD_FOV_UPDATE 34
#define VFE_CMD_MAIN_SCALER_UPDATE 35
#define VFE_CMD_WB_UPDATE 36
#define VFE_CMD_COLOR_COR_UPDATE 37
#define VFE_CMD_RGB_G_UPDATE 38
#define VFE_CMD_LA_UPDATE 39
#define VFE_CMD_CHROMA_EN_UPDATE 40
#define VFE_CMD_CHROMA_SUP_UPDATE 41
#define VFE_CMD_MCE_UPDATE 42
#define VFE_CMD_SK_ENHAN_UPDATE 43
#define VFE_CMD_S2CbCr_UPDATE 44
#define VFE_CMD_S2Y_UPDATE 45
#define VFE_CMD_ASF_UPDATE 46
#define VFE_CMD_FRAME_SKIP_UPDATE 47
#define VFE_CMD_CAMIF_FRAME_UPDATE 48
#define VFE_CMD_STATS_AF_UPDATE 49
#define VFE_CMD_STATS_AE_UPDATE 50
#define VFE_CMD_STATS_AWB_UPDATE 51
#define VFE_CMD_STATS_RS_UPDATE 52
#define VFE_CMD_STATS_CS_UPDATE 53
#define VFE_CMD_STATS_SKIN_UPDATE 54
#define VFE_CMD_STATS_IHIST_UPDATE 55
#define VFE_CMD_DUMMY_4 56
#define VFE_CMD_EPOCH1_ACK 57
#define VFE_CMD_EPOCH2_ACK 58
#define VFE_CMD_START_RECORDING 59
#define VFE_CMD_STOP_RECORDING 60
#define VFE_CMD_DUMMY_5 61
#define VFE_CMD_DUMMY_6 62
#define VFE_CMD_CAPTURE 63
#define VFE_CMD_DUMMY_7 64
#define VFE_CMD_STOP 65
#define VFE_CMD_GET_HW_VERSION 66
#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67
#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68
#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69
#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70
#define VFE_CMD_JPEG_OUT_BUF_ENQ 71
#define VFE_CMD_RAW_OUT_BUF_ENQ 72
#define VFE_CMD_RAW_IN_BUF_ENQ 73
#define VFE_CMD_STATS_AF_ENQ 74
#define VFE_CMD_STATS_AE_ENQ 75
#define VFE_CMD_STATS_AWB_ENQ 76
#define VFE_CMD_STATS_RS_ENQ 77
#define VFE_CMD_STATS_CS_ENQ 78
#define VFE_CMD_STATS_SKIN_ENQ 79
#define VFE_CMD_STATS_IHIST_ENQ 80
#define VFE_CMD_DUMMY_8 81
#define VFE_CMD_JPEG_ENC_CFG 82
#define VFE_CMD_DUMMY_9 83
#define VFE_CMD_STATS_AF_START 84
#define VFE_CMD_STATS_AF_STOP 85
#define VFE_CMD_STATS_AE_START 86
#define VFE_CMD_STATS_AE_STOP 87
#define VFE_CMD_STATS_AWB_START 88
#define VFE_CMD_STATS_AWB_STOP 89
#define VFE_CMD_STATS_RS_START 90
#define VFE_CMD_STATS_RS_STOP 91
#define VFE_CMD_STATS_CS_START 92
#define VFE_CMD_STATS_CS_STOP 93
#define VFE_CMD_STATS_SKIN_START 94
#define VFE_CMD_STATS_SKIN_STOP 95
#define VFE_CMD_STATS_IHIST_START 96
#define VFE_CMD_STATS_IHIST_STOP 97
#define VFE_CMD_DUMMY_10 98
#define VFE_CMD_SYNC_TIMER_SETTING 99
#define VFE_CMD_ASYNC_TIMER_SETTING 100
#define VFE_CMD_LIVESHOT 101
#define VFE_CMD_LA_SETUP 102
#define VFE_CMD_LINEARIZATION_CFG 103
#define VFE_CMD_DEMOSAICV3 104
#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105
#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106
#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107
#define VFE_CMD_DEMOSAICV3_ABF_CFG 108
#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109
#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110
#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111
#define VFE_CMD_XBAR_CFG 112
#define VFE_CMD_MODULE_CFG 113
#define VFE_CMD_ZSL 114
#define VFE_CMD_LINEARIZATION_UPDATE 115
#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116
#define VFE_CMD_CLF_CFG 117
#define VFE_CMD_CLF_LUMA_UPDATE 118
#define VFE_CMD_CLF_CHROMA_UPDATE 119
#define VFE_CMD_PCA_ROLL_OFF_CFG 120
#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
#define VFE_CMD_GET_REG_DUMP 122
#define VFE_CMD_GET_LINEARIZATON_TABLE 123
#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124
#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125
#define VFE_CMD_GET_RGB_G_TABLE 126
#define VFE_CMD_GET_LA_TABLE 127
#define VFE_CMD_DEMOSAICV3_UPDATE 128
#define VFE_CMD_ACTIVE_REGION_CFG 129
#define VFE_CMD_COLOR_PROCESSING_CONFIG 130
#define VFE_CMD_STATS_WB_AEC_CONFIG 131
#define VFE_CMD_STATS_WB_AEC_UPDATE 132
#define VFE_CMD_Y_GAMMA_CONFIG 133
#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134
#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135
#define VFE_CMD_CAPTURE_RAW 136
#define VFE_CMD_STOP_LIVESHOT 137
#define VFE_CMD_RECONFIG_VFE 138
#define VFE_CMD_STATS_REQBUF 139
#define VFE_CMD_STATS_ENQUEUEBUF 140
#define VFE_CMD_STATS_FLUSH_BUFQ 141
#define VFE_CMD_STATS_UNREGBUF 142
#define VFE_CMD_STATS_BG_START 143
#define VFE_CMD_STATS_BG_STOP 144
#define VFE_CMD_STATS_BF_START 145
#define VFE_CMD_STATS_BF_STOP 146
#define VFE_CMD_STATS_BHIST_START 147
#define VFE_CMD_STATS_BHIST_STOP 148
#define VFE_CMD_RESET_2 149
#define VFE_CMD_FOV_ENC_CFG 150
#define VFE_CMD_FOV_VIEW_CFG 151
#define VFE_CMD_FOV_ENC_UPDATE 152
#define VFE_CMD_FOV_VIEW_UPDATE 153
#define VFE_CMD_SCALER_ENC_CFG 154
#define VFE_CMD_SCALER_VIEW_CFG 155
#define VFE_CMD_SCALER_ENC_UPDATE 156
#define VFE_CMD_SCALER_VIEW_UPDATE 157
#define VFE_CMD_COLORXFORM_ENC_CFG 158
#define VFE_CMD_COLORXFORM_VIEW_CFG 159
#define VFE_CMD_COLORXFORM_ENC_UPDATE 160
#define VFE_CMD_COLORXFORM_VIEW_UPDATE 161
#define VFE_CMD_TEST_GEN_CFG 162
#define VFE_CMD_STATS_BE_START 163
#define VFE_CMD_STATS_BE_STOP 164
struct msm_isp_cmd {
int32_t id;
uint16_t length;
void * value;
};
#define VPE_CMD_DUMMY_0 0
#define VPE_CMD_INIT 1
#define VPE_CMD_DEINIT 2
#define VPE_CMD_ENABLE 3
#define VPE_CMD_DISABLE 4
#define VPE_CMD_RESET 5
#define VPE_CMD_FLUSH 6
#define VPE_CMD_OPERATION_MODE_CFG 7
#define VPE_CMD_INPUT_PLANE_CFG 8
#define VPE_CMD_OUTPUT_PLANE_CFG 9
#define VPE_CMD_INPUT_PLANE_UPDATE 10
#define VPE_CMD_SCALE_CFG_TYPE 11
#define VPE_CMD_ZOOM 13
#define VPE_CMD_MAX 14
#define MSM_PP_CMD_TYPE_NOT_USED 0
#define MSM_PP_CMD_TYPE_VPE 1
#define MSM_PP_CMD_TYPE_MCTL 2
#define MCTL_CMD_DUMMY_0 0
#define MCTL_CMD_GET_FRAME_BUFFER 1
#define MCTL_CMD_PUT_FRAME_BUFFER 2
#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3
#define MCTL_PP_EVENT_NOTUSED 0
#define MCTL_PP_EVENT_CMD_ACK 1
#define VPE_OPERATION_MODE_CFG_LEN 4
#define VPE_INPUT_PLANE_CFG_LEN 24
#define VPE_OUTPUT_PLANE_CFG_LEN 20
#define VPE_INPUT_PLANE_UPDATE_LEN 12
#define VPE_SCALER_CONFIG_LEN 260
#define VPE_DIS_OFFSET_CFG_LEN 12
#define CAPTURE_WIDTH 1280
#define IMEM_Y_SIZE (CAPTURE_WIDTH * 16)
#define IMEM_CBCR_SIZE (CAPTURE_WIDTH * 8)
#define IMEM_Y_PING_OFFSET 0x2E000000
#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE)
#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE)
#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE)
struct msm_vpe_op_mode_cfg {
uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN];
};
struct msm_vpe_input_plane_cfg {
uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN];
};
struct msm_vpe_output_plane_cfg {
uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN];
};
struct msm_vpe_input_plane_update_cfg {
uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN];
};
struct msm_vpe_scaler_cfg {
uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN];
};
struct msm_vpe_flush_frame_buffer {
uint32_t src_buf_handle;
uint32_t dest_buf_handle;
int path;
};
struct msm_mctl_pp_frame_buffer {
uint32_t buf_handle;
int path;
};
struct msm_mctl_pp_divert_pp {
int path;
int enable;
};
struct msm_vpe_clock_rate {
uint32_t rate;
};
#define MSM_MCTL_PP_VPE_FRAME_ACK (1 << 0)
#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1 << 1)
#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0)
#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1)
#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2)
#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3)
#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4)
#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5)
#define VFE_OUTPUTS_PREVIEW BIT(6)
#define VFE_OUTPUTS_VIDEO BIT(7)
#define VFE_OUTPUTS_RAW BIT(8)
#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9)
#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10)
#define VFE_OUTPUTS_RDI0 BIT(11)
#define VFE_OUTPUTS_RDI1 BIT(12)
struct msm_frame_info {
uint32_t inst_handle;
uint32_t path;
};
#endif

91
sdm710/kernel-headers/media/msm_jpeg.h
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@@ -1,91 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_LINUX_MSM_JPEG_H
#define __UAPI_LINUX_MSM_JPEG_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define OUTPUT_H2V1 0
#define OUTPUT_H2V2 1
#define OUTPUT_BYTE 6
#define MSM_JPEG_IOCTL_MAGIC 'g'
#define MSM_JPEG_IOCTL_GET_HW_VERSION _IOW(MSM_JPEG_IOCTL_MAGIC, 1, struct msm_jpeg_hw_cmd)
#define MSM_JPEG_IOCTL_RESET _IOW(MSM_JPEG_IOCTL_MAGIC, 2, struct msm_jpeg_ctrl_cmd)
#define MSM_JPEG_IOCTL_STOP _IOW(MSM_JPEG_IOCTL_MAGIC, 3, struct msm_jpeg_hw_cmds)
#define MSM_JPEG_IOCTL_START _IOW(MSM_JPEG_IOCTL_MAGIC, 4, struct msm_jpeg_hw_cmds)
#define MSM_JPEG_IOCTL_INPUT_BUF_ENQUEUE _IOW(MSM_JPEG_IOCTL_MAGIC, 5, struct msm_jpeg_buf)
#define MSM_JPEG_IOCTL_INPUT_GET _IOW(MSM_JPEG_IOCTL_MAGIC, 6, struct msm_jpeg_buf)
#define MSM_JPEG_IOCTL_INPUT_GET_UNBLOCK _IOW(MSM_JPEG_IOCTL_MAGIC, 7, int)
#define MSM_JPEG_IOCTL_OUTPUT_BUF_ENQUEUE _IOW(MSM_JPEG_IOCTL_MAGIC, 8, struct msm_jpeg_buf)
#define MSM_JPEG_IOCTL_OUTPUT_GET _IOW(MSM_JPEG_IOCTL_MAGIC, 9, struct msm_jpeg_buf)
#define MSM_JPEG_IOCTL_OUTPUT_GET_UNBLOCK _IOW(MSM_JPEG_IOCTL_MAGIC, 10, int)
#define MSM_JPEG_IOCTL_EVT_GET _IOW(MSM_JPEG_IOCTL_MAGIC, 11, struct msm_jpeg_ctrl_cmd)
#define MSM_JPEG_IOCTL_EVT_GET_UNBLOCK _IOW(MSM_JPEG_IOCTL_MAGIC, 12, int)
#define MSM_JPEG_IOCTL_HW_CMD _IOW(MSM_JPEG_IOCTL_MAGIC, 13, struct msm_jpeg_hw_cmd)
#define MSM_JPEG_IOCTL_HW_CMDS _IOW(MSM_JPEG_IOCTL_MAGIC, 14, struct msm_jpeg_hw_cmds)
#define MSM_JPEG_IOCTL_TEST_DUMP_REGION _IOW(MSM_JPEG_IOCTL_MAGIC, 15, unsigned long)
#define MSM_JPEG_IOCTL_SET_CLK_RATE _IOW(MSM_JPEG_IOCTL_MAGIC, 16, unsigned int)
#define MSM_JPEG_MODE_REALTIME_ENCODE 0
#define MSM_JPEG_MODE_OFFLINE_ENCODE 1
#define MSM_JPEG_MODE_REALTIME_ROTATION 2
#define MSM_JPEG_MODE_OFFLINE_ROTATION 3
struct msm_jpeg_ctrl_cmd {
uint32_t type;
uint32_t len;
void * value;
};
#define MSM_JPEG_EVT_RESET 0
#define MSM_JPEG_EVT_SESSION_DONE 1
#define MSM_JPEG_EVT_ERR 2
struct msm_jpeg_buf {
uint32_t type;
int fd;
void * vaddr;
uint32_t y_off;
uint32_t y_len;
uint32_t framedone_len;
uint32_t cbcr_off;
uint32_t cbcr_len;
uint32_t num_of_mcu_rows;
uint32_t offset;
uint32_t pln2_off;
uint32_t pln2_len;
};
#define MSM_JPEG_HW_CMD_TYPE_READ 0
#define MSM_JPEG_HW_CMD_TYPE_WRITE 1
#define MSM_JPEG_HW_CMD_TYPE_WRITE_OR 2
#define MSM_JPEG_HW_CMD_TYPE_UWAIT 3
#define MSM_JPEG_HW_CMD_TYPE_MWAIT 4
#define MSM_JPEG_HW_CMD_TYPE_MDELAY 5
#define MSM_JPEG_HW_CMD_TYPE_UDELAY 6
struct msm_jpeg_hw_cmd {
uint32_t type : 4;
uint32_t n : 12;
uint32_t offset : 16;
uint32_t mask;
union {
uint32_t data;
uint32_t * pdata;
};
};
struct msm_jpeg_hw_cmds {
uint32_t m;
struct msm_jpeg_hw_cmd hw_cmd[1];
};
#endif

29
sdm710/kernel-headers/media/msm_jpeg_dma.h
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@@ -1,29 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MSM_JPEG_DMA__
#define __UAPI_MSM_JPEG_DMA__
#include <linux/videodev2.h>
#define V4L2_CID_JPEG_DMA_SPEED (V4L2_CID_PRIVATE_BASE)
#define V4L2_CID_JPEG_DMA_MAX_DOWN_SCALE (V4L2_CID_PRIVATE_BASE + 1)
struct msm_jpeg_dma_buff {
int32_t fd;
uint32_t offset;
};
#endif

1398
sdm710/kernel-headers/media/msm_media_info.h
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File diff suppressed because it is too large Load Diff

90
sdm710/kernel-headers/media/msm_mercury.h
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@@ -1,90 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MSM_MERCURY_H
#define __UAPI_MSM_MERCURY_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define MSM_MERCURY_HW_VERSION_REG 0x0004
#define OUTPUT_H2V1 0
#define OUTPUT_H2V2 1
#define OUTPUT_BYTE 6
#define MSM_MERCURY_MODE_REALTIME_ENCODE 0
#define MSM_MERCURY_MODE_OFFLINE_ENCODE 1
#define MSM_MERCURY_MODE_REALTIME_ROTATION 2
#define MSM_MERCURY_MODE_OFFLINE_ROTATION 3
#define MSM_MERCURY_EVT_RESET 1
#define MSM_MERCURY_EVT_FRAMEDONE 2
#define MSM_MERCURY_EVT_ERR 3
#define MSM_MERCURY_EVT_UNBLOCK 4
#define MSM_MERCURY_HW_CMD_TYPE_READ 0
#define MSM_MERCURY_HW_CMD_TYPE_WRITE 1
#define MSM_MERCURY_HW_CMD_TYPE_WRITE_OR 2
#define MSM_MERCURY_HW_CMD_TYPE_UWAIT 3
#define MSM_MERCURY_HW_CMD_TYPE_MWAIT 4
#define MSM_MERCURY_HW_CMD_TYPE_MDELAY 5
#define MSM_MERCURY_HW_CMD_TYPE_UDELAY 6
#define MSM_MCR_IOCTL_MAGIC 'g'
#define MSM_MCR_IOCTL_GET_HW_VERSION _IOW(MSM_MCR_IOCTL_MAGIC, 1, struct msm_mercury_hw_cmd *)
#define MSM_MCR_IOCTL_RESET _IOW(MSM_MCR_IOCTL_MAGIC, 2, struct msm_mercury_ctrl_cmd *)
#define MSM_MCR_IOCTL_STOP _IOW(MSM_MCR_IOCTL_MAGIC, 3, struct msm_mercury_hw_cmds *)
#define MSM_MCR_IOCTL_START _IOW(MSM_MCR_IOCTL_MAGIC, 4, struct msm_mercury_hw_cmds *)
#define MSM_MCR_IOCTL_INPUT_BUF_CFG _IOW(MSM_MCR_IOCTL_MAGIC, 5, struct msm_mercury_buf *)
#define MSM_MCR_IOCTL_INPUT_GET _IOW(MSM_MCR_IOCTL_MAGIC, 6, struct msm_mercury_buf *)
#define MSM_MCR_IOCTL_INPUT_GET_UNBLOCK _IOW(MSM_MCR_IOCTL_MAGIC, 7, int)
#define MSM_MCR_IOCTL_OUTPUT_BUF_CFG _IOW(MSM_MCR_IOCTL_MAGIC, 8, struct msm_mercury_buf *)
#define MSM_MCR_IOCTL_OUTPUT_GET _IOW(MSM_MCR_IOCTL_MAGIC, 9, struct msm_mercury_buf *)
#define MSM_MCR_IOCTL_OUTPUT_GET_UNBLOCK _IOW(MSM_MCR_IOCTL_MAGIC, 10, int)
#define MSM_MCR_IOCTL_EVT_GET _IOW(MSM_MCR_IOCTL_MAGIC, 11, struct msm_mercury_ctrl_cmd *)
#define MSM_MCR_IOCTL_EVT_GET_UNBLOCK _IOW(MSM_MCR_IOCTL_MAGIC, 12, int)
#define MSM_MCR_IOCTL_HW_CMD _IOW(MSM_MCR_IOCTL_MAGIC, 13, struct msm_mercury_hw_cmd *)
#define MSM_MCR_IOCTL_HW_CMDS _IOW(MSM_MCR_IOCTL_MAGIC, 14, struct msm_mercury_hw_cmds *)
#define MSM_MCR_IOCTL_TEST_DUMP_REGION _IOW(MSM_MCR_IOCTL_MAGIC, 15, unsigned long)
struct msm_mercury_ctrl_cmd {
uint32_t type;
uint32_t len;
void * value;
};
struct msm_mercury_buf {
uint32_t type;
int fd;
void * vaddr;
uint32_t y_off;
uint32_t y_len;
uint32_t framedone_len;
uint32_t cbcr_off;
uint32_t cbcr_len;
uint32_t num_of_mcu_rows;
uint32_t offset;
};
struct msm_mercury_hw_cmd {
uint32_t type : 4;
uint32_t n : 12;
uint32_t offset : 16;
uint32_t mask;
union {
uint32_t data;
uint32_t * pdata;
};
};
struct msm_mercury_hw_cmds {
uint32_t m;
struct msm_mercury_hw_cmd hw_cmd[1];
};
#endif

103
sdm710/kernel-headers/media/msm_sde_rotator.h
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@@ -1,103 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MSM_SDE_ROTATOR_H__
#define __UAPI_MSM_SDE_ROTATOR_H__
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
#define SDE_PIX_FMT_XRGB_8888 V4L2_PIX_FMT_XBGR32
#define SDE_PIX_FMT_ARGB_8888 V4L2_PIX_FMT_ABGR32
#define SDE_PIX_FMT_ABGR_8888 V4L2_PIX_FMT_SDE_ABGR_8888
#define SDE_PIX_FMT_RGBA_8888 V4L2_PIX_FMT_SDE_RGBA_8888
#define SDE_PIX_FMT_BGRA_8888 V4L2_PIX_FMT_ARGB32
#define SDE_PIX_FMT_RGBX_8888 V4L2_PIX_FMT_SDE_RGBX_8888
#define SDE_PIX_FMT_BGRX_8888 V4L2_PIX_FMT_XRGB32
#define SDE_PIX_FMT_XBGR_8888 V4L2_PIX_FMT_SDE_XBGR_8888
#define SDE_PIX_FMT_RGBA_5551 V4L2_PIX_FMT_SDE_RGBA_5551
#define SDE_PIX_FMT_ARGB_1555 V4L2_PIX_FMT_ARGB555
#define SDE_PIX_FMT_ABGR_1555 V4L2_PIX_FMT_SDE_ABGR_1555
#define SDE_PIX_FMT_BGRA_5551 V4L2_PIX_FMT_SDE_BGRA_5551
#define SDE_PIX_FMT_BGRX_5551 V4L2_PIX_FMT_SDE_BGRX_5551
#define SDE_PIX_FMT_RGBX_5551 V4L2_PIX_FMT_SDE_RGBX_5551
#define SDE_PIX_FMT_XBGR_1555 V4L2_PIX_FMT_SDE_XBGR_1555
#define SDE_PIX_FMT_XRGB_1555 V4L2_PIX_FMT_XRGB555
#define SDE_PIX_FMT_ARGB_4444 V4L2_PIX_FMT_ARGB444
#define SDE_PIX_FMT_RGBA_4444 V4L2_PIX_FMT_SDE_RGBA_4444
#define SDE_PIX_FMT_BGRA_4444 V4L2_PIX_FMT_SDE_BGRA_4444
#define SDE_PIX_FMT_ABGR_4444 V4L2_PIX_FMT_SDE_ABGR_4444
#define SDE_PIX_FMT_RGBX_4444 V4L2_PIX_FMT_SDE_RGBX_4444
#define SDE_PIX_FMT_XRGB_4444 V4L2_PIX_FMT_XRGB444
#define SDE_PIX_FMT_BGRX_4444 V4L2_PIX_FMT_SDE_BGRX_4444
#define SDE_PIX_FMT_XBGR_4444 V4L2_PIX_FMT_SDE_XBGR_4444
#define SDE_PIX_FMT_RGB_888 V4L2_PIX_FMT_RGB24
#define SDE_PIX_FMT_BGR_888 V4L2_PIX_FMT_BGR24
#define SDE_PIX_FMT_RGB_565 V4L2_PIX_FMT_RGB565
#define SDE_PIX_FMT_BGR_565 V4L2_PIX_FMT_SDE_BGR_565
#define SDE_PIX_FMT_Y_CB_CR_H2V2 V4L2_PIX_FMT_YUV420
#define SDE_PIX_FMT_Y_CR_CB_H2V2 V4L2_PIX_FMT_YVU420
#define SDE_PIX_FMT_Y_CR_CB_GH2V2 V4L2_PIX_FMT_SDE_Y_CR_CB_GH2V2
#define SDE_PIX_FMT_Y_CBCR_H2V2 V4L2_PIX_FMT_NV12
#define SDE_PIX_FMT_Y_CRCB_H2V2 V4L2_PIX_FMT_NV21
#define SDE_PIX_FMT_Y_CBCR_H1V2 V4L2_PIX_FMT_SDE_Y_CBCR_H1V2
#define SDE_PIX_FMT_Y_CRCB_H1V2 V4L2_PIX_FMT_SDE_Y_CRCB_H1V2
#define SDE_PIX_FMT_Y_CBCR_H2V1 V4L2_PIX_FMT_NV16
#define SDE_PIX_FMT_Y_CRCB_H2V1 V4L2_PIX_FMT_NV61
#define SDE_PIX_FMT_YCBYCR_H2V1 V4L2_PIX_FMT_YUYV
#define SDE_PIX_FMT_Y_CBCR_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_VENUS
#define SDE_PIX_FMT_Y_CRCB_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CRCB_H2V2_VENUS
#define SDE_PIX_FMT_RGBA_8888_UBWC V4L2_PIX_FMT_RGBA8888_UBWC
#define SDE_PIX_FMT_RGBX_8888_UBWC V4L2_PIX_FMT_SDE_RGBX_8888_UBWC
#define SDE_PIX_FMT_RGB_565_UBWC V4L2_PIX_FMT_SDE_RGB_565_UBWC
#define SDE_PIX_FMT_Y_CBCR_H2V2_UBWC V4L2_PIX_FMT_NV12_UBWC
#define SDE_PIX_FMT_RGBA_1010102 V4L2_PIX_FMT_SDE_RGBA_1010102
#define SDE_PIX_FMT_RGBX_1010102 V4L2_PIX_FMT_SDE_RGBX_1010102
#define SDE_PIX_FMT_ARGB_2101010 V4L2_PIX_FMT_SDE_ARGB_2101010
#define SDE_PIX_FMT_XRGB_2101010 V4L2_PIX_FMT_SDE_XRGB_2101010
#define SDE_PIX_FMT_BGRA_1010102 V4L2_PIX_FMT_SDE_BGRA_1010102
#define SDE_PIX_FMT_BGRX_1010102 V4L2_PIX_FMT_SDE_BGRX_1010102
#define SDE_PIX_FMT_ABGR_2101010 V4L2_PIX_FMT_SDE_ABGR_2101010
#define SDE_PIX_FMT_XBGR_2101010 V4L2_PIX_FMT_SDE_XBGR_2101010
#define SDE_PIX_FMT_RGBA_1010102_UBWC V4L2_PIX_FMT_SDE_RGBA_1010102_UBWC
#define SDE_PIX_FMT_RGBX_1010102_UBWC V4L2_PIX_FMT_SDE_RGBX_1010102_UBWC
#define SDE_PIX_FMT_Y_CBCR_H2V2_P010 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010
#define SDE_PIX_FMT_Y_CBCR_H2V2_P010_VENUS V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010_VENUS
#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_TP10
#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC V4L2_PIX_FMT_NV12_TP10_UBWC
#define SDE_PIX_FMT_Y_CBCR_H2V2_P010_UBWC V4L2_PIX_FMT_NV12_P010_UBWC
struct msm_sde_rotator_fence {
__u32 index;
__u32 type;
__s32 fd;
__u32 reserved[5];
};
struct msm_sde_rotator_comp_ratio {
__u32 index;
__u32 type;
__u32 numer;
__u32 denom;
__u32 reserved[4];
};
#define VIDIOC_G_SDE_ROTATOR_FENCE _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_sde_rotator_fence)
#define VIDIOC_S_SDE_ROTATOR_FENCE _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_sde_rotator_fence)
#define VIDIOC_G_SDE_ROTATOR_COMP_RATIO _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_sde_rotator_comp_ratio)
#define VIDIOC_S_SDE_ROTATOR_COMP_RATIO _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_sde_rotator_comp_ratio)
#define V4L2_CID_SDE_ROTATOR_SECURE (V4L2_CID_USER_BASE + 0x1000)
#define V4L2_CID_SDE_ROTATOR_SECURE_CAMERA (V4L2_CID_USER_BASE + 0x2000)
#endif

384
sdm710/kernel-headers/media/msm_vidc.h
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@@ -1,384 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __MSM_VIDC_H__
#define __MSM_VIDC_H__
#include <linux/types.h>
#define MSM_VIDC_HAL_INTERLACE_COLOR_FORMAT_NV12 0x2
#define MSM_VIDC_HAL_INTERLACE_COLOR_FORMAT_NV12_UBWC 0x8002
#define MSM_VIDC_4x_1 0x1
#define MSM_VIDC_EXTRADATA_FRAME_QP_ADV 0x1
struct msm_vidc_extradata_header {
unsigned int size;
unsigned int : 32;
unsigned int : 32;
unsigned int type;
unsigned int data_size;
unsigned char data[1];
};
struct msm_vidc_interlace_payload {
unsigned int format;
unsigned int color_format;
};
struct msm_vidc_framerate_payload {
unsigned int frame_rate;
};
struct msm_vidc_ts_payload {
unsigned int timestamp_lo;
unsigned int timestamp_hi;
};
struct msm_vidc_concealmb_payload {
unsigned int num_mbs;
};
struct msm_vidc_recoverysei_payload {
unsigned int flags;
};
struct msm_vidc_aspect_ratio_payload {
unsigned int size;
unsigned int version;
unsigned int port_index;
unsigned int aspect_width;
unsigned int aspect_height;
};
struct msm_vidc_mpeg2_seqdisp_payload {
unsigned int video_format;
unsigned int color_descp;
unsigned int color_primaries;
unsigned int transfer_char;
unsigned int matrix_coeffs;
unsigned int disp_width;
unsigned int disp_height;
};
struct msm_vidc_vc1_seqdisp_payload {
unsigned int prog_seg_format;
unsigned int uv_sampl_fmt;
unsigned int color_format;
unsigned int color_primaries;
unsigned int transfer_char;
unsigned int matrix_coeffs;
unsigned int aspect_ratio;
unsigned int aspect_horiz;
unsigned int aspect_vert;
};
struct msm_vidc_input_crop_payload {
unsigned int size;
unsigned int version;
unsigned int port_index;
unsigned int left;
unsigned int top;
unsigned int width;
unsigned int height;
};
struct msm_vidc_misr_info {
unsigned int misr_dpb_luma;
unsigned int misr_dpb_chroma;
unsigned int misr_opb_luma;
unsigned int misr_opb_chroma;
};
struct msm_vidc_output_crop_payload {
unsigned int size;
unsigned int version;
unsigned int port_index;
unsigned int left;
unsigned int top;
unsigned int display_width;
unsigned int display_height;
unsigned int width;
unsigned int height;
unsigned int frame_num;
unsigned int bit_depth_y;
unsigned int bit_depth_c;
struct msm_vidc_misr_info misr_info[2];
};
struct msm_vidc_digital_zoom_payload {
unsigned int size;
unsigned int version;
unsigned int port_index;
unsigned int zoom_width;
unsigned int zoom_height;
};
struct msm_vidc_extradata_index {
unsigned int type;
union {
struct msm_vidc_input_crop_payload input_crop;
struct msm_vidc_digital_zoom_payload digital_zoom;
struct msm_vidc_aspect_ratio_payload aspect_ratio;
};
};
struct msm_vidc_panscan_window {
unsigned int panscan_height_offset;
unsigned int panscan_width_offset;
unsigned int panscan_window_width;
unsigned int panscan_window_height;
};
struct msm_vidc_panscan_window_payload {
unsigned int num_panscan_windows;
struct msm_vidc_panscan_window wnd[1];
};
struct msm_vidc_stream_userdata_payload {
unsigned int type;
unsigned int data[1];
};
struct msm_vidc_frame_qp_payload {
unsigned int frame_qp;
unsigned int qp_sum;
unsigned int skip_qp_sum;
unsigned int skip_num_blocks;
unsigned int total_num_blocks;
};
struct msm_vidc_frame_bits_info_payload {
unsigned int frame_bits;
unsigned int header_bits;
};
struct msm_vidc_s3d_frame_packing_payload {
unsigned int fpa_id;
unsigned int cancel_flag;
unsigned int fpa_type;
unsigned int quin_cunx_flag;
unsigned int content_interprtation_type;
unsigned int spatial_flipping_flag;
unsigned int frame0_flipped_flag;
unsigned int field_views_flag;
unsigned int current_frame_is_frame0_flag;
unsigned int frame0_self_contained_flag;
unsigned int frame1_self_contained_flag;
unsigned int frame0_graid_pos_x;
unsigned int frame0_graid_pos_y;
unsigned int frame1_graid_pos_x;
unsigned int frame1_graid_pos_y;
unsigned int fpa_reserved_byte;
unsigned int fpa_repetition_period;
unsigned int fpa_extension_flag;
};
struct msm_vidc_vqzip_sei_payload {
unsigned int size;
unsigned int data[1];
};
struct msm_vidc_ubwc_cr_stats_info {
unsigned int stats_tile_32;
unsigned int stats_tile_64;
unsigned int stats_tile_96;
unsigned int stats_tile_128;
unsigned int stats_tile_160;
unsigned int stats_tile_192;
unsigned int stats_tile_256;
};
struct msm_vidc_yuv_stats_payload {
unsigned int frame_qp;
unsigned int texture;
unsigned int luma_in_q16;
unsigned int frame_difference;
};
struct msm_vidc_vpx_colorspace_payload {
unsigned int color_space;
unsigned int yuv_range_flag;
unsigned int sumsampling_x;
unsigned int sumsampling_y;
};
struct msm_vidc_roi_qp_payload {
int upper_qp_offset;
int lower_qp_offset;
unsigned int b_roi_info;
int mbi_info_size;
unsigned int data[1];
};
struct msm_vidc_mastering_display_colour_sei_payload {
unsigned int nDisplayPrimariesX[3];
unsigned int nDisplayPrimariesY[3];
unsigned int nWhitePointX;
unsigned int nWhitePointY;
unsigned int nMaxDisplayMasteringLuminance;
unsigned int nMinDisplayMasteringLuminance;
};
struct msm_vidc_content_light_level_sei_payload {
unsigned int nMaxContentLight;
unsigned int nMaxPicAverageLight;
};
struct msm_vidc_vui_display_info_payload {
unsigned int video_signal_present_flag;
unsigned int video_format;
unsigned int bit_depth_y;
unsigned int bit_depth_c;
unsigned int video_full_range_flag;
unsigned int color_description_present_flag;
unsigned int color_primaries;
unsigned int transfer_characteristics;
unsigned int matrix_coefficients;
unsigned int chroma_location_info_present_flag;
unsigned int chroma_format_idc;
unsigned int separate_color_plane_flag;
unsigned int chroma_sample_loc_type_top_field;
unsigned int chroma_sample_loc_type_bottom_field;
};
enum msm_vidc_extradata_type {
MSM_VIDC_EXTRADATA_NONE = 0x00000000,
MSM_VIDC_EXTRADATA_MB_QUANTIZATION = 0x00000001,
MSM_VIDC_EXTRADATA_INTERLACE_VIDEO = 0x00000002,
MSM_VIDC_EXTRADATA_VC1_FRAMEDISP = 0x00000003,
MSM_VIDC_EXTRADATA_VC1_SEQDISP = 0x00000004,
MSM_VIDC_EXTRADATA_TIMESTAMP = 0x00000005,
MSM_VIDC_EXTRADATA_S3D_FRAME_PACKING = 0x00000006,
MSM_VIDC_EXTRADATA_FRAME_RATE = 0x00000007,
MSM_VIDC_EXTRADATA_PANSCAN_WINDOW = 0x00000008,
MSM_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 0x00000009,
MSM_VIDC_EXTRADATA_MPEG2_SEQDISP = 0x0000000D,
MSM_VIDC_EXTRADATA_STREAM_USERDATA = 0x0000000E,
MSM_VIDC_EXTRADATA_FRAME_QP = 0x0000000F,
MSM_VIDC_EXTRADATA_FRAME_BITS_INFO = 0x00000010,
MSM_VIDC_EXTRADATA_VQZIP_SEI = 0x00000011,
MSM_VIDC_EXTRADATA_ROI_QP = 0x00000013,
#define MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO
MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO = 0x00000014,
#define MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI
MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI = 0x00000015,
#define MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI
MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI = 0x00000016,
#define MSM_VIDC_EXTRADATA_PQ_INFO MSM_VIDC_EXTRADATA_PQ_INFO
MSM_VIDC_EXTRADATA_PQ_INFO = 0x00000017,
#define MSM_VIDC_EXTRADATA_COLOUR_REMAPPING_INFO_SEI MSM_VIDC_EXTRADATA_COLOUR_REMAPPING_INFO_SEI
MSM_VIDC_EXTRADATA_COLOUR_REMAPPING_INFO_SEI = 0x00000018,
#define MSM_VIDC_EXTRADATA_UBWC_CR_STAT_INFO MSM_VIDC_EXTRADATA_UBWC_CR_STAT_INFO
MSM_VIDC_EXTRADATA_UBWC_CR_STAT_INFO = 0x00000019,
MSM_VIDC_EXTRADATA_INPUT_CROP = 0x0700000E,
#define MSM_VIDC_EXTRADATA_OUTPUT_CROP MSM_VIDC_EXTRADATA_OUTPUT_CROP
MSM_VIDC_EXTRADATA_OUTPUT_CROP = 0x0700000F,
MSM_VIDC_EXTRADATA_DIGITAL_ZOOM = 0x07000010,
MSM_VIDC_EXTRADATA_MULTISLICE_INFO = 0x7F100000,
MSM_VIDC_EXTRADATA_NUM_CONCEALED_MB = 0x7F100001,
MSM_VIDC_EXTRADATA_INDEX = 0x7F100002,
MSM_VIDC_EXTRADATA_ASPECT_RATIO = 0x7F100003,
MSM_VIDC_EXTRADATA_METADATA_LTR = 0x7F100004,
MSM_VIDC_EXTRADATA_METADATA_FILLER = 0x7FE00002,
MSM_VIDC_EXTRADATA_METADATA_MBI = 0x7F100005,
#define MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO
MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO = 0x7F100006,
MSM_VIDC_EXTRADATA_YUVSTATS_INFO = 0x7F100007,
};
enum msm_vidc_interlace_type {
MSM_VIDC_INTERLACE_FRAME_PROGRESSIVE = 0x01,
MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST = 0x02,
MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST = 0x04,
MSM_VIDC_INTERLACE_FRAME_TOPFIELDFIRST = 0x08,
MSM_VIDC_INTERLACE_FRAME_BOTTOMFIELDFIRST = 0x10,
#define MSM_VIDC_INTERLACE_FRAME_MBAFF MSM_VIDC_INTERLACE_FRAME_MBAFF
MSM_VIDC_INTERLACE_FRAME_MBAFF = 0x20,
};
#define MSM_VIDC_FRAMEPACK_CHECKERBOARD 0x00
#define MSM_VIDC_FRAMEPACK_COLUMN_INTERLEAVE 0x01
#define MSM_VIDC_FRAMEPACK_ROW_INTERLEAVE 0x02
#define MSM_VIDC_FRAMEPACK_SIDE_BY_SIDE 0x03
#define MSM_VIDC_FRAMEPACK_TOP_BOTTOM 0x04
#define MSM_VIDC_FRAMEPACK_TEMPORAL_INTERLEAVE 0x05
enum msm_vidc_recovery_sei {
MSM_VIDC_FRAME_RECONSTRUCTION_INCORRECT = 0x0,
MSM_VIDC_FRAME_RECONSTRUCTION_CORRECT = 0x01,
MSM_VIDC_FRAME_RECONSTRUCTION_APPROXIMATELY_CORRECT = 0x02,
};
enum msm_vidc_userdata_type {
MSM_VIDC_USERDATA_TYPE_FRAME = 0x1,
MSM_VIDC_USERDATA_TYPE_TOP_FIELD = 0x2,
MSM_VIDC_USERDATA_TYPE_BOTTOM_FIELD = 0x3,
};
enum msm_vidc_h264_color_primaries_values {
MSM_VIDC_RESERVED_1 = 0,
MSM_VIDC_BT709_5 = 1,
MSM_VIDC_UNSPECIFIED = 2,
MSM_VIDC_RESERVED_2 = 3,
MSM_VIDC_BT470_6_M = 4,
MSM_VIDC_BT601_6_625 = 5,
MSM_VIDC_BT470_6_BG = MSM_VIDC_BT601_6_625,
MSM_VIDC_BT601_6_525 = 6,
MSM_VIDC_SMPTE_240M = 7,
MSM_VIDC_GENERIC_FILM = 8,
MSM_VIDC_BT2020 = 9,
};
enum msm_vidc_vp9_color_primaries_values {
MSM_VIDC_CS_UNKNOWN,
MSM_VIDC_CS_BT_601,
MSM_VIDC_CS_BT_709,
MSM_VIDC_CS_SMPTE_170,
MSM_VIDC_CS_SMPTE_240,
MSM_VIDC_CS_BT_2020,
MSM_VIDC_CS_RESERVED,
MSM_VIDC_CS_RGB,
};
enum msm_vidc_h264_matrix_coeff_values {
MSM_VIDC_MATRIX_RGB = 0,
MSM_VIDC_MATRIX_BT_709_5 = 1,
MSM_VIDC_MATRIX_UNSPECIFIED = 2,
MSM_VIDC_MATRIX_RESERVED = 3,
MSM_VIDC_MATRIX_FCC_47 = 4,
MSM_VIDC_MATRIX_601_6_625 = 5,
MSM_VIDC_MATRIX_BT470_BG = MSM_VIDC_MATRIX_601_6_625,
MSM_VIDC_MATRIX_601_6_525 = 6,
MSM_VIDC_MATRIX_SMPTE_170M = MSM_VIDC_MATRIX_601_6_525,
MSM_VIDC_MATRIX_SMPTE_240M = 7,
MSM_VIDC_MATRIX_Y_CG_CO = 8,
MSM_VIDC_MATRIX_BT_2020 = 9,
MSM_VIDC_MATRIX_BT_2020_CONST = 10,
};
enum msm_vidc_h264_transfer_chars_values {
MSM_VIDC_TRANSFER_RESERVED_1 = 0,
MSM_VIDC_TRANSFER_BT709_5 = 1,
MSM_VIDC_TRANSFER_UNSPECIFIED = 2,
MSM_VIDC_TRANSFER_RESERVED_2 = 3,
MSM_VIDC_TRANSFER_BT_470_6_M = 4,
MSM_VIDC_TRANSFER_BT_470_6_BG = 5,
MSM_VIDC_TRANSFER_601_6_625 = 6,
MSM_VIDC_TRANSFER_601_6_525 = MSM_VIDC_TRANSFER_601_6_625,
MSM_VIDC_TRANSFER_SMPTE_240M = 7,
MSM_VIDC_TRANSFER_LINEAR = 8,
MSM_VIDC_TRANSFER_LOG_100_1 = 9,
MSM_VIDC_TRANSFER_LOG_100_SQRT10_1 = 10,
MSM_VIDC_TRANSFER_IEC_61966 = 11,
MSM_VIDC_TRANSFER_BT_1361 = 12,
MSM_VIDC_TRANSFER_SRGB = 13,
MSM_VIDC_TRANSFER_BT_2020_10 = 14,
MSM_VIDC_TRANSFER_BT_2020_12 = 15,
#define MSM_VIDC_TRANSFER_SMPTE_ST2084 MSM_VIDC_TRANSFER_SMPTE_ST2084
MSM_VIDC_TRANSFER_SMPTE_ST2084 = 16,
#define MSM_VIDC_TRANSFER_SMPTE_ST428_1 MSM_VIDC_TRANSFER_SMPTE_ST428_1
MSM_VIDC_TRANSFER_SMPTE_ST428_1 = 17,
#define MSM_VIDC_TRANSFER_HLG MSM_VIDC_TRANSFER_HLG
MSM_VIDC_TRANSFER_HLG = 18,
};
enum msm_vidc_pixel_depth {
MSM_VIDC_BIT_DEPTH_8,
MSM_VIDC_BIT_DEPTH_10,
MSM_VIDC_BIT_DEPTH_UNSUPPORTED = 0XFFFFFFFF,
};
enum msm_vidc_video_format {
MSM_VIDC_COMPONENT,
MSM_VIDC_PAL,
MSM_VIDC_NTSC,
MSM_VIDC_SECAM,
MSM_VIDC_MAC,
MSM_VIDC_UNSPECIFIED_FORMAT,
MSM_VIDC_RESERVED_1_FORMAT,
MSM_VIDC_RESERVED_2_FORMAT,
};
enum msm_vidc_color_desc_flag {
MSM_VIDC_COLOR_DESC_NOT_PRESENT,
MSM_VIDC_COLOR_DESC_PRESENT,
};
#define MSM_VIDC_PIC_STRUCT_MAYBE_INTERLACED 0x0
#define MSM_VIDC_PIC_STRUCT_PROGRESSIVE 0x1
#define MSM_VIDC_PIC_STRUCT_UNKNOWN 0XFFFFFFFF
#define MSM_VIDC_ALL_LAYER_ID 0xFF
#endif

184
sdm710/kernel-headers/media/msm_vpu.h
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@@ -1,184 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _H_MSM_VPU_H_
#define _H_MSM_VPU_H_
#include <linux/videodev2.h>
#define V4L2_BUF_FLAG_CDS_ENABLE 0x10000000
#define V4L2_PLANE_MEM_OFFSET 0
enum vpu_colorspace {
VPU_CS_MIN = 0,
VPU_CS_RGB_FULL = 1,
VPU_CS_RGB_LIMITED = 2,
VPU_CS_REC601_FULL = 3,
VPU_CS_REC601_LIMITED = 4,
VPU_CS_REC709_FULL = 5,
VPU_CS_REC709_LIMITED = 6,
VPU_CS_SMPTE240_FULL = 7,
VPU_CS_SMPTE240_LIMITED = 8,
VPU_CS_MAX = 9,
};
#define VPU_FMT_EXT_FLAG_BT 1
#define VPU_FMT_EXT_FLAG_TB 2
#define VPU_FMT_EXT_FLAG_3D 4
struct v4l2_format_vpu_extension {
__u8 flag;
__u8 gap_in_lines;
};
#define V4L2_PIX_FMT_XRGB2 v4l2_fourcc('X', 'R', 'G', '2')
#define V4L2_PIX_FMT_XBGR2 v4l2_fourcc('X', 'B', 'G', '2')
#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'L')
#define V4L2_PIX_FMT_YUV8 v4l2_fourcc('Y', 'U', 'V', '8')
#define V4L2_PIX_FMT_YUV10 v4l2_fourcc('Y', 'U', 'V', 'L')
#define V4L2_PIX_FMT_YUYV10BWC v4l2_fourcc('Y', 'B', 'W', 'C')
#define VPU_INPUT_TYPE_HOST 0
#define VPU_INPUT_TYPE_VCAP 1
#define VPU_OUTPUT_TYPE_HOST 0
#define VPU_OUTPUT_TYPE_DISPLAY 1
#define VPU_PIPE_VCAP0 (1 << 16)
#define VPU_PIPE_VCAP1 (1 << 17)
#define VPU_PIPE_DISPLAY0 (1 << 18)
#define VPU_PIPE_DISPLAY1 (1 << 19)
#define VPU_PIPE_DISPLAY2 (1 << 20)
#define VPU_PIPE_DISPLAY3 (1 << 21)
#define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000)
enum VPU_PRIVATE_EVENT {
VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE,
VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1,
VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2,
VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3,
VPU_EVENT_SESSION_CREATED = VPU_EVENT_START + 4,
VPU_EVENT_SESSION_FREED = VPU_EVENT_START + 5,
VPU_EVENT_SESSION_CLIENT_EXITED = VPU_EVENT_START + 6,
VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11,
VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12,
VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13,
VPU_EVENT_END
};
struct vpu_ctrl_standard {
__u32 enable;
__s32 value;
};
struct vpu_ctrl_auto_manual {
__u32 enable;
__u32 auto_mode;
__s32 value;
};
struct vpu_ctrl_range_mapping {
__u32 enable;
__u32 y_range;
__u32 uv_range;
};
#define VPU_ACTIVE_REGION_N_EXCLUSIONS 1
struct vpu_ctrl_active_region_param {
__u32 enable;
__u32 num_exclusions;
struct v4l2_rect detection_region;
struct v4l2_rect excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS];
};
struct vpu_ctrl_deinterlacing_mode {
__u32 field_polarity;
__u32 mvp_mode;
};
struct vpu_ctrl_hqv {
__u32 enable;
__u32 sharpen_strength;
__u32 auto_nr_strength;
};
struct vpu_info_frame_timestamp {
__u32 pts_low;
__u32 pts_high;
__u32 qtime_low;
__u32 qtime_high;
};
struct vpu_control {
__u32 control_id;
union control_data {
__s32 value;
struct vpu_ctrl_standard standard;
struct vpu_ctrl_auto_manual auto_manual;
struct vpu_ctrl_range_mapping range_mapping;
struct vpu_ctrl_active_region_param active_region_param;
struct v4l2_rect active_region_result;
struct vpu_ctrl_deinterlacing_mode deinterlacing_mode;
struct vpu_ctrl_hqv hqv;
struct vpu_info_frame_timestamp timestamp;
__u8 reserved[124];
} data;
};
#define VPU_CTRL_ID_MIN 0
#define VPU_CTRL_NOISE_REDUCTION 1
#define VPU_CTRL_IMAGE_ENHANCEMENT 2
#define VPU_CTRL_ANAMORPHIC_SCALING 3
#define VPU_CTRL_DIRECTIONAL_INTERPOLATION 4
#define VPU_CTRL_BACKGROUND_COLOR 5
#define VPU_CTRL_RANGE_MAPPING 6
#define VPU_CTRL_DEINTERLACING_MODE 7
#define VPU_CTRL_ACTIVE_REGION_PARAM 8
#define VPU_CTRL_ACTIVE_REGION_RESULT 9
#define VPU_CTRL_PRIORITY 10
#define VPU_CTRL_CONTENT_PROTECTION 11
#define VPU_CTRL_DISPLAY_REFRESH_RATE 12
#define VPU_CTRL_HQV 20
#define VPU_CTRL_HQV_SHARPEN 21
#define VPU_CTRL_HQV_AUTONR 22
#define VPU_CTRL_ACE 23
#define VPU_CTRL_ACE_BRIGHTNESS 24
#define VPU_CTRL_ACE_CONTRAST 25
#define VPU_CTRL_2D3D 26
#define VPU_CTRL_2D3D_DEPTH 27
#define VPU_CTRL_FRC 28
#define VPU_CTRL_FRC_MOTION_SMOOTHNESS 29
#define VPU_CTRL_FRC_MOTION_CLEAR 30
#define VPU_INFO_TIMESTAMP 35
#define VPU_CTRL_TIMESTAMP_INFO_MODE 36
#define VPU_INFO_STATISTICS 37
#define VPU_CTRL_LATENCY 38
#define VPU_CTRL_LATENCY_MODE 39
#define VPU_CTRL_ID_MAX 40
#define VPU_MAX_EXT_DATA_SIZE 720
struct vpu_control_extended {
__u32 type;
__u32 data_len;
void * data_ptr;
__u32 buf_size;
void * buf_ptr;
};
struct vpu_control_port {
__u32 control_id;
__u32 port;
union control_port_data {
__u32 framerate;
} data;
};
#define VPU_CTRL_FPS 1000
#define VPU_ATTACH_TO_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 1), int)
#define VPU_QUERY_SESSIONS _IOR('V', (BASE_VIDIOC_PRIVATE + 0), int)
#define VPU_CREATE_SESSION _IOR('V', (BASE_VIDIOC_PRIVATE + 2), int)
#define VPU_JOIN_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 3), int)
#define VPU_CREATE_OUTPUT2 _IO('V', (BASE_VIDIOC_PRIVATE + 5))
#define VPU_COMMIT_CONFIGURATION _IO('V', (BASE_VIDIOC_PRIVATE + 10))
#define VPU_FLUSH_BUFS _IOW('V', (BASE_VIDIOC_PRIVATE + 15), enum v4l2_buf_type)
#define VPU_G_CONTROL _IOWR('V', (BASE_VIDIOC_PRIVATE + 20), struct vpu_control)
#define VPU_S_CONTROL _IOW('V', (BASE_VIDIOC_PRIVATE + 21), struct vpu_control)
#define VPU_G_CONTROL_EXTENDED _IOWR('V', (BASE_VIDIOC_PRIVATE + 22), struct vpu_control_extended)
#define VPU_S_CONTROL_EXTENDED _IOW('V', (BASE_VIDIOC_PRIVATE + 23), struct vpu_control_extended)
#define VPU_G_CONTROL_PORT _IOWR('V', (BASE_VIDIOC_PRIVATE + 24), struct vpu_control_port)
#define VPU_S_CONTROL_PORT _IOW('V', (BASE_VIDIOC_PRIVATE + 25), struct vpu_control_port)
#endif

162
sdm710/kernel-headers/media/msmb_camera.h
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@@ -1,162 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_LINUX_MSMB_CAMERA_H
#define __UAPI_LINUX_MSMB_CAMERA_H
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
#include <linux/media.h>
#define MSM_CAM_LOGSYNC_FILE_NAME "logsync"
#define MSM_CAM_LOGSYNC_FILE_BASEDIR "camera"
#define MSM_CAM_V4L2_IOCTL_NOTIFY _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct msm_v4l2_event_data)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_META _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct msm_v4l2_event_data)
#define MSM_CAM_V4L2_IOCTL_CMD_ACK _IOW('V', BASE_VIDIOC_PRIVATE + 32, struct msm_v4l2_event_data)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR _IOW('V', BASE_VIDIOC_PRIVATE + 33, struct msm_v4l2_event_data)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG _IOW('V', BASE_VIDIOC_PRIVATE + 34, struct msm_v4l2_event_data)
#define MSM_CAM_V4L2_IOCTL_DAEMON_DISABLED _IOW('V', BASE_VIDIOC_PRIVATE + 35, struct msm_v4l2_event_data)
#define QCAMERA_VNODE_GROUP_ID MEDIA_ENT_F_IO_V4L
#define MSM_CAMERA_NAME "msm_camera"
#define MSM_CONFIGURATION_NAME "msm_config"
#define MSM_CAMERA_SUBDEV_BASE (MEDIA_ENT_F_OLD_BASE + 0xF00)
#define MSM_CAMERA_SUBDEV_CSIPHY (MSM_CAMERA_SUBDEV_BASE + 0)
#define MSM_CAMERA_SUBDEV_CSID (MSM_CAMERA_SUBDEV_BASE + 13)
#define MSM_CAMERA_SUBDEV_ISPIF (MSM_CAMERA_SUBDEV_BASE + 2)
#define MSM_CAMERA_SUBDEV_VFE (MSM_CAMERA_SUBDEV_BASE + 3)
#define MSM_CAMERA_SUBDEV_AXI (MSM_CAMERA_SUBDEV_BASE + 4)
#define MSM_CAMERA_SUBDEV_VPE (MSM_CAMERA_SUBDEV_BASE + 5)
#define MSM_CAMERA_SUBDEV_SENSOR (MSM_CAMERA_SUBDEV_BASE + 6)
#define MSM_CAMERA_SUBDEV_ACTUATOR (MSM_CAMERA_SUBDEV_BASE + 7)
#define MSM_CAMERA_SUBDEV_EEPROM (MSM_CAMERA_SUBDEV_BASE + 8)
#define MSM_CAMERA_SUBDEV_CPP (MSM_CAMERA_SUBDEV_BASE + 9)
#define MSM_CAMERA_SUBDEV_CCI (MSM_CAMERA_SUBDEV_BASE + 10)
#define MSM_CAMERA_SUBDEV_LED_FLASH (MSM_CAMERA_SUBDEV_BASE + 11)
#define MSM_CAMERA_SUBDEV_STROBE_FLASH (MSM_CAMERA_SUBDEV_BASE + 12)
#define MSM_CAMERA_SUBDEV_BUF_MNGR (MSM_CAMERA_SUBDEV_BASE + 1)
#define MSM_CAMERA_SUBDEV_SENSOR_INIT (MSM_CAMERA_SUBDEV_BASE + 14)
#define MSM_CAMERA_SUBDEV_OIS (MSM_CAMERA_SUBDEV_BASE + 15)
#define MSM_CAMERA_SUBDEV_FLASH (MSM_CAMERA_SUBDEV_BASE + 16)
#define MSM_CAMERA_SUBDEV_IR_LED (MSM_CAMERA_SUBDEV_BASE + 17)
#define MSM_CAMERA_SUBDEV_IR_CUT (MSM_CAMERA_SUBDEV_BASE + 18)
#define MSM_CAMERA_SUBDEV_EXT (MSM_CAMERA_SUBDEV_BASE + 19)
#define MSM_CAMERA_SUBDEV_TOF (MSM_CAMERA_SUBDEV_BASE + 20)
#define MSM_CAMERA_SUBDEV_LASER_LED (MSM_CAMERA_SUBDEV_BASE + 21)
#define MSM_MAX_CAMERA_SENSORS 5
#define MSM_CAMERA_MAX_STREAM_BUF 72
#define MSM_CAMERA_MAX_USER_BUFF_CNT 16
#define MSM_CAMERA_FEATURE_BASE 0x00010000
#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1)
#define MSM_CAMERA_STATUS_BASE 0x00020000
#define MSM_CAMERA_STATUS_FAIL (MSM_CAMERA_STATUS_BASE + 1)
#define MSM_CAMERA_STATUS_SUCCESS (MSM_CAMERA_STATUS_BASE + 2)
#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000)
#define MSM_CAMERA_EVENT_MIN 0
#define MSM_CAMERA_NEW_SESSION (MSM_CAMERA_EVENT_MIN + 1)
#define MSM_CAMERA_DEL_SESSION (MSM_CAMERA_EVENT_MIN + 2)
#define MSM_CAMERA_SET_PARM (MSM_CAMERA_EVENT_MIN + 3)
#define MSM_CAMERA_GET_PARM (MSM_CAMERA_EVENT_MIN + 4)
#define MSM_CAMERA_MAPPING_CFG (MSM_CAMERA_EVENT_MIN + 5)
#define MSM_CAMERA_MAPPING_SES (MSM_CAMERA_EVENT_MIN + 6)
#define MSM_CAMERA_MSM_NOTIFY (MSM_CAMERA_EVENT_MIN + 7)
#define MSM_CAMERA_EVENT_MAX (MSM_CAMERA_EVENT_MIN + 8)
#define MSM_CAMERA_PRIV_S_CROP (V4L2_CID_PRIVATE_BASE + 1)
#define MSM_CAMERA_PRIV_G_CROP (V4L2_CID_PRIVATE_BASE + 2)
#define MSM_CAMERA_PRIV_G_FMT (V4L2_CID_PRIVATE_BASE + 3)
#define MSM_CAMERA_PRIV_S_FMT (V4L2_CID_PRIVATE_BASE + 4)
#define MSM_CAMERA_PRIV_TRY_FMT (V4L2_CID_PRIVATE_BASE + 5)
#define MSM_CAMERA_PRIV_METADATA (V4L2_CID_PRIVATE_BASE + 6)
#define MSM_CAMERA_PRIV_QUERY_CAP (V4L2_CID_PRIVATE_BASE + 7)
#define MSM_CAMERA_PRIV_STREAM_ON (V4L2_CID_PRIVATE_BASE + 8)
#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9)
#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10)
#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11)
#define MSM_CAMERA_PRIV_SHUTDOWN (V4L2_CID_PRIVATE_BASE + 12)
#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC (V4L2_CID_PRIVATE_BASE + 13)
#define MSM_CAMERA_PRIV_G_SESSION_ID (V4L2_CID_PRIVATE_BASE + 14)
#define MSM_CAMERA_PRIV_CMD_MAX 20
#define MSM_CAMERA_CMD_SUCCESS 0x00000001
#define MSM_CAMERA_BUF_MAP_SUCCESS 0x00000002
#define MSM_CAMERA_ERR_EVT_BASE 0x00010000
#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1)
#define MSM_CAMERA_ERR_MAPPING (MSM_CAMERA_ERR_EVT_BASE + 2)
#define MSM_CAMERA_ERR_DEVICE_BUSY (MSM_CAMERA_ERR_EVT_BASE + 3)
struct msm_v4l2_event_data {
unsigned int command;
unsigned int status;
unsigned int session_id;
unsigned int stream_id;
unsigned int map_op;
unsigned int map_buf_idx;
unsigned int notify;
unsigned int arg_value;
unsigned int ret_value;
unsigned int v4l2_event_type;
unsigned int v4l2_event_id;
unsigned int handle;
unsigned int nop6;
unsigned int nop7;
unsigned int nop8;
unsigned int nop9;
};
struct msm_v4l2_format_data {
enum v4l2_buf_type type;
unsigned int width;
unsigned int height;
unsigned int pixelformat;
unsigned char num_planes;
unsigned int plane_sizes[VIDEO_MAX_PLANES];
};
#define msm_v4l2_fourcc(a,b,c,d) ((__u32) (a) | ((__u32) (b) << 8) | ((__u32) (c) << 16) | ((__u32) (d) << 24))
#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M')
#define MSM_V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E')
#define MSM_V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F')
#define MSM_V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B')
#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T')
#define MSM_V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S')
#define MSM_V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S')
#define MSM_V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G')
#define MSM_V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F')
#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T')
enum smmu_attach_mode {
NON_SECURE_MODE = 0x01,
SECURE_MODE = 0x02,
MAX_PROTECTION_MODE = 0x03,
};
struct msm_camera_smmu_attach_type {
enum smmu_attach_mode attach;
};
struct msm_camera_user_buf_cont_t {
unsigned int buf_cnt;
unsigned int buf_idx[MSM_CAMERA_MAX_USER_BUFF_CNT];
};
struct msm_camera_return_buf {
__u32 index;
__u32 reserved;
};
#define MSM_CAMERA_PRIV_IOCTL_ID_BASE 0
#define MSM_CAMERA_PRIV_IOCTL_ID_RETURN_BUF 1
struct msm_camera_private_ioctl_arg {
__u32 id;
__u32 size;
__u32 result;
__u32 reserved;
__u64 ioctl_ptr;
};
#define VIDIOC_MSM_CAMERA_PRIVATE_IOCTL_CMD _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_private_ioctl_arg)
#endif

61
sdm710/kernel-headers/media/msmb_generic_buf_mgr.h
View File

@@ -1,61 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MEDIA_MSMB_GENERIC_BUF_MGR_H__
#define __UAPI_MEDIA_MSMB_GENERIC_BUF_MGR_H__
#include <media/msmb_camera.h>
enum msm_camera_buf_mngr_cmd {
MSM_CAMERA_BUF_MNGR_CONT_MAP,
MSM_CAMERA_BUF_MNGR_CONT_UNMAP,
MSM_CAMERA_BUF_MNGR_CONT_MAX,
};
enum msm_camera_buf_mngr_buf_type {
MSM_CAMERA_BUF_MNGR_BUF_PLANAR,
MSM_CAMERA_BUF_MNGR_BUF_USER,
MSM_CAMERA_BUF_MNGR_BUF_INVALID,
};
struct msm_buf_mngr_info {
uint32_t session_id;
uint32_t stream_id;
uint32_t frame_id;
struct timeval timestamp;
uint32_t index;
uint32_t reserved;
enum msm_camera_buf_mngr_buf_type type;
struct msm_camera_user_buf_cont_t user_buf;
};
struct msm_buf_mngr_main_cont_info {
uint32_t session_id;
uint32_t stream_id;
enum msm_camera_buf_mngr_cmd cmd;
uint32_t cnt;
int32_t cont_fd;
};
#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_BASE 0
#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_GET_BUF_BY_IDX 1
#define VIDIOC_MSM_BUF_MNGR_GET_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info)
#define VIDIOC_MSM_BUF_MNGR_PUT_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info)
#define VIDIOC_MSM_BUF_MNGR_BUF_DONE _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info)
#define VIDIOC_MSM_BUF_MNGR_CONT_CMD _IOWR('V', BASE_VIDIOC_PRIVATE + 36, struct msm_buf_mngr_main_cont_info)
#define VIDIOC_MSM_BUF_MNGR_INIT _IOWR('V', BASE_VIDIOC_PRIVATE + 37, struct msm_buf_mngr_info)
#define VIDIOC_MSM_BUF_MNGR_DEINIT _IOWR('V', BASE_VIDIOC_PRIVATE + 38, struct msm_buf_mngr_info)
#define VIDIOC_MSM_BUF_MNGR_FLUSH _IOWR('V', BASE_VIDIOC_PRIVATE + 39, struct msm_buf_mngr_info)
#define VIDIOC_MSM_BUF_MNGR_IOCTL_CMD _IOWR('V', BASE_VIDIOC_PRIVATE + 40, struct msm_camera_private_ioctl_arg)
#define VIDIOC_MSM_BUF_MNGR_BUF_ERROR _IOWR('V', BASE_VIDIOC_PRIVATE + 41, struct msm_buf_mngr_info)
#endif

778
sdm710/kernel-headers/media/msmb_isp.h
View File

@@ -1,778 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MSMB_ISP__
#define __UAPI_MSMB_ISP__
#include <linux/videodev2.h>
#include <media/msmb_camera.h>
#define MAX_PLANES_PER_STREAM 3
#define MAX_NUM_STREAM 7
#define ISP_VERSION_48 48
#define ISP_VERSION_47 47
#define ISP_VERSION_46 46
#define ISP_VERSION_44 44
#define ISP_VERSION_40 40
#define ISP_VERSION_32 32
#define ISP_NATIVE_BUF_BIT (0x10000 << 0)
#define ISP0_BIT (0x10000 << 1)
#define ISP1_BIT (0x10000 << 2)
#define ISP_META_CHANNEL_BIT (0x10000 << 3)
#define ISP_SCRATCH_BUF_BIT (0x10000 << 4)
#define ISP_OFFLINE_STATS_BIT (0x10000 << 5)
#define ISP_SVHDR_IN_BIT (0x10000 << 6)
#define ISP_SVHDR_OUT_BIT (0x10000 << 7)
#define ISP_STATS_STREAM_BIT 0x80000000
#define VFE_HW_LIMIT 1
struct msm_vfe_cfg_cmd_list;
enum ISP_START_PIXEL_PATTERN {
ISP_BAYER_RGRGRG,
ISP_BAYER_GRGRGR,
ISP_BAYER_BGBGBG,
ISP_BAYER_GBGBGB,
ISP_YUV_YCbYCr,
ISP_YUV_YCrYCb,
ISP_YUV_CbYCrY,
ISP_YUV_CrYCbY,
ISP_PIX_PATTERN_MAX
};
enum msm_vfe_plane_fmt {
Y_PLANE,
CB_PLANE,
CR_PLANE,
CRCB_PLANE,
CBCR_PLANE,
VFE_PLANE_FMT_MAX
};
enum msm_vfe_input_src {
VFE_PIX_0,
VFE_RAW_0,
VFE_RAW_1,
VFE_RAW_2,
VFE_SRC_MAX,
};
enum msm_vfe_axi_stream_src {
PIX_ENCODER,
PIX_VIEWFINDER,
PIX_VIDEO,
CAMIF_RAW,
IDEAL_RAW,
RDI_INTF_0,
RDI_INTF_1,
RDI_INTF_2,
VFE_AXI_SRC_MAX
};
enum msm_vfe_frame_skip_pattern {
NO_SKIP,
EVERY_2FRAME,
EVERY_3FRAME,
EVERY_4FRAME,
EVERY_5FRAME,
EVERY_6FRAME,
EVERY_7FRAME,
EVERY_8FRAME,
EVERY_16FRAME,
EVERY_32FRAME,
SKIP_ALL,
SKIP_RANGE,
MAX_SKIP,
};
#define MSM_VFE_STREAM_STOP_PERIOD 15
enum msm_isp_stats_type {
MSM_ISP_STATS_AEC,
MSM_ISP_STATS_AF,
MSM_ISP_STATS_AWB,
MSM_ISP_STATS_RS,
MSM_ISP_STATS_CS,
MSM_ISP_STATS_IHIST,
MSM_ISP_STATS_SKIN,
MSM_ISP_STATS_BG,
MSM_ISP_STATS_BF,
MSM_ISP_STATS_BE,
MSM_ISP_STATS_BHIST,
MSM_ISP_STATS_BF_SCALE,
MSM_ISP_STATS_HDR_BE,
MSM_ISP_STATS_HDR_BHIST,
MSM_ISP_STATS_AEC_BG,
MSM_ISP_STATS_MAX
};
struct msm_isp_sw_framskip {
uint32_t stats_type_mask;
uint32_t stream_src_mask;
enum msm_vfe_frame_skip_pattern skip_mode;
uint32_t min_frame_id;
uint32_t max_frame_id;
};
enum msm_vfe_testgen_color_pattern {
COLOR_BAR_8_COLOR,
UNICOLOR_WHITE,
UNICOLOR_YELLOW,
UNICOLOR_CYAN,
UNICOLOR_GREEN,
UNICOLOR_MAGENTA,
UNICOLOR_RED,
UNICOLOR_BLUE,
UNICOLOR_BLACK,
MAX_COLOR,
};
enum msm_vfe_camif_input {
CAMIF_DISABLED,
CAMIF_PAD_REG_INPUT,
CAMIF_MIDDI_INPUT,
CAMIF_MIPI_INPUT,
};
struct msm_vfe_fetch_engine_cfg {
uint32_t input_format;
uint32_t buf_width;
uint32_t buf_height;
uint32_t fetch_width;
uint32_t fetch_height;
uint32_t x_offset;
uint32_t y_offset;
uint32_t buf_stride;
};
enum msm_vfe_camif_output_format {
CAMIF_QCOM_RAW,
CAMIF_MIPI_RAW,
CAMIF_PLAIN_8,
CAMIF_PLAIN_16,
CAMIF_MAX_FORMAT,
};
struct msm_vfe_camif_subsample_cfg {
uint32_t irq_subsample_period;
uint32_t irq_subsample_pattern;
uint32_t sof_counter_step;
uint32_t pixel_skip;
uint32_t line_skip;
uint32_t first_line;
uint32_t last_line;
uint32_t first_pixel;
uint32_t last_pixel;
enum msm_vfe_camif_output_format output_format;
};
struct msm_vfe_camif_cfg {
uint32_t lines_per_frame;
uint32_t pixels_per_line;
uint32_t first_pixel;
uint32_t last_pixel;
uint32_t first_line;
uint32_t last_line;
uint32_t epoch_line0;
uint32_t epoch_line1;
uint32_t is_split;
enum msm_vfe_camif_input camif_input;
struct msm_vfe_camif_subsample_cfg subsample_cfg;
};
struct msm_vfe_testgen_cfg {
uint32_t lines_per_frame;
uint32_t pixels_per_line;
uint32_t v_blank;
uint32_t h_blank;
enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern;
uint32_t rotate_period;
enum msm_vfe_testgen_color_pattern color_bar_pattern;
uint32_t burst_num_frame;
};
enum msm_vfe_inputmux {
CAMIF,
TESTGEN,
EXTERNAL_READ,
};
enum msm_vfe_stats_composite_group {
STATS_COMPOSITE_GRP_NONE,
STATS_COMPOSITE_GRP_1,
STATS_COMPOSITE_GRP_2,
STATS_COMPOSITE_GRP_MAX,
};
enum msm_vfe_hvx_streaming_cmd {
HVX_DISABLE,
HVX_ONE_WAY,
HVX_ROUND_TRIP
};
struct msm_vfe_pix_cfg {
struct msm_vfe_camif_cfg camif_cfg;
struct msm_vfe_testgen_cfg testgen_cfg;
struct msm_vfe_fetch_engine_cfg fetch_engine_cfg;
enum msm_vfe_inputmux input_mux;
enum ISP_START_PIXEL_PATTERN pixel_pattern;
uint32_t input_format;
enum msm_vfe_hvx_streaming_cmd hvx_cmd;
uint32_t is_split;
};
struct msm_vfe_rdi_cfg {
uint8_t cid;
uint8_t frame_based;
};
struct msm_vfe_input_cfg {
union {
struct msm_vfe_pix_cfg pix_cfg;
struct msm_vfe_rdi_cfg rdi_cfg;
} d;
enum msm_vfe_input_src input_src;
uint32_t input_pix_clk;
};
struct msm_vfe_fetch_eng_start {
uint32_t session_id;
uint32_t stream_id;
uint32_t buf_idx;
uint8_t offline_mode;
uint32_t fd;
uint32_t buf_addr;
uint32_t frame_id;
};
enum msm_vfe_fetch_eng_pass {
OFFLINE_FIRST_PASS,
OFFLINE_SECOND_PASS,
OFFLINE_MAX_PASS,
};
struct msm_vfe_fetch_eng_multi_pass_start {
uint32_t session_id;
uint32_t stream_id;
uint32_t buf_idx;
uint8_t offline_mode;
uint32_t fd;
uint32_t buf_addr;
uint32_t frame_id;
uint32_t output_buf_idx;
uint32_t input_buf_offset;
enum msm_vfe_fetch_eng_pass offline_pass;
uint32_t output_stream_id;
};
struct msm_vfe_axi_plane_cfg {
uint32_t output_width;
uint32_t output_height;
uint32_t output_stride;
uint32_t output_scan_lines;
uint32_t output_plane_format;
uint32_t plane_addr_offset;
uint8_t csid_src;
uint8_t rdi_cid;
};
enum msm_stream_rdi_input_type {
MSM_CAMERA_RDI_MIN,
MSM_CAMERA_RDI_PDAF,
MSM_CAMERA_RDI_MAX,
};
struct msm_vfe_axi_stream_request_cmd {
uint32_t session_id;
uint32_t stream_id;
uint32_t vt_enable;
uint32_t output_format;
enum msm_vfe_axi_stream_src stream_src;
struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
uint32_t burst_count;
uint32_t hfr_mode;
uint8_t frame_base;
uint32_t init_frame_drop;
enum msm_vfe_frame_skip_pattern frame_skip_pattern;
uint8_t buf_divert;
uint32_t axi_stream_handle;
uint32_t controllable_output;
uint32_t burst_len;
enum msm_stream_rdi_input_type rdi_input_type;
};
struct msm_vfe_axi_stream_release_cmd {
uint32_t stream_handle;
};
enum msm_vfe_axi_stream_cmd {
STOP_STREAM,
START_STREAM,
STOP_IMMEDIATELY,
};
struct msm_vfe_axi_stream_cfg_cmd {
uint8_t num_streams;
uint32_t stream_handle[VFE_AXI_SRC_MAX];
enum msm_vfe_axi_stream_cmd cmd;
uint8_t sync_frame_id_src;
};
enum msm_vfe_axi_stream_update_type {
ENABLE_STREAM_BUF_DIVERT,
DISABLE_STREAM_BUF_DIVERT,
UPDATE_STREAM_FRAMEDROP_PATTERN,
UPDATE_STREAM_STATS_FRAMEDROP_PATTERN,
UPDATE_STREAM_AXI_CONFIG,
UPDATE_STREAM_REQUEST_FRAMES,
UPDATE_STREAM_ADD_BUFQ,
UPDATE_STREAM_REMOVE_BUFQ,
UPDATE_STREAM_SW_FRAME_DROP,
UPDATE_STREAM_REQUEST_FRAMES_VER2,
UPDATE_STREAM_OFFLINE_AXI_CONFIG,
};
#define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2
enum msm_vfe_iommu_type {
IOMMU_ATTACH,
IOMMU_DETACH,
};
enum msm_vfe_buff_queue_id {
VFE_BUF_QUEUE_DEFAULT,
VFE_BUF_QUEUE_SHARED,
VFE_BUF_QUEUE_MAX,
};
struct msm_vfe_axi_stream_cfg_update_info {
uint32_t stream_handle;
uint32_t output_format;
uint32_t user_stream_id;
uint32_t frame_id;
enum msm_vfe_frame_skip_pattern skip_pattern;
struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
struct msm_isp_sw_framskip sw_skip_info;
};
struct msm_vfe_axi_stream_cfg_update_info_req_frm {
uint32_t stream_handle;
uint32_t user_stream_id;
uint32_t frame_id;
uint32_t buf_index;
};
struct msm_vfe_axi_halt_cmd {
uint32_t stop_camif;
uint32_t overflow_detected;
uint32_t blocking_halt;
};
struct msm_vfe_axi_reset_cmd {
uint32_t blocking;
uint32_t frame_id;
};
struct msm_vfe_axi_restart_cmd {
uint32_t enable_camif;
};
struct msm_vfe_axi_stream_update_cmd {
uint32_t num_streams;
enum msm_vfe_axi_stream_update_type update_type;
union {
struct msm_vfe_axi_stream_cfg_update_info update_info[MSM_ISP_STATS_MAX];
struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2;
};
};
struct msm_vfe_smmu_attach_cmd {
uint32_t security_mode;
uint32_t iommu_attach_mode;
};
struct msm_vfe_stats_stream_request_cmd {
uint32_t session_id;
uint32_t stream_id;
enum msm_isp_stats_type stats_type;
uint32_t composite_flag;
uint32_t framedrop_pattern;
uint32_t init_frame_drop;
uint32_t irq_subsample_pattern;
uint32_t buffer_offset;
uint32_t stream_handle;
};
struct msm_vfe_stats_stream_release_cmd {
uint32_t stream_handle;
};
struct msm_vfe_stats_stream_cfg_cmd {
uint8_t num_streams;
uint32_t stream_handle[MSM_ISP_STATS_MAX];
uint8_t enable;
uint32_t stats_burst_len;
};
enum msm_vfe_reg_cfg_type {
VFE_WRITE,
VFE_WRITE_MB,
VFE_READ,
VFE_CFG_MASK,
VFE_WRITE_DMI_16BIT,
VFE_WRITE_DMI_32BIT,
VFE_WRITE_DMI_64BIT,
VFE_READ_DMI_16BIT,
VFE_READ_DMI_32BIT,
VFE_READ_DMI_64BIT,
GET_MAX_CLK_RATE,
GET_CLK_RATES,
GET_ISP_ID,
VFE_HW_UPDATE_LOCK,
VFE_HW_UPDATE_UNLOCK,
SET_WM_UB_SIZE,
SET_UB_POLICY,
GET_VFE_HW_LIMIT,
};
struct msm_vfe_cfg_cmd2 {
uint16_t num_cfg;
uint16_t cmd_len;
void * cfg_data;
void * cfg_cmd;
};
struct msm_vfe_cfg_cmd_list {
struct msm_vfe_cfg_cmd2 cfg_cmd;
struct msm_vfe_cfg_cmd_list * next;
uint32_t next_size;
};
struct msm_vfe_reg_rw_info {
uint32_t reg_offset;
uint32_t cmd_data_offset;
uint32_t len;
};
struct msm_vfe_reg_mask_info {
uint32_t reg_offset;
uint32_t mask;
uint32_t val;
};
struct msm_vfe_reg_dmi_info {
uint32_t hi_tbl_offset;
uint32_t lo_tbl_offset;
uint32_t len;
};
struct msm_vfe_reg_cfg_cmd {
union {
struct msm_vfe_reg_rw_info rw_info;
struct msm_vfe_reg_mask_info mask_info;
struct msm_vfe_reg_dmi_info dmi_info;
} u;
enum msm_vfe_reg_cfg_type cmd_type;
};
enum vfe_sd_type {
VFE_SD_0 = 0,
VFE_SD_1,
VFE_SD_COMMON,
VFE_SD_MAX,
};
#define MS_NUM_SLAVE_MAX 1
enum msm_vfe_dual_hw_type {
DUAL_NONE = 0,
DUAL_HW_VFE_SPLIT = 1,
DUAL_HW_MASTER_SLAVE = 2,
};
enum msm_vfe_dual_hw_ms_type {
MS_TYPE_NONE,
MS_TYPE_MASTER,
MS_TYPE_SLAVE,
};
struct msm_isp_set_dual_hw_ms_cmd {
uint8_t num_src;
enum msm_vfe_dual_hw_ms_type dual_hw_ms_type;
enum msm_vfe_input_src primary_intf;
enum msm_vfe_input_src input_src[VFE_SRC_MAX];
uint32_t sof_delta_threshold;
};
enum msm_isp_buf_type {
ISP_PRIVATE_BUF,
ISP_SHARE_BUF,
MAX_ISP_BUF_TYPE,
};
struct msm_isp_unmap_buf_req {
uint32_t fd;
};
struct msm_isp_buf_request {
uint32_t session_id;
uint32_t stream_id;
uint8_t num_buf;
uint32_t handle;
enum msm_isp_buf_type buf_type;
};
struct msm_isp_buf_request_ver2 {
uint32_t session_id;
uint32_t stream_id;
uint8_t num_buf;
uint32_t handle;
enum msm_isp_buf_type buf_type;
enum smmu_attach_mode security_mode;
uint32_t reserved[4];
};
struct msm_isp_qbuf_plane {
uint32_t addr;
uint32_t offset;
uint32_t length;
};
struct msm_isp_qbuf_buffer {
struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];
uint32_t num_planes;
};
struct msm_isp_qbuf_info {
uint32_t handle;
int32_t buf_idx;
struct msm_isp_qbuf_buffer buffer;
uint32_t dirty_buf;
};
struct msm_isp_clk_rates {
uint32_t svs_rate;
uint32_t nominal_rate;
uint32_t high_rate;
};
struct msm_vfe_axi_src_state {
enum msm_vfe_input_src input_src;
uint32_t src_active;
uint32_t src_frame_id;
};
enum msm_isp_event_mask_index {
ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0,
ISP_EVENT_MASK_INDEX_ERROR = 1,
ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2,
ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3,
ISP_EVENT_MASK_INDEX_REG_UPDATE = 4,
ISP_EVENT_MASK_INDEX_SOF = 5,
ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6,
ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7,
ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8,
ISP_EVENT_MASK_INDEX_BUF_DONE = 9,
ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10,
ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11,
ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12,
};
#define ISP_EVENT_SUBS_MASK_NONE 0
#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY)
#define ISP_EVENT_SUBS_MASK_ERROR (1 << ISP_EVENT_MASK_INDEX_ERROR)
#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT)
#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE)
#define ISP_EVENT_SUBS_MASK_REG_UPDATE (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE)
#define ISP_EVENT_SUBS_MASK_SOF (1 << ISP_EVENT_MASK_INDEX_SOF)
#define ISP_EVENT_SUBS_MASK_BUF_DIVERT (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT)
#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY)
#define ISP_EVENT_SUBS_MASK_FE_READ_DONE (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE)
#define ISP_EVENT_SUBS_MASK_BUF_DONE (1 << ISP_EVENT_MASK_INDEX_BUF_DONE)
#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING)
#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH)
#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR)
enum msm_isp_event_idx {
ISP_REG_UPDATE = 0,
ISP_EPOCH_0 = 1,
ISP_EPOCH_1 = 2,
ISP_START_ACK = 3,
ISP_STOP_ACK = 4,
ISP_IRQ_VIOLATION = 5,
ISP_STATS_OVERFLOW = 6,
ISP_BUF_DONE = 7,
ISP_FE_RD_DONE = 8,
ISP_IOMMU_P_FAULT = 9,
ISP_ERROR = 10,
ISP_HW_FATAL_ERROR = 11,
ISP_PING_PONG_MISMATCH = 12,
ISP_REG_UPDATE_MISSING = 13,
ISP_BUF_FATAL_ERROR = 14,
ISP_EVENT_MAX = 15
};
#define ISP_EVENT_OFFSET 8
#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START)
#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))
#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))
#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE)
#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0)
#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1)
#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK)
#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK)
#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
#define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR)
#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE)
#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1)
#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE)
#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE)
#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE)
#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE)
#define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT)
#define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR)
#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH)
#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING)
#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR)
#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE)
struct msm_isp_buf_event {
uint32_t session_id;
uint32_t stream_id;
uint32_t handle;
uint32_t output_format;
int8_t buf_idx;
};
struct msm_isp_fetch_eng_event {
uint32_t session_id;
uint32_t stream_id;
uint32_t handle;
uint32_t fd;
int8_t buf_idx;
int8_t offline_mode;
};
struct msm_isp_stats_event {
uint32_t stats_mask;
uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX];
uint8_t pd_stats_idx;
};
struct msm_isp_stream_ack {
uint32_t session_id;
uint32_t stream_id;
uint32_t handle;
};
enum msm_vfe_error_type {
ISP_ERROR_NONE,
ISP_ERROR_CAMIF,
ISP_ERROR_BUS_OVERFLOW,
ISP_ERROR_RETURN_EMPTY_BUFFER,
ISP_ERROR_FRAME_ID_MISMATCH,
ISP_ERROR_MAX,
};
struct msm_isp_error_info {
enum msm_vfe_error_type err_type;
uint32_t session_id;
uint32_t stream_id;
uint32_t stream_id_mask;
};
struct msm_isp_ms_delta_info {
uint8_t num_delta_info;
uint32_t delta[MS_NUM_SLAVE_MAX];
};
struct msm_isp_output_info {
uint8_t regs_not_updated;
uint16_t output_err_mask;
uint8_t stream_framedrop_mask;
uint16_t stats_framedrop_mask;
};
struct msm_isp_sof_info {
uint8_t regs_not_updated;
uint16_t reg_update_fail_mask;
uint32_t stream_get_buf_fail_mask;
uint16_t stats_get_buf_fail_mask;
struct msm_isp_ms_delta_info ms_delta_info;
uint16_t axi_updating_mask;
uint32_t reg_update_fail_mask_ext;
};
#define AXI_UPDATING_MASK 1
#define REG_UPDATE_FAIL_MASK_EXT 1
struct msm_isp_event_data {
struct timeval timestamp;
struct timeval mono_timestamp;
uint32_t frame_id;
union {
struct msm_isp_stats_event stats;
struct msm_isp_buf_event buf_done;
struct msm_isp_fetch_eng_event fetch_done;
struct msm_isp_error_info error_info;
struct msm_isp_output_info output_info;
struct msm_isp_sof_info sof_info;
} u;
};
enum msm_vfe_ahb_clk_vote {
MSM_ISP_CAMERA_AHB_SVS_VOTE = 1,
MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2,
MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3,
MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4,
};
struct msm_isp_ahb_clk_cfg {
uint32_t vote;
uint32_t reserved[2];
};
enum msm_vfe_dual_cam_sync_mode {
MSM_ISP_DUAL_CAM_ASYNC,
MSM_ISP_DUAL_CAM_SYNC,
};
struct msm_isp_dual_hw_master_slave_sync {
uint32_t sync_mode;
uint32_t reserved[2];
};
struct msm_vfe_dual_lpm_mode {
enum msm_vfe_axi_stream_src stream_src[VFE_AXI_SRC_MAX];
uint32_t num_src;
uint32_t lpm_mode;
};
#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8')
#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8')
#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8')
#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8')
#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4')
#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4')
#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4')
#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4')
#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0')
#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0')
#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0')
#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0')
#define V4L2_PIX_FMT_P16BGGR12 v4l2_fourcc('P', 'B', 'G', '2')
#define V4L2_PIX_FMT_P16GBRG12 v4l2_fourcc('P', 'G', 'B', '2')
#define V4L2_PIX_FMT_P16GRBG12 v4l2_fourcc('P', 'G', 'R', '2')
#define V4L2_PIX_FMT_P16RGGB12 v4l2_fourcc('P', 'R', 'G', '2')
#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
#define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0')
#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4')
#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4')
#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')
#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4')
enum msm_isp_ioctl_cmd_code {
MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE,
MSM_ISP_REQUEST_BUF,
MSM_ISP_ENQUEUE_BUF,
MSM_ISP_RELEASE_BUF,
MSM_ISP_REQUEST_STREAM,
MSM_ISP_CFG_STREAM,
MSM_ISP_RELEASE_STREAM,
MSM_ISP_INPUT_CFG,
MSM_ISP_SET_SRC_STATE,
MSM_ISP_REQUEST_STATS_STREAM,
MSM_ISP_CFG_STATS_STREAM,
MSM_ISP_RELEASE_STATS_STREAM,
MSM_ISP_REG_UPDATE_CMD,
MSM_ISP_UPDATE_STREAM,
MSM_VFE_REG_LIST_CFG,
MSM_ISP_SMMU_ATTACH,
MSM_ISP_UPDATE_STATS_STREAM,
MSM_ISP_AXI_HALT,
MSM_ISP_AXI_RESET,
MSM_ISP_AXI_RESTART,
MSM_ISP_FETCH_ENG_START,
MSM_ISP_DEQUEUE_BUF,
MSM_ISP_SET_DUAL_HW_MASTER_SLAVE,
MSM_ISP_MAP_BUF_START_FE,
MSM_ISP_UNMAP_BUF,
MSM_ISP_AHB_CLK_CFG,
MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC,
MSM_ISP_FETCH_ENG_MULTI_PASS_START,
MSM_ISP_MAP_BUF_START_MULTI_PASS_FE,
MSM_ISP_REQUEST_BUF_VER2,
MSM_ISP_DUAL_HW_LPM_MODE,
};
#define VIDIOC_MSM_VFE_REG_CFG _IOWR('V', MSM_VFE_REG_CFG, struct msm_vfe_cfg_cmd2)
#define VIDIOC_MSM_ISP_REQUEST_BUF _IOWR('V', MSM_ISP_REQUEST_BUF, struct msm_isp_buf_request)
#define VIDIOC_MSM_ISP_ENQUEUE_BUF _IOWR('V', MSM_ISP_ENQUEUE_BUF, struct msm_isp_qbuf_info)
#define VIDIOC_MSM_ISP_RELEASE_BUF _IOWR('V', MSM_ISP_RELEASE_BUF, struct msm_isp_buf_request)
#define VIDIOC_MSM_ISP_REQUEST_STREAM _IOWR('V', MSM_ISP_REQUEST_STREAM, struct msm_vfe_axi_stream_request_cmd)
#define VIDIOC_MSM_ISP_CFG_STREAM _IOWR('V', MSM_ISP_CFG_STREAM, struct msm_vfe_axi_stream_cfg_cmd)
#define VIDIOC_MSM_ISP_RELEASE_STREAM _IOWR('V', MSM_ISP_RELEASE_STREAM, struct msm_vfe_axi_stream_release_cmd)
#define VIDIOC_MSM_ISP_INPUT_CFG _IOWR('V', MSM_ISP_INPUT_CFG, struct msm_vfe_input_cfg)
#define VIDIOC_MSM_ISP_SET_SRC_STATE _IOWR('V', MSM_ISP_SET_SRC_STATE, struct msm_vfe_axi_src_state)
#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM _IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, struct msm_vfe_stats_stream_request_cmd)
#define VIDIOC_MSM_ISP_CFG_STATS_STREAM _IOWR('V', MSM_ISP_CFG_STATS_STREAM, struct msm_vfe_stats_stream_cfg_cmd)
#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM _IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, struct msm_vfe_stats_stream_release_cmd)
#define VIDIOC_MSM_ISP_REG_UPDATE_CMD _IOWR('V', MSM_ISP_REG_UPDATE_CMD, enum msm_vfe_input_src)
#define VIDIOC_MSM_ISP_UPDATE_STREAM _IOWR('V', MSM_ISP_UPDATE_STREAM, struct msm_vfe_axi_stream_update_cmd)
#define VIDIOC_MSM_VFE_REG_LIST_CFG _IOWR('V', MSM_VFE_REG_LIST_CFG, struct msm_vfe_cfg_cmd_list)
#define VIDIOC_MSM_ISP_SMMU_ATTACH _IOWR('V', MSM_ISP_SMMU_ATTACH, struct msm_vfe_smmu_attach_cmd)
#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM _IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, struct msm_vfe_axi_stream_update_cmd)
#define VIDIOC_MSM_ISP_AXI_HALT _IOWR('V', MSM_ISP_AXI_HALT, struct msm_vfe_axi_halt_cmd)
#define VIDIOC_MSM_ISP_AXI_RESET _IOWR('V', MSM_ISP_AXI_RESET, struct msm_vfe_axi_reset_cmd)
#define VIDIOC_MSM_ISP_AXI_RESTART _IOWR('V', MSM_ISP_AXI_RESTART, struct msm_vfe_axi_restart_cmd)
#define VIDIOC_MSM_ISP_FETCH_ENG_START _IOWR('V', MSM_ISP_FETCH_ENG_START, struct msm_vfe_fetch_eng_start)
#define VIDIOC_MSM_ISP_DEQUEUE_BUF _IOWR('V', MSM_ISP_DEQUEUE_BUF, struct msm_isp_qbuf_info)
#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE _IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, struct msm_isp_set_dual_hw_ms_cmd)
#define VIDIOC_MSM_ISP_MAP_BUF_START_FE _IOWR('V', MSM_ISP_MAP_BUF_START_FE, struct msm_vfe_fetch_eng_start)
#define VIDIOC_MSM_ISP_UNMAP_BUF _IOWR('V', MSM_ISP_UNMAP_BUF, struct msm_isp_unmap_buf_req)
#define VIDIOC_MSM_ISP_AHB_CLK_CFG _IOWR('V', MSM_ISP_AHB_CLK_CFG, struct msm_isp_ahb_clk_cfg)
#define VIDIOC_MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC _IOWR('V', MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, struct msm_isp_dual_hw_master_slave_sync)
#define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, struct msm_vfe_fetch_eng_multi_pass_start)
#define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, struct msm_vfe_fetch_eng_multi_pass_start)
#define VIDIOC_MSM_ISP_REQUEST_BUF_VER2 _IOWR('V', MSM_ISP_REQUEST_BUF_VER2, struct msm_isp_buf_request_ver2)
#define VIDIOC_MSM_ISP_DUAL_HW_LPM_MODE _IOWR('V', MSM_ISP_DUAL_HW_LPM_MODE, struct msm_vfe_dual_lpm_mode)
#endif

169
sdm710/kernel-headers/media/msmb_ispif.h
View File

@@ -1,169 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef UAPI_MSMB_ISPIF_H
#define UAPI_MSMB_ISPIF_H
#include <linux/types.h>
#include <linux/ioctl.h>
#include <linux/videodev2.h>
#define CSID_VERSION_V20 0x02000011
#define CSID_VERSION_V22 0x02001000
#define CSID_VERSION_V30 0x30000000
#define CSID_VERSION_V3 0x30000000
enum msm_ispif_vfe_intf {
VFE0,
VFE1,
VFE_MAX
};
#define VFE0_MASK (1 << VFE0)
#define VFE1_MASK (1 << VFE1)
enum msm_ispif_intftype {
PIX0,
RDI0,
PIX1,
RDI1,
RDI2,
INTF_MAX
};
#define MAX_PARAM_ENTRIES (INTF_MAX * 2)
#define MAX_CID_CH 8
#define MAX_CID_CH_PARAM_ENTRY 3
#define PIX0_MASK (1 << PIX0)
#define PIX1_MASK (1 << PIX1)
#define RDI0_MASK (1 << RDI0)
#define RDI1_MASK (1 << RDI1)
#define RDI2_MASK (1 << RDI2)
enum msm_ispif_vc {
VC0,
VC1,
VC2,
VC3,
VC_MAX
};
enum msm_ispif_cid {
CID0,
CID1,
CID2,
CID3,
CID4,
CID5,
CID6,
CID7,
CID8,
CID9,
CID10,
CID11,
CID12,
CID13,
CID14,
CID15,
CID_MAX
};
enum msm_ispif_csid {
CSID0,
CSID1,
CSID2,
CSID3,
CSID_MAX
};
enum msm_ispif_pixel_odd_even {
PIX_EVEN,
PIX_ODD
};
enum msm_ispif_pixel_pack_mode {
PACK_BYTE,
PACK_PLAIN_PACK,
PACK_NV_P8,
PACK_NV_P16
};
struct msm_ispif_pack_cfg {
int pixel_swap_en;
enum msm_ispif_pixel_odd_even even_odd_sel;
enum msm_ispif_pixel_pack_mode pack_mode;
};
struct msm_ispif_params_entry {
enum msm_ispif_vfe_intf vfe_intf;
enum msm_ispif_intftype intftype;
int num_cids;
enum msm_ispif_cid cids[MAX_CID_CH_PARAM_ENTRY];
enum msm_ispif_csid csid;
int crop_enable;
uint16_t crop_start_pixel;
uint16_t crop_end_pixel;
};
struct msm_ispif_right_param_entry {
enum msm_ispif_cid cids[MAX_CID_CH_PARAM_ENTRY];
enum msm_ispif_csid csid;
};
struct msm_ispif_param_data_ext {
uint32_t num;
struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES];
struct msm_ispif_pack_cfg pack_cfg[CID_MAX];
struct msm_ispif_right_param_entry right_entries[MAX_PARAM_ENTRIES];
uint32_t stereo_enable;
uint16_t line_width[VFE_MAX];
};
struct msm_ispif_param_data {
uint32_t num;
struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES];
};
struct msm_isp_info {
uint32_t max_resolution;
uint32_t id;
uint32_t ver;
};
struct msm_ispif_vfe_info {
int num_vfe;
struct msm_isp_info info[VFE_MAX];
};
enum ispif_cfg_type_t {
ISPIF_CLK_ENABLE,
ISPIF_CLK_DISABLE,
ISPIF_INIT,
ISPIF_CFG,
ISPIF_START_FRAME_BOUNDARY,
ISPIF_RESTART_FRAME_BOUNDARY,
ISPIF_STOP_FRAME_BOUNDARY,
ISPIF_STOP_IMMEDIATELY,
ISPIF_RELEASE,
ISPIF_ENABLE_REG_DUMP,
ISPIF_SET_VFE_INFO,
ISPIF_CFG2,
ISPIF_CFG_STEREO,
};
struct ispif_cfg_data {
enum ispif_cfg_type_t cfg_type;
union {
int reg_dump;
uint32_t csid_version;
struct msm_ispif_vfe_info vfe_info;
struct msm_ispif_param_data params;
};
};
struct ispif_cfg_data_ext {
enum ispif_cfg_type_t cfg_type;
void * data;
uint32_t size;
};
#define ISPIF_RDI_PACK_MODE_SUPPORT 1
#define ISPIF_3D_SUPPORT 1
#define ISPIF_LINE_WIDTH_SUPPORT 1
#define VIDIOC_MSM_ISPIF_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data)
#define VIDIOC_MSM_ISPIF_CFG_EXT _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct ispif_cfg_data_ext)
#endif

193
sdm710/kernel-headers/media/msmb_pproc.h
View File

@@ -1,193 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __UAPI_MSMB_PPROC_H
#define __UAPI_MSMB_PPROC_H
#include <linux/videodev2.h>
#include <linux/types.h>
#include <media/msmb_generic_buf_mgr.h>
#define MAX_PLANES VIDEO_MAX_PLANES
#define PARTIAL_FRAME_STRIPE_COUNT 4
#define MAX_NUM_CPP_STRIPS 8
#define MSM_CPP_MAX_NUM_PLANES 3
#define MSM_CPP_MIN_FRAME_LENGTH 13
#define MSM_CPP_MAX_FRAME_LENGTH 4096
#define MSM_CPP_MAX_FW_NAME_LEN 32
#define MAX_FREQ_TBL 10
#define MSM_OUTPUT_BUF_CNT 8
enum msm_cpp_frame_type {
MSM_CPP_OFFLINE_FRAME,
MSM_CPP_REALTIME_FRAME,
};
enum msm_vpe_frame_type {
MSM_VPE_OFFLINE_FRAME,
MSM_VPE_REALTIME_FRAME,
};
struct msm_cpp_buffer_info_t {
int32_t fd;
uint32_t index;
uint32_t offset;
uint8_t native_buff;
uint8_t processed_divert;
uint32_t identity;
};
struct msm_cpp_stream_buff_info_t {
uint32_t identity;
uint32_t num_buffs;
struct msm_cpp_buffer_info_t * buffer_info;
};
enum msm_cpp_batch_mode_t {
BATCH_MODE_NONE,
BATCH_MODE_VIDEO,
BATCH_MODE_PREVIEW
};
struct msm_cpp_batch_info_t {
enum msm_cpp_batch_mode_t batch_mode;
uint32_t batch_size;
uint32_t intra_plane_offset[MAX_PLANES];
uint32_t pick_preview_idx;
uint32_t cont_idx;
};
struct msm_cpp_frame_info_t {
int32_t frame_id;
struct timeval timestamp;
uint32_t inst_id;
uint32_t identity;
uint32_t client_id;
enum msm_cpp_frame_type frame_type;
uint32_t num_strips;
uint32_t msg_len;
uint32_t * cpp_cmd_msg;
int src_fd;
int dst_fd;
struct timeval in_time, out_time;
void * cookie;
int32_t * status;
int32_t duplicate_output;
uint32_t duplicate_identity;
uint32_t feature_mask;
uint8_t we_disable;
struct msm_cpp_buffer_info_t input_buffer_info;
struct msm_cpp_buffer_info_t output_buffer_info[MSM_OUTPUT_BUF_CNT];
struct msm_cpp_buffer_info_t duplicate_buffer_info;
struct msm_cpp_buffer_info_t tnr_scratch_buffer_info[2];
uint32_t reserved;
uint8_t partial_frame_indicator;
uint8_t first_payload;
uint8_t last_payload;
uint32_t first_stripe_index;
uint32_t last_stripe_index;
uint32_t stripe_info_offset;
uint32_t stripe_info;
struct msm_cpp_batch_info_t batch_info;
};
struct msm_cpp_pop_stream_info_t {
int32_t frame_id;
uint32_t identity;
};
struct cpp_hw_info {
uint32_t cpp_hw_version;
uint32_t cpp_hw_caps;
unsigned long freq_tbl[MAX_FREQ_TBL];
uint32_t freq_tbl_count;
};
struct msm_vpe_frame_strip_info {
uint32_t src_w;
uint32_t src_h;
uint32_t dst_w;
uint32_t dst_h;
uint32_t src_x;
uint32_t src_y;
uint32_t phase_step_x;
uint32_t phase_step_y;
uint32_t phase_init_x;
uint32_t phase_init_y;
};
struct msm_vpe_buffer_info_t {
int32_t fd;
uint32_t index;
uint32_t offset;
uint8_t native_buff;
uint8_t processed_divert;
};
struct msm_vpe_stream_buff_info_t {
uint32_t identity;
uint32_t num_buffs;
struct msm_vpe_buffer_info_t * buffer_info;
};
struct msm_vpe_frame_info_t {
int32_t frame_id;
struct timeval timestamp;
uint32_t inst_id;
uint32_t identity;
uint32_t client_id;
enum msm_vpe_frame_type frame_type;
struct msm_vpe_frame_strip_info strip_info;
unsigned long src_fd;
unsigned long dst_fd;
struct ion_handle * src_ion_handle;
struct ion_handle * dest_ion_handle;
unsigned long src_phyaddr;
unsigned long dest_phyaddr;
unsigned long src_chroma_plane_offset;
unsigned long dest_chroma_plane_offset;
struct timeval in_time, out_time;
void * cookie;
struct msm_vpe_buffer_info_t input_buffer_info;
struct msm_vpe_buffer_info_t output_buffer_info;
};
struct msm_pproc_queue_buf_info {
struct msm_buf_mngr_info buff_mgr_info;
uint8_t is_buf_dirty;
};
struct msm_cpp_clock_settings_t {
unsigned long clock_rate;
uint64_t avg;
uint64_t inst;
};
#define VIDIOC_MSM_CPP_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_GET_INST_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_LOAD_FIRMWARE _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_GET_HW_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_FLUSH_QUEUE _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_ENQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_TRANSACTION_SETUP _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_GET_EVENTPAYLOAD _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_GET_INST_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_ENQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_DEQUEUE_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_QUEUE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_APPEND_STREAM_BUFF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_SET_CLOCK _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_POP_STREAM_BUFFER _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_IOMMU_ATTACH _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_IOMMU_DETACH _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_DELETE_STREAM_BUFF _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_camera_v4l2_ioctl_t)
#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0)
#define V4L2_EVENT_VPE_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 1)
struct msm_camera_v4l2_ioctl_t {
uint32_t id;
size_t len;
int32_t trans_code;
void * ioctl_ptr;
};
#endif

30
sdm710/kernel-headers/scsi/ufs/ioctl.h
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@@ -1,30 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef UAPI_UFS_IOCTL_H_
#define UAPI_UFS_IOCTL_H_
#include <linux/types.h>
#define UFS_IOCTL_QUERY 0x5388
struct ufs_ioctl_query_data {
__u32 opcode;
__u8 idn;
__u16 buf_size;
__u8 buffer[0];
};
#endif

86
sdm710/kernel-headers/scsi/ufs/ufs.h
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@@ -1,86 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef UAPI_UFS_H_
#define UAPI_UFS_H_
#define MAX_QUERY_IDN 0x18
enum flag_idn {
QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
QUERY_FLAG_IDN_BKOPS_EN = 0x04,
QUERY_FLAG_IDN_RESERVED1 = 0x05,
QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
QUERY_FLAG_IDN_RESERVED2 = 0x07,
QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
QUERY_FLAG_IDN_BUSY_RTC = 0x09,
QUERY_FLAG_IDN_MANUAL_GC_CONT = 0x0E,
};
enum attr_idn {
QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
QUERY_ATTR_IDN_RESERVED = 0x01,
QUERY_ATTR_IDN_POWER_MODE = 0x02,
QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
QUERY_ATTR_IDN_EE_STATUS = 0x0E,
QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
QUERY_ATTR_IDN_CNTX_CONF = 0x10,
QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
QUERY_ATTR_IDN_MANUAL_GC_STATUS = 0x17,
};
#define QUERY_ATTR_IDN_BOOT_LU_EN_MAX 0x02
enum desc_idn {
QUERY_DESC_IDN_DEVICE = 0x0,
QUERY_DESC_IDN_CONFIGURAION = 0x1,
QUERY_DESC_IDN_UNIT = 0x2,
QUERY_DESC_IDN_RFU_0 = 0x3,
QUERY_DESC_IDN_INTERCONNECT = 0x4,
QUERY_DESC_IDN_STRING = 0x5,
QUERY_DESC_IDN_RFU_1 = 0x6,
QUERY_DESC_IDN_GEOMETRY = 0x7,
QUERY_DESC_IDN_POWER = 0x8,
QUERY_DESC_IDN_HEALTH = 0x9,
QUERY_DESC_IDN_RFU_2 = 0xA,
QUERY_DESC_IDN_MAX,
};
enum query_opcode {
UPIU_QUERY_OPCODE_NOP = 0x0,
UPIU_QUERY_OPCODE_READ_DESC = 0x1,
UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
UPIU_QUERY_OPCODE_MAX,
};
#define UPIU_QUERY_OPCODE_HIGH_HPB 0x5500
#define UPIU_QUERY_OPCODE_HIGH(opcode) ((opcode) >> 16)
#define UPIU_QUERY_OPCODE_LOW(opcode) ((opcode) & 0xffff)
#endif

830
sdm710/kernel-headers/sound/asound.h
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@@ -1,830 +0,0 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __SOUND_ASOUND_H
#define __SOUND_ASOUND_H
#ifdef __linux__
#include <linux/types.h>
#else
#include <sys/ioctl.h>
#endif
#include <stdlib.h>
#include <time.h>
#define SNDRV_PROTOCOL_VERSION(major,minor,subminor) (((major) << 16) | ((minor) << 8) | (subminor))
#define SNDRV_PROTOCOL_MAJOR(version) (((version) >> 16) & 0xffff)
#define SNDRV_PROTOCOL_MINOR(version) (((version) >> 8) & 0xff)
#define SNDRV_PROTOCOL_MICRO(version) ((version) & 0xff)
#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion,uversion) (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion)))
struct snd_aes_iec958 {
unsigned char status[24];
unsigned char subcode[147];
unsigned char pad;
unsigned char dig_subframe[4];
};
struct snd_cea_861_aud_if {
unsigned char db1_ct_cc;
unsigned char db2_sf_ss;
unsigned char db3;
unsigned char db4_ca;
unsigned char db5_dminh_lsv;
};
#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
enum {
SNDRV_HWDEP_IFACE_OPL2 = 0,
SNDRV_HWDEP_IFACE_OPL3,
SNDRV_HWDEP_IFACE_OPL4,
SNDRV_HWDEP_IFACE_SB16CSP,
SNDRV_HWDEP_IFACE_EMU10K1,
SNDRV_HWDEP_IFACE_YSS225,
SNDRV_HWDEP_IFACE_ICS2115,
SNDRV_HWDEP_IFACE_SSCAPE,
SNDRV_HWDEP_IFACE_VX,
SNDRV_HWDEP_IFACE_MIXART,
SNDRV_HWDEP_IFACE_USX2Y,
SNDRV_HWDEP_IFACE_EMUX_WAVETABLE,
SNDRV_HWDEP_IFACE_BLUETOOTH,
SNDRV_HWDEP_IFACE_USX2Y_PCM,
SNDRV_HWDEP_IFACE_PCXHR,
SNDRV_HWDEP_IFACE_SB_RC,
SNDRV_HWDEP_IFACE_HDA,
SNDRV_HWDEP_IFACE_USB_STREAM,
SNDRV_HWDEP_IFACE_FW_DICE,
SNDRV_HWDEP_IFACE_FW_FIREWORKS,
SNDRV_HWDEP_IFACE_FW_BEBOB,
SNDRV_HWDEP_IFACE_FW_OXFW,
SNDRV_HWDEP_IFACE_FW_DIGI00X,
SNDRV_HWDEP_IFACE_FW_TASCAM,
SNDRV_HWDEP_IFACE_LINE6,
SNDRV_HWDEP_IFACE_AUDIO_BE,
SNDRV_HWDEP_IFACE_AUDIO_CODEC,
SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_AUDIO_CODEC
};
struct snd_hwdep_info {
unsigned int device;
int card;
unsigned char id[64];
unsigned char name[80];
int iface;
unsigned char reserved[64];
};
struct snd_hwdep_dsp_status {
unsigned int version;
unsigned char id[32];
unsigned int num_dsps;
unsigned int dsp_loaded;
unsigned int chip_ready;
unsigned char reserved[16];
};
struct snd_hwdep_dsp_image {
unsigned int index;
unsigned char name[64];
unsigned char * image;
size_t length;
unsigned long driver_data;
};
#define SNDRV_HWDEP_IOCTL_PVERSION _IOR('H', 0x00, int)
#define SNDRV_HWDEP_IOCTL_INFO _IOR('H', 0x01, struct snd_hwdep_info)
#define SNDRV_HWDEP_IOCTL_DSP_STATUS _IOR('H', 0x02, struct snd_hwdep_dsp_status)
#define SNDRV_HWDEP_IOCTL_DSP_LOAD _IOW('H', 0x03, struct snd_hwdep_dsp_image)
#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 13)
typedef unsigned long snd_pcm_uframes_t;
typedef signed long snd_pcm_sframes_t;
enum {
SNDRV_PCM_CLASS_GENERIC = 0,
SNDRV_PCM_CLASS_MULTI,
SNDRV_PCM_CLASS_MODEM,
SNDRV_PCM_CLASS_DIGITIZER,
SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER,
};
enum {
SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0,
SNDRV_PCM_SUBCLASS_MULTI_MIX,
SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX,
};
enum {
SNDRV_PCM_STREAM_PLAYBACK = 0,
SNDRV_PCM_STREAM_CAPTURE,
SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE,
};
typedef int __bitwise snd_pcm_access_t;
#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((snd_pcm_access_t) 0)
#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((snd_pcm_access_t) 1)
#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((snd_pcm_access_t) 2)
#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((snd_pcm_access_t) 3)
#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((snd_pcm_access_t) 4)
#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED
typedef int __bitwise snd_pcm_format_t;
#define SNDRV_PCM_FORMAT_S8 ((snd_pcm_format_t) 0)
#define SNDRV_PCM_FORMAT_U8 ((snd_pcm_format_t) 1)
#define SNDRV_PCM_FORMAT_S16_LE ((snd_pcm_format_t) 2)
#define SNDRV_PCM_FORMAT_S16_BE ((snd_pcm_format_t) 3)
#define SNDRV_PCM_FORMAT_U16_LE ((snd_pcm_format_t) 4)
#define SNDRV_PCM_FORMAT_U16_BE ((snd_pcm_format_t) 5)
#define SNDRV_PCM_FORMAT_S24_LE ((snd_pcm_format_t) 6)
#define SNDRV_PCM_FORMAT_S24_BE ((snd_pcm_format_t) 7)
#define SNDRV_PCM_FORMAT_U24_LE ((snd_pcm_format_t) 8)
#define SNDRV_PCM_FORMAT_U24_BE ((snd_pcm_format_t) 9)
#define SNDRV_PCM_FORMAT_S32_LE ((snd_pcm_format_t) 10)
#define SNDRV_PCM_FORMAT_S32_BE ((snd_pcm_format_t) 11)
#define SNDRV_PCM_FORMAT_U32_LE ((snd_pcm_format_t) 12)
#define SNDRV_PCM_FORMAT_U32_BE ((snd_pcm_format_t) 13)
#define SNDRV_PCM_FORMAT_FLOAT_LE ((snd_pcm_format_t) 14)
#define SNDRV_PCM_FORMAT_FLOAT_BE ((snd_pcm_format_t) 15)
#define SNDRV_PCM_FORMAT_FLOAT64_LE ((snd_pcm_format_t) 16)
#define SNDRV_PCM_FORMAT_FLOAT64_BE ((snd_pcm_format_t) 17)
#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((snd_pcm_format_t) 18)
#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((snd_pcm_format_t) 19)
#define SNDRV_PCM_FORMAT_MU_LAW ((snd_pcm_format_t) 20)
#define SNDRV_PCM_FORMAT_A_LAW ((snd_pcm_format_t) 21)
#define SNDRV_PCM_FORMAT_IMA_ADPCM ((snd_pcm_format_t) 22)
#define SNDRV_PCM_FORMAT_MPEG ((snd_pcm_format_t) 23)
#define SNDRV_PCM_FORMAT_GSM ((snd_pcm_format_t) 24)
#define SNDRV_PCM_FORMAT_SPECIAL ((snd_pcm_format_t) 31)
#define SNDRV_PCM_FORMAT_S24_3LE ((snd_pcm_format_t) 32)
#define SNDRV_PCM_FORMAT_S24_3BE ((snd_pcm_format_t) 33)
#define SNDRV_PCM_FORMAT_U24_3LE ((snd_pcm_format_t) 34)
#define SNDRV_PCM_FORMAT_U24_3BE ((snd_pcm_format_t) 35)
#define SNDRV_PCM_FORMAT_S20_3LE ((snd_pcm_format_t) 36)
#define SNDRV_PCM_FORMAT_S20_3BE ((snd_pcm_format_t) 37)
#define SNDRV_PCM_FORMAT_U20_3LE ((snd_pcm_format_t) 38)
#define SNDRV_PCM_FORMAT_U20_3BE ((snd_pcm_format_t) 39)
#define SNDRV_PCM_FORMAT_S18_3LE ((snd_pcm_format_t) 40)
#define SNDRV_PCM_FORMAT_S18_3BE ((snd_pcm_format_t) 41)
#define SNDRV_PCM_FORMAT_U18_3LE ((snd_pcm_format_t) 42)
#define SNDRV_PCM_FORMAT_U18_3BE ((snd_pcm_format_t) 43)
#define SNDRV_PCM_FORMAT_G723_24 ((snd_pcm_format_t) 44)
#define SNDRV_PCM_FORMAT_G723_24_1B ((snd_pcm_format_t) 45)
#define SNDRV_PCM_FORMAT_G723_40 ((snd_pcm_format_t) 46)
#define SNDRV_PCM_FORMAT_G723_40_1B ((snd_pcm_format_t) 47)
#define SNDRV_PCM_FORMAT_DSD_U8 ((snd_pcm_format_t) 48)
#define SNDRV_PCM_FORMAT_DSD_U16_LE ((snd_pcm_format_t) 49)
#define SNDRV_PCM_FORMAT_DSD_U32_LE ((snd_pcm_format_t) 50)
#define SNDRV_PCM_FORMAT_DSD_U16_BE ((snd_pcm_format_t) 51)
#define SNDRV_PCM_FORMAT_DSD_U32_BE ((snd_pcm_format_t) 52)
#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_DSD_U32_BE
#ifdef SNDRV_LITTLE_ENDIAN
#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE
#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE
#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE
#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE
#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE
#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE
#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE
#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE
#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE
#endif
#ifdef SNDRV_BIG_ENDIAN
#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE
#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE
#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE
#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE
#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE
#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE
#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE
#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE
#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE
#endif
typedef int __bitwise snd_pcm_subformat_t;
#define SNDRV_PCM_SUBFORMAT_STD ((snd_pcm_subformat_t) 0)
#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD
#define SNDRV_PCM_INFO_MMAP 0x00000001
#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002
#define SNDRV_PCM_INFO_DOUBLE 0x00000004
#define SNDRV_PCM_INFO_BATCH 0x00000010
#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100
#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200
#define SNDRV_PCM_INFO_COMPLEX 0x00000400
#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000
#define SNDRV_PCM_INFO_OVERRANGE 0x00020000
#define SNDRV_PCM_INFO_RESUME 0x00040000
#define SNDRV_PCM_INFO_PAUSE 0x00080000
#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000
#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000
#define SNDRV_PCM_INFO_SYNC_START 0x00400000
#define SNDRV_PCM_INFO_NO_PERIOD_WAKEUP 0x00800000
#define SNDRV_PCM_INFO_HAS_WALL_CLOCK 0x01000000
#define SNDRV_PCM_INFO_HAS_LINK_ATIME 0x01000000
#define SNDRV_PCM_INFO_HAS_LINK_ABSOLUTE_ATIME 0x02000000
#define SNDRV_PCM_INFO_HAS_LINK_ESTIMATED_ATIME 0x04000000
#define SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 0x08000000
#define SNDRV_PCM_INFO_DRAIN_TRIGGER 0x40000000
#define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000
typedef int __bitwise snd_pcm_state_t;
#define SNDRV_PCM_STATE_OPEN ((snd_pcm_state_t) 0)
#define SNDRV_PCM_STATE_SETUP ((snd_pcm_state_t) 1)
#define SNDRV_PCM_STATE_PREPARED ((snd_pcm_state_t) 2)
#define SNDRV_PCM_STATE_RUNNING ((snd_pcm_state_t) 3)
#define SNDRV_PCM_STATE_XRUN ((snd_pcm_state_t) 4)
#define SNDRV_PCM_STATE_DRAINING ((snd_pcm_state_t) 5)
#define SNDRV_PCM_STATE_PAUSED ((snd_pcm_state_t) 6)
#define SNDRV_PCM_STATE_SUSPENDED ((snd_pcm_state_t) 7)
#define SNDRV_PCM_STATE_DISCONNECTED ((snd_pcm_state_t) 8)
#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED
enum {
SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000,
SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000,
SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000,
};
union snd_pcm_sync_id {
unsigned char id[16];
unsigned short id16[8];
unsigned int id32[4];
};
struct snd_pcm_info {
unsigned int device;
unsigned int subdevice;
int stream;
int card;
unsigned char id[64];
unsigned char name[80];
unsigned char subname[32];
int dev_class;
int dev_subclass;
unsigned int subdevices_count;
unsigned int subdevices_avail;
union snd_pcm_sync_id sync;
unsigned char reserved[64];
};
typedef int snd_pcm_hw_param_t;
#define SNDRV_PCM_HW_PARAM_ACCESS 0
#define SNDRV_PCM_HW_PARAM_FORMAT 1
#define SNDRV_PCM_HW_PARAM_SUBFORMAT 2
#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS
#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT
#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8
#define SNDRV_PCM_HW_PARAM_FRAME_BITS 9
#define SNDRV_PCM_HW_PARAM_CHANNELS 10
#define SNDRV_PCM_HW_PARAM_RATE 11
#define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12
#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13
#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14
#define SNDRV_PCM_HW_PARAM_PERIODS 15
#define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16
#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17
#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18
#define SNDRV_PCM_HW_PARAM_TICK_TIME 19
#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS
#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME
#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1 << 0)
#define SNDRV_PCM_HW_PARAMS_EXPORT_BUFFER (1 << 1)
#define SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP (1 << 2)
struct snd_interval {
unsigned int min, max;
unsigned int openmin : 1, openmax : 1, integer : 1, empty : 1;
};
#define SNDRV_MASK_MAX 256
struct snd_mask {
__u32 bits[(SNDRV_MASK_MAX + 31) / 32];
};
struct snd_pcm_hw_params {
unsigned int flags;
struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - SNDRV_PCM_HW_PARAM_FIRST_MASK + 1];
struct snd_mask mres[5];
struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1];
struct snd_interval ires[9];
unsigned int rmask;
unsigned int cmask;
unsigned int info;
unsigned int msbits;
unsigned int rate_num;
unsigned int rate_den;
snd_pcm_uframes_t fifo_size;
unsigned char reserved[64];
};
enum {
SNDRV_PCM_TSTAMP_NONE = 0,
SNDRV_PCM_TSTAMP_ENABLE,
SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE,
};
struct snd_pcm_sw_params {
int tstamp_mode;
unsigned int period_step;
unsigned int sleep_min;
snd_pcm_uframes_t avail_min;
snd_pcm_uframes_t xfer_align;
snd_pcm_uframes_t start_threshold;
snd_pcm_uframes_t stop_threshold;
snd_pcm_uframes_t silence_threshold;
snd_pcm_uframes_t silence_size;
snd_pcm_uframes_t boundary;
unsigned int proto;
unsigned int tstamp_type;
unsigned char reserved[56];
};
struct snd_pcm_channel_info {
unsigned int channel;
__kernel_off_t offset;
unsigned int first;
unsigned int step;
};
enum {
SNDRV_PCM_AUDIO_TSTAMP_TYPE_COMPAT = 0,
SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT = 1,
SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK = 2,
SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ABSOLUTE = 3,
SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_ESTIMATED = 4,
SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED = 5,
SNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED
};
struct snd_pcm_status {
snd_pcm_state_t state;
struct timespec trigger_tstamp;
struct timespec tstamp;
snd_pcm_uframes_t appl_ptr;
snd_pcm_uframes_t hw_ptr;
snd_pcm_sframes_t delay;
snd_pcm_uframes_t avail;
snd_pcm_uframes_t avail_max;
snd_pcm_uframes_t overrange;
snd_pcm_state_t suspended_state;
__u32 audio_tstamp_data;
struct timespec audio_tstamp;
struct timespec driver_tstamp;
__u32 audio_tstamp_accuracy;
unsigned char reserved[52 - 2 * sizeof(struct timespec)];
};
struct snd_pcm_mmap_status {
snd_pcm_state_t state;
int pad1;
snd_pcm_uframes_t hw_ptr;
struct timespec tstamp;
snd_pcm_state_t suspended_state;
struct timespec audio_tstamp;
};
struct snd_pcm_mmap_control {
snd_pcm_uframes_t appl_ptr;
snd_pcm_uframes_t avail_min;
};
#define SNDRV_PCM_SYNC_PTR_HWSYNC (1 << 0)
#define SNDRV_PCM_SYNC_PTR_APPL (1 << 1)
#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1 << 2)
struct snd_pcm_sync_ptr {
unsigned int flags;
union {
struct snd_pcm_mmap_status status;
unsigned char reserved[64];
} s;
union {
struct snd_pcm_mmap_control control;
unsigned char reserved[64];
} c;
};
struct snd_xferi {
snd_pcm_sframes_t result;
void * buf;
snd_pcm_uframes_t frames;
};
struct snd_xfern {
snd_pcm_sframes_t result;
void * * bufs;
snd_pcm_uframes_t frames;
};
enum {
SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0,
SNDRV_PCM_TSTAMP_TYPE_MONOTONIC,
SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW,
SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW,
};
enum {
SNDRV_CHMAP_UNKNOWN = 0,
SNDRV_CHMAP_NA,
SNDRV_CHMAP_MONO,
SNDRV_CHMAP_FL,
SNDRV_CHMAP_FR,
SNDRV_CHMAP_RL,
SNDRV_CHMAP_RR,
SNDRV_CHMAP_FC,
SNDRV_CHMAP_LFE,
SNDRV_CHMAP_SL,
SNDRV_CHMAP_SR,
SNDRV_CHMAP_RC,
SNDRV_CHMAP_FLC,
SNDRV_CHMAP_FRC,
SNDRV_CHMAP_RLC,
SNDRV_CHMAP_RRC,
SNDRV_CHMAP_FLW,
SNDRV_CHMAP_FRW,
SNDRV_CHMAP_FLH,
SNDRV_CHMAP_FCH,
SNDRV_CHMAP_FRH,
SNDRV_CHMAP_TC,
SNDRV_CHMAP_TFL,
SNDRV_CHMAP_TFR,
SNDRV_CHMAP_TFC,
SNDRV_CHMAP_TRL,
SNDRV_CHMAP_TRR,
SNDRV_CHMAP_TRC,
SNDRV_CHMAP_TFLC,
SNDRV_CHMAP_TFRC,
SNDRV_CHMAP_TSL,
SNDRV_CHMAP_TSR,
SNDRV_CHMAP_LLFE,
SNDRV_CHMAP_RLFE,
SNDRV_CHMAP_BC,
SNDRV_CHMAP_BLC,
SNDRV_CHMAP_BRC,
SNDRV_CHMAP_LAST = SNDRV_CHMAP_BRC,
};
#define SNDRV_CHMAP_POSITION_MASK 0xffff
#define SNDRV_CHMAP_PHASE_INVERSE (0x01 << 16)
#define SNDRV_CHMAP_DRIVER_SPEC (0x02 << 16)
#define SNDRV_PCM_IOCTL_PVERSION _IOR('A', 0x00, int)
#define SNDRV_PCM_IOCTL_INFO _IOR('A', 0x01, struct snd_pcm_info)
#define SNDRV_PCM_IOCTL_TSTAMP _IOW('A', 0x02, int)
#define SNDRV_PCM_IOCTL_TTSTAMP _IOW('A', 0x03, int)
#define SNDRV_PCM_IOCTL_HW_REFINE _IOWR('A', 0x10, struct snd_pcm_hw_params)
#define SNDRV_PCM_IOCTL_HW_PARAMS _IOWR('A', 0x11, struct snd_pcm_hw_params)
#define SNDRV_PCM_IOCTL_HW_FREE _IO('A', 0x12)
#define SNDRV_PCM_IOCTL_SW_PARAMS _IOWR('A', 0x13, struct snd_pcm_sw_params)
#define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status)
#define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t)
#define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22)
#define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr)
#define SNDRV_PCM_IOCTL_STATUS_EXT _IOWR('A', 0x24, struct snd_pcm_status)
#define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info)
#define SNDRV_PCM_IOCTL_PREPARE _IO('A', 0x40)
#define SNDRV_PCM_IOCTL_RESET _IO('A', 0x41)
#define SNDRV_PCM_IOCTL_START _IO('A', 0x42)
#define SNDRV_PCM_IOCTL_DROP _IO('A', 0x43)
#define SNDRV_PCM_IOCTL_DRAIN _IO('A', 0x44)
#define SNDRV_PCM_IOCTL_PAUSE _IOW('A', 0x45, int)
#define SNDRV_PCM_IOCTL_REWIND _IOW('A', 0x46, snd_pcm_uframes_t)
#define SNDRV_PCM_IOCTL_RESUME _IO('A', 0x47)
#define SNDRV_PCM_IOCTL_XRUN _IO('A', 0x48)
#define SNDRV_PCM_IOCTL_FORWARD _IOW('A', 0x49, snd_pcm_uframes_t)
#define SNDRV_PCM_IOCTL_WRITEI_FRAMES _IOW('A', 0x50, struct snd_xferi)
#define SNDRV_PCM_IOCTL_READI_FRAMES _IOR('A', 0x51, struct snd_xferi)
#define SNDRV_PCM_IOCTL_WRITEN_FRAMES _IOW('A', 0x52, struct snd_xfern)
#define SNDRV_PCM_IOCTL_READN_FRAMES _IOR('A', 0x53, struct snd_xfern)
#define SNDRV_PCM_IOCTL_LINK _IOW('A', 0x60, int)
#define SNDRV_PCM_IOCTL_UNLINK _IO('A', 0x61)
#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0)
enum {
SNDRV_RAWMIDI_STREAM_OUTPUT = 0,
SNDRV_RAWMIDI_STREAM_INPUT,
SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT,
};
#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001
#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002
#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004
struct snd_rawmidi_info {
unsigned int device;
unsigned int subdevice;
int stream;
int card;
unsigned int flags;
unsigned char id[64];
unsigned char name[80];
unsigned char subname[32];
unsigned int subdevices_count;
unsigned int subdevices_avail;
unsigned char reserved[64];
};
struct snd_rawmidi_params {
int stream;
size_t buffer_size;
size_t avail_min;
unsigned int no_active_sensing : 1;
unsigned char reserved[16];
};
struct snd_rawmidi_status {
int stream;
struct timespec tstamp;
size_t avail;
size_t xruns;
unsigned char reserved[16];
};
#define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int)
#define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info)
#define SNDRV_RAWMIDI_IOCTL_PARAMS _IOWR('W', 0x10, struct snd_rawmidi_params)
#define SNDRV_RAWMIDI_IOCTL_STATUS _IOWR('W', 0x20, struct snd_rawmidi_status)
#define SNDRV_RAWMIDI_IOCTL_DROP _IOW('W', 0x30, int)
#define SNDRV_RAWMIDI_IOCTL_DRAIN _IOW('W', 0x31, int)
#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6)
enum {
SNDRV_TIMER_CLASS_NONE = - 1,
SNDRV_TIMER_CLASS_SLAVE = 0,
SNDRV_TIMER_CLASS_GLOBAL,
SNDRV_TIMER_CLASS_CARD,
SNDRV_TIMER_CLASS_PCM,
SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM,
};
enum {
SNDRV_TIMER_SCLASS_NONE = 0,
SNDRV_TIMER_SCLASS_APPLICATION,
SNDRV_TIMER_SCLASS_SEQUENCER,
SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
};
#define SNDRV_TIMER_GLOBAL_SYSTEM 0
#define SNDRV_TIMER_GLOBAL_RTC 1
#define SNDRV_TIMER_GLOBAL_HPET 2
#define SNDRV_TIMER_GLOBAL_HRTIMER 3
#define SNDRV_TIMER_FLG_SLAVE (1 << 0)
struct snd_timer_id {
int dev_class;
int dev_sclass;
int card;
int device;
int subdevice;
};
struct snd_timer_ginfo {
struct snd_timer_id tid;
unsigned int flags;
int card;
unsigned char id[64];
unsigned char name[80];
unsigned long reserved0;
unsigned long resolution;
unsigned long resolution_min;
unsigned long resolution_max;
unsigned int clients;
unsigned char reserved[32];
};
struct snd_timer_gparams {
struct snd_timer_id tid;
unsigned long period_num;
unsigned long period_den;
unsigned char reserved[32];
};
struct snd_timer_gstatus {
struct snd_timer_id tid;
unsigned long resolution;
unsigned long resolution_num;
unsigned long resolution_den;
unsigned char reserved[32];
};
struct snd_timer_select {
struct snd_timer_id id;
unsigned char reserved[32];
};
struct snd_timer_info {
unsigned int flags;
int card;
unsigned char id[64];
unsigned char name[80];
unsigned long reserved0;
unsigned long resolution;
unsigned char reserved[64];
};
#define SNDRV_TIMER_PSFLG_AUTO (1 << 0)
#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1 << 1)
#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1 << 2)
struct snd_timer_params {
unsigned int flags;
unsigned int ticks;
unsigned int queue_size;
unsigned int reserved0;
unsigned int filter;
unsigned char reserved[60];
};
struct snd_timer_status {
struct timespec tstamp;
unsigned int resolution;
unsigned int lost;
unsigned int overrun;
unsigned int queue;
unsigned char reserved[64];
};
#define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int)
#define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id)
#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int)
#define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo)
#define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams)
#define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus)
#define SNDRV_TIMER_IOCTL_SELECT _IOW('T', 0x10, struct snd_timer_select)
#define SNDRV_TIMER_IOCTL_INFO _IOR('T', 0x11, struct snd_timer_info)
#define SNDRV_TIMER_IOCTL_PARAMS _IOW('T', 0x12, struct snd_timer_params)
#define SNDRV_TIMER_IOCTL_STATUS _IOR('T', 0x14, struct snd_timer_status)
#define SNDRV_TIMER_IOCTL_START _IO('T', 0xa0)
#define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1)
#define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2)
#define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3)
struct snd_timer_read {
unsigned int resolution;
unsigned int ticks;
};
enum {
SNDRV_TIMER_EVENT_RESOLUTION = 0,
SNDRV_TIMER_EVENT_TICK,
SNDRV_TIMER_EVENT_START,
SNDRV_TIMER_EVENT_STOP,
SNDRV_TIMER_EVENT_CONTINUE,
SNDRV_TIMER_EVENT_PAUSE,
SNDRV_TIMER_EVENT_EARLY,
SNDRV_TIMER_EVENT_SUSPEND,
SNDRV_TIMER_EVENT_RESUME,
SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10,
SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10,
SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10,
SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10,
SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10,
SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10,
};
struct snd_timer_tread {
int event;
struct timespec tstamp;
unsigned int val;
};
#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7)
struct snd_ctl_card_info {
int card;
int pad;
unsigned char id[16];
unsigned char driver[16];
unsigned char name[32];
unsigned char longname[80];
unsigned char reserved_[16];
unsigned char mixername[80];
unsigned char components[128];
};
typedef int __bitwise snd_ctl_elem_type_t;
#define SNDRV_CTL_ELEM_TYPE_NONE ((snd_ctl_elem_type_t) 0)
#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((snd_ctl_elem_type_t) 1)
#define SNDRV_CTL_ELEM_TYPE_INTEGER ((snd_ctl_elem_type_t) 2)
#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((snd_ctl_elem_type_t) 3)
#define SNDRV_CTL_ELEM_TYPE_BYTES ((snd_ctl_elem_type_t) 4)
#define SNDRV_CTL_ELEM_TYPE_IEC958 ((snd_ctl_elem_type_t) 5)
#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((snd_ctl_elem_type_t) 6)
#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64
typedef int __bitwise snd_ctl_elem_iface_t;
#define SNDRV_CTL_ELEM_IFACE_CARD ((snd_ctl_elem_iface_t) 0)
#define SNDRV_CTL_ELEM_IFACE_HWDEP ((snd_ctl_elem_iface_t) 1)
#define SNDRV_CTL_ELEM_IFACE_MIXER ((snd_ctl_elem_iface_t) 2)
#define SNDRV_CTL_ELEM_IFACE_PCM ((snd_ctl_elem_iface_t) 3)
#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((snd_ctl_elem_iface_t) 4)
#define SNDRV_CTL_ELEM_IFACE_TIMER ((snd_ctl_elem_iface_t) 5)
#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((snd_ctl_elem_iface_t) 6)
#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER
#define SNDRV_CTL_ELEM_ACCESS_READ (1 << 0)
#define SNDRV_CTL_ELEM_ACCESS_WRITE (1 << 1)
#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE)
#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1 << 2)
#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1 << 3)
#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1 << 4)
#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1 << 5)
#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_TLV_WRITE)
#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1 << 6)
#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1 << 8)
#define SNDRV_CTL_ELEM_ACCESS_LOCK (1 << 9)
#define SNDRV_CTL_ELEM_ACCESS_OWNER (1 << 10)
#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1 << 28)
#define SNDRV_CTL_ELEM_ACCESS_USER (1 << 29)
#define SNDRV_CTL_POWER_D0 0x0000
#define SNDRV_CTL_POWER_D1 0x0100
#define SNDRV_CTL_POWER_D2 0x0200
#define SNDRV_CTL_POWER_D3 0x0300
#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3 | 0x0000)
#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3 | 0x0001)
#define SNDRV_CTL_ELEM_ID_NAME_MAXLEN 44
struct snd_ctl_elem_id {
unsigned int numid;
snd_ctl_elem_iface_t iface;
unsigned int device;
unsigned int subdevice;
unsigned char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
unsigned int index;
};
struct snd_ctl_elem_list {
unsigned int offset;
unsigned int space;
unsigned int used;
unsigned int count;
struct snd_ctl_elem_id * pids;
unsigned char reserved[50];
};
struct snd_ctl_elem_info {
struct snd_ctl_elem_id id;
snd_ctl_elem_type_t type;
unsigned int access;
unsigned int count;
__kernel_pid_t owner;
union {
struct {
long min;
long max;
long step;
} integer;
struct {
long long min;
long long max;
long long step;
} integer64;
struct {
unsigned int items;
unsigned int item;
char name[64];
__u64 names_ptr;
unsigned int names_length;
} enumerated;
unsigned char reserved[128];
} value;
union {
unsigned short d[4];
unsigned short * d_ptr;
} dimen;
unsigned char reserved[64 - 4 * sizeof(unsigned short)];
};
struct snd_ctl_elem_value {
struct snd_ctl_elem_id id;
unsigned int indirect : 1;
union {
union {
long value[128];
long * value_ptr;
} integer;
union {
long long value[64];
long long * value_ptr;
} integer64;
union {
unsigned int item[128];
unsigned int * item_ptr;
} enumerated;
union {
unsigned char data[512];
unsigned char * data_ptr;
} bytes;
struct snd_aes_iec958 iec958;
} value;
struct timespec tstamp;
unsigned char reserved[128 - sizeof(struct timespec)];
};
struct snd_ctl_tlv {
unsigned int numid;
unsigned int length;
unsigned int tlv[0];
};
#define SNDRV_CTL_IOCTL_PVERSION _IOR('U', 0x00, int)
#define SNDRV_CTL_IOCTL_CARD_INFO _IOR('U', 0x01, struct snd_ctl_card_info)
#define SNDRV_CTL_IOCTL_ELEM_LIST _IOWR('U', 0x10, struct snd_ctl_elem_list)
#define SNDRV_CTL_IOCTL_ELEM_INFO _IOWR('U', 0x11, struct snd_ctl_elem_info)
#define SNDRV_CTL_IOCTL_ELEM_READ _IOWR('U', 0x12, struct snd_ctl_elem_value)
#define SNDRV_CTL_IOCTL_ELEM_WRITE _IOWR('U', 0x13, struct snd_ctl_elem_value)
#define SNDRV_CTL_IOCTL_ELEM_LOCK _IOW('U', 0x14, struct snd_ctl_elem_id)
#define SNDRV_CTL_IOCTL_ELEM_UNLOCK _IOW('U', 0x15, struct snd_ctl_elem_id)
#define SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS _IOWR('U', 0x16, int)
#define SNDRV_CTL_IOCTL_ELEM_ADD _IOWR('U', 0x17, struct snd_ctl_elem_info)
#define SNDRV_CTL_IOCTL_ELEM_REPLACE _IOWR('U', 0x18, struct snd_ctl_elem_info)
#define SNDRV_CTL_IOCTL_ELEM_REMOVE _IOWR('U', 0x19, struct snd_ctl_elem_id)
#define SNDRV_CTL_IOCTL_TLV_READ _IOWR('U', 0x1a, struct snd_ctl_tlv)
#define SNDRV_CTL_IOCTL_TLV_WRITE _IOWR('U', 0x1b, struct snd_ctl_tlv)
#define SNDRV_CTL_IOCTL_TLV_COMMAND _IOWR('U', 0x1c, struct snd_ctl_tlv)
#define SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE _IOWR('U', 0x20, int)
#define SNDRV_CTL_IOCTL_HWDEP_INFO _IOR('U', 0x21, struct snd_hwdep_info)
#define SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE _IOR('U', 0x30, int)
#define SNDRV_CTL_IOCTL_PCM_INFO _IOWR('U', 0x31, struct snd_pcm_info)
#define SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE _IOW('U', 0x32, int)
#define SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE _IOWR('U', 0x40, int)
#define SNDRV_CTL_IOCTL_RAWMIDI_INFO _IOWR('U', 0x41, struct snd_rawmidi_info)
#define SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE _IOW('U', 0x42, int)
#define SNDRV_CTL_IOCTL_POWER _IOWR('U', 0xd0, int)
#define SNDRV_CTL_IOCTL_POWER_STATE _IOR('U', 0xd1, int)
enum sndrv_ctl_event_type {
SNDRV_CTL_EVENT_ELEM = 0,
SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM,
};
#define SNDRV_CTL_EVENT_MASK_VALUE (1 << 0)
#define SNDRV_CTL_EVENT_MASK_INFO (1 << 1)
#define SNDRV_CTL_EVENT_MASK_ADD (1 << 2)
#define SNDRV_CTL_EVENT_MASK_TLV (1 << 3)
#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U)
struct snd_ctl_event {
int type;
union {
struct {
unsigned int mask;
struct snd_ctl_elem_id id;
} elem;
unsigned char data8[60];
} data;
};
#define SNDRV_CTL_NAME_NONE ""
#define SNDRV_CTL_NAME_PLAYBACK "Playback "
#define SNDRV_CTL_NAME_CAPTURE "Capture "
#define SNDRV_CTL_NAME_IEC958_NONE ""
#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch"
#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume"
#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default"
#define SNDRV_CTL_NAME_IEC958_MASK "Mask"
#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask"
#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask"
#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream"
#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_ ##direction SNDRV_CTL_NAME_IEC958_ ##what
#endif

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