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mhi: core: Add support for new MHI hardware channel

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Add support for new MHI hardware channel 102 to be
use by MHI clients as ADPL channel.

CRs-Fixed: 1027069
Change-Id: Ib3c2019fc269064d097bb7f40f01d4580e63a603
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
This commit is contained in:
Sujeev Dias
2016-09-13 16:55:01 -07:00
parent 219eb11023
commit fcfe80f8cc
7 changed files with 34 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/platform/msm/mhi/mhi.h
View File

@@ -277,6 +277,8 @@ struct mhi_ring {
u32 overwrite_en;
enum MHI_CHAN_DIR dir;
struct db_mode db_mode;
u32 msi_disable_cntr;
u32 msi_enable_cntr;
};
enum MHI_CMD_STATUS {
@@ -351,12 +353,6 @@ struct mhi_client_handle {
int event_ring_index;
};
enum MHI_EVENT_POLLING {
MHI_EVENT_POLLING_DISABLED = 0x0,
MHI_EVENT_POLLING_ENABLED = 0x1,
MHI_EVENT_POLLING_reserved = 0x80000000
};
enum MHI_TYPE_EVENT_RING {
MHI_ER_DATA_TYPE = 0x1,
MHI_ER_CTRL_TYPE = 0x2,
@@ -393,8 +389,6 @@ struct mhi_counters {
u32 m3_event_timeouts;
u32 m0_event_timeouts;
u32 m2_event_timeouts;
u32 msi_disable_cntr;
u32 msi_enable_cntr;
u32 nr_irq_migrations;
u32 *msi_counter;
u32 *ev_counter;

18
drivers/platform/msm/mhi/mhi_hwio.h
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
/* Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -23,14 +23,14 @@
#define MHICFG (0x10)
#define MHICFG_RESERVED_BITS31_24_MASK 0xff000000
#define MHICFG_RESERVED_BITS31_24_SHIFT 0x18
#define MHICFG_NER_MASK 0xff0000
#define MHICFG_NER_SHIFT 0x10
#define MHICFG_RESERVED_BITS15_8_MASK 0xff00
#define MHICFG_RESERVED_BITS15_8_SHIFT 0x8
#define MHICFG_NCH_MASK 0xff
#define MHICFG_NCH_SHIFT 0x0
#define MHICFG_NHWER_MASK (0xff000000)
#define MHICFG_NHWER_SHIFT (24)
#define MHICFG_NER_MASK (0xff0000)
#define MHICFG_NER_SHIFT (16)
#define MHICFG_NHWCH_MASK (0xff00)
#define MHICFG_NHWCH_SHIFT (8)
#define MHICFG_NCH_MASK (0xff)
#define MHICFG_NCH_SHIFT (0)
#define CHDBOFF (0x18)

26
drivers/platform/msm/mhi/mhi_isr.c
View File

@@ -277,20 +277,22 @@ struct mhi_result *mhi_poll(struct mhi_client_handle *client_handle)
void mhi_mask_irq(struct mhi_client_handle *client_handle)
{
disable_irq_nosync(MSI_TO_IRQ(client_handle->mhi_dev_ctxt,
client_handle->msi_vec));
client_handle->mhi_dev_ctxt->counters.msi_disable_cntr++;
if (client_handle->mhi_dev_ctxt->counters.msi_disable_cntr >
(client_handle->mhi_dev_ctxt->counters.msi_enable_cntr + 1))
mhi_log(MHI_MSG_INFO, "No nested IRQ disable Allowed\n");
struct mhi_device_ctxt *mhi_dev_ctxt =
client_handle->mhi_dev_ctxt;
struct mhi_ring *ev_ring = &mhi_dev_ctxt->
mhi_local_event_ctxt[client_handle->event_ring_index];
disable_irq_nosync(MSI_TO_IRQ(mhi_dev_ctxt, client_handle->msi_vec));
ev_ring->msi_disable_cntr++;
}
void mhi_unmask_irq(struct mhi_client_handle *client_handle)
{
client_handle->mhi_dev_ctxt->counters.msi_enable_cntr++;
enable_irq(MSI_TO_IRQ(client_handle->mhi_dev_ctxt,
client_handle->msi_vec));
if (client_handle->mhi_dev_ctxt->counters.msi_enable_cntr >
client_handle->mhi_dev_ctxt->counters.msi_disable_cntr)
mhi_log(MHI_MSG_INFO, "No nested IRQ enable Allowed\n");
struct mhi_device_ctxt *mhi_dev_ctxt =
client_handle->mhi_dev_ctxt;
struct mhi_ring *ev_ring = &mhi_dev_ctxt->
mhi_local_event_ctxt[client_handle->event_ring_index];
ev_ring->msi_enable_cntr++;
enable_irq(MSI_TO_IRQ(mhi_dev_ctxt, client_handle->msi_vec));
}

1
drivers/platform/msm/mhi/mhi_macros.h
View File

@@ -96,7 +96,6 @@
((_mhi_dev_ctxt)->mmio_info.nr_event_rings - \
((_mhi_dev_ctxt)->mmio_info.nr_hw_event_rings)))
/* MHI Transfer Ring Elements 7.4.1*/
#define TX_TRB_LEN
#define MHI_TX_TRB_LEN__SHIFT (0)

5
drivers/platform/msm/mhi/mhi_mmio_ops.c
View File

@@ -144,6 +144,11 @@ int mhi_init_mmio(struct mhi_device_ctxt *mhi_dev_ctxt)
MHICFG,
MHICFG_NER_MASK, MHICFG_NER_SHIFT,
mhi_dev_ctxt->mmio_info.nr_event_rings);
mhi_reg_write_field(mhi_dev_ctxt, mhi_dev_ctxt->mmio_info.mmio_addr,
MHICFG,
MHICFG_NHWER_MASK,
MHICFG_NHWER_SHIFT,
mhi_dev_ctxt->mmio_info.nr_hw_event_rings);
pcie_dword_val = mhi_dev_ctxt->dev_space.ring_ctxt.dma_cc_list;
pcie_word_val = HIGH_WORD(pcie_dword_val);

6
drivers/platform/msm/mhi/mhi_sys.c
View File

@@ -237,7 +237,7 @@ static ssize_t mhi_dbgfs_state_read(struct file *fp, char __user *buf,
amnt_copied =
scnprintf(mhi_dev_ctxt->chan_info,
MHI_LOG_SIZE,
"%s %s %s %d %s %d %s %d %s %d %s %d %s %d %s %d %s %d %s %d %s %d, %s, %d, %s %d\n",
"%s %s %s %d %s %d %s %d %s %d %s %d %s %d %s %d %s %d %s %d %s %d\n",
"Our State:",
TO_MHI_STATE_STR(mhi_dev_ctxt->mhi_state),
"M0->M1:",
@@ -256,10 +256,6 @@ static ssize_t mhi_dbgfs_state_read(struct file *fp, char __user *buf,
mhi_dev_ctxt->counters.m3_event_timeouts,
"M0_ev_TO:",
mhi_dev_ctxt->counters.m0_event_timeouts,
"MSI_d:",
mhi_dev_ctxt->counters.msi_disable_cntr,
"MSI_e:",
mhi_dev_ctxt->counters.msi_enable_cntr,
"outstanding_acks:",
atomic_read(&mhi_dev_ctxt->counters.outbound_acks),
"LPM:",

5
include/linux/msm_mhi.h
View File

@@ -63,9 +63,10 @@ enum MHI_CLIENT_CHANNEL {
MHI_CLIENT_RESERVED_1_UPPER = 99,
MHI_CLIENT_IP_HW_0_OUT = 100,
MHI_CLIENT_IP_HW_0_IN = 101,
MHI_CLIENT_RESERVED_2_LOWER = 102,
MHI_CLIENT_IP_HW_ADPL_IN = 102,
MHI_CLIENT_RESERVED_2_LOWER = 103,
MHI_CLIENT_RESERVED_2_UPPER = 127,
MHI_MAX_CHANNELS = 102
MHI_MAX_CHANNELS = 103
};
enum MHI_CB_REASON {