Merge "ARM: dts: msm: Add dtsi changes for lahaina target"

Kbuild

@@ -83,6 +83,10 @@ ifeq ($(CONFIG_ARCH_QTI_VM),y)
 dtbo-y += sa8797p-gunyah-vm-cnss.dtbo
 endif
 
+ifeq ($(CONFIG_ARCH_YUPIK),y)
+dtbo-y += lahaina-qca6490-cnss.dtbo
+endif
+
 always-y	:= $(dtb-y) $(dtbo-y)
 subdir-y	:= $(dts-dirs)
 clean-files	:= *.dtb *.dtbo

lahaina-qca6490-cnss.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "lahaina-qca6490-cnss.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. YupikP IoT HSP";
+	compatible = "qcom,yupikp-iot-idp", "qcom,yupikp-iot", "qcom,idp";
+	qcom,msm-id = <497 0x10000>, <498 0x10000>, <575 0x10000>, <576 0x10000>;
+	qcom,board-id = <34 1>;
+};

lahaina-qca6490-cnss.dtsi

@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interconnect/qcom,yupik.h>
+
+&soc {
+	wlan: qcom,cnss-qca6490@b0000000 {
+		compatible = "qcom,cnss-qca6490";
+		reg = <0xb0000000 0x10000>;
+		reg-names = "smmu_iova_ipa";
+		wlan-en-gpio = <&tlmm 84 0>;
+		qcom,bt-en-gpio = <&tlmm 85 0>;
+		pinctrl-names = "wlan_en_active", "wlan_en_sleep";
+		pinctrl-0 = <&cnss_wlan_en_active>;
+		pinctrl-1 = <&cnss_wlan_en_sleep>;
+		qcom,wlan-rc-num = <0>;
+		qcom,wlan;
+		qcom,wlan-ramdump-dynamic = <0x420000>;
+		qcom,wlan-cbc-enabled;
+
+		vdd-wlan-aon-supply = <&S7B>;
+		qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>;
+		vdd-wlan-dig-supply = <&S7B>;
+		qcom,vdd-wlan-dig-config = <950000 952000 0 0 1>;
+		vdd-wlan-io-supply = <&L19B>;
+		qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
+		vdd-wlan-rfa1-supply = <&S1B>;
+		qcom,vdd-wlan-rfa1-config = <1880000 2040000 0 0 1>;
+		vdd-wlan-rfa2-supply = <&S8B>;
+		qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
+		wlan-ant-switch-supply = <&L11C>;
+		qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>;
+
+		interconnects =
+		<&aggre1_noc MASTER_PCIE_0 &aggre1_noc SLAVE_ANOC_PCIE_GEM_NOC>,
+		<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
+		interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
+
+		qcom,icc-path-count = <2>;
+		qcom,bus-bw-cfg-count = <9>;
+		qcom,bus-bw-cfg =
+		/** ICC Path 1 **/
+		<0 0>, /* no vote */
+		/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
+		<2250 390000>,
+		/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
+		<7500 390000>,
+		/* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
+		<30000 790000>,
+		/* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
+		<100000 790000>,
+		/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */
+		<175000 1600000>,
+		/* Ultra high */
+		<0 0>,
+		/* Super High */
+		<0 0>,
+		/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
+		 * ddr: 547.2 MHz
+		 */
+		<7500 390000>,
+
+		/** ICC Path 2 **/
+		<0 0>,
+		<2250 1804800>,
+		<7500 1804800>,
+		<30000 1804800>,
+		<100000 1804800>,
+		<175000 6220800>,
+		<0 0>,
+		<0 0>,
+		<7500 2188800>;
+	};
+};
+
+&pcie0_rp {
+
+	cnss_pci: cnss_pci {
+		reg = <0 0 0 0 0>;
+		qcom,iommu-group = <&cnss_pci_iommu_group>;
+		memory-region = <&cnss_wlan_mem &cnss_pci0_iommu_region_partition>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cnss_pci_iommu_group: cnss_pci_iommu_group {
+			qcom,iommu-msi-size = <0x1000>;
+			qcom,iommu-geometry = <0xa0000000 0x10010000>;
+			qcom,iommu-dma = "fastmap";
+			qcom,iommu-pagetable = "coherent";
+			qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
+					    "non-fatal";
+		};
+
+		cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
+			/**
+			 * qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000> conversion:
+			 * 0x0 0xA0000000 - first range from above dma-addr pool
+			 * 0x0 0xB0000000 = 0xa0000000 + 0x10000000
+			 * 0x0 0x50000000 = 100000000 - 0xB0000000
+			 */
+			 /* address-cells =3 size-cells=2 from yupik-pcie.dtsi */
+			iommu-addresses = <&cnss_pci 0x0 0x0 0x0 0x0 0xa0000000>,
+					  <&cnss_pci 0x0 0x0 0xB0000000 0x0 0x50000000>;
+		};
+	};
+};