msm: kgsl: Map fusa resource during first boot only
Fusa registers are accessed during first boot only. Thus, remove it from regmap and map it temporarily during first boot. Change-Id: If0ca6b2f36092f0448bdc7b6a7bf945a078bab92 Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com> Signed-off-by: Hui Li <quic_hul@quicinc.com>
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@@ -1225,6 +1225,7 @@
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(((1 << A6XX_GPU_LLC_SCID_NUM_BITS) - 1) << A6XX_GPUHTW_LLC_SCID_SHIFT)
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/* FUSA registers */
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#define A6XX_GPU_FUSA_REG_BASE 0x3FC00
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#define A6XX_GPU_FUSA_REG_ECC_CTRL 0x3FC00
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#define A6XX_GPU_FUSA_REG_CSR_PRIY 0x3FC52
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#define A6XX_GPU_FUSA_DISABLE_NUM_BITS 4
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3
adreno.c
3
adreno.c
@@ -1307,9 +1307,6 @@ int adreno_device_probe(struct platform_device *pdev,
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/* Add CX_DBGC block to the regmap*/
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kgsl_regmap_add_region(&device->regmap, pdev, "cx_dbgc", NULL, NULL);
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/* Add FUSA block to the regmap */
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kgsl_regmap_add_region(&device->regmap, pdev, "fusa", NULL, NULL);
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/* Probe for the optional CX_MISC block */
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adreno_cx_misc_probe(device);
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@@ -90,6 +90,26 @@ static struct gmu_vma_entry a6xx_gmu_vma[] = {
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},
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};
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static void _regwrite(void __iomem *regbase, u32 offsetwords, u32 value)
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{
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void __iomem *reg;
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reg = regbase + (offsetwords << 2);
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__raw_writel(value, reg);
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}
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static void _regrmw(void __iomem *regbase, u32 offsetwords, u32 mask, u32 or)
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{
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void __iomem *reg;
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u32 val;
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reg = regbase + (offsetwords << 2);
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val = __raw_readl(reg);
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/* Make sure the read posted and all pending writes are done */
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mb();
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__raw_writel((val & ~mask) | or, reg);
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}
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static ssize_t log_stream_enable_store(struct kobject *kobj,
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struct kobj_attribute *attr, const char *buf, size_t count)
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{
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@@ -277,15 +297,6 @@ struct adreno_device *a6xx_gmu_to_adreno(struct a6xx_gmu_device *gmu)
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#define PDC_CMD_OFFSET 4
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#define PDC_ENABLE_REG_VALUE 0x80000001
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static void _regwrite(void __iomem *regbase,
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unsigned int offsetwords, unsigned int value)
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{
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void __iomem *reg;
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reg = regbase + (offsetwords << 2);
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__raw_writel(value, reg);
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}
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void a6xx_load_rsc_ucode(struct adreno_device *adreno_dev)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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@@ -3160,17 +3171,32 @@ void a6xx_disable_gpu_irq(struct adreno_device *adreno_dev)
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}
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void a6xx_fusa_init(struct adreno_device *adreno_dev)
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static void a6xx_fusa_init(struct adreno_device *adreno_dev)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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void __iomem *fusa_virt = NULL;
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struct resource *res;
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if (adreno_is_a663(adreno_dev)) {
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/* disable fusa mode in bu stage */
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kgsl_regrmw(device, A6XX_GPU_FUSA_REG_ECC_CTRL,
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A6XX_GPU_FUSA_DISABLE_MASK, A6XX_GPU_FUSA_DISABLE_BITS);
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kgsl_regrmw(device, A6XX_GPU_FUSA_REG_CSR_PRIY,
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A6XX_GPU_FUSA_DISABLE_MASK, A6XX_GPU_FUSA_DISABLE_BITS);
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if (!adreno_is_a663(adreno_dev))
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return;
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res = platform_get_resource_byname(device->pdev,
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IORESOURCE_MEM, "fusa");
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if (res)
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fusa_virt = ioremap(res->start, resource_size(res));
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if (!fusa_virt) {
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dev_err(device->dev, "Failed to map fusa\n");
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return;
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}
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/* Disable fusa mode in boot stage */
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_regrmw(fusa_virt, A6XX_GPU_FUSA_REG_ECC_CTRL - A6XX_GPU_FUSA_REG_BASE,
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A6XX_GPU_FUSA_DISABLE_MASK, A6XX_GPU_FUSA_DISABLE_BITS);
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_regrmw(fusa_virt, A6XX_GPU_FUSA_REG_CSR_PRIY - A6XX_GPU_FUSA_REG_BASE,
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A6XX_GPU_FUSA_DISABLE_MASK, A6XX_GPU_FUSA_DISABLE_BITS);
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iounmap(fusa_virt);
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}
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static int a6xx_gpu_boot(struct adreno_device *adreno_dev)
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@@ -215,12 +215,6 @@ void a6xx_enable_gpu_irq(struct adreno_device *adreno_dev);
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*/
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void a6xx_disable_gpu_irq(struct adreno_device *adreno_dev);
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/**
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* a6xx_fusa_init - Init gpu fusa
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* @adreno_dev: Pointer to the adreno device
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*/
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void a6xx_fusa_init(struct adreno_device *adreno_dev);
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/**
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* a6xx_gmu_snapshot- Take snapshot for gmu targets
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* @adreno_dev: Pointer to the adreno device
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