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qcacld-3.0: enable srri/drri on ddr

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The SRRI/DRRI can be read from DDR instead of doing an
actual hardware read. This mechanism is compiled out by
default.

Change-Id: I8fc6c8817b5958f3d00b47ccd3dba36b354097e8
CRs-Fixed: 932344
This commit is contained in:
Sanjay Devnani
2015-11-12 14:43:58 -08:00
committed by Prakash Dhavali
parent 9ce15778e1
commit b925d7efcc
7 changed files with 255 additions and 29 deletions
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1
Kbuild
View File

@@ -909,6 +909,7 @@ endif
ifeq (y,$(filter y,$(CONFIG_CNSS_ADRASTEA) $(CONFIG_ICNSS)))
CDEFINES += -DQCA_WIFI_3_0_ADRASTEA
CDEFINES += -DADRASTEA_SHADOW_REGISTERS
CDEFINES += -DADRASTEA_RRI_ON_DDR
endif
ifeq ($(CONFIG_WLAN_FASTPATH), y)

1
core/hif/inc/hif.h
View File

@@ -314,6 +314,7 @@ struct ol_softc {
cdf_spinlock_t irq_lock;
uint32_t ce_irq_summary;
#endif
uint32_t *vaddr_rri_on_ddr;
};
typedef enum {

5
core/hif/inc/regtable_ce.h
View File

@@ -208,8 +208,8 @@ struct ce_reg_def {
uint32_t d_HOST_IS_COPY_COMPLETE_MASK;
uint32_t d_CE_WRAPPER_BASE_ADDRESS;
uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS;
uint32_t d_CE_WRAPPER_INDEX_BASE_LOW;
uint32_t d_CE_WRAPPER_INDEX_BASE_HIGH;
uint32_t d_CE_DDR_ADDRESS_FOR_RRI_LOW;
uint32_t d_CE_DDR_ADDRESS_FOR_RRI_HIGH;
uint32_t d_HOST_IE_ADDRESS;
uint32_t d_HOST_IE_COPY_COMPLETE_MASK;
uint32_t d_SR_BA_ADDRESS;
@@ -243,6 +243,7 @@ struct ce_reg_def {
uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK;
uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB;
uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB;
uint32_t d_CE_CTRL1_IDX_UPD_EN_MASK;
uint32_t d_CE_WRAPPER_DEBUG_OFFSET;
uint32_t d_CE_WRAPPER_DEBUG_SEL_MSB;
uint32_t d_CE_WRAPPER_DEBUG_SEL_LSB;

31
core/hif/src/adrastea_reg_def.h
View File

@@ -1190,6 +1190,9 @@
/* End auto-generated headers from register parser */
#define A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW 0x0024C004
#define A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH 0x0024C008
#define MISSING 0
#define MISSING_FOR_ADRASTEA MISSING
#define ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS 0
@@ -1385,9 +1388,21 @@
#define ADRASTEA_HOST_IS_COPY_COMPLETE_MASK \
ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___M
#define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
#define ADRASTEA_CE_WRAPPER_INDEX_BASE_LOW 0x0004
#define ADRASTEA_CE_WRAPPER_INDEX_BASE_HIGH 0x0008
#define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET \
(ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY\
- ADRASTEA_CE_WRAPPER_BASE_ADDRESS)
/*
* Base address where the CE source and destination ring read
* indices are written to be viewed by host.
*/
#define ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_LOW \
(A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW\
- ADRASTEA_CE_WRAPPER_BASE_ADDRESS)
#define ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_HIGH \
(A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH - ADRASTEA_CE_WRAPPER_BASE_ADDRESS)
#define ADRASTEA_HOST_IE_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE\
- ADRASTEA_CE0_BASE_ADDRESS)
@@ -2191,9 +2206,11 @@ struct ce_reg_def adrastea_ce_targetdef = {
.d_HOST_IS_COPY_COMPLETE_MASK = ADRASTEA_HOST_IS_COPY_COMPLETE_MASK,
.d_CE_WRAPPER_BASE_ADDRESS = ADRASTEA_CE_WRAPPER_BASE_ADDRESS,
.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
.d_CE_WRAPPER_INDEX_BASE_LOW = ADRASTEA_CE_WRAPPER_INDEX_BASE_LOW,
.d_CE_WRAPPER_INDEX_BASE_HIGH = ADRASTEA_CE_WRAPPER_INDEX_BASE_HIGH,
ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET,
.d_CE_DDR_ADDRESS_FOR_RRI_LOW =
ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_LOW,
.d_CE_DDR_ADDRESS_FOR_RRI_HIGH =
ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_HIGH,
.d_HOST_IE_ADDRESS = ADRASTEA_HOST_IE_OFFSET,
.d_HOST_IE_COPY_COMPLETE_MASK = ADRASTEA_HOST_IE_COPY_COMPLETE_MASK,
.d_SR_BA_ADDRESS = ADRASTEA_SR_BA_OFFSET,
@@ -2233,6 +2250,8 @@ struct ce_reg_def adrastea_ce_targetdef = {
ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
.d_CE_CTRL1_IDX_UPD_EN_MASK =
ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___M,
.d_CE_WRAPPER_DEBUG_OFFSET = ADRASTEA_CE_WRAPPER_DEBUG_OFFSET,
.d_CE_WRAPPER_DEBUG_SEL_MSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MSB,
.d_CE_WRAPPER_DEBUG_SEL_LSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_LSB,

150
core/hif/src/ce/ce_main.c
View File

@@ -77,6 +77,7 @@ static int hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info);
static int hif_post_recv_buffers(struct ol_softc *scn);
static void hif_config_rri_on_ddr(struct ol_softc *scn);
static void ce_poll_timeout(void *arg)
{
@@ -2244,6 +2245,8 @@ int hif_config_ce(hif_handle_t hif_hdl)
#endif
#endif
hif_config_rri_on_ddr(scn);
/* During CE initializtion */
scn->ce_count = HOST_CE_COUNT;
A_TARGET_ACCESS_LIKELY(scn);
@@ -2471,7 +2474,7 @@ u32 shadow_sr_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr)
addr = SHADOW_VALUE7;
break;
default:
printk("invalid CE ctrl_addr\n");
HIF_ERROR("invalid CE ctrl_addr\n");
CDF_ASSERT(0);
}
@@ -2497,7 +2500,7 @@ u32 shadow_dst_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr)
addr = SHADOW_VALUE20;
break;
default:
printk("invalid CE ctrl_addr\n");
HIF_ERROR("invalid CE ctrl_addr\n");
CDF_ASSERT(0);
}
@@ -2627,3 +2630,146 @@ int hif_map_service_to_pipe(struct ol_softc *scn, uint16_t svc_id,
return status;
}
#ifdef SHADOW_REG_DEBUG
inline uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct ol_softc *scn,
uint32_t CE_ctrl_addr)
{
uint32_t read_from_hw, srri_from_ddr = 0;
read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_SRRI_ADDRESS);
srri_from_ddr = SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr));
if (read_from_hw != srri_from_ddr) {
HIF_ERROR("error: read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x\n",
srri_from_ddr, read_from_hw,
CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr));
CDF_ASSERT(0);
}
return srri_from_ddr;
}
inline uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct ol_softc *scn,
uint32_t CE_ctrl_addr)
{
uint32_t read_from_hw, drri_from_ddr = 0;
read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_DRRI_ADDRESS);
drri_from_ddr = DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr));
if (read_from_hw != drri_from_ddr) {
HIF_ERROR("error: read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x\n",
drri_from_ddr, read_from_hw,
CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr));
CDF_ASSERT(0);
}
return drri_from_ddr;
}
#endif
/**
* hif_get_src_ring_read_index(): Called to get the SRRI
*
* @scn: ol_softc pointer
* @CE_ctrl_addr: base address of the CE whose RRI is to be read
*
* This function returns the SRRI to the caller. For CEs that
* dont have interrupts enabled, we look at the DDR based SRRI
*
* Return: SRRI
*/
inline unsigned int hif_get_src_ring_read_index(struct ol_softc *scn,
uint32_t CE_ctrl_addr)
{
struct CE_attr attr;
attr = host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)];
if (attr.flags & CE_ATTR_DISABLE_INTR)
return CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr);
else
return A_TARGET_READ(scn,
(CE_ctrl_addr) + CURRENT_SRRI_ADDRESS);
}
/**
* hif_get_dst_ring_read_index(): Called to get the DRRI
*
* @scn: ol_softc pointer
* @CE_ctrl_addr: base address of the CE whose RRI is to be read
*
* This function returns the DRRI to the caller. For CEs that
* dont have interrupts enabled, we look at the DDR based DRRI
*
* Return: DRRI
*/
inline unsigned int hif_get_dst_ring_read_index(struct ol_softc *scn,
uint32_t CE_ctrl_addr)
{
struct CE_attr attr;
attr = host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)];
if (attr.flags & CE_ATTR_DISABLE_INTR)
return CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr);
else
return A_TARGET_READ(scn,
(CE_ctrl_addr) + CURRENT_DRRI_ADDRESS);
}
#ifdef ADRASTEA_RRI_ON_DDR
/**
* hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism
*
* @scn: ol_softc pointer
*
* This function allocates non cached memory on ddr and sends
* the physical address of this memory to the CE hardware. The
* hardware updates the RRI on this particular location.
*
* Return: None
*/
static inline void hif_config_rri_on_ddr(struct ol_softc *scn)
{
unsigned int i;
cdf_dma_addr_t paddr_rri_on_ddr;
uint32_t high_paddr, low_paddr;
scn->vaddr_rri_on_ddr =
(uint32_t *)cdf_os_mem_alloc_consistent(scn->cdf_dev,
(CE_COUNT*sizeof(uint32_t)), &paddr_rri_on_ddr, 0);
low_paddr = BITS0_TO_31(paddr_rri_on_ddr);
high_paddr = BITS32_TO_35(paddr_rri_on_ddr);
HIF_ERROR("%s using srri and drri from DDR\n", __func__);
WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, low_paddr);
WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, high_paddr);
for (i = 0; i < CE_COUNT; i++)
CE_IDX_UPD_EN_SET(scn, CE_BASE_ADDRESS(i));
cdf_mem_zero(scn->vaddr_rri_on_ddr, CE_COUNT*sizeof(uint32_t));
return;
}
#else
/**
* hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism
*
* @scn: ol_softc pointer
*
* This is a dummy implementation for platforms that don't
* support this functionality.
*
* Return: None
*/
static inline void hif_config_rri_on_ddr(struct ol_softc *scn)
{
return;
}
#endif

92
core/hif/src/ce/ce_reg.h
View File

@@ -28,6 +28,9 @@
#ifndef __CE_REG_H__
#define __CE_REG_H__
#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \
- CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
#define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS)
#define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS)
#define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK)
@@ -102,10 +105,10 @@
#define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS)
#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \
(scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)
#define CE_WRAPPER_INDEX_BASE_LOW \
(scn->target_ce_def->d_CE_WRAPPER_INDEX_BASE_LOW)
#define CE_WRAPPER_INDEX_BASE_HIGH \
(scn->target_ce_def->d_CE_WRAPPER_INDEX_BASE_HIGH)
#define CE_DDR_ADDRESS_FOR_RRI_LOW \
(scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW)
#define CE_DDR_ADDRESS_FOR_RRI_HIGH \
(scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH)
#define HOST_IE_COPY_COMPLETE_MASK \
(scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK)
#define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS)
@@ -143,6 +146,7 @@
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
(scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
#define CE_CTRL1_DMAX_LENGTH_LSB (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB)
#define CE_CTRL1_IDX_UPD_EN (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK)
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \
(scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \
@@ -243,8 +247,52 @@
#define CE_DEBUG_SEL_GET(x) (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB)
#define CE_DEBUG_SEL_SET(x) (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK)
uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct ol_softc *scn,
uint32_t CE_ctrl_addr);
uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct ol_softc *scn,
uint32_t CE_ctrl_addr);
#define BITS0_TO_31(val) ((uint32_t)((uint64_t)(paddr_rri_on_ddr)\
& (uint64_t)(0xFFFFFFFF)))
#define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(paddr_rri_on_ddr)\
& (uint64_t)(0xF00000000))>>32))
#define VADDR_FOR_CE(scn, CE_ctrl_addr)\
((uint32_t *)((uint64_t)(scn->vaddr_rri_on_ddr) + \
COPY_ENGINE_ID(CE_ctrl_addr)*sizeof(uint32_t)))
#define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF)
#define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF)
#ifdef SHADOW_REG_DEBUG
#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)
#define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
DEBUG_CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)
#else
#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
#define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
#endif
unsigned int hif_get_src_ring_read_index(struct ol_softc *scn,
uint32_t CE_ctrl_addr);
unsigned int hif_get_dst_ring_read_index(struct ol_softc *scn,
uint32_t CE_ctrl_addr);
#ifdef ADRASTEA_RRI_ON_DDR
#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
hif_get_src_ring_read_index(scn, CE_ctrl_addr)
#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
hif_get_dst_ring_read_index(scn, CE_ctrl_addr)
#else
#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \
A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS)
#endif
#define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr))
@@ -264,6 +312,11 @@
CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \
CE_CTRL1_DMAX_LENGTH_SET(n))
#define CE_IDX_UPD_EN_SET(scn, CE_ctrl_addr) \
A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
(A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
| CE_CTRL1_IDX_UPD_EN))
#define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \
A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER)
@@ -299,8 +352,6 @@
& ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \
CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n))
#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr) \
A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS)
#define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr))
@@ -384,14 +435,6 @@
#define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \
A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask))
#define CE_WRAPPER_INDEX_BASE_LOW_SET(scn, n) \
A_TARGET_WRITE(scn, \
CE_WRAPPER_INDEX_BASE_LOW + CE_WRAPPER_BASE_ADDRESS, n)
#define CE_WRAPPER_INDEX_BASE_HIGH_SET(scn, n) \
A_TARGET_WRITE(scn, \
CE_WRAPPER_INDEX_BASE_HIGH + CE_WRAPPER_BASE_ADDRESS, n)
#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
@@ -424,6 +467,24 @@
A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \
CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
#define READ_CE_DDR_ADDRESS_FOR_RRI_LOW(scn) \
(A_TARGET_READ(scn, \
CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW))
#define READ_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn) \
(A_TARGET_READ(scn, \
CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH))
#define WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, val) \
(A_TARGET_WRITE(scn, \
CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW, \
val))
#define WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, val) \
(A_TARGET_WRITE(scn, \
CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH, \
val))
/*Macro to increment CE packet errors*/
#define OL_ATH_CE_PKT_ERROR_COUNT_INCR(_scn, _ce_ecode) \
do { if (_ce_ecode == CE_RING_DELTA_FAIL) \
@@ -442,9 +503,6 @@
#define NUM_SHADOW_REGISTERS 24
#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \
- CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
u32 shadow_sr_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr);
u32 shadow_dst_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr);
#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \

4
core/hif/src/qca6180def.h
View File

@@ -899,8 +899,8 @@ struct ce_reg_def qca6180_ce_targetdef = {
.d_CE_WRAPPER_BASE_ADDRESS = QCA6180_CE_WRAPPER_BASE_ADDRESS,
.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
.d_CE_WRAPPER_INDEX_BASE_LOW = QCA6180_CE_WRAPPER_INDEX_BASE_LOW,
.d_CE_WRAPPER_INDEX_BASE_HIGH = QCA6180_CE_WRAPPER_INDEX_BASE_HIGH,
.d_CE_DDR_ADDRESS_FOR_RRI_LOW = QCA6180_CE_WRAPPER_INDEX_BASE_LOW,
.d_CE_DDR_ADDRESS_FOR_RRI_HIGH = QCA6180_CE_WRAPPER_INDEX_BASE_HIGH,
.d_HOST_IE_ADDRESS = QCA6180_HOST_IE_ADDRESS,
.d_HOST_IE_COPY_COMPLETE_MASK = QCA6180_HOST_IE_COPY_COMPLETE_MASK,
.d_SR_BA_ADDRESS = QCA6180_SR_BA_ADDRESS,