Mahadevan 2eabb846d6 disp: msm: sde: avoid double clearing of INTR registers
When there is CPU processing delay between first INTR clear and
second INTR clear there is a chance that the second register
write might clear the next frames interrupts which will avoid
triggering the irq callbacks causing software hung. This
patch avoids such a scenario by removing such double clearing
of INTR registers.

Change-Id: I8407991769c69d2d2c691763240671d5f3c0416d
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
2025-09-20 16:38:10 +01:00
2025-08-10 14:26:58 +05:30
2025-08-03 09:05:09 +05:30
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