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[ALPS05340604] DRAM:modify dram driver for DDR400.fix f meters calculate

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modify dram driver for DDR400.fix f meters calculate

MTK-Commit-Id: 437bf94112fda16d4dd6015cbe95bdee2ff4e386

Change-Id: Ie3ff51da6f36bf1b43a42b1c94b185c7c18fe21c
Signed-off-by: jay dong <jay.dong@mediatek.com>
CR-Id: ALPS05340604
Feature: DRAM
This commit is contained in:
mtk20497
2020-09-14 12:22:33 +08:00
committed by Jay Dong
parent b67445065d
commit dd2361d1bb
3 changed files with 19 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/mediatek/mt6853.dts
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@@ -1733,8 +1733,10 @@ page_owner=on loop.max_part=7";
<0x08b4 0x00000002 1>;
fbksel = <0x070c 0x00000040 6>,
<0x070c 0x00000040 6>;
dqopen = <0x0870 0x00100000 20>,
dqsopen = <0x0870 0x00100000 20>,
<0x0870 0x00100000 20>;
dqopen = <0x0870 0x00200000 21>,
<0x0870 0x00200000 21>;
};
emichn: emichn@10235000 {

16
drivers/memory/mediatek/dramc.c
View File

@@ -65,6 +65,8 @@ static int fmeter_v1_init(struct platform_device *pdev,
"cldiv2", (unsigned int *)(fmeter_dev_ptr->cldiv2), 6);
ret |= of_property_read_u32_array(dramc_node,
"fbksel", (unsigned int *)(fmeter_dev_ptr->fbksel), 6);
ret |= of_property_read_u32_array(dramc_node,
"dqsopen", (unsigned int *)(fmeter_dev_ptr->dqsopen), 6);
ret |= of_property_read_u32_array(dramc_node,
"dqopen", (unsigned int *)(fmeter_dev_ptr->dqopen), 6);
@@ -471,6 +473,8 @@ static unsigned int decode_freq(unsigned int vco_freq)
return 1200;
case 754:
return 800;
case 396:
return 400;
}
return vco_freq;
@@ -491,6 +495,7 @@ static unsigned int fmeter_v1(struct dramc_dev_t *dramc_dev_ptr)
unsigned int offset;
unsigned int vco_freq;
unsigned int fbksel;
unsigned int dqsopen;
unsigned int dqopen;
shu_lv_val = (readl(dramc_dev_ptr->ddrphy_chn_base_nao[0] +
@@ -545,6 +550,12 @@ static unsigned int fmeter_v1(struct dramc_dev_t *dramc_dev_ptr)
fmeter_dev_ptr->fbksel[pll_id_val].mask) >>
fmeter_dev_ptr->fbksel[pll_id_val].shift;
offset = fmeter_dev_ptr->dqsopen[pll_id_val].offset +
fmeter_dev_ptr->shu_of * shu_lv_val;
dqsopen = (readl(dramc_dev_ptr->ddrphy_chn_base_ao[0] + offset) &
fmeter_dev_ptr->dqsopen[pll_id_val].mask) >>
fmeter_dev_ptr->dqsopen[pll_id_val].shift;
offset = fmeter_dev_ptr->dqopen[pll_id_val].offset +
fmeter_dev_ptr->shu_of * shu_lv_val;
dqopen = (readl(dramc_dev_ptr->ddrphy_chn_base_ao[0] + offset) &
@@ -553,7 +564,10 @@ static unsigned int fmeter_v1(struct dramc_dev_t *dramc_dev_ptr)
vco_freq = ((fmeter_dev_ptr->crystal_freq >> prediv_val) *
(sdmpcw_val >> 8)) >> posdiv_val >> ckdiv4_val >>
pll_md_val >> cldiv2_val << fbksel >> (dqopen << 1);
pll_md_val >> cldiv2_val << fbksel;
if (dqsopen == 1 || dqopen == 1)
vco_freq >>= 2;
return decode_freq(vco_freq);
}

1
include/memory/mediatek/dramc.h
View File

@@ -31,6 +31,7 @@ struct fmeter_dev_t {
struct reg_ctrl_t ckdiv4[2];
struct reg_ctrl_t cldiv2[2];
struct reg_ctrl_t fbksel[2];
struct reg_ctrl_t dqsopen[2];
struct reg_ctrl_t dqopen[2];
};