arm64/dts: Import realme dts files

Signed-off-by: SagarMakhar <sagarmakhar@gmail.com>

arch/arm64/boot/dts/19721/Makefile

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0
+
+
+dtbo-$(CONFIG_ARCH_ATOLL) += \
+	atollp-idp-overlay.dtbo\
+	atoll-ab-idp-overlay.dtbo
+
+atoll-idp-overlay.dtbo-base := atoll.dtb
+atoll-ab-idp-overlay.dtbo-base := atoll-ab.dtb
+
+always		:= $(dtb-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb *.dtbo

arch/arm64/boot/dts/19721/apq8016-sbc-pmic-pins.dtsi

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
+
+&pm8916_gpios {
+
+	usb_hub_reset_pm: usb_hub_reset_pm {
+		pinconf {
+			pins = "gpio3";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			output-low;
+		};
+	};
+
+	usb_sw_sel_pm: usb_sw_sel_pm {
+		pinconf {
+			pins = "gpio4";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			power-source = <PM8916_GPIO_VPH>;
+			input-disable;
+			output-high;
+		};
+	};
+
+	pm8916_gpios_leds: pm8916_gpios_leds {
+		pinconf {
+			pins = "gpio1", "gpio2";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			output-low;
+		};
+	};
+};
+
+&pm8916_mpps {
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&ls_exp_gpio_f>;
+
+	ls_exp_gpio_f: pm8916_mpp4 {
+		pinconf {
+			pins = "mpp4";
+			function = "digital";
+			output-low;
+			power-source = <PM8916_MPP_L5>;	// 1.8V
+		};
+	};
+
+	pm8916_mpps_leds: pm8916_mpps_leds {
+		pinconf {
+			pins = "mpp2", "mpp3";
+			function = "digital";
+			output-low;
+		};
+	};
+};

arch/arm64/boot/dts/19721/apq8016-sbc-soc-pins.dtsi

@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/gpio/gpio.h>
+
+&msmgpio {
+
+	msmgpio_leds: msmgpio_leds {
+		pinconf {
+			pins = "gpio21", "gpio120";
+			function = "gpio";
+			output-low;
+		};
+	};
+
+	usb_id_default: usb-id-default {
+		pinmux {
+			function = "gpio";
+			pins = "gpio121";
+		};
+
+		pinconf {
+			pins = "gpio121";
+			drive-strength = <8>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
+	adv7533_int_active: adv533_int_active {
+		pinmux {
+			function = "gpio";
+			pins = "gpio31";
+		};
+		pinconf {
+			pins = "gpio31";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	adv7533_int_suspend: adv7533_int_suspend {
+		pinmux {
+			function = "gpio";
+			pins = "gpio31";
+		};
+		pinconf {
+			pins = "gpio31";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
+	adv7533_switch_active: adv7533_switch_active {
+		pinmux {
+			function = "gpio";
+			pins = "gpio32";
+		};
+		pinconf {
+			pins = "gpio32";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	adv7533_switch_suspend: adv7533_switch_suspend {
+		pinmux {
+			function = "gpio";
+			pins = "gpio32";
+		};
+		pinconf {
+			pins = "gpio32";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
+	msm_key_volp_n_default: msm_key_volp_n_default {
+		pinmux {
+			function = "gpio";
+			pins = "gpio107";
+		};
+		pinconf {
+			pins = "gpio107";
+			drive-strength = <8>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+};

arch/arm64/boot/dts/19721/apq8016-sbc.dts

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "apq8016-sbc.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
+	compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc";
+};

arch/arm64/boot/dts/19721/apq8016-sbc.dtsi

@@ -0,0 +1,502 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "msm8916.dtsi"
+#include "pm8916.dtsi"
+#include "apq8016-sbc-soc-pins.dtsi"
+#include "apq8016-sbc-pmic-pins.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/sound/apq8016-lpass.h>
+
+/ {
+	aliases {
+		serial0 = &blsp1_uart2;
+		serial1 = &blsp1_uart1;
+		usid0 = &pm8916_0;
+		i2c0	= &blsp_i2c2;
+		i2c1	= &blsp_i2c6;
+		i2c3	= &blsp_i2c4;
+		spi0	= &blsp_spi5;
+		spi1	= &blsp_spi3;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	reserved-memory {
+		ramoops@bff00000{
+			compatible = "ramoops";
+			reg = <0x0 0xbff00000 0x0 0x100000>;
+
+			record-size = <0x20000>;
+			console-size = <0x20000>;
+			ftrace-size = <0x20000>;
+		};
+	};
+
+	soc {
+		dma@7884000 {
+			status = "okay";
+		};
+
+		serial@78af000 {
+			label = "LS-UART0";
+			status = "okay";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp1_uart1_default>;
+			pinctrl-1 = <&blsp1_uart1_sleep>;
+		};
+
+		serial@78b0000 {
+			label = "LS-UART1";
+			status = "okay";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp1_uart2_default>;
+			pinctrl-1 = <&blsp1_uart2_sleep>;
+		};
+
+		i2c@78b6000 {
+		/* On Low speed expansion */
+			label = "LS-I2C0";
+			status = "okay";
+		};
+
+		i2c@78b8000 {
+		/* On High speed expansion */
+			label = "HS-I2C2";
+			status = "okay";
+
+			adv_bridge: bridge@39 {
+				status = "okay";
+
+				compatible = "adi,adv7533";
+				reg = <0x39>;
+
+				interrupt-parent = <&msmgpio>;
+				interrupts = <31 2>;
+
+				adi,dsi-lanes = <4>;
+				clocks = <&rpmcc RPM_SMD_BB_CLK2>;
+				clock-names = "cec";
+
+				pd-gpios = <&msmgpio 32 0>;
+
+				avdd-supply = <&pm8916_l6>;
+				v1p2-supply = <&pm8916_l6>;
+				v3p3-supply = <&pm8916_l17>;
+
+				pinctrl-names = "default","sleep";
+				pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>;
+				pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>;
+				#sound-dai-cells = <1>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						adv7533_in: endpoint {
+							remote-endpoint = <&dsi0_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						adv7533_out: endpoint {
+							remote-endpoint = <&hdmi_con>;
+						};
+					};
+				};
+			};
+		};
+
+		i2c@78ba000 {
+		/* On Low speed expansion */
+			label = "LS-I2C1";
+			status = "okay";
+		};
+
+		spi@78b7000 {
+		/* On High speed expansion */
+			label = "HS-SPI1";
+			status = "okay";
+		};
+
+		spi@78b9000 {
+		/* On Low speed expansion */
+			label = "LS-SPI0";
+			status = "okay";
+		};
+
+		leds {
+			pinctrl-names = "default";
+			pinctrl-0 = <&msmgpio_leds>,
+				    <&pm8916_gpios_leds>,
+				    <&pm8916_mpps_leds>;
+
+			compatible = "gpio-leds";
+
+			led@1 {
+				label = "apq8016-sbc:green:user1";
+				gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "heartbeat";
+				default-state = "off";
+			};
+
+			led@2 {
+				label = "apq8016-sbc:green:user2";
+				gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "mmc0";
+				default-state = "off";
+			};
+
+			led@3 {
+				label = "apq8016-sbc:green:user3";
+				gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "mmc1";
+				default-state = "off";
+			};
+
+			led@4 {
+				label = "apq8016-sbc:green:user4";
+				gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "none";
+				default-state = "off";
+			};
+
+			led@5 {
+				label = "apq8016-sbc:yellow:wlan";
+				gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "phy0tx";
+				default-state = "off";
+			};
+
+			led@6 {
+				label = "apq8016-sbc:blue:bt";
+				gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "bluetooth-power";
+				default-state = "off";
+			};
+		};
+
+		sdhci@07824000 {
+			vmmc-supply = <&pm8916_l8>;
+			vqmmc-supply = <&pm8916_l5>;
+
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
+			pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
+			status = "okay";
+		};
+
+		sdhci@07864000 {
+			vmmc-supply = <&pm8916_l11>;
+			vqmmc-supply = <&pm8916_l12>;
+
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+			pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+			cd-gpios = <&msmgpio 38 0x1>;
+			status = "okay";
+		};
+
+		usb@78d9000 {
+			extcon = <&usb_id>;
+			status = "okay";
+			adp-disable;
+			hnp-disable;
+			srp-disable;
+			dr_mode = "host";
+			pinctrl-names = "default";
+			pinctrl-0 = <&usb_sw_sel_pm>;
+			ulpi {
+				phy {
+					v1p8-supply = <&pm8916_l7>;
+					v3p3-supply = <&pm8916_l13>;
+					extcon = <&usb_id>;
+				};
+			};
+		};
+
+		lpass@07708000 {
+			status = "okay";
+		};
+
+		mdss@1a00000 {
+			status = "okay";
+
+			mdp@1a01000 {
+				status = "okay";
+			};
+
+			dsi@1a98000 {
+				status = "okay";
+
+				vdda-supply = <&pm8916_l2>;
+				vddio-supply = <&pm8916_l6>;
+
+				ports {
+					port@1 {
+						endpoint {
+							remote-endpoint = <&adv7533_in>;
+							data-lanes = <0 1 2 3>;
+						};
+					};
+				};
+			};
+
+			dsi-phy@1a98300 {
+				status = "okay";
+
+				vddio-supply = <&pm8916_l6>;
+			};
+		};
+
+		lpass_codec: codec{
+			status = "okay";
+		};
+
+		/*
+		Internal Codec
+			playback - Primary MI2S
+			capture - Ter MI2S
+
+		External Primary:
+			playback - secondary MI2S
+			capture - Quat MI2S
+
+		External Secondary:
+			playback - Quat MI2S
+			capture - Quat MI2S
+
+		*/
+
+                sound: sound {
+                        compatible = "qcom,apq8016-sbc-sndcard";
+                        reg = <0x07702000 0x4>, <0x07702004 0x4>;
+                        reg-names = "mic-iomux", "spkr-iomux";
+
+                        status = "okay";
+                        pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
+                        pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
+                        pinctrl-names = "default", "sleep";
+                        qcom,model = "DB410c";
+                        qcom,audio-routing =
+                                "AMIC2", "MIC BIAS Internal2",
+                                "AMIC3", "MIC BIAS External1";
+			external-dai-link@0 {
+				link-name = "ADV7533";
+				cpu { /* QUAT */
+					sound-dai = <&lpass MI2S_QUATERNARY>;
+				};
+				codec {
+					sound-dai = <&adv_bridge 0>;
+				};
+			};
+
+                        internal-codec-playback-dai-link@0 {            /* I2S - Internal codec */
+                                link-name = "WCD";
+                                cpu { /* PRIMARY */
+                                        sound-dai = <&lpass MI2S_PRIMARY>;
+                                };
+                                codec {
+                                        sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
+                                };
+                        };
+
+                        internal-codec-capture-dai-link@0 {             /* I2S - Internal codec */
+                                link-name = "WCD-Capture";
+                                cpu { /* PRIMARY */
+                                        sound-dai = <&lpass MI2S_TERTIARY>;
+                                };
+                                codec {
+                                        sound-dai = <&lpass_codec 1>, <&wcd_codec 1>;
+                                };
+                        };
+                };
+
+		wcnss@a21b000 {
+			status = "okay";
+		};
+	};
+
+	usb2513 {
+		compatible = "smsc,usb3503";
+		reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>;
+		initial-mode = <1>;
+	};
+
+	usb_id: usb-id {
+		compatible = "linux,extcon-usb-gpio";
+		vbus-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_id_default>;
+	};
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&adv7533_out>;
+			};
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&msm_key_volp_n_default>;
+
+		button@0 {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&wcd_codec {
+        status = "okay";
+        clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
+        clock-names = "mclk";
+};
+
+&smd_rpm_regulators {
+	vdd_l1_l2_l3-supply = <&pm8916_s3>;
+	vdd_l5-supply = <&pm8916_s3>;
+	vdd_l4_l5_l6-supply = <&pm8916_s4>;
+	vdd_l7-supply = <&pm8916_s4>;
+
+	s1 {
+		regulator-min-microvolt = <375000>;
+		regulator-max-microvolt = <1562000>;
+	};
+
+	s3 {
+		regulator-min-microvolt = <375000>;
+		regulator-max-microvolt = <1562000>;
+	};
+
+	s4 {
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	l1 {
+		regulator-min-microvolt = <375000>;
+		regulator-max-microvolt = <1525000>;
+	};
+
+	l2 {
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+	};
+
+	l3 {
+		regulator-min-microvolt = <375000>;
+		regulator-max-microvolt = <1525000>;
+	};
+
+	l4 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	l5 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	l6 {
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	l7 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	l8 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	l9 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	l10 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	l11 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	l12 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	l13 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	l14 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	/**
+	 * 1.8v required on LS expansion
+	 * for mezzanine boards
+	 */
+	l15 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+		regulator-always-on;
+	};
+
+	l16 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+
+	l17 {
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	l18 {
+		regulator-min-microvolt = <1750000>;
+		regulator-max-microvolt = <3337000>;
+	};
+};

arch/arm64/boot/dts/19721/apq8096-db820c-pins.dtsi

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+&msmgpio {
+	sdc2_cd_on: sdc2_cd_on {
+		mux {
+			pins = "gpio38";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio38";
+			bias-pull-up;		/* pull up */
+			drive-strength = <16>;	/* 16 MA */
+		};
+	};
+
+	sdc2_cd_off: sdc2_cd_off {
+		mux {
+			pins = "gpio38";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio38";
+			bias-pull-up;		/* pull up */
+			drive-strength = <2>;	/* 2 MA */
+		};
+	};
+};

arch/arm64/boot/dts/19721/apq8096-db820c-pmic-pins.dtsi

@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+&pm8994_gpios {
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&ls_exp_gpio_f>;
+
+	ls_exp_gpio_f: pm8994_gpio5 {
+		pinconf {
+			pins = "gpio5";
+			output-low;
+			power-source = <2>; // PM8994_GPIO_S4, 1.8V
+		};
+	};
+
+	volume_up_gpio: pm8996_gpio2 {
+		pinconf {
+			pins = "gpio2";
+			function = "normal";
+			input-enable;
+			drive-push-pull;
+			bias-pull-up;
+			qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+			power-source = <PM8994_GPIO_S4>; // 1.8V
+		};
+	};
+
+	usb3_vbus_det_gpio: pm8996_gpio22 {
+		pinconf {
+			pins = "gpio22";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			input-enable;
+			bias-pull-down;
+			qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+			power-source = <PM8994_GPIO_S4>; // 1.8V
+		};
+	};
+};
+
+&pmi8994_gpios {
+	usb2_vbus_det_gpio: pmi8996_gpio6 {
+		pinconf {
+			pins = "gpio6";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			input-enable;
+			bias-pull-down;
+			qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+			power-source = <PM8994_GPIO_S4>; // 1.8V
+		};
+	};
+};

arch/arm64/boot/dts/19721/apq8096-db820c.dts

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "apq8096-db820c.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. DB820c";
+	compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
+};

arch/arm64/boot/dts/19721/apq8096-db820c.dtsi

@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "msm8996.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include "apq8096-db820c-pins.dtsi"
+#include "apq8096-db820c-pmic-pins.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	aliases {
+		serial0 = &blsp2_uart1;
+		serial1 = &blsp2_uart2;
+		i2c0	= &blsp1_i2c2;
+		i2c1	= &blsp2_i2c1;
+		i2c2	= &blsp2_i2c0;
+		spi0	= &blsp1_spi0;
+		spi1	= &blsp2_spi5;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	soc {
+		serial@75b0000 {
+			label = "LS-UART1";
+			status = "okay";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp2_uart1_2pins_default>;
+			pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
+		};
+
+		serial@75b1000 {
+			label = "LS-UART0";
+			status = "okay";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp2_uart2_4pins_default>;
+			pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
+		};
+
+		i2c@07577000 {
+		/* On Low speed expansion */
+			label = "LS-I2C0";
+			status = "okay";
+		};
+
+		i2c@075b6000 {
+		/* On Low speed expansion */
+			label = "LS-I2C1";
+			status = "okay";
+		};
+
+		spi@07575000 {
+		/* On Low speed expansion */
+			label = "LS-SPI0";
+			status = "okay";
+		};
+
+		i2c@075b5000 {
+		/* On High speed expansion */
+			label = "HS-I2C2";
+			status = "okay";
+		};
+
+		spi@075ba000{
+		/* On High speed expansion */
+			label = "HS-SPI1";
+			status = "okay";
+		};
+
+		sdhci@74a4900 {
+		/* External SD card */
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+			pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+			cd-gpios = <&msmgpio 38 0x1>;
+			status = "okay";
+		};
+
+		phy@34000 {
+			status = "okay";
+		};
+
+		phy@7410000 {
+			status = "okay";
+		};
+
+		phy@7411000 {
+			status = "okay";
+		};
+
+		phy@7412000 {
+			status = "okay";
+		};
+
+		usb@6a00000 {
+			status = "okay";
+
+			dwc3@6a00000 {
+				extcon = <&usb3_id>;
+				dr_mode = "otg";
+			};
+		};
+
+		usb3_id: usb3-id {
+			compatible = "linux,extcon-usb-gpio";
+			id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&usb3_vbus_det_gpio>;
+		};
+
+		usb@7600000 {
+			status = "okay";
+
+			dwc3@7600000 {
+				extcon = <&usb2_id>;
+				dr_mode = "otg";
+				maximum-speed = "high-speed";
+			};
+		};
+
+		usb2_id: usb2-id {
+			compatible = "linux,extcon-usb-gpio";
+			id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&usb2_vbus_det_gpio>;
+		};
+	};
+
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&volume_up_gpio>;
+
+		button@0 {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	rpm-glink {
+		rpm_requests {
+			pm8994-regulators {
+				vdd_l1-supply = <&pm8994_s3>;
+				vdd_l2_l26_l28-supply = <&pm8994_s3>;
+				vdd_l3_l11-supply = <&pm8994_s3>;
+				vdd_l4_l27_l31-supply = <&pm8994_s3>;
+				vdd_l5_l7-supply = <&pm8994_s5>;
+				vdd_l14_l15-supply = <&pm8994_s5>;
+				vdd_l20_l21-supply = <&pm8994_s5>;
+				vdd_l25-supply = <&pm8994_s3>;
+
+				s3 {
+					regulator-min-microvolt = <1300000>;
+					regulator-max-microvolt = <1300000>;
+				};
+				s4 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+				s5 {
+					regulator-min-microvolt = <2150000>;
+					regulator-max-microvolt = <2150000>;
+				};
+				s7 {
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <800000>;
+				};
+
+				l1 {
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+				};
+				l2 {
+					regulator-min-microvolt = <1250000>;
+					regulator-max-microvolt = <1250000>;
+				};
+				l3 {
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <850000>;
+				};
+				l4 {
+					regulator-min-microvolt = <1225000>;
+					regulator-max-microvolt = <1225000>;
+				};
+				l6 {
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+				l8 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+				l9 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+				l10 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+				l11 {
+					regulator-min-microvolt = <1150000>;
+					regulator-max-microvolt = <1150000>;
+				};
+				l12 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+				l13 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <2950000>;
+				};
+				l14 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+				l15 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+				l16 {
+					regulator-min-microvolt = <2700000>;
+					regulator-max-microvolt = <2700000>;
+				};
+				l17 {
+					regulator-min-microvolt = <2500000>;
+					regulator-max-microvolt = <2500000>;
+				};
+				l18 {
+					regulator-min-microvolt = <2700000>;
+					regulator-max-microvolt = <2900000>;
+				};
+				l19 {
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+				};
+				l20 {
+					regulator-min-microvolt = <2950000>;
+					regulator-max-microvolt = <2950000>;
+					regulator-allow-set-load;
+				};
+				l21 {
+					regulator-min-microvolt = <2950000>;
+					regulator-max-microvolt = <2950000>;
+				};
+				l22 {
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+				l23 {
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+				l24 {
+					regulator-min-microvolt = <3075000>;
+					regulator-max-microvolt = <3075000>;
+				};
+				l25 {
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-allow-set-load;
+				};
+				l27 {
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+				};
+				l28 {
+					regulator-min-microvolt = <925000>;
+					regulator-max-microvolt = <925000>;
+					regulator-allow-set-load;
+				};
+				l29 {
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+				l30 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+				l32 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/atoll-ab-atp-overlay.dts

@@ -0,0 +1,36 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "atoll-atp.dtsi"
+#include "atoll-audio-overlay.dtsi"
+
+/ {
+	model = "ATP";
+	compatible = "qcom,atoll-ab-idp", "qcom,atoll-ab", "qcom,idp", "qcom,atp";
+	qcom,msm-id = <443 0x0>;
+	qcom,board-id = <33 0>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};
+
+&tx_swr_gpios {
+	qcom,chip-wakeup-reg = <0x01FFB000>;
+	qcom,chip-wakeup-maskbit = <0>;
+	qcom,chip-wakeup-default-val = <0x1>;
+};

arch/arm64/boot/dts/19721/atoll-ab-atp.dts

@@ -0,0 +1,23 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll-ab.dtsi"
+#include "atoll-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL-AB PM6150 ATP";
+	compatible = "qcom,atoll-ab-idp", "qcom,atoll-ab",
+			"qcom,idp", "qcom,atp";
+	qcom,board-id = <33 0>;
+};

arch/arm64/boot/dts/19721/atoll-ab-idp-overlay.dts

@@ -0,0 +1,37 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "atoll-idp.dtsi"
+#include "atoll-audio-overlay.dtsi"
+
+/ {
+	model = "IDP";
+	compatible = "qcom,atoll-ab-idp", "qcom,atoll-ab", "qcom,idp";
+	qcom,msm-id = <443 0x0>;
+	qcom,board-id = <34 0>;
+	oppo,dtsi_no = <19721>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};
+
+&tx_swr_gpios {
+	qcom,chip-wakeup-reg = <0x01FFB000>;
+	qcom,chip-wakeup-maskbit = <0>;
+	qcom,chip-wakeup-default-val = <0x1>;
+};

arch/arm64/boot/dts/19721/atoll-ab-idp.dts

@@ -0,0 +1,26 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll-ab.dtsi"
+#include "atoll-idp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL-AB PM6150 IDP";
+	compatible = "qcom,atoll-ab-idp", "qcom,atoll-ab", "qcom,idp";
+	qcom,board-id = <34 0>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};

arch/arm64/boot/dts/19721/atoll-ab-qrd-overlay.dts

@@ -0,0 +1,23 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "atoll-qrd.dtsi"
+
+/ {
+	model = "QRD";
+	compatible = "qcom,atoll-ab-qrd", "qcom,atoll-ab", "qcom,qrd";
+	qcom,msm-id = <443 0x0>;
+	qcom,board-id = <0x1000B 0>;
+};

arch/arm64/boot/dts/19721/atoll-ab-qrd.dts

@@ -0,0 +1,28 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll-ab.dtsi"
+#include "atoll-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL-AB PM6150 QRD";
+	compatible = "qcom,atoll-ab-qrd", "qcom,atoll-ab", "qcom,qrd";
+	qcom,board-id = <0x1000B 0>;
+};
+
+&tx_swr_gpios {
+	qcom,chip-wakeup-reg = <0x01FFB000>;
+	qcom,chip-wakeup-maskbit = <0>;
+	qcom,chip-wakeup-default-val = <0x1>;
+};

arch/arm64/boot/dts/19721/atoll-ab.dts

@@ -0,0 +1,23 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll-ab.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL-AB SoC";
+	compatible = "qcom,atoll";
+	qcom,pmic-name = "PM6150";
+	qcom,board-id = <0 0>;
+	oppo,dtsi_no = <19721>;
+};

arch/arm64/boot/dts/19721/atoll-ab.dtsi

@@ -0,0 +1,19 @@
+/* Copyright (c) 2019, The Linux Foundation.All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "atoll.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL-AB";
+	qcom,msm-name = "ATOLL-AB";
+	qcom,msm-id = <443 0x0>;
+};

arch/arm64/boot/dts/19721/atoll-atp-overlay.dts

@@ -0,0 +1,30 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "atoll-atp.dtsi"
+#include "atoll-audio-overlay.dtsi"
+
+/ {
+	model = "ATP";
+	compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp", "qcom,atp";
+	qcom,msm-id = <407 0x0>;
+	qcom,board-id = <33 0>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};

arch/arm64/boot/dts/19721/atoll-atp.dts

@@ -0,0 +1,22 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll.dtsi"
+#include "atoll-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL PM6150 ATP";
+	compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp", "qcom,atp";
+	qcom,board-id = <33 0>;
+};

arch/arm64/boot/dts/19721/atoll-atp.dtsi

@@ -0,0 +1,302 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "sdmmagpie-thermal-overlay.dtsi"
+#include "atoll-sde-display.dtsi"
+
+&soc {
+	mtp_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+		#include "qg-batterydata-alium-3600mah.dtsi"
+	};
+};
+
+&pm6150l_vadc {
+	pa_therm1 {
+		reg = <ADC_AMUX_THM3_PU2>;
+		label = "pa_therm1";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm6150l_adc_tm {
+	io-channels = <&pm6150l_vadc ADC_AMUX_THM1_PU2>,
+			<&pm6150l_vadc ADC_AMUX_THM2_PU2>,
+			<&pm6150l_vadc ADC_AMUX_THM3_PU2>,
+			<&pm6150l_vadc ADC_GPIO1_PU2>;
+
+	pa_therm1 {
+		reg = <ADC_AMUX_THM3_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&usb0 {
+	extcon = <&pm6150_pdphy>, <&pm6150_charger>, <&eud>;
+};
+
+&usb_qmp_dp_phy {
+	extcon = <&pm6150_pdphy>;
+};
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v3";
+
+	vdda-phy-supply = <&pm6150_l4>; /* 0.9v */
+	vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */
+	vdda-phy-max-microamp = <62900>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&ufs_phy_gdsc>;
+	vdd-hba-fixed-regulator;
+	vcc-supply = <&pm6150_l19>;
+	vcc-voltage-level = <2960000 2960000>;
+	vcc-max-microamp = <600000>;
+	vccq2-supply = <&pm6150_l12>;
+	vccq2-voltage-level = <1750000 1950000>;
+	vccq2-max-microamp = <600000>;
+
+	qcom,vddp-ref-clk-supply = <&pm6150l_l3>; /* PX10 */
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	status = "ok";
+};
+
+&sdhc_1 {
+	vdd-supply = <&pm6150_l19>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&pm6150_l12>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+	status = "ok";
+};
+
+&sdhc_2 {
+	vdd-supply = <&pm6150l_l9>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&pm6150l_l6>;
+	qcom,vdd-io-voltage-level = <1800000 2950000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+	cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
+
+	status = "ok";
+};
+
+&thermal_zones {
+	pa-therm1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm6150l_adc_tm ADC_AMUX_THM3_PU2>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
+&pm6150a_amoled {
+	status = "ok";
+};
+
+&pm6150_qg {
+	qcom,battery-data = <&mtp_batterydata>;
+	qcom,qg-iterm-ma = <100>;
+	qcom,hold-soc-while-full;
+	qcom,linearize-soc;
+	qcom,cl-feedback-on;
+};
+
+&pm6150_charger {
+	io-channels = <&pm6150_vadc ADC_USB_IN_V_16>,
+		      <&pm6150_vadc ADC_USB_IN_I>,
+		      <&pm6150_vadc ADC_CHG_TEMP>,
+		      <&pm6150_vadc ADC_DIE_TEMP>,
+		      <&pm6150_vadc ADC_AMUX_THM3_PU2>,
+		      <&pm6150_vadc ADC_SBUx>,
+		      <&pm6150_vadc ADC_VPH_PWR>;
+	io-channel-names = "usb_in_voltage",
+			   "usb_in_current",
+			   "chg_temp",
+			   "die_temp",
+			   "conn_temp",
+			   "sbux_res",
+			   "vph_voltage";
+	qcom,battery-data = <&mtp_batterydata>;
+	qcom,auto-recharge-soc = <98>;
+	qcom,step-charging-enable;
+	qcom,sw-jeita-enable;
+	qcom,fcc-stepping-enable;
+	qcom,suspend-input-on-debug-batt;
+	qcom,sec-charger-config = <3>;
+	qcom,thermal-mitigation = <4200000 3500000 3000000
+			2500000 2000000 1500000 1000000 500000>;
+	dpdm-supply = <&qusb_phy0>;
+	qcom,charger-temp-max = <800>;
+	qcom,smb-temp-max = <800>;
+	qcom,disable-sw-thermal-regulation;
+	qcom,disable-fcc-restriction;
+};
+
+&pm6150l_gpios {
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio2";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			linux,can-disable;
+			debounce-interval = <15>;
+			gpio-key,wakeup;
+		};
+	};
+};
+
+&qupv3_se0_i2c {
+	status = "ok";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,nq-nci";
+		reg = <0x28>;
+		qcom,nq-irq = <&tlmm 37 0x00>;
+		qcom,nq-ven = <&tlmm 12 0x00>;
+		qcom,nq-firm = <&tlmm 36 0x00>;
+		qcom,nq-clkreq = <&tlmm 31 0x00>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <37 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active
+				&nfc_clk_req_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+				&nfc_clk_req_suspend>;
+	};
+};
+
+&qupv3_se7_i2c {
+	status = "ok";
+
+	synaptics_tcm@20 {
+		compatible = "synaptics,tcm-i2c";
+		reg = <0x20>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <9 0x2008>;
+		pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+			"pmx_ts_release";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+		vdd-supply = <&pm6150_l10>;
+		avdd-supply = <&pm6150l_l7>;
+		synaptics,pwr-reg-name = "avdd";
+		synaptics,bus-reg-name = "vdd";
+		synaptics,irq-gpio = <&tlmm 9 0x2008>;
+		synaptics,irq-on-state = <0>;
+		synaptics,reset-gpio = <&tlmm 8 0x00>;
+		synaptics,reset-on-state = <0>;
+		synaptics,reset-active-ms = <20>;
+		synaptics,reset-delay-ms = <200>;
+		synaptics,power-delay-ms = <200>;
+		synaptics,ubl-i2c-addr = <0x20>;
+	};
+};
+
+&dsi_rm69299_visionox_amoled_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <255>;
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+};
+
+&dsi_rm69299_visionox_amoled_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <255>;
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+};
+
+&dsi_sim_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+};
+
+&dsi_sim_vid {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+};
+
+&sde_dp {
+	 qcom,dp-aux-switch=<&fsa4480>;
+};

arch/arm64/boot/dts/19721/atoll-audio-overlay.dtsi

@@ -0,0 +1,686 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "atoll-lpi.dtsi"
+#include <dt-bindings/clock/qcom,audio-ext-clk-v2.h>
+#include <dt-bindings/sound/audio-codec-port-types.h>
+#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
+
+&bolero {
+	//#ifndef OPLUS_ARCH_EXTENDS
+	//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Modify for disable wsa
+	//qcom,num-macros = <4>;
+	//#else /* OPLUS_ARCH_EXTENDS */
+	qcom,num-macros = <3>;
+	//#endif /* OPLUS_ARCH_EXTENDS */
+	bolero-clk-rsc-mngr {
+		compatible = "qcom,bolero-clk-rsc-mngr";
+		qcom,fs-gen-sequence = <0x3000 0x1>, <0x3004 0x1>, <0x3080 0x2>;
+	qcom,rx_mclk_mode_muxsel = <0x627240D8>;
+	qcom,wsa_mclk_mode_muxsel = <0x627220D8>;
+	qcom,va_mclk_mode_muxsel = <0x627A0000>;
+
+	clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
+			"wsa_core_clk", "wsa_npl_clk", "va_core_clk",
+			"va_npl_clk";
+	clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
+		<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
+		<&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
+		<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
+	};
+
+	tx_macro: tx-macro@62620000 {
+		compatible = "qcom,tx-macro";
+		reg = <0x62620000 0x0>;
+		clock-names = "tx_core_clk", "tx_npl_clk";
+		clocks = <&clock_audio_tx_1 0>,
+			 <&clock_audio_tx_2 0>;
+		qcom,tx-swr-gpios = <&tx_swr_gpios>;
+		qcom,tx-dmic-sample-rate = <2400000>;
+		swr2: tx_swr_master {
+			compatible = "qcom,swr-mstr";
+			#address-cells = <2>;
+			#size-cells = <0>;
+			clock-names = "lpass_core_hw_vote",
+					"lpass_audio_hw_vote";
+			clocks = <&lpass_core_hw_vote 0>,
+					<&lpass_audio_hw_vote 0>;
+			qcom,swr_master_id = <3>;
+			swrm-io-base = <0x62630000 0x0>;
+			qcom,mipi-sdw-block-packing-mode = <1>;
+			interrupts = <0 296 0>, <0 555 0>;
+			interrupt-names = "swr_master_irq", "swr_wake_irq";
+			qcom,swr-wakeup-required = <0>;
+			qcom,swr-num-ports = <5>;
+			qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
+				<2 ADC1 0x1>, <2 ADC2 0x2>,
+				<3 ADC3 0x1>, <3 ADC4 0x2>,
+				<4 DMIC0 0x1>, <4 DMIC1 0x2>,
+				<4 DMIC2 0x4>, <4 DMIC3 0x8>,
+				<5 DMIC4 0x1>, <5 DMIC5 0x2>,
+				<5 DMIC6 0x4>, <5 DMIC7 0x8>;
+			qcom,swr-num-dev = <1>;
+			qcom,swr-clock-stop-mode0 = <1>;
+			qcom,swr-mstr-irq-wakeup-capable = <1>;
+			wcd938x_tx_slave: wcd938x-tx-slave {
+				//#ifdef OPLUS_ARCH_EXTENDS
+				//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for use wcd937x codec
+				status = "disabled";
+				//#endif /* OPLUS_ARCH_EXTENDS */
+				compatible = "qcom,wcd938x-slave";
+				reg = <0x0D 0x01170223>;
+			};
+			wcd937x_tx_slave: wcd937x-tx-slave {
+				//#ifndef OPLUS_ARCH_EXTENDS
+				//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Delete for use wcd937x codec
+				//status = "disabled";
+				//#endif /* OPLUS_ARCH_EXTENDS */
+				compatible = "qcom,wcd937x-slave";
+				reg = <0x0A 0x01170223>;
+			};
+		};
+	};
+
+	rx_macro: rx-macro@62600000 {
+		compatible = "qcom,rx-macro";
+		reg = <0x62600000 0x0>;
+		clock-names = "rx_core_clk", "rx_npl_clk";
+		clocks = <&clock_audio_rx_1 0>,
+			 <&clock_audio_rx_2 0>;
+		qcom,rx-swr-gpios = <&rx_swr_gpios>;
+		qcom,rx_mclk_mode_muxsel = <0x627240D8>;
+		qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
+		qcom,default-clk-id = <TX_CORE_CLK>;
+		swr1: rx_swr_master {
+			compatible = "qcom,swr-mstr";
+			#address-cells = <2>;
+			#size-cells = <0>;
+			clock-names = "lpass_core_hw_vote",
+					"lpass_audio_hw_vote";
+			clocks = <&lpass_core_hw_vote 0>,
+					<&lpass_audio_hw_vote 0>;
+			qcom,swr_master_id = <2>;
+			swrm-io-base = <0x62610000 0x0>;
+			interrupts = <0 297 0>;
+			interrupt-names = "swr_master_irq";
+			qcom,swr-num-ports = <5>;
+			qcom,swr-port-mapping = <1 HPH_L 0x1>,
+				<1 HPH_R 0x2>, <2 CLSH 0x1>,
+				<3 COMP_L 0x1>, <3 COMP_R 0x2>,
+				<4 LO 0x1>, <5 DSD_L 0x1>,
+				<5 DSD_R 0x2>;
+			qcom,swr-num-dev = <1>;
+			qcom,swr-clock-stop-mode0 = <1>;
+			wcd938x_rx_slave: wcd938x-rx-slave {
+				//#ifdef OPLUS_ARCH_EXTENDS
+				//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for use wcd937x codec
+				status = "disabled";
+				//#endif /* OPLUS_ARCH_EXTENDS */
+				compatible = "qcom,wcd938x-slave";
+				reg = <0x0D 0x01170224>;
+			};
+			wcd937x_rx_slave: wcd937x-rx-slave {
+				//#ifndef OPLUS_ARCH_EXTENDS
+				//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Delete for use wcd937x codec
+				//status = "disabled";
+				//#endif /* OPLUS_ARCH_EXTENDS */
+				compatible = "qcom,wcd937x-slave";
+				reg = <0x0A 0x01170224>;
+			};
+		};
+	};
+
+	wsa_macro: wsa-macro@62640000 {
+		//#ifdef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for disable wsa
+		status = "disabled";
+		//#endif /* OPLUS_ARCH_EXTENDS */
+		compatible = "qcom,wsa-macro";
+		reg = <0x62640000 0x0>;
+		clock-names = "wsa_core_clk", "wsa_npl_clk";
+		clocks = <&clock_audio_wsa_1 0>,
+			 <&clock_audio_wsa_2 0>;
+		qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
+		qcom,wsa_mclk_mode_muxsel = <0x627220D8>;
+		qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
+		qcom,default-clk-id = <TX_CORE_CLK>;
+		swr0: wsa_swr_master {
+			compatible = "qcom,swr-mstr";
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,swr_master_id = <1>;
+			clock-names = "lpass_core_hw_vote",
+					"lpass_audio_hw_vote";
+			clocks = <&lpass_core_hw_vote 0>,
+					<&lpass_audio_hw_vote 0>;
+			swrm-io-base = <0x62650000 0x0>;
+			qcom,mipi-sdw-block-packing-mode = <0>;
+			interrupts = <0 295 0>;
+			interrupt-names = "swr_master_irq";
+			qcom,swr-num-ports = <8>;
+			qcom,swr-port-mapping = <1 SPKR_L 0x1>,
+				<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
+				<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
+				<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
+				<8 SPKR_R_VI 0x3>;
+			qcom,swr-num-dev = <2>;
+			wsa881x_0211: wsa881x@20170211 {
+				compatible = "qcom,wsa881x";
+				reg = <0x10 0x20170211>;
+				qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+				qcom,bolero-handle = <&bolero>;
+			};
+
+			wsa881x_0212: wsa881x@20170212 {
+				compatible = "qcom,wsa881x";
+				reg = <0x10 0x20170212>;
+				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+				qcom,bolero-handle = <&bolero>;
+			};
+
+			wsa881x_0213: wsa881x@21170213 {
+				compatible = "qcom,wsa881x";
+				reg = <0x10 0x21170213>;
+				qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+				qcom,bolero-handle = <&bolero>;
+			};
+
+			wsa881x_0214: wsa881x@21170214 {
+				compatible = "qcom,wsa881x";
+				reg = <0x10 0x21170214>;
+				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+				qcom,bolero-handle = <&bolero>;
+			};
+		};
+
+	};
+
+	va_macro: va-macro@62770000 {
+		compatible = "qcom,va-macro";
+		reg = <0x62770000 0x0>;
+		clock-names = "lpass_audio_hw_vote";
+		clocks = <&lpass_audio_hw_vote 0>;
+		qcom,va-clk-mux-select = <1>;
+		qcom,va-island-mode-muxsel = <0x627A0000>;
+		qcom,va-dmic-sample-rate = <600000>;
+		qcom,default-clk-id = <TX_CORE_CLK>;
+	};
+
+	wcd938x_codec: wcd938x-codec {
+		//#ifdef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for use wcd937x codec
+		status = "disabled";
+		//#endif /* OPLUS_ARCH_EXTENDS */
+		compatible = "qcom,wcd938x-codec";
+		qcom,split-codec = <1>;
+		qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+			<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
+			<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
+			<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
+			<4 DSD_R 0x2 0 DSD_R>;
+		qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+			<0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
+			<1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
+			<2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
+			<2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
+			<3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
+			<3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
+
+		qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
+		qcom,rx-slave = <&wcd938x_rx_slave>;
+		qcom,tx-slave = <&wcd938x_tx_slave>;
+
+		cdc-vdd-rxtx-supply = <&L10A>;
+		qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
+		qcom,cdc-vdd-rxtx-current = <30000>;
+
+		cdc-vddio-supply = <&L10A>;
+		qcom,cdc-vddio-voltage = <1800000 1800000>;
+		qcom,cdc-vddio-current = <30000>;
+
+		cdc-vdd-buck-supply = <&L15A>;
+		qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+		qcom,cdc-vdd-buck-current = <650000>;
+
+		cdc-vdd-mic-bias-supply = <&BOB>;
+		qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>;
+		qcom,cdc-vdd-mic-bias-current = <30000>;
+
+		qcom,cdc-micbias1-mv = <1800>;
+		qcom,cdc-micbias2-mv = <1800>;
+		qcom,cdc-micbias3-mv = <1800>;
+		qcom,cdc-micbias4-mv = <1800>;
+
+		qcom,cdc-static-supplies = "cdc-vdd-rxtx",
+					   "cdc-vddio",
+					   "cdc-vdd-mic-bias";
+		qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
+	};
+
+	wcd937x_codec: wcd937x-codec {
+		//#ifndef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Delete for use wcd937x codec
+		//status = "disabled";
+		//#endif /* OPLUS_ARCH_EXTENDS */
+		compatible = "qcom,wcd937x-codec";
+		qcom,split-codec = <1>;
+		qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+			<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
+			<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
+			<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
+			<4 DSD_R 0x2 0 DSD_R>;
+		qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+			<1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>,
+			<2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>,
+			<2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>,
+			<3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,
+			<3 DMIC5 0x8 0 DMIC7>;
+
+		qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
+		qcom,rx-slave = <&wcd937x_rx_slave>;
+		qcom,tx-slave = <&wcd937x_tx_slave>;
+
+		cdc-vdd-ldo-rxtx-supply = <&L10A>;
+		qcom,cdc-vdd-ldo-rxtx-voltage = <1800000 1800000>;
+		qcom,cdc-vdd-ldo-rxtx-current = <25000>;
+
+		cdc-vddpx-1-supply = <&L10A>;
+		qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
+		qcom,cdc-vddpx-1-current = <10000>;
+
+		cdc-vdd-buck-supply = <&L15A>;
+		qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+		qcom,cdc-vdd-buck-current = <650000>;
+
+		cdc-vdd-mic-bias-supply = <&BOB>;
+		qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>;
+		qcom,cdc-vdd-mic-bias-current = <30000>;
+
+		//#ifndef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Modify for AMIC bias to 2.7V
+		/*
+		qcom,cdc-micbias1-mv = <1800>;
+		qcom,cdc-micbias2-mv = <1800>;
+		qcom,cdc-micbias3-mv = <1800>;
+		*/
+		//#else /* OPLUS_ARCH_EXTENDS */
+		qcom,cdc-micbias1-mv = <2700>;
+		qcom,cdc-micbias2-mv = <2700>;
+		qcom,cdc-micbias3-mv = <2700>;
+		//#endif /* OPLUS_ARCH_EXTENDS */
+
+		qcom,cdc-static-supplies = "cdc-vdd-ldo-rxtx",
+					   "cdc-vddpx-1",
+					   "cdc-vdd-mic-bias";
+		qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
+	};
+};
+
+&atoll_snd {
+	qcom,model = "atoll-idp-snd-card";
+	qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
+	qcom,audio-routing =
+		"AMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Analog Mic1",
+		"AMIC2", "MIC BIAS2",
+		"MIC BIAS2", "Analog Mic2",
+		"AMIC3", "MIC BIAS3",
+		"MIC BIAS3", "Analog Mic3",
+		"AMIC4", "MIC BIAS4",
+		"MIC BIAS4", "Analog Mic4",
+		"TX DMIC0", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic0",
+		"TX DMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic1",
+		"TX DMIC2", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic2",
+		"TX DMIC3", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic3",
+		"TX DMIC4", "MIC BIAS4",
+		"MIC BIAS4", "Digital Mic4",
+		"IN1_HPHL", "HPHL_OUT",
+		"IN2_HPHR", "HPHR_OUT",
+		"IN3_AUX", "AUX_OUT",
+		"TX SWR_ADC0", "ADC1_OUTPUT",
+		//#ifndef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Modify for AMIC2/AMIC3 not work
+		//"TX SWR_ADC1", "ADC2_OUTPUT",
+		//"TX SWR_ADC2", "ADC3_OUTPUT",
+		//"TX SWR_ADC3", "ADC4_OUTPUT",
+		//#else /* OPLUS_ARCH_EXTENDS */
+		"TX SWR_ADC2", "ADC2_OUTPUT",
+		//#endif /* OPLUS_ARCH_EXTENDS */
+		"TX SWR_DMIC0", "DMIC1_OUTPUT",
+		"TX SWR_DMIC1", "DMIC2_OUTPUT",
+		"TX SWR_DMIC2", "DMIC3_OUTPUT",
+		"TX SWR_DMIC3", "DMIC4_OUTPUT",
+		"TX SWR_DMIC4", "DMIC5_OUTPUT",
+		"TX SWR_DMIC5", "DMIC6_OUTPUT",
+		"TX SWR_DMIC6", "DMIC7_OUTPUT",
+		"TX SWR_DMIC7", "DMIC8_OUTPUT",
+		"WSA SRC0_INP", "SRC0",
+		"WSA_TX DEC0_INP", "TX DEC0 MUX",
+		"WSA_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC0_INP", "TX DEC0 MUX",
+		"RX_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC2_INP", "TX DEC2 MUX",
+		"RX_TX DEC3_INP", "TX DEC3 MUX",
+		"SpkrLeft IN", "WSA_SPK1 OUT",
+		"SpkrRight IN", "WSA_SPK2 OUT",
+		"VA_AIF1 CAP", "VA_SWR_CLK",
+		"VA_AIF2 CAP", "VA_SWR_CLK",
+		"VA_AIF3 CAP", "VA_SWR_CLK",
+		"VA MIC BIAS1", "Digital Mic0",
+		"VA MIC BIAS1", "Digital Mic1",
+		"VA MIC BIAS3", "Digital Mic2",
+		"VA MIC BIAS3", "Digital Mic3",
+		"VA MIC BIAS4", "Digital Mic4",
+		"VA DMIC0", "VA MIC BIAS1",
+		"VA DMIC1", "VA MIC BIAS1",
+		"VA DMIC2", "VA MIC BIAS3",
+		"VA DMIC3", "VA MIC BIAS3",
+		"VA DMIC4", "VA MIC BIAS4",
+		"VA SWR_ADC0", "VA_SWR_CLK",
+		"VA SWR_ADC1", "VA_SWR_CLK",
+		"VA SWR_ADC2", "VA_SWR_CLK",
+		"VA SWR_ADC3", "VA_SWR_CLK",
+		"VA SWR_MIC0", "VA_SWR_CLK",
+		"VA SWR_MIC1", "VA_SWR_CLK",
+		"VA SWR_MIC2", "VA_SWR_CLK",
+		"VA SWR_MIC3", "VA_SWR_CLK",
+		"VA SWR_MIC4", "VA_SWR_CLK",
+		"VA SWR_MIC5", "VA_SWR_CLK",
+		"VA SWR_MIC6", "VA_SWR_CLK",
+		"VA SWR_MIC7", "VA_SWR_CLK",
+		"VA SWR_ADC0", "ADC1_OUTPUT",
+		//#ifndef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Modify for AMIC2/AMIC3 not work
+		//"VA SWR_ADC1", "ADC2_OUTPUT",
+		//"VA SWR_ADC2", "ADC3_OUTPUT",
+		//"VA SWR_ADC3", "ADC4_OUTPUT",
+		//#else /* OPLUS_ARCH_EXTENDS */
+		"VA SWR_ADC2", "ADC2_OUTPUT",
+		//#endif /* OPLUS_ARCH_EXTENDS */
+		"VA SWR_MIC0", "DMIC1_OUTPUT",
+		"VA SWR_MIC1", "DMIC2_OUTPUT",
+		"VA SWR_MIC2", "DMIC3_OUTPUT",
+		"VA SWR_MIC3", "DMIC4_OUTPUT",
+		"VA SWR_MIC4", "DMIC5_OUTPUT",
+		"VA SWR_MIC5", "DMIC6_OUTPUT",
+		"VA SWR_MIC6", "DMIC7_OUTPUT",
+		"VA SWR_MIC7", "DMIC8_OUTPUT";
+	qcom,msm-mbhc-hphl-swh = <1>;
+	qcom,msm-mbhc-gnd-swh = <1>;
+	//#ifdef OPLUS_ARCH_EXTENDS
+	//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.HEADSETDET, 2020/07/30, Add for disable qcom moisture detect
+	qcom,msm-mbhc-moist-cfg = <1>, <3>, <0>;
+	//#endif /* OPLUS_ARCH_EXTENDS */
+	qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+	qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+	qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
+	//#ifdef OPLUS_ARCH_EXTENDS
+	//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30,, Add for MI2S gpio
+	//for tfa98xx i2s
+	qcom,tert-mi2s-gpios = <&cdc_mi2s_2_gpios>;
+	//#endif /* OPLUS_ARCH_EXTENDS */
+	asoc-codec  = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
+	asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+				"msm-ext-disp-audio-codec-rx";
+	//#ifndef OPLUS_ARCH_EXTENDS
+	//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Modify for disable wsa
+	/*
+	qcom,wsa-max-devs = <2>;
+	qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
+			<&wsa881x_0213>, <&wsa881x_0214>;
+	qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+				  "SpkrLeft", "SpkrRight";
+	*/
+	//#else /* OPLUS_ARCH_EXTENDS */
+	qcom,wsa-max-devs = <0>;
+	//#endif /* OPLUS_ARCH_EXTENDS */
+	qcom,codec-max-aux-devs = <1>;
+	//#ifndef OPLUS_ARCH_EXTENDS
+	//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Modify for use wcd937x codec
+	//qcom,codec-aux-devs = <&wcd938x_codec>;
+	//#else /* OPLUS_ARCH_EXTENDS */
+	qcom,codec-aux-devs = <&wcd937x_codec>;
+	//#endif /* OPLUS_ARCH_EXTENDS */
+	qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>,
+				  <&lpi_tlmm>, <&bolero>;
+
+	/* #ifdef OPLUS_ARCH_EXTENDS */
+	/* Suresh.Alla@MULTIMEDIA.AUDIODRIVER.HEADSETDET, 2020/07/30, Add for HeadsetDet. */
+	qcom,msm-mbhc-hs-mic-max-threshold-mv = <2600>;
+	qcom,msm-mbhc-hs-mic-min-threshold-mv = <75>;
+	/* #endif OPLUS_ARCH_EXTENDS */
+
+	/* #ifdef OPLUS_ARCH_EXTENDS */
+	/* Suresh.Alla@MULTIMEDIA.AUDIODRIVER.HEADSETDET, 2020/07/30, Add for mbhc cross connection. */
+	oppo,mbhc-check-cross-conn = <0>;
+	/* #endif OPLUS_ARCH_EXTENDS */
+};
+
+&q6core {
+	cdc_dmic01_gpios: cdc_dmic01_pinctrl {
+		/* #ifdef OPLUS_ARCH_EXTENDS */
+		/* Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for not use dmic */
+		status = "disabled";
+		/* #endif OPLUS_ARCH_EXTENDS */
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
+		pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
+		qcom,lpi-gpios;
+	};
+
+	cdc_dmic23_gpios: cdc_dmic23_pinctrl {
+		/* #ifdef OPLUS_ARCH_EXTENDS */
+		/* Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for not use dmic */
+		status = "disabled";
+		/* #endif OPLUS_ARCH_EXTENDS */
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
+		pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
+		qcom,lpi-gpios;
+	};
+
+	cdc_dmic45_gpios: cdc_dmic45_pinctrl {
+		/* #ifdef OPLUS_ARCH_EXTENDS */
+		/* Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for not use dmic */
+		status = "disabled";
+		/* #endif OPLUS_ARCH_EXTENDS */
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
+		pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
+		qcom,lpi-gpios;
+	};
+
+	wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
+		//#ifdef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for disable wsa
+		status = "disabled";
+		//#endif /* OPLUS_ARCH_EXTENDS */
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
+		pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
+		qcom,lpi-gpios;
+	};
+
+	rx_swr_gpios: rx_swr_clk_data_pinctrl {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>;
+		pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>;
+		qcom,lpi-gpios;
+	};
+
+	tx_swr_gpios: tx_swr_clk_data_pinctrl {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
+			     &tx_swr_data1_active &tx_swr_data2_active>;
+		pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
+			    &tx_swr_data1_sleep &tx_swr_data2_sleep>;
+		qcom,lpi-gpios;
+		//#ifdef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.HEADSETDET, 2020/07/30, Add for headset detect in suspend state
+		qcom,chip-wakeup-reg = <0x01FFB000>;
+		qcom,chip-wakeup-maskbit = <0>;
+		qcom,chip-wakeup-default-val = <0x1>;
+		//#endif /* OPLUS_ARCH_EXTENDS */
+	};
+
+	//#ifdef OPLUS_ARCH_EXTENDS
+	//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for Tertiary MI2S gpio
+	cdc_mi2s_2_gpios: msm_cdc_pinctrl {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&mi2s_2_active>;
+		pinctrl-1 = <&mi2s_2_sleep>;
+	};
+	//#endif /* OPLUS_ARCH_EXTENDS */
+};
+
+&soc {
+	wsa_spkr_en1: wsa_spkr_en1_pinctrl {
+		//#ifdef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for disable wsa
+		status = "disabled";
+		//#endif /* OPLUS_ARCH_EXTENDS */
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&spkr_1_sd_n_active>;
+		pinctrl-1 = <&spkr_1_sd_n_sleep>;
+	};
+
+	wsa_spkr_en2: wsa_spkr_en2_pinctrl {
+		//#ifdef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for disable wsa
+		status = "disabled";
+		//#endif /* OPLUS_ARCH_EXTENDS */
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&spkr_2_sd_n_active>;
+		pinctrl-1 = <&spkr_2_sd_n_sleep>;
+	};
+
+	wcd_rst_gpio: msm_cdc_pinctrl@58 {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&wcd_reset_active>;
+		pinctrl-1 = <&wcd_reset_sleep>;
+	};
+
+	clock_audio_wsa_1: wsa_core_clk {
+		compatible = "qcom,audio-ref-clk";
+		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
+		qcom,codec-lpass-ext-clk-freq = <19200000>;
+		qcom,codec-lpass-clk-id = <0x309>;
+		#clock-cells = <1>;
+	};
+
+	clock_audio_wsa_2: wsa_npl_clk {
+		compatible = "qcom,audio-ref-clk";
+		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_3>;
+		qcom,codec-lpass-ext-clk-freq = <19200000>;
+		qcom,codec-lpass-clk-id = <0x30A>;
+		#clock-cells = <1>;
+	};
+
+	clock_audio_rx_1: rx_core_clk {
+		compatible = "qcom,audio-ref-clk";
+		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
+		qcom,codec-lpass-ext-clk-freq = <22579200>;
+		qcom,codec-lpass-clk-id = <0x30E>;
+		#clock-cells = <1>;
+	};
+
+	clock_audio_rx_2: rx_npl_clk {
+		compatible = "qcom,audio-ref-clk";
+		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
+		qcom,codec-lpass-ext-clk-freq = <22579200>;
+		qcom,codec-lpass-clk-id = <0x30F>;
+		#clock-cells = <1>;
+	};
+
+	clock_audio_tx_1: tx_core_clk {
+		compatible = "qcom,audio-ref-clk";
+		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
+		qcom,codec-lpass-ext-clk-freq = <19200000>;
+		qcom,codec-lpass-clk-id = <0x30C>;
+		#clock-cells = <1>;
+	};
+
+	clock_audio_tx_2: tx_npl_clk {
+		compatible = "qcom,audio-ref-clk";
+		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
+		qcom,codec-lpass-ext-clk-freq = <19200000>;
+		qcom,codec-lpass-clk-id = <0x30D>;
+		#clock-cells = <1>;
+	};
+
+	clock_audio_va_1: va_core_clk {
+		compatible = "qcom,audio-ref-clk";
+		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
+		qcom,codec-lpass-ext-clk-freq = <19200000>;
+		qcom,codec-lpass-clk-id = <0x30B>;
+		#clock-cells = <1>;
+	};
+
+	clock_audio_va_2: va_npl_clk {
+		compatible = "qcom,audio-ref-clk";
+		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
+		qcom,codec-lpass-ext-clk-freq = <19200000>;
+		qcom,codec-lpass-clk-id = <0x310>;
+		#clock-cells = <1>;
+	};
+};
+
+&va_cdc_dma_0_tx {
+	qcom,msm-dai-is-island-supported = <1>;
+};
+
+/* #ifdef OPLUS_ARCH_EXTENDS */
+/*Kaiqin.Huang@MULTIMEDIA.AUDIODRIVER.SMARTPA, 2020/10/29, Add for tfa98xx smartpa*/
+&qupv3_se5_i2c {
+	status = "okay";
+	tfa98xx@34 {
+		compatible = "nxp,tfa98xx";
+		reg = <0x34>;
+		reset-gpio = <&tlmm 51 0>;
+		irq-gpio = <&tlmm 68 0>;
+		tfa98xx_fw_name = "tfa98xx.cnt";
+		tfa_min_range = <4800>;
+		tfa_max_range = <7800>;
+		status = "okay";
+	};
+};
+/* #endif OPLUS_ARCH_EXTENDS */
+
+/* #ifdef OPLUS_ARCH_EXTENDS */
+/*Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Add for SmartPA i2s config*/
+&dai_mi2s2 {
+	compatible = "qcom,msm-dai-q6-mi2s";
+	qcom,msm-dai-q6-mi2s-dev-id = <2>;
+	qcom,msm-mi2s-rx-lines = <2>;
+	qcom,msm-mi2s-tx-lines = <1>;
+};
+/* #endif OPLUS_ARCH_EXTENDS */
+
+/* #ifdef OPLUS_ARCH_EXTENDS */
+/* Chunyu.xie@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/08/09, Add for oplus extend aduio config */
+#include "oplus-audio-extend.dtsi"
+/* #endif OPLUS_ARCH_EXTENDS */

arch/arm64/boot/dts/19721/atoll-audio.dtsi

@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/qcom,audio-ext-clk-v2.h>
+#include "msm-audio-lpass.dtsi"
+
+&msm_audio_ion {
+	iommus = <&apps_smmu 0x1001 0x0>;
+	qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+};
+
+&soc {
+	qcom,avtimer@62DF0000 {
+		compatible = "qcom,avtimer";
+		reg = <0x62DF000C 0x4>,
+		      <0x62DF0010 0x4>;
+		reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
+		qcom,clk-div = <192>;
+		qcom,clk-mult = <10>;
+	};
+
+	dai_dp1: qcom,msm-dai-q6-dp1 {
+		compatible = "qcom,msm-dai-q6-hdmi";
+		qcom,msm-dai-q6-dev-id = <1>;
+	};
+};
+
+&dai_dp {
+	qcom,msm-dai-q6-dev-id = <0>;
+};
+
+&audio_apr {
+	q6core: qcom,q6core-audio {
+		compatible = "qcom,q6core-audio";
+
+		lpass_core_hw_vote: vote_lpass_core_hw {
+			compatible = "qcom,audio-ref-clk";
+			qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
+			#clock-cells = <1>;
+		};
+
+		lpass_audio_hw_vote: vote_lpass_audio_hw {
+			compatible = "qcom,audio-ref-clk";
+			qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
+			#clock-cells = <1>;
+		};
+
+		bolero: bolero-cdc {
+			compatible = "qcom,bolero-codec";
+			clock-names = "lpass_core_hw_vote",
+					"lpass_audio_hw_vote";
+			clocks = <&lpass_core_hw_vote 0>,
+					<&lpass_audio_hw_vote 0>;
+			bolero-clk-rsc-mngr {
+				compatible = "qcom,bolero-clk-rsc-mngr";
+			};
+
+			tx_macro: tx-macro@62620000 {
+				swr2: tx_swr_master {
+				};
+			};
+
+			rx_macro: rx-macro@62600000 {
+				swr1: rx_swr_master {
+				};
+			};
+
+			wsa_macro: wsa-macro@62640000 {
+				swr0: wsa_swr_master {
+				};
+			};
+		};
+	};
+};
+
+&q6core {
+	atoll_snd: sound {
+		compatible = "qcom,kona-asoc-snd";
+		//#ifndef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Modify for use MI2S
+		//qcom,mi2s-audio-intf = <0>;
+		//#else /* OPLUS_ARCH_EXTENDS */
+		qcom,mi2s-audio-intf = <1>;
+		//#endif /* OPLUS_ARCH_EXTENDS */
+		qcom,auxpcm-audio-intf = <0>;
+		qcom,tdm-audio-intf = <0>;
+		qcom,wcn-btfm = <1>;
+		qcom,ext-disp-audio-rx = <1>;
+		qcom,afe-rxtx-lb = <0>;
+
+		clock-names = "lpass_audio_hw_vote";
+		clocks = <&lpass_audio_hw_vote 0>;
+
+		asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+				<&loopback>, <&compress>, <&hostless>,
+				<&afe>, <&lsm>, <&routing>, <&compr>,
+				<&pcm_noirq>;
+		asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+				"msm-pcm-dsp.2", "msm-voip-dsp",
+				"msm-pcm-voice", "msm-pcm-loopback",
+				"msm-compress-dsp", "msm-pcm-hostless",
+				"msm-pcm-afe", "msm-lsm-client",
+				"msm-pcm-routing", "msm-compr-dsp",
+				"msm-pcm-dsp-noirq";
+		asoc-cpu = <&dai_dp>, <&dai_dp1>,
+				<&dai_mi2s0>, <&dai_mi2s1>,
+				<&dai_mi2s2>, <&dai_mi2s3>,
+				<&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>,
+				<&dai_sec_auxpcm>, <&dai_tert_auxpcm>,
+				<&dai_quat_auxpcm>, <&dai_quin_auxpcm>,
+				<&dai_sen_auxpcm>,
+				<&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
+				<&afe_proxy_tx>, <&incall_record_rx>,
+				<&incall_record_tx>, <&incall_music_rx>,
+				<&incall_music_2_rx>,
+				<&usb_audio_rx>, <&usb_audio_tx>,
+				<&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>,
+				<&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
+				<&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
+				<&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
+				<&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
+				<&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>,
+				<&dai_sen_tdm_rx_0>, <&dai_sen_tdm_tx_0>,
+				<&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>,
+				<&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>,
+				<&wsa_cdc_dma_2_tx>,
+				<&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>,
+				<&va_cdc_dma_2_tx>,
+				<&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>,
+				<&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>,
+				<&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>,
+				<&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>,
+				<&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>,
+				<&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>,
+				<&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>,
+				<&afe_loopback_tx>,
+				<&proxy_rx>, <&proxy_tx>;
+		asoc-cpu-names = "msm-dai-q6-dp.0", "msm-dai-q6-dp.1",
+				"msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
+				"msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
+				"msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5",
+				"msm-dai-q6-auxpcm.1",
+				"msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3",
+				"msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5",
+				"msm-dai-q6-auxpcm.6", "msm-dai-q6-dev.224",
+				"msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
+				"msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
+				"msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
+				"msm-dai-q6-dev.32770",
+				"msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673",
+				"msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399",
+				"msm-dai-q6-dev.16401",
+				"msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865",
+				"msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881",
+				"msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897",
+				"msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913",
+				"msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929",
+				"msm-dai-q6-tdm.36944", "msm-dai-q6-tdm.36945",
+				"msm-dai-cdc-dma-dev.45056",
+				"msm-dai-cdc-dma-dev.45057",
+				"msm-dai-cdc-dma-dev.45058",
+				"msm-dai-cdc-dma-dev.45059",
+				"msm-dai-cdc-dma-dev.45061",
+				"msm-dai-cdc-dma-dev.45089",
+				"msm-dai-cdc-dma-dev.45091",
+				"msm-dai-cdc-dma-dev.45093",
+				"msm-dai-cdc-dma-dev.45104",
+				"msm-dai-cdc-dma-dev.45105",
+				"msm-dai-cdc-dma-dev.45106",
+				"msm-dai-cdc-dma-dev.45107",
+				"msm-dai-cdc-dma-dev.45108",
+				"msm-dai-cdc-dma-dev.45109",
+				"msm-dai-cdc-dma-dev.45110",
+				"msm-dai-cdc-dma-dev.45111",
+				"msm-dai-cdc-dma-dev.45112",
+				"msm-dai-cdc-dma-dev.45113",
+				"msm-dai-cdc-dma-dev.45114",
+				"msm-dai-cdc-dma-dev.45115",
+				"msm-dai-cdc-dma-dev.45116",
+				"msm-dai-cdc-dma-dev.45118",
+				"msm-dai-q6-dev.24577",
+				"msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195";
+		fsa4480-i2c-handle = <&fsa4480>;
+	};
+};
+
+&qupv3_se11_i2c {
+	fsa4480: fsa4480@42 {
+		compatible = "qcom,fsa4480-i2c";
+		reg = <0x42>;
+		pinctrl-names = "default";
+		/* Hongwei.Di@BSP.CHG.Basic, 2020/09/17, remove fsa switch pinctrl for usb */
+		//pinctrl-0 = <&fsa_usbc_ana_en>;
+	};
+};

arch/arm64/boot/dts/19721/atoll-camera-sensor-idp.dtsi

@@ -0,0 +1,640 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/qcom,camcc-atoll.h>
+
+&soc {
+	led_flash_rear: qcom,camera-flash@0 {
+		cell-index = <0>;
+		reg = <0x00 0x00>;
+		compatible = "qcom,camera-flash";
+		qcom,flash-name = "pmic";
+		flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+		torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+		switch-source = <&pm6150l_switch2 &pm6150l_switch2>;
+		status = "ok";
+	};
+
+	led_flash_rear_aux: qcom,camera-flash@1 {
+		cell-index = <1>;
+		reg = <0x01 0x00>;
+		compatible = "qcom,camera-flash";
+		flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+		torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+		switch-source = <&pm6150l_switch2 &pm6150l_switch2>;
+		status = "ok";
+	};
+
+	led_flash_triple_rear: qcom,camera-flash@4 {
+		cell-index = <4>;
+		reg = <0x04 0x00>;
+		compatible = "qcom,camera-flash";
+		flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+		torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+		switch-source = <&pm6150l_switch2 &pm6150l_switch2>;
+		status = "ok";
+	};
+
+	led_flash_triple_rear_aux: qcom,camera-flash@5 {
+		cell-index = <5>;
+		reg = <0x05 0x00>;
+		compatible = "qcom,camera-flash";
+		flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+		torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+		switch-source = <&pm6150l_switch2 &pm6150l_switch2>;
+		status = "ok";
+	};
+
+	led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+		cell-index = <6>;
+		reg = <0x06 0x00>;
+		compatible = "qcom,camera-flash";
+		flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+		torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+		switch-source = <&pm6150l_switch2 &pm6150l_switch2>;
+		status = "ok";
+	};
+};
+
+&cam_cci0 {
+	qcom,cam-res-mgr {
+		compatible = "qcom,cam-res-mgr";
+		status = "ok";
+	};
+
+	actuator_rear: qcom,actuator@0 {
+		cell-index = <0>;
+		reg = <0x0>;
+		compatible = "qcom,actuator";
+		cci-master = <0>;
+		cam_vaf-supply = <&L6P>;
+		regulator-names = "cam_vaf";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <2800000>;
+		rgltr-max-voltage = <2800000>;
+		rgltr-load-current = <100000>;
+	};
+	actuator_rear_aux1: qcom,actuator@1 {
+		cell-index = <1>;
+		reg = <0x1>;
+		compatible = "qcom,actuator";
+		//cci-device = <0>;
+		cci-master = <1>;
+		cam_vaf-supply = <&L6P>;
+		regulator-names = "cam_vaf";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <2800000>;
+		rgltr-max-voltage = <2800000>;
+		rgltr-load-current = <100000>;
+	};
+	eeprom_rear: qcom,eeprom@0 {
+		cell-index = <0>;
+		reg = <0>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L3P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		cam_vaf-supply = <&L6P>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk", "cam_vaf";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>;
+		rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>;
+		rgltr-load-current = <0 110000 650000 0 110000>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk0_active
+				&cam_sensor_rear_active>;
+		pinctrl-1 = <&cam_sensor_mclk0_suspend
+				&cam_sensor_rear_suspend>;
+/*#ifndef ODM_LQ_EDIT*/
+/* liujiawei  ODM.BSP.CHG  2019-10-10  for charge */
+		//gpios = <&tlmm 13 0>,
+		//	<&tlmm 30 0>;
+/*#else*/
+		gpios = <&tlmm 13 0>,
+			<&tlmm 21 0>;
+/*#endif*/
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK0",
+					"CAM_RESET0";
+		sensor-mode = <0>;
+		cci-master = <0>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+//imx471
+	eeprom_front: qcom,eeprom@2 {
+		cell-index = <2>;
+		reg = <0x2>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1050000 0>;
+		rgltr-max-voltage = <1800000 2800000 1050000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk1_active
+				 &cam_sensor_front_active>;
+		pinctrl-1 = <&cam_sensor_mclk1_suspend
+				 &cam_sensor_front_suspend>;
+		gpios = <&tlmm 14 0>,
+			<&tlmm 29 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK1",
+					"CAM_RESET1";
+		sensor-mode = <0>;
+		//cci-device = <0>;
+		cci-master = <1>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+	eeprom_rear_aux2: qcom,eeprom@3 {
+		cell-index = <3>;
+		reg = <0x3>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_vdig-supply = <&L2P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1050000 0>;
+		rgltr-max-voltage = <1800000 2800000 1050000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk4_active
+				 &cam_rear_aux2_reset_active>;
+		pinctrl-1 = <&cam_sensor_mclk4_suspend
+				 &cam_rear_aux2_reset_suspend>;
+		gpios = <&tlmm 23 0>,
+			<&tlmm 22 0>;
+		gpio-reset = <1>;
+		//gpio-custom1 = <2>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK4",
+					"CAM_RESET4";
+		sensor-mode = <0>;
+		//cci-device = <0>;
+		cci-master = <1>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK4_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+	eeprom_front_aux: qcom,eeprom@5 {
+		cell-index = <5>;
+		reg = <5>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L7P>;
+		cam_vdig-supply = <&L2P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1200000 0>;
+		rgltr-max-voltage = <1800000 2800000 1200000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk2_active
+				 &cam_sensor_active_front>;
+		pinctrl-1 = <&cam_sensor_mclk2_suspend
+				 &cam_sensor_suspend_front>;
+		gpios = <&tlmm 15 0>,
+			<&tlmm 32 0>,
+			<&tlmm 67 0>;
+		gpio-reset = <1>;
+		gpio-custom1 = <2>;
+		gpio-req-tbl-num = <0 1 2>;
+		gpio-req-tbl-flags = <1 0 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK2",
+					"CAM_RESET2",
+					"CAM_CUSTOM1";
+		sensor-mode = <0>;
+		//cci-device = <0>;
+		cci-master = <0>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+	eeprom_triple_rear_aux2: qcom,eeprom@6 {
+		cell-index = <6>;
+		reg = <6>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L3P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		cam_vaf-supply = <&L6P>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk", "cam_vaf";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>;
+		rgltr-load-current = <0 80000 105000 0 100000>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk2_active
+				&cam_sensor_front_active>;
+		pinctrl-1 = <&cam_sensor_mclk2_suspend
+				&cam_sensor_front_suspend>;
+		gpios = <&tlmm 15 0>,
+			<&tlmm 29 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK2",
+					"CAM_RESET2";
+		sensor-mode = <0>;
+		cci-device = <1>;
+		cci-master = <0>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <19200000>;
+	};
+//s5kgw1
+	qcom,cam-sensor@0 {
+		cell-index = <0>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x0>;
+		csiphy-sd-index = <0>;
+		sensor-position-roll = <90>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <180>;
+		led-flash-src = <&led_flash_rear>;
+		eeprom-src = <&eeprom_rear>;
+		actuator-src = <&actuator_rear>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L3P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1050000 0>;
+		rgltr-max-voltage = <1800000 2800000 1050000 0>;
+		rgltr-load-current = <0 110000 650000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk0_active
+				&cam_sensor_rear_active>;
+		pinctrl-1 = <&cam_sensor_mclk0_suspend
+				&cam_sensor_rear_suspend>;
+/*#ifndef ODM_LQ_EDIT*/
+/* liujiawei  ODM.BSP.CHG  2019-10-10  for charge */
+		//gpios = <&tlmm 13 0>,
+		//	<&tlmm 30 0>;
+/*#else*/
+		gpios = <&tlmm 13 0>,
+			<&tlmm 21 0>;
+/*#endif*/
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK0",
+					"CAM_RESET0";
+		sensor-mode = <0>;
+		cci-master = <0>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+//imx471
+	qcom,cam-sensor@2 {
+		cell-index = <2>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x2>;
+		csiphy-sd-index = <2>;
+		sensor-position-roll = <270>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <0>;
+		eeprom-src = <&eeprom_front>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1050000 0>;
+		rgltr-max-voltage = <1800000 2800000 1050000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk1_active
+				 &cam_sensor_front_active>;
+		pinctrl-1 = <&cam_sensor_mclk1_suspend
+				 &cam_sensor_front_suspend>;
+		gpios = <&tlmm 14 0>,
+			<&tlmm 29 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK1",
+					"CAM_RESET1";
+		sensor-mode = <0>;
+		cci-device = <0>;
+		cci-master = <1>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+//s5k3m5sx
+	qcom,cam-sensor@3 {
+		cell-index = <3>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x3>;
+		csiphy-sd-index = <3>;
+		sensor-position-roll = <270>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <0>;
+		eeprom-src = <&eeprom_rear_aux2>;
+		actuator-src = <&actuator_rear_aux1>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_vdig-supply = <&L2P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1050000 0>;
+		rgltr-max-voltage = <1800000 2800000 1050000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk4_active
+				 &cam_rear_aux2_reset_active>;
+		pinctrl-1 = <&cam_sensor_mclk4_suspend
+				 &cam_rear_aux2_reset_suspend>;
+		gpios = <&tlmm 23 0>,
+			<&tlmm 22 0>;
+		gpio-reset = <1>;
+		//gpio-custom1 = <2>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK4",
+					"CAM_RESET4";
+		sensor-mode = <0>;
+		cci-device = <0>;
+		cci-master = <1>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK4_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+//gc8054
+	qcom,cam-sensor@5 {
+        cell-index = <5>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x5>;
+		csiphy-sd-index = <1>;
+		sensor-position-roll = <270>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <0>;
+		eeprom-src = <&eeprom_front_aux>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L7P>;
+		cam_vdig-supply = <&L2P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1200000 0>;
+		rgltr-max-voltage = <1800000 2800000 1200000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk2_active
+				 &cam_sensor_active_front>;
+		pinctrl-1 = <&cam_sensor_mclk2_suspend
+				 &cam_sensor_suspend_front>;
+		gpios = <&tlmm 15 0>,
+			<&tlmm 32 0>,
+			<&tlmm 67 0>;
+		gpio-reset = <1>;
+		gpio-custom1 = <2>;
+		gpio-req-tbl-num = <0 1 2>;
+		gpio-req-tbl-flags = <1 0 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK2",
+					"CAM_RESET2",
+					"CAM_CUSTOM1";
+		sensor-mode = <0>;
+		//cci-device = <0>;
+		cci-master = <0>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+};
+&cam_cci1 {
+	qcom,cam-res-mgr {
+		compatible = "qcom,cam-res-mgr";
+		status = "ok";
+	};
+	eeprom_rear_aux: qcom,eeprom@1 {
+		cell-index = <1>;
+		reg = <1>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_vdig-supply = <&L2P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1200000 0>;
+		rgltr-max-voltage = <1800000 2800000 1200000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk3_active
+				&cam_sensor_rear2_active>;
+		pinctrl-1 = <&cam_sensor_mclk3_suspend
+				&cam_sensor_rear2_suspend>;
+		gpios = <&tlmm 16 0>,
+			<&tlmm 5 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK3",
+					"CAM_RESET3";
+		sensor-mode = <0>;
+		cci-device = <1>;
+		cci-master = <0>; //2
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+	eeprom_rear_aux3: qcom,eeprom@4 {
+		cell-index = <4>;
+		reg = <4>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 0>;
+		rgltr-max-voltage = <1800000 2800000 0>;
+		rgltr-load-current = <0 80000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk3_active
+				 &cam_sensor_tof_active>;
+		pinctrl-1 = <&cam_sensor_mclk3_suspend
+				 &cam_sensor_tof_suspend>;
+		gpios = <&tlmm 16 0>,
+			<&tlmm 24 0>,
+			<&tlmm 107 0>;
+		gpio-reset = <1>;
+		gpio-custom1 = <2>;
+		gpio-req-tbl-num = <0 1 2>;
+		gpio-req-tbl-flags = <1 0 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK3",
+					"CAM_RESET3",
+					"CAM_CUSTOM1";
+		sensor-mode = <0>;
+		cci-device = <1>;
+		cci-master = <0>; //2
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+//h846
+    qcom,cam-sensor@1 {
+		cell-index = <1>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x1>;
+		csiphy-sd-index = <1>;
+		sensor-position-roll = <90>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <180>;
+		eeprom-src = <&eeprom_rear_aux>;
+		led-flash-src = <&led_flash_rear_aux>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_vdig-supply = <&L2P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1200000 0>;
+		rgltr-max-voltage = <1800000 2800000 1200000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk3_active
+				&cam_sensor_rear2_active>;
+		pinctrl-1 = <&cam_sensor_mclk3_suspend
+				&cam_sensor_rear2_suspend>;
+		gpios = <&tlmm 16 0>,
+			<&tlmm 5 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK3",
+					"CAM_RESET3";
+		sensor-mode = <0>;
+		cci-device = <1>;
+		cci-master = <0>; //2
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+//gc2375h
+	qcom,cam-sensor@4 {
+		cell-index = <4>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x4>;
+		csiphy-sd-index = <3>;
+		sensor-position-roll = <90>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <180>;
+		led-flash-src = <&led_flash_rear>;
+		eeprom-src = <&eeprom_rear_aux3>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 0>;
+		rgltr-max-voltage = <1800000 2800000 0>;
+		rgltr-load-current = <0 80000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk3_active
+				 &cam_sensor_tof_active>;
+		pinctrl-1 = <&cam_sensor_mclk3_suspend
+				 &cam_sensor_tof_suspend>;
+		gpios = <&tlmm 16 0>,
+			<&tlmm 24 0>,
+			<&tlmm 107 0>;
+		gpio-reset = <1>;
+		gpio-custom1 = <2>;
+		gpio-req-tbl-num = <0 1 2>;
+		gpio-req-tbl-flags = <1 0 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK3",
+					"CAM_RESET3",
+					"CAM_CUSTOM1";
+		sensor-mode = <0>;
+		cci-device = <1>;
+		cci-master = <0>; //2
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+};

arch/arm64/boot/dts/19721/atoll-camera-sensor-idps.dtsi

@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/qcom,camcc-atoll.h>
+
+&soc {
+	led_flash_rear: qcom,camera-flash@0 {
+		cell-index = <0>;
+		reg = <0x00 0x00>;
+		compatible = "qcom,camera-flash";
+		flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+		torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+		switch-source = <&pm6150l_switch2 &pm6150l_switch2>;
+		status = "ok";
+	};
+
+	led_flash_rear_aux: qcom,camera-flash@1 {
+		cell-index = <1>;
+		reg = <0x01 0x00>;
+		compatible = "qcom,camera-flash";
+		flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+		torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+		switch-source = <&pm6150l_switch2 &pm6150l_switch2>;
+		status = "ok";
+	};
+};
+
+&cam_cci0 {
+	qcom,cam-res-mgr {
+		compatible = "qcom,cam-res-mgr";
+		status = "ok";
+	};
+
+	actuator_rear: qcom,actuator@0 {
+		cell-index = <0>;
+		reg = <0x0>;
+		compatible = "qcom,actuator";
+		cci-master = <0>;
+		cam_vaf-supply = <&L6P>;
+		regulator-names = "cam_vaf";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <2800000>;
+		rgltr-max-voltage = <2800000>;
+		rgltr-load-current = <100000>;
+	};
+
+	eeprom_rear: qcom,eeprom@0 {
+		cell-index = <0>;
+		reg = <0>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		cam_vaf-supply = <&L6P>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk", "cam_vaf";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>;
+		rgltr-load-current = <0 80000 105000 0 100000>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk0_active
+				&cam_sensor_rear_active>;
+		pinctrl-1 = <&cam_sensor_mclk0_suspend
+				&cam_sensor_rear_suspend>;
+		gpios = <&tlmm 13 0>,
+			<&tlmm 30 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK0",
+					"CAM_RESET0";
+		sensor-mode = <0>;
+		cci-master = <0>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+
+	eeprom_front: qcom,eeprom@2 {
+		cell-index = <2>;
+		reg = <0x2>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L3P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk2_active
+				 &cam_sensor_front_active>;
+		pinctrl-1 = <&cam_sensor_mclk2_suspend
+				 &cam_sensor_front_suspend>;
+		gpios = <&tlmm 15 0>,
+			<&tlmm 24 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK2",
+					"CAM_RESET2";
+		sensor-mode = <0>;
+		cci-device = <0>;
+		cci-master = <1>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+
+	qcom,cam-sensor@0 {
+		cell-index = <0>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x0>;
+		csiphy-sd-index = <0>;
+		sensor-position-roll = <90>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <180>;
+		led-flash-src = <&led_flash_rear>;
+		eeprom-src = <&eeprom_rear>;
+		actuator-src = <&actuator_rear>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk0_active
+				&cam_sensor_rear_active>;
+		pinctrl-1 = <&cam_sensor_mclk0_suspend
+				&cam_sensor_rear_suspend>;
+		gpios = <&tlmm 13 0>,
+			<&tlmm 30 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK0",
+					"CAM_RESET0";
+		sensor-mode = <0>;
+		cci-master = <0>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+
+	qcom,cam-sensor@1 {
+		cell-index = <1>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x1>;
+		csiphy-sd-index = <1>;
+		sensor-position-roll = <90>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <180>;
+		led-flash-src = <&led_flash_rear_aux>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L3P>;
+		cam_vdig-supply = <&L2P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk1_active
+				&cam_sensor_rear2_active>;
+		pinctrl-1 = <&cam_sensor_mclk1_suspend
+				&cam_sensor_rear2_suspend>;
+		gpios = <&tlmm 14 0>,
+			<&tlmm 25 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK1",
+					"CAM_RESET1";
+		sensor-mode = <0>;
+		cci-master = <1>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+
+	qcom,cam-sensor@2 {
+		cell-index = <2>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x2>;
+		csiphy-sd-index = <2>;
+		sensor-position-roll = <270>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <0>;
+		eeprom-src = <&eeprom_front>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L3P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk2_active
+				 &cam_sensor_front_active>;
+		pinctrl-1 = <&cam_sensor_mclk2_suspend
+				 &cam_sensor_front_suspend>;
+		gpios = <&tlmm 15 0>,
+			<&tlmm 24 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK2",
+					"CAM_RESET2";
+		sensor-mode = <0>;
+		cci-device = <0>;
+		cci-master = <1>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+};

arch/arm64/boot/dts/19721/atoll-camera-sensor-qrd.dtsi

@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/qcom,camcc-atoll.h>
+
+&soc {
+	led_flash_rear: qcom,camera-flash@0 {
+		cell-index = <0>;
+		reg = <0x00 0x00>;
+		compatible = "qcom,camera-flash";
+		flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+		torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+		switch-source = <&pm6150l_switch2 &pm6150l_switch2>;
+		status = "ok";
+	};
+
+	led_flash_rear_aux: qcom,camera-flash@1 {
+		cell-index = <1>;
+		reg = <0x01 0x00>;
+		compatible = "qcom,camera-flash";
+		flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+		torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+		switch-source = <&pm6150l_switch2 &pm6150l_switch2>;
+		status = "ok";
+	};
+
+	vreg_tof: regulator-dbb1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_tof";
+		regulator-min-microvolt = <3600000>;
+		regulator-max-microvolt = <3600000>;
+		gpio = <&tlmm 118 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <1000>;
+		enable-active-high;
+	};
+
+	qcom,cam-res-mgr {
+		compatible = "qcom,cam-res-mgr";
+		status = "ok";
+	};
+};
+
+&cam_cci0 {
+	actuator_rear: qcom,actuator@0 {
+		cell-index = <0>;
+		reg = <0x0>;
+		compatible = "qcom,actuator";
+		cci-master = <0>;
+		cam_vaf-supply = <&L6P>;
+		regulator-names = "cam_vaf";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <2800000>;
+		rgltr-max-voltage = <2800000>;
+		rgltr-load-current = <100000>;
+	};
+
+	eeprom_rear: qcom,eeprom@0 {
+		cell-index = <0>;
+		reg = <0>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		cam_vaf-supply = <&L6P>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk", "cam_vaf";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>;
+		rgltr-load-current = <0 80000 105000 0 100000>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk0_active
+				&cam_sensor_rear_active>;
+		pinctrl-1 = <&cam_sensor_mclk0_suspend
+				&cam_sensor_rear_suspend>;
+		gpios = <&tlmm 13 0>,
+			<&tlmm 30 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK0",
+					"CAM_RESET0";
+		sensor-mode = <0>;
+		cci-master = <0>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+
+	eeprom_front: qcom,eeprom@2 {
+		cell-index = <2>;
+		reg = <0x2>;
+		compatible = "qcom,eeprom";
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L3P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk2_active
+				 &cam_sensor_front_active>;
+		pinctrl-1 = <&cam_sensor_mclk2_suspend
+				 &cam_sensor_front_suspend>;
+		gpios = <&tlmm 15 0>,
+			<&tlmm 29 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK2",
+					"CAM_RESET2";
+		sensor-mode = <0>;
+		cci-device = <0>;
+		cci-master = <1>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+
+	qcom,cam-sensor@0 {
+		cell-index = <0>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x0>;
+		csiphy-sd-index = <0>;
+		sensor-position-roll = <90>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <180>;
+		led-flash-src = <&led_flash_rear>;
+		eeprom-src = <&eeprom_rear>;
+		actuator-src = <&actuator_rear>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L4P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk0_active
+				&cam_sensor_rear_active>;
+		pinctrl-1 = <&cam_sensor_mclk0_suspend
+				&cam_sensor_rear_suspend>;
+		gpios = <&tlmm 13 0>,
+			<&tlmm 30 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK0",
+					"CAM_RESET0";
+		sensor-mode = <0>;
+		cci-master = <0>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+
+	qcom,cam-sensor@1 {
+		cell-index = <1>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x1>;
+		csiphy-sd-index = <1>;
+		sensor-position-roll = <90>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <180>;
+		led-flash-src = <&led_flash_rear_aux>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L3P>;
+		cam_vdig-supply = <&L2P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk1_active
+				&cam_sensor_rear2_active>;
+		pinctrl-1 = <&cam_sensor_mclk1_suspend
+				&cam_sensor_rear2_suspend>;
+		gpios = <&tlmm 14 0>,
+			<&tlmm 25 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK1",
+					"CAM_RESET1";
+		sensor-mode = <0>;
+		cci-master = <1>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+
+	qcom,cam-sensor@2 {
+		cell-index = <2>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x2>;
+		csiphy-sd-index = <2>;
+		sensor-position-roll = <270>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <0>;
+		eeprom-src = <&eeprom_front>;
+		cam_vio-supply = <&L5P>;
+		cam_vana-supply = <&L3P>;
+		cam_vdig-supply = <&L1P>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 2800000 1104000 0>;
+		rgltr-max-voltage = <1800000 2800000 1104000 0>;
+		rgltr-load-current = <0 80000 105000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk2_active
+				 &cam_sensor_front_active>;
+		pinctrl-1 = <&cam_sensor_mclk2_suspend
+				 &cam_sensor_front_suspend>;
+		gpios = <&tlmm 15 0>,
+			<&tlmm 29 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK2",
+					"CAM_RESET2";
+		sensor-mode = <0>;
+		cci-device = <0>;
+		cci-master = <1>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+};
+
+&cam_cci1 {
+	qcom,cam-sensor@3 {
+		cell-index = <3>;
+		compatible = "qcom,cam-sensor";
+		reg = <0x3>;
+		csiphy-sd-index = <3>;
+		sensor-position-roll = <90>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <180>;
+		cam_vio-supply = <&L5P>;
+		cam_vdig-supply = <&vreg_tof>;
+		cam_clk-supply = <&titan_top_gdsc>;
+		regulator-names = "cam_vio", "cam_vdig",
+			"cam_clk";
+		rgltr-cntrl-support;
+		rgltr-min-voltage = <1800000 3600000 0>;
+		rgltr-max-voltage = <1800000 3600000 0>;
+		rgltr-load-current = <0 120000 0>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk3_active
+				 &cam_sensor_tof_active>;
+		pinctrl-1 = <&cam_sensor_mclk3_suspend
+				 &cam_sensor_tof_suspend>;
+		gpios = <&tlmm 16 0>,
+			<&tlmm 24 0>;
+		gpio-reset = <1>;
+		gpio-req-tbl-num = <0 1>;
+		gpio-req-tbl-flags = <1 0>;
+		gpio-req-tbl-label = "CAMIF_MCLK3",
+					"CAM_RESET3";
+		sensor-mode = <0>;
+		cci-device = <1>;
+		cci-master = <0>;
+		status = "ok";
+		clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "turbo";
+		clock-rates = <24000000>;
+	};
+};

arch/arm64/boot/dts/19721/atoll-gdsc.dtsi

@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+	/* GDSCs in Global CC */
+	ufs_phy_gdsc: qcom,gdsc@177004 {
+		compatible = "qcom,gdsc";
+		regulator-name = "ufs_phy_gdsc";
+		reg = <0x177004 0x4>;
+		qcom,poll-cfg-gdscr;
+		status = "disabled";
+	};
+
+	usb30_prim_gdsc: qcom,gdsc@10f004 {
+		compatible = "qcom,gdsc";
+		regulator-name = "usb30_prim_gdsc";
+		reg = <0x10f004 0x4>;
+		qcom,poll-cfg-gdscr;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d040 {
+		compatible = "qcom,gdsc";
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
+		reg = <0x17d040 0x4>;
+		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
+		status = "disabled";
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d044 {
+		compatible = "qcom,gdsc";
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
+		reg = <0x17d044 0x4>;
+		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
+		status = "disabled";
+	};
+
+	/* GDSCs in Camera CC */
+	bps_gdsc: qcom,gdsc@ad06004 {
+		compatible = "qcom,gdsc";
+		regulator-name = "bps_gdsc";
+		reg = <0xad06004 0x4>;
+		qcom,poll-cfg-gdscr;
+		status = "disabled";
+	};
+
+	ipe_0_gdsc: qcom,gdsc@ad07004 {
+		compatible = "qcom,gdsc";
+		regulator-name = "ipe_0_gdsc";
+		reg = <0xad07004 0x4>;
+		qcom,poll-cfg-gdscr;
+		status = "disabled";
+	};
+
+	ife_0_gdsc: qcom,gdsc@ad09004 {
+		compatible = "qcom,gdsc";
+		regulator-name = "ife_0_gdsc";
+		reg = <0xad09004 0x4>;
+		qcom,poll-cfg-gdscr;
+		status = "disabled";
+	};
+
+	ife_1_gdsc: qcom,gdsc@ad0a004 {
+		compatible = "qcom,gdsc";
+		regulator-name = "ife_1_gdsc";
+		reg = <0xad0a004 0x4>;
+		qcom,poll-cfg-gdscr;
+		status = "disabled";
+	};
+
+	titan_top_gdsc: qcom,gdsc@ad0b134 {
+		compatible = "qcom,gdsc";
+		regulator-name = "titan_top_gdsc";
+		reg = <0xad0b134 0x4>;
+		qcom,poll-cfg-gdscr;
+		status = "disabled";
+	};
+
+	/* GDSCs in Display CC */
+	mdss_core_gdsc: qcom,gdsc@af03000 {
+		compatible = "qcom,gdsc";
+		regulator-name = "mdss_core_gdsc";
+		reg = <0xaf03000 0x4>;
+		qcom,poll-cfg-gdscr;
+		qcom,support-hw-trigger;
+		status = "disabled";
+		proxy-supply = <&mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+	};
+
+	/* GDSCs in Graphics CC */
+	gpu_cx_hw_ctrl: syscon@5091540 {
+		compatible = "syscon";
+		reg = <0x5091540 0x4>;
+	};
+
+	gpu_gx_domain_addr: syscon@5091508 {
+		compatible = "syscon";
+		reg = <0x5091508 0x4>;
+	};
+
+	gpu_gx_sw_reset: syscon@5091008 {
+		compatible = "syscon";
+		reg = <0x5091008 0x4>;
+	};
+
+	gpu_cx_gdsc: qcom,gdsc@509106c {
+		compatible = "qcom,gdsc";
+		regulator-name = "gpu_cx_gdsc";
+		reg = <0x509106c 0x4>;
+		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
+		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
+		qcom,clk-dis-wait-val = <8>;
+		status = "disabled";
+	};
+
+	gpu_gx_gdsc: qcom,gdsc@509100c {
+		compatible = "qcom,gdsc";
+		regulator-name = "gpu_gx_gdsc";
+		reg = <0x509100c 0x4>;
+		qcom,poll-cfg-gdscr;
+		domain-addr = <&gpu_gx_domain_addr>;
+		sw-reset = <&gpu_gx_sw_reset>;
+		status = "disabled";
+	};
+
+	/* GDSCs in Video CC */
+	vcodec0_gdsc: qcom,gdsc@ab00874 {
+		compatible = "qcom,gdsc";
+		regulator-name = "vcodec0_gdsc";
+		reg = <0xab00874 0x4>;
+		status = "disabled";
+	};
+
+	venus_gdsc: qcom,gdsc@ab00814 {
+		compatible = "qcom,gdsc";
+		regulator-name = "venus_gdsc";
+		reg = <0xab00814 0x4>;
+		status = "disabled";
+	};
+
+	/* GDSCs in NPU CC */
+	npu_core_gdsc: qcom,gdsc@9981004 {
+		compatible = "qcom,gdsc";
+		regulator-name = "npu_core_gdsc";
+		reg = <0x9981004 0x4>;
+		status = "disabled";
+	};
+};

arch/arm64/boot/dts/19721/atoll-idp-overlay.dts

@@ -0,0 +1,38 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "atoll-idp.dtsi"
+#include "atoll-audio-overlay.dtsi"
+
+/ {
+	model = "IDP";
+	compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp";
+	qcom,msm-id = <407 0x0>;
+	qcom,board-id = <34 0>;
+	oppo,dtsi_no = <19721>;
+};
+
+//#ifdef OPLUS_BUG_STABILITY
+/* Shusheng.Bei@MULTIMEDIA.DISPLAY.LCD, 2020/10/20, add for bring up 19721 NT36672C JDI panel */
+/*&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};*/
+&dsi_nt36672c_jdi_video_display {
+        qcom,dsi-display-active;
+ };
+//#endif /* OPLUS_BUG_STABILITY */
+

arch/arm64/boot/dts/19721/atoll-idp.dts

@@ -0,0 +1,26 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll.dtsi"
+#include "atoll-idp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL PM6150 IDP";
+	compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp";
+	qcom,board-id = <34 0>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};

arch/arm64/boot/dts/19721/atoll-idp.dtsi

@@ -0,0 +1,737 @@
+/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "atoll-camera-sensor-idp.dtsi"
+#include "atoll-sde-display.dtsi"
+#include "sdmmagpie-thermal-overlay.dtsi"
+
+&soc {
+	//#ifdef VENDOR_EDIT
+	/* Yu.Kun@CN.NFC.Basic.Hardware, 2020/03/24, Add for oppo nfc chipset */
+	nfc_chipset {
+		compatible = "oppo-nfc-chipset";
+		chipset-19721-26 = "SN100T";
+	};
+	//#endif /* VENDOR_EDIT */
+
+	mtp_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+		#include "qg-batterydata-alium-3600mah.dtsi"
+	};
+	//#ifdef VENDOR_EDIT
+	/*yajie.chen @BSP.sensor, 2020/04/03, Add for sensor dts*/
+	/*enum sensor_id { OPPO_ACCEL,OPPO_GYRO,OPPO_MAG,OPPO_LIGHT,OPPO_PROXIMITY,OPPO_SAR,OPPO_CT,OPPO_BAROMETER,SENSORS_NUM};*/
+	oplus_sensor {
+		compatible = "oplus,sensor-devinfo";
+		als-row-coe = <110>;
+		/*enum {LSM6DSM = 0x01, BMI160 = 0x02, LSM6DS3 = 0x04};*/
+		gsensor@0 {
+			sensor-name = <0x02>;//BMI160
+			sensor-direction = <7>;
+			sensor-index = <0>;//source num
+			sensor-type = <0>;//OPPO_ACCEL
+		};
+		gsensor@1 {
+			sensor-name = <0x04>;//LSM6DS3
+			sensor-direction = <0>;
+			sensor-index = <1>;//source num
+			sensor-type = <0>;//OPPO_ACCEL
+		};
+		/* enum {AKM0991X = 0x01, MMC5603 = 0x02};*/
+        msensor@0 {
+            sensor-name = <0x01>;//AKM0991X
+            sensor-direction = <0>;
+            sensor-index = <1>;
+            sensor-type = <2>;//OPPO_MAG
+            mag-para1 {
+                parameter-number= <18>;
+                projects-num = <3>;
+                match-projects = <19720 19721 19728>;
+                soft-mag-parameter = <9886 0 280 1 63 0 242 0 10310 0 313 1 163 1 134 1 10269 0>;//e00 sign e01 sign...
+            };
+            mag-para2 {
+                parameter-number= <18>;
+                projects-num = <1>;
+                match-projects = <19726>;
+                soft-mag-parameter = <10617 0 1256 0 199 0 1194 0 9605 0 138 1 498 0 1171 1 10202 0>;//e00 sign e01 sign...
+            };
+
+        };
+        /*enum {STK3A5X=0x01,TCS3701=0x02,TCS3408=0x04};*/
+        /*lsensor@0 {
+            sensor-name = <0x01>;//STK3A5X=0x01
+            sensor-index = <0>;
+            sensor-type = <3>;//OPPO_LIGHT
+            bus-number = <5>;
+            irq-number = <93>;
+			als-type = <2>;
+			is-unit-device = <1>;
+			is-als-dri = <1>;
+			als-factor = <110>;
+			is_als_initialed = <0>;
+			als_buffer_length = <10>;
+		};
+		psensor@0 {
+			sensor-name = <0x01>;//STK3A5X
+			sensor-index = <0>;
+			sensor-type = <4>;//OPPO_PROXIMITY
+			bus-number = <5>;
+			irq-number = <93>;
+			ps-cail-type = <2>;
+			ps-type = <1>;
+			is_ps_initialzed = <0>;
+			low_step = <300>;
+			high_step = <400>;
+			low_limit = <400>;
+			high_limit = <600>;
+			dirty_low_step = <100>;
+			dirty_high_step = <150>;
+			ps_dirty_limit = <1020>;
+			ps_ir_limit = <500>;
+			ps_adjust_min = <0>;
+			ps_adjust_max = <600>;
+			sampling_count = <5>;
+			step_max = <400>;
+			step_min = <100>;
+			step_div = <1500>;
+			anti_shake_delta = <80>;
+			dynamic_cali_max = <1024>;
+			raw2offset_radio = <20800>;
+			offset_max = <250>;
+			offset_range_min = <0xFFFFFF01>;// -255
+			offset_range_max = <255>;
+			force_cali_limit = <2000>;
+			cali_jitter_limit = <20>;
+			cal_offset_margin = <80>;
+		};*/
+		/*virtual sensor
+		enum sensor_algo_id {
+			OPPO_PICKUP_DETECT,
+			OPPO_LUX_AOD,
+			OPPO_TP_GESTURE,
+			OPPO_FP_DISPLAY,
+			OPPO_FREE_FALL,
+			OPPO_CAMERA_PROTECT,
+			SENSOR_ALGO_NUM
+		}*/
+		pickup_detect {
+			sensor-type = <0>; //OPPO_PICKUP_DETECT
+			is-virtual-sensor;
+			is-need-prox = <1>;
+			prox-type = <0>; // 0 - proximity; 1 - proximity_fake
+		};
+		lux_aod {
+			sensor-type = <1>; //OPPO_LUX_AOD
+			is-virtual-sensor;
+			thrd-low = <12>;
+			thrd-high = <50>;
+			als-type = <1>; // 0 - ambient_light; 1 - wise_light
+		};
+		fp_display {
+			sensor-type = <3>; //OPPO_FP_DISPLAY
+			is-virtual-sensor;
+			prox-type = <0>; // 0 - proximity; 1 - proximity_fake
+		};
+		free_fall {
+			sensor-type = <4>; //OPPO_FREE_FALL
+			is-virtual-sensor;
+		};
+	};
+	//#endif /*VENDOR_EDIT*/
+	
+	//#ifdef VENDOR_EDIT
+	/* ZhangKe@Network.RF 2020/10/15 modify for oppo rf cable monitor */
+	oplus_rf_cable {
+		compatible = "oplus,rf_cable";
+		interrupt-parent = <&tlmm>;
+		rf_cable_support_num = <1>;
+		rf,cable0-gpio = <&tlmm 118 0>;
+		rf,cable-support-timer = <0>;
+		pinctrl-names = "rf_cable_active";
+		pinctrl-0 = <&rf_cable0_active>;
+	};
+	//#endif /* VENDOR_EDIT */
+};
+/*#ifndef ODM_LQ_EDIT*/
+/*liujiawei@ODM_LQ.BSP.CHG,2020/07/22, remove pa_therm1 */
+/*
+&pm6150l_vadc {
+	pa_therm1 {
+		reg = <ADC_AMUX_THM3_PU2>;
+		label = "pa_therm1";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm6150l_adc_tm {
+	io-channels = <&pm6150l_vadc ADC_AMUX_THM1_PU2>,
+			<&pm6150l_vadc ADC_AMUX_THM2_PU2>,
+			<&pm6150l_vadc ADC_AMUX_THM3_PU2>,
+			<&pm6150l_vadc ADC_GPIO1_PU2>;
+
+	pa_therm1 {
+		reg = <ADC_AMUX_THM3_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+*/
+/*endif*/
+&usb0 {
+	extcon = <&pm6150_pdphy>, <&pm6150_charger>, <&eud>;
+};
+
+&usb_qmp_dp_phy {
+	extcon = <&pm6150_pdphy>;
+};
+
+//#ifdef VENDOR_EDIT
+//tongfeng.huang@BSP.CHG.Basic  2019/11/20  add for board-id adc
+&pm6150_gpios{
+	gpio10_adc {
+		gpio10_adc_default: gpio10_adc_default {
+			pins = "gpio10"; /* GPIO 10 */
+			function = "normal"; /* normal */
+			bias-high-impedance; /* DISABLE GPIO10 for ADC*/
+		};
+	};
+};
+//#endif
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v3";
+
+	vdda-phy-supply = <&pm6150_l4>; /* 0.9v */
+	vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */
+	vdda-phy-max-microamp = <62900>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&ufs_phy_gdsc>;
+	vdd-hba-fixed-regulator;
+	vcc-supply = <&pm6150_l19>;
+	vcc-voltage-level = <2960000 2960000>;
+	vcc-max-microamp = <600000>;
+	vccq2-supply = <&pm6150_l12>;
+	vccq2-voltage-level = <1750000 1950000>;
+	vccq2-max-microamp = <600000>;
+
+	qcom,vddp-ref-clk-supply = <&pm6150l_l3>; /* PX10 */
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	status = "ok";
+};
+
+&sdhc_1 {
+	vdd-supply = <&pm6150_l19>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&pm6150_l12>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+	status = "ok";
+};
+
+&sdhc_2 {
+	vdd-supply = <&pm6150l_l9>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&pm6150l_l6>;
+	qcom,vdd-io-voltage-level = <1800000 2950000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	pinctrl-names = "active", "sleep";
+//#ifndef VENDOR_EDIT
+//huyu@BSP.Storage.Sdcard,2020/08/12 Add for SDcard detect
+	//pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+//#else
+	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on &sd_detect_default>;
+//#endif
+	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+//#ifndef VENDOR_EDIT
+//huyu@BSP.Storage.Sdcard,2020/08/12 Add for SDcard detect
+	//cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
+//#else
+    cd-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>;
+//#endif
+
+	status = "ok";
+};
+
+&thermal_zones {
+/*#ifndef ODM_LQ_EDIT*/
+/*liujiawei@ODM_LQ.BSP.CHG,2020/07/22, remove pa_therm1 */
+/*
+	pa-therm1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm6150l_adc_tm ADC_AMUX_THM3_PU2>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+*/
+/*endif*/
+	quiet-therm-step {
+		status = "disabled";
+	};
+};
+
+&pm6150a_amoled {
+	status = "ok";
+};
+
+&pm6150_qg {
+	qcom,battery-data = <&mtp_batterydata>;
+	qcom,qg-iterm-ma = <100>;
+	qcom,hold-soc-while-full;
+	qcom,linearize-soc;
+	qcom,cl-feedback-on;
+};
+
+&pm6150_charger {
+	io-channels = <&pm6150_vadc ADC_USB_IN_V_16>,
+		      <&pm6150_vadc ADC_USB_IN_I>,
+		      <&pm6150_vadc ADC_CHG_TEMP>,
+		      <&pm6150_vadc ADC_DIE_TEMP>,
+//#ifdef VENDOR_EDIT
+/*Gang.Yan@BSP.CHG.Basic 2020/04/14  for usbtemp */
+//		      <&pm6150_vadc ADC_AMUX_THM3_PU2>,
+//#endif
+		      <&pm6150_vadc ADC_SBUx>,
+//#ifdef VENDOR_EDIT
+/* lizhijie@BSP.CHG.Basic 2020/02/25  for usbtemp */
+		      <&pm6150_vadc ADC_AMUX_THM2>,
+		      <&pm6150_vadc ADC_AMUX_THM3>,
+//#endif
+		      <&pm6150_vadc ADC_VPH_PWR>;
+	io-channel-names = "usb_in_voltage",
+			   "usb_in_current",
+			   "chg_temp",
+			   "die_temp",
+//#ifdef VENDOR_EDIT
+/*Gang.Yan@BSP.CHG.Basic 2020/04/14  for usbtemp */
+//			   "conn_temp",
+//#endif
+			   "sbux_res",
+//#ifdef VENDOR_EDIT
+/* lizhijie@BSP.CHG.Basic 2020/02/25  for usbtemp */
+			   "usb_temp_adc",
+     		   "usb_supplementary_temp_adc",
+//#endif
+			   "vph_voltage";
+	qcom,battery-data = <&mtp_batterydata>;
+//#ifndef VENDOR_EDIT
+/* lizhijie@BSP.CHG.Basic 2020/02/25  for charger */
+//	qcom,auto-recharge-soc = <98>;
+//	qcom,step-charging-enable;
+//	qcom,sw-jeita-enable;
+//	qcom,fcc-stepping-enable;
+//	qcom,suspend-input-on-debug-batt;
+//	qcom,sec-charger-config = <3>;
+//	qcom,thermal-mitigation = <4200000 3500000 3000000
+//			2500000 2000000 1500000 1000000 500000>;
+//#endif
+
+	dpdm-supply = <&qusb_phy0>;
+//#ifndef VENDOR_EDIT
+/* lizhijie@BSP.CHG.Basic 2020/02/25  for charger */
+//	qcom,charger-temp-max = <800>;
+//	qcom,smb-temp-max = <800>;
+//	qcom,fcc-step-delay-ms = <100>;
+//	qcom,fcc-step-size-ua = <100000>;
+//	qcom,disable-sw-thermal-regulation;
+//	qcom,disable-fcc-restriction;
+//	qcom,smb-internal-pull-kohm = <0>;
+//#endif
+};
+
+&pm6150l_gpios {
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio2";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+};
+
+&soc {
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		/*#ifdef ODM_LQ_EDIT*/
+		/*shentaotao@ODM_LQ@BSP.KEY,2019/11/22,modified for EVT2-2 volume key*/
+		pinctrl-0 = <&key_vol_down_default>;
+		/*#else*/
+		/*
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			linux,can-disable;
+			debounce-interval = <15>;
+			gpio-key,wakeup;
+		};
+                */
+		/*#endif ODM_LQ_EDIT*/
+/*#ifdef ODM_LQ_EDIT*/
+/*Hongbin.Chen@ODM_LQ@BSP.Key,2019/10/08 Modify for config volum down key*/
+		vol_down {
+			label = "volume_down";
+			gpios = <&tlmm 117 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEDOWN>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+/*#endif  ODM_LQ_EDIT*/
+	};
+    // #ifdef OPLUS_FEATURE_SECURITY_COMMON
+    /* Rui.Tuo@BSP.Security.Basic 2020-10-01 add for oplus_secure_common */
+    oplus_secure_common {
+        compatible = "oplus,secure_common";
+    };
+    //#endif //OPLUS_FEATURE_SECURITY_COMMON
+
+//#ifdef OPLUS_FEATURE_FINGERPRINT
+/*wuzhipeng@ODM_LQ@BSP.fingerprint,2019/10/08 for goodix fingerprint*/
+		oppo_fp_common {
+			compatible = "oplus,fp_common";
+			oplus,fp_pinctrl_type = <1>;
+			oplus,fp_gpio_num = <1>;
+			qcom,platform-fp-id-gpio = <&pm6150_gpios 5 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "pullup", "pulldown";
+			pinctrl-0 = <&fingerprint_pins_pullup>;
+			pinctrl-1 = <&fingerprint_pins_pulldown>;
+			oplus,fp_gpio_pin = <1276>; // &pm6150_gpios 5, Q = 1275, R = 1276
+
+			goodix_optical {
+				oplus,fp-id = <0>; /* pin state unconnected, fp id mapping table. if pin state pullup, id = 2 */
+				vendor-chip = <16>; /* please refer to the struct fp_vendor_t in oppo_fp_commmon.n */
+				eng-menu = "-1,-1"; /* represents SNR, inclination test item in engineer menu, and 0/1 means off/on */
+				chip-name = "G_3626";  /* /proc/fp_id, will be displayed in engineer menu  */
+			};
+			fpc_optical {
+				oplus,fp-id = <1>; /* pin state pulldown, fp id mapping table */
+				vendor-chip = <20>; /* please refer to the struct fp_vendor_t in oppo_fp_commmon.n */
+				eng-menu = "-1,-1"; /* represents SNR, inclination test item in engineer menu, and 0/1 means off/on */
+				chip-name = "F_1540";  /* /proc/fp_id, will be displayed in engineer menu  */
+			};
+		};
+
+		goodix_fp {
+			status = "ok";
+			compatible = "goodix,goodix_fp";
+			interrupt-parent = <&tlmm>;
+			interrupts = <90 0>;
+			ldo-supply = <&pm6150_l18>;
+			ldo-config = <2960000 2960000 50000>;
+			goodix,gpio_irq = <&tlmm 90 0x00>;
+			goodix,gpio_reset = <&tlmm 92 0x00>;
+			pinctrl-names = "default";
+//			pinctrl-0 = <&gpio_goodix_irq_default>;
+//			pinctrl-1 = <&goodix_pwr_default>;
+			power-num = <2> ;
+			power_source_1 {
+				power-mode = <1>;   /* 1 = ldo power, refer to oplus_fp_common.h*/
+				power-name = "ldo";
+				power-config = "ldo-config";
+				delay-time = <0>;
+			};
+
+
+
+		};
+
+		fpc1020 {
+			status = "ok";
+			compatible = "fpc,fpc1020";
+			interrupt-parent = <&tlmm>;
+			interrupts = <90 0x0>;
+			ldo-supply = <&pm6150_l10>;
+			ldo-config = <1800000 1800000 60000>;
+			fpc,rst-gpio    = <&tlmm 92 0x0>;
+			fpc,irq-gpio    = <&tlmm 90 0x0>;
+			pinctrl-names = "default";
+		};
+//#endif /*OPLUS_FEATURE_FINGERPRINT*/
+};
+
+&qupv3_se7_i2c {
+/*#ifndef ODM_LQ_EDIT*/
+/*liujiawei@ODM_LQ@BSP.CHG,2019/10/08,modified for disable qupv3_se7_i2c*/
+//	status = "ok";
+/*#else*/
+	status = "disabled";
+/*#endif*/
+
+	qcom,i2c-touch-active = "synaptics,tcm-i2c";
+
+	synaptics_tcm@20 {
+		compatible = "synaptics,tcm-i2c";
+		reg = <0x20>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <9 0x2008>;
+		pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+			"pmx_ts_release";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+		vdd-supply = <&pm6150_l10>;
+		avdd-supply = <&pm6150l_l7>;
+		synaptics,pwr-reg-name = "avdd";
+		synaptics,bus-reg-name = "vdd";
+		synaptics,irq-gpio = <&tlmm 9 0x2008>;
+		synaptics,irq-on-state = <0>;
+		synaptics,reset-gpio = <&tlmm 8 0x00>;
+		synaptics,reset-on-state = <0>;
+		synaptics,reset-active-ms = <20>;
+		synaptics,reset-delay-ms = <200>;
+		synaptics,power-delay-ms = <200>;
+		synaptics,ubl-i2c-addr = <0x20>;
+	};
+
+	atmel_mxt_ts@4a {
+		compatible = "atmel,maxtouch";
+		reg = <0x4a>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <9 0x2008>;
+		avdd-supply = <&pm6150l_l7>;
+		vdd-supply = <&pm6150_l10>;
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		reset-gpios = <&tlmm 8 0x00>;
+		irq-gpios = <&tlmm 9 0x2008>;
+
+		atmel,xy_switch;
+		atmel,panel-coords = <0 0 479 799>;
+		atmel,display-coords = <0 0 339 769>;
+	};
+};
+
+/*zhaifeibiao@ODM_LQ@BSP.touch,2020/11/03,Add for oppo project*/
+&qupv3_se10_spi {
+	status = "ok";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	 NovatekJDI@0 {
+		status = "ok";
+		compatible = "novatek,nf_nt36672c";
+		reg = <1>; //Same as CS ID
+		chip-name = "NT36672C_NF";
+ 
+		//modify by zhaifeibiao@ODM_LQ@BSP.TP for spi frequency, 2020/11/03
+		spi-max-frequency = <15000000>;	//4800000,9600000,15000000,19200000
+		interrupt-parent = <&tlmm>;
+		interrupts = <9 0x2008>;
+		//touch_vddio-supply = <&L13A>;	//add by zhaifeibiao@ODM_LQ@BSP.TP for vddio, 2020/11/03
+		//touch_lab-supply = <&lcdb_ldo_vreg>;	//add by zhaifeibiao@ODM_LQ@BSP.TP for lab, 2020/11/03
+		//touch_ibb-supply = <&lcdb_ncp_vreg>;	//add by zhaifeibiao@ODM_LQ@BSP.TP for ibb, 2020/11/03
+		reset-gpio = <&tlmm 8 0x00>;
+		irq-gpio = <&tlmm 9 0x2001>;
+		cs-gpio = <&tlmm 89 0x01>;            // add by zhaifeibiao@ODM_LQ@BSP.TP for CS.2020/11/03
+		//boe-touchpanel,tx-rx-num = <18 36>;   //boe channel=<18 36> add by zhaifeibiao@ODM_LQ@BSP.TP for selftest, 2020/11/03
+		touchpanel,tx-rx-num = <16 36>;   //jdi channel=<16 36> add by zhaifeibiao@ODM_LQ@BSP.TP for selftest, 2020/11/03
+		touchpanel,max-num-support = <10>;
+		touchpanel,panel-coords = <1080 2400>;
+		touchpanel,display-coords = <1080 2400>;
+		touchpanel,touchmajor-limit = <0 54>;
+
+		vid_len = <0>;
+		project_id = <19721>;
+		platform_support_project = <19721 19721>;
+		platform_support_project_dir = <19721 19721>;
+		platform_support_project_commandline = "dsi_nt36672c_jdi_video_display", "dsi_nt36672c_boe_video_display";
+		platform_support_project_external_name = "NVT_JDI";
+
+		incell_screen;
+		fw_update_in_probe_with_headfile;
+		fw_edge_limit_support;
+		black_gesture_support;
+		charger_pump_support;
+		headset_pump_support;
+		//spurious_fingerprint_support;
+		//lcd_trigger_fp_check;
+		esd_handle_support;
+		black_gesture_test_support;
+		game_switch_support;
+		noflash_support;
+		lcd_trigger_load_tp_fw_support;
+		smart_gesture_support;
+		new_set_irq_wake_support;
+		pressure_report_support;
+		fw_update_app_support;
+		cs_gpio_need_pull;
+		irq_need_dev_resume_ok;
+		touchpanel,button-type = <4>;
+	};
+	NovatekBOE@1 {
+		status = "ok";
+		compatible = "novatek,nf_nt36672c";
+		reg = <1>; //Same as CS ID
+		chip-name = "NT36672C_NF";
+
+		//modify by zhaifeibiao@ODM_LQ@BSP.TP for spi frequency, 2020/11/03
+		spi-max-frequency = <15000000>;	//4800000,9600000,15000000,19200000
+		interrupt-parent = <&tlmm>;
+		interrupts = <9 0x2008>;
+		//touch_vddio-supply = <&L13A>;	//add by zhaifeibiao@ODM_LQ@BSP.TP for vddio, 2020/11/03
+		//touch_lab-supply = <&lcdb_ldo_vreg>;	//add by zhaifeibiao@ODM_LQ@BSP.TP for lab, 2020/11/03
+		//touch_ibb-supply = <&lcdb_ncp_vreg>;	//add by zhaifeibiao@ODM_LQ@BSP.TP for ibb, 2020/11/03
+		reset-gpio = <&tlmm 8 0x00>;
+		irq-gpio = <&tlmm 9 0x2001>;
+		cs-gpio = <&tlmm 89 0x01>;            // add by zhaifeibiao@ODM_LQ@BSP.TP for CS.2020/11/03
+		//boe-touchpanel,tx-rx-num = <18 36>;   //boe channel=<18 36> add by zhaifeibiao@ODM_LQ@BSP.TP for selftest, 2020/11/03
+		touchpanel,tx-rx-num = <18 36>;   //jdi channel=<16 36> add by zhaifeibiao@ODM_LQ@BSP.TP for selftest, 2020/11/03
+		touchpanel,max-num-support = <10>;
+		touchpanel,panel-coords = <1080 2400>;
+		touchpanel,display-coords = <1080 2400>;
+		touchpanel,touchmajor-limit = <0 54>;
+
+		vid_len = <0>;
+		project_id = <19721>;
+		platform_support_project = <19721 19721>;
+		platform_support_project_dir = <19721 19721>;
+		platform_support_project_commandline = "dsi_nt36672c_jdi_video_display", "dsi_nt36672c_boe_video_display";
+		platform_support_project_external_name = "NVT_BOE";
+
+		incell_screen;
+		fw_update_in_probe_with_headfile;
+		fw_edge_limit_support;
+		black_gesture_support;
+		charger_pump_support;
+		headset_pump_support;
+		//spurious_fingerprint_support;
+		//lcd_trigger_fp_check;
+		esd_handle_support;
+		black_gesture_test_support;
+		game_switch_support;
+		noflash_support;
+		lcd_trigger_load_tp_fw_support;
+		smart_gesture_support;
+		new_set_irq_wake_support;
+		pressure_report_support;
+		fw_update_app_support;
+		cs_gpio_need_pull;
+		irq_need_dev_resume_ok;
+		touchpanel,button-type = <4>;
+	};
+};
+/*zhaifeibiao@ODM_LQ@BSP.touch,2020/11/03,Add for oppo project*/
+
+&dsi_rm69299_visionox_amoled_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <255>;
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+};
+
+&dsi_rm69299_visionox_amoled_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <255>;
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+};
+
+&dsi_nt36672c_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <255>;
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+	qcom,platform-bklight-en-gpio = <&pm6150l_gpios 10 0>;
+	qcom,platform-en-gpio = <&pm6150l_gpios 4 0>;
+};
+
+&qupv3_se0_i2c {
+	status = "ok";
+       //#ifndef VENDOR_EDIT
+       //Weiwei.Deng@CN.NFC.Basic.Hardware.2354150, 2019/09/26, reset nfc i2c freq to default value
+       //qcom,clk-freq-out = <1000000>;
+       //#endif /* VENDOR_EDIT */
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,nq-nci";
+		reg = <0x28>;
+		qcom,nq-irq = <&tlmm 37 0x00>;
+		qcom,nq-ven = <&tlmm 12 0x00>;
+		qcom,nq-firm = <&tlmm 36 0x00>;
+		qcom,nq-clkreq = <&tlmm 31 0x00>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <37 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active
+				&nfc_clk_req_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+				&nfc_clk_req_suspend>;
+	};
+};
+
+/* Hongwei.Di@BSP.CHG.Basic, 2020/09/16, remove fsa switch for usb */
+/*	
+&sde_dp{
+	qcom,dp-aux-switch = <&fsa4480>;
+};*/
+
+/* Hongwei.Di@BSP.CHG.Basic, 2020/09/16, remove fsa switch for usb */
+&fsa4480{
+	status="disabled";
+};
+
+//#ifdef VENDOR_EDIT
+///* lizhijie@BSP.CHG.Basic  2020-02-25  oppo charge edit dts */
+#include "oppo-charge.dtsi"
+//endif

arch/arm64/boot/dts/19721/atoll-ion.dtsi

@@ -0,0 +1,56 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+	qcom,ion {
+		compatible = "qcom,msm-ion";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		system_heap: qcom,ion-heap@25 {
+			reg = <25>;
+			qcom,ion-heap-type = "SYSTEM";
+		};
+
+		qcom,ion-heap@27 { /* QSEECOM HEAP */
+			reg = <27>;
+			memory-region = <&qseecom_mem>;
+			qcom,ion-heap-type = "DMA";
+		};
+
+		qcom,ion-heap@19 { /* QSEECOM TA HEAP */
+			reg = <19>;
+			memory-region = <&qseecom_ta_mem>;
+			qcom,ion-heap-type = "DMA";
+		};
+
+		qcom,ion-heap@9 {
+			reg = <9>;
+			qcom,ion-heap-type = "SYSTEM_SECURE";
+		};
+
+		qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
+			reg = <10>;
+			memory-region = <&secure_display_memory>;
+			qcom,ion-heap-type = "HYP_CMA";
+		};
+
+		qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */
+			reg = <14>;
+			qcom,ion-heap-type = "SECURE_CARVEOUT";
+			cdsp {
+				memory-region = <&cdsp_sec_mem>;
+				token = <0x20000000>;
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/atoll-lpi.dtsi

@@ -0,0 +1,423 @@
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&q6core {
+	lpi_tlmm: lpi_pinctrl@627C0000 {
+		compatible = "qcom,lpi-pinctrl";
+		reg = <0x627C0000 0x0>;
+		qcom,num-gpios = <15>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		qcom,slew-reg = <0x6295A000 0x0>;
+		qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
+				      <0x00002000>, <0x00003000>,
+				      <0x00004000>, <0x00005000>,
+				      <0x00006000>, <0x00007000>,
+				      <0x00008000>, <0x00009000>,
+				      <0x0000A000>, <0x0000B000>,
+				      <0x0000C000>, <0x0000D000>,
+				      <0x0000E000>;
+
+		qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
+					   <0x00000004>, <0x00000008>,
+					   <0x0000000A>, <0x0000000C>,
+					   <0x00000000>, <0x00000000>,
+					   <0x00000000>, <0x00000000>,
+					   <0x00000010>, <0x00000012>,
+					   <0x00000000>, <0x00000000>,
+					   <0x00000000>;
+
+		clock-names = "lpass_core_hw_vote",
+				"lpass_audio_hw_vote";
+		clocks = <&lpass_core_hw_vote 0>,
+				<&lpass_audio_hw_vote 0>;
+
+		cdc_dmic01_clk_active: dmic01_clk_active {
+			mux {
+				pins = "gpio6";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio6";
+				drive-strength = <8>;
+				output-high;
+			};
+		};
+
+		cdc_dmic01_clk_sleep: dmic01_clk_sleep {
+			mux {
+				pins = "gpio6";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio6";
+				drive-strength = <2>;
+				bias-disable;
+				output-low;
+			};
+		};
+
+		cdc_dmic01_data_active: dmic01_data_active {
+			mux {
+				pins = "gpio7";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <8>;
+				input-enable;
+			};
+		};
+
+		cdc_dmic01_data_sleep: dmic01_data_sleep {
+			mux {
+				pins = "gpio7";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <2>;
+				pull-down;
+				input-enable;
+			};
+		};
+
+		cdc_dmic23_clk_active: dmic23_clk_active {
+			mux {
+				pins = "gpio8";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio8";
+				drive-strength = <8>;
+				output-high;
+			};
+		};
+
+		cdc_dmic23_clk_sleep: dmic23_clk_sleep {
+			mux {
+				pins = "gpio8";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio8";
+				drive-strength = <2>;
+				bias-disable;
+				output-low;
+			};
+		};
+
+		cdc_dmic23_data_active: dmic23_data_active {
+			mux {
+				pins = "gpio9";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <8>;
+				input-enable;
+			};
+		};
+
+		cdc_dmic23_data_sleep: dmic23_data_sleep {
+			mux {
+				pins = "gpio9";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <2>;
+				pull-down;
+				input-enable;
+			};
+		};
+
+		cdc_dmic45_clk_active: dmic45_clk_active {
+			mux {
+				pins = "gpio12";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio12";
+				drive-strength = <8>;
+				output-high;
+			};
+		};
+
+		cdc_dmic45_clk_sleep: dmic45_clk_sleep {
+			mux {
+				pins = "gpio12";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio12";
+				drive-strength = <2>;
+				bias-disable;
+				output-low;
+			};
+		};
+
+		cdc_dmic45_data_active: dmic45_data_active {
+			mux {
+				pins = "gpio13";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio13";
+				drive-strength = <8>;
+				input-enable;
+			};
+		};
+
+		cdc_dmic45_data_sleep: dmic45_data_sleep {
+			mux {
+				pins = "gpio13";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio13";
+				drive-strength = <2>;
+				pull-down;
+				input-enable;
+			};
+		};
+
+		tx_swr_clk_sleep: tx_swr_clk_sleep {
+			mux {
+				pins = "gpio0";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <10>;
+				bias-bus-hold;
+			};
+		};
+
+		tx_swr_clk_active: tx_swr_clk_active {
+			mux {
+				pins = "gpio0";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <10>;
+				slew-rate = <3>;
+				bias-disable;
+			};
+		};
+
+		tx_swr_data0_sleep: tx_swr_data0_sleep {
+			mux {
+				pins = "gpio1";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <10>;
+				bias-bus-hold;
+			};
+		};
+
+		tx_swr_data0_active: tx_swr_data0_active {
+			mux {
+				pins = "gpio1";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <10>;
+				slew-rate = <3>;
+				bias-bus-hold;
+			};
+		};
+
+		wsa_swr_clk_sleep: wsa_swr_clk_sleep {
+			mux {
+				pins = "gpio10";
+				function = "func2";
+			};
+
+			config {
+				pins = "gpio10";
+				drive-strength = <10>;
+				bias-bus-hold;
+			};
+		};
+
+		wsa_swr_clk_active: wsa_swr_clk_active {
+			mux {
+				pins = "gpio10";
+				function = "func2";
+			};
+
+			config {
+				pins = "gpio10";
+				drive-strength = <10>;
+				slew-rate = <3>;
+				bias-bus-hold;
+			};
+		};
+
+		wsa_swr_data_sleep: wsa_swr_data_sleep {
+			mux {
+				pins = "gpio11";
+				function = "func2";
+			};
+
+			config {
+				pins = "gpio11";
+				drive-strength = <10>;
+				bias-bus-hold;
+			};
+		};
+
+		wsa_swr_data_active: wsa_swr_data_active {
+			mux {
+				pins = "gpio11";
+				function = "func2";
+			};
+
+			config {
+				pins = "gpio11";
+				drive-strength = <10>;
+				slew-rate = <3>;
+				bias-bus-hold;
+			};
+		};
+
+		tx_swr_data1_sleep: tx_swr_data1_sleep {
+			mux {
+				pins = "gpio2";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio2";
+				drive-strength = <10>;
+				bias-bus-hold;
+			};
+		};
+
+		tx_swr_data1_active: tx_swr_data1_active {
+			mux {
+				pins = "gpio2";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio2";
+				drive-strength = <10>;
+				slew-rate = <3>;
+				bias-bus-hold;
+			};
+		};
+
+		tx_swr_data2_sleep: tx_swr_data2_sleep {
+			mux {
+				pins = "gpio14";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio14";
+				drive-strength = <10>;
+				bias-bus-hold;
+			};
+		};
+
+		tx_swr_data2_active: tx_swr_data2_active {
+			mux {
+				pins = "gpio14";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio14";
+				drive-strength = <10>;
+				slew-rate = <3>;
+				bias-bus-hold;
+			};
+		};
+
+		rx_swr_clk_sleep: rx_swr_clk_sleep {
+			mux {
+				pins = "gpio3";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio3";
+				drive-strength = <10>;
+				bias-bus-hold;
+			};
+		};
+
+		rx_swr_clk_active: rx_swr_clk_active {
+			mux {
+				pins = "gpio3";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio3";
+				drive-strength = <10>;
+				slew-rate = <3>;
+				bias-disable;
+			};
+		};
+
+		rx_swr_data_sleep: rx_swr_data_sleep {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <10>;
+				bias-bus-hold;
+			};
+		};
+
+		rx_swr_data_active: rx_swr_data_active {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <10>;
+				slew-rate = <3>;
+				bias-bus-hold;
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/atoll-npu.dtsi

@@ -0,0 +1,171 @@
+/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+	msm_npu: qcom,msm_npu@9800000 {
+		compatible = "qcom,msm-npu";
+		status = "ok";
+		reg = <0x9900000 0x20000>,
+			<0x99f0000 0x10000>,
+			<0x9980000 0x10000>,
+			<0x17c00000 0x10000>,
+			<0x01f40000 0x40000>,
+			<0x780000 0x7000>;
+		reg-names = "tcm", "core", "cc", "apss_shared", "tcsr",
+			"qfprom_physical";
+		interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
+			"general_irq";
+		iommus = <&apps_smmu 0x1441 0x0>, <&apps_smmu 0x1442 0x0>,
+			<&apps_smmu 0x1461 0x0>, <&apps_smmu 0x1462 0x0>,
+			<&apps_smmu 0x1481 0x0>, <&apps_smmu 0x1482 0x0>;
+
+		clocks = <&clock_npucc NPU_CC_XO_CLK>,
+			<&clock_npucc NPU_CC_CORE_CLK>,
+			<&clock_npucc NPU_CC_CAL_HM0_CLK>,
+			<&clock_npucc NPU_CC_CAL_HM0_CDC_CLK>,
+			<&clock_npucc NPU_CC_NOC_AXI_CLK>,
+			<&clock_npucc NPU_CC_NOC_AHB_CLK>,
+			<&clock_npucc NPU_CC_NOC_DMA_CLK>,
+			<&clock_npucc NPU_CC_RSC_XO_CLK>,
+			<&clock_npucc NPU_CC_S2P_CLK>,
+			<&clock_npucc NPU_CC_BWMON_CLK>,
+			<&clock_npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,
+			<&clock_npucc NPU_CC_BTO_CORE_CLK>,
+			<&clock_npucc NPU_DSP_CORE_CLK_SRC>;
+		clock-names = "xo_clk",
+			"npu_core_clk",
+			"cal_hm0_clk",
+			"cal_hm0_cdc_clk",
+			"axi_clk",
+			"ahb_clk",
+			"dma_clk",
+			"rsc_xo_clk",
+			"s2p_clk",
+			"bwmon_clk",
+			"cal_hm0_perf_cnt_clk",
+			"bto_core_clk",
+			"dsp_core_clk_src";
+
+		vdd-supply = <&npu_core_gdsc>;
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		qcom,proxy-reg-names ="vdd", "vdd_cx";
+		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		#cooling-cells = <2>;
+		mboxes = <&apcs_glb2 4>,
+			<&apcs_glb2 6>;
+		mbox-names = "glink", "smp2p";
+		#mbox-cells = <1>;
+		qcom,npubw-devs = <&npu_npu_ddr_bw>, <&npudsp_npu_ddr_bw>;
+		qcom,npubw-dev-names = "ddr_bw", "dsp_ddr_bw";
+		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>,
+			<MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_CLK_CTL>;
+		qcom,npu-pwrlevels {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "qcom,npu-pwrlevels";
+			initial-pwrlevel = <4>;
+			qcom,npu-pwrlevel@0 {
+				reg = <0>;
+				vreg = <1>;
+				clk-freq = <19200000
+					100000000
+					192000000
+					192000000
+					150000000
+					30000000
+					200000000
+					19200000
+					50000000
+					19200000
+					192000000
+					19200000
+					300000000>;
+			};
+
+			qcom,npu-pwrlevel@1 {
+				reg = <1>;
+				vreg = <2>;
+				clk-freq = <19200000
+					200000000
+					268800000
+					268800000
+					200000000
+					37500000
+					300000000
+					19200000
+					50000000
+					19200000
+					268800000
+					19200000
+					400000000>;
+			};
+
+			qcom,npu-pwrlevel@2 {
+				reg = <2>;
+				vreg = <3>;
+				clk-freq = <19200000
+					333000000
+					403200000
+					403200000
+					300000000
+					37500000
+					403000000
+					19200000
+					50000000
+					19200000
+					403200000
+					19200000
+					500000000>;
+			};
+
+			qcom,npu-pwrlevel@3 {
+				reg = <3>;
+				vreg = <4>;
+				clk-freq = <19200000
+					428000000
+					515000000
+					515000000
+					403000000
+					75000000
+					600000000
+					19200000
+					100000000
+					19200000
+					515000000
+					19200000
+					660000000>;
+			};
+
+			qcom,npu-pwrlevel@4 {
+				reg = <4>;
+				vreg = <6>;
+				clk-freq = <19200000
+					500000000
+					748800000
+					748800000
+					533000000
+					75000000
+					710000000
+					19200000
+					100000000
+					19200000
+					748800000
+					19200000
+					800000000>;
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/atoll-pm.dtsi

@@ -0,0 +1,171 @@
+/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+	qcom,lpm-levels {
+		compatible = "qcom,lpm-levels";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,pm-cluster@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			label = "L3";
+			qcom,psci-mode-shift = <4>;
+			qcom,psci-mode-mask = <0xfff>;
+			qcom,clstr-tmr-add = <1000>;
+
+			qcom,pm-cluster-level@0 { /* D1 */
+				reg = <0>;
+				label = "l3-wfi";
+				qcom,psci-mode = <0x1>;
+				qcom,entry-latency-us = <660>;
+				qcom,exit-latency-us = <600>;
+				qcom,min-residency-us = <1260>;
+			};
+
+			qcom,pm-cluster-level@1 { /* D4 */
+				reg = <1>;
+				label = "l3-pc";
+				qcom,psci-mode = <0x4>;
+				qcom,entry-latency-us = <2752>;
+				qcom,exit-latency-us = <3048>;
+				qcom,min-residency-us = <6118>;
+				qcom,min-child-idx = <2>;
+				qcom,is-reset;
+			};
+
+			qcom,pm-cluster-level@2 { /* Cx Ret */
+				reg = <2>;
+				label = "cx-ret";
+				qcom,psci-mode = <0x124>;
+				qcom,entry-latency-us = <3638>;
+				qcom,exit-latency-us = <4562>;
+				qcom,min-residency-us = <8467>;
+				qcom,min-child-idx = <2>;
+				qcom,is-reset;
+				qcom,notify-rpm;
+			};
+
+			qcom,pm-cluster-level@3 { /* LLCC off, AOSS sleep */
+				reg = <3>;
+				label = "llcc-off";
+				qcom,psci-mode = <0xB24>;
+				qcom,entry-latency-us = <3263>;
+				qcom,exit-latency-us = <6562>;
+				qcom,min-residency-us = <9826>;
+				qcom,min-child-idx = <2>;
+				qcom,is-reset;
+				qcom,notify-rpm;
+			};
+
+			qcom,pm-cpu@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				qcom,psci-mode-shift = <0>;
+				qcom,psci-mode-mask = <0xf>;
+				qcom,disable-ipi-prediction;
+				qcom,ref-stddev = <500>;
+				qcom,tmr-add = <1000>;
+				qcom,ref-premature-cnt = <1>;
+				qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4
+									&CPU5>;
+
+				qcom,pm-cpu-level@0 { /* C1 */
+					reg = <0>;
+					label = "wfi";
+					qcom,psci-cpu-mode = <0x1>;
+					qcom,entry-latency-us = <61>;
+					qcom,exit-latency-us = <60>;
+					qcom,min-residency-us = <121>;
+				};
+
+				qcom,pm-cpu-level@1 {  /* C3 */
+					reg = <1>;
+					label = "pc";
+					qcom,psci-cpu-mode = <0x3>;
+					qcom,entry-latency-us = <549>;
+					qcom,exit-latency-us = <901>;
+					qcom,min-residency-us = <1774>;
+					qcom,is-reset;
+					qcom,use-broadcast-timer;
+				};
+
+				qcom,pm-cpu-level@2 {  /* C4 */
+					reg = <2>;
+					label = "rail-pc";
+					qcom,psci-cpu-mode = <0x4>;
+					qcom,entry-latency-us = <702>;
+					qcom,exit-latency-us = <915>;
+					qcom,min-residency-us = <4001>;
+					qcom,is-reset;
+					qcom,use-broadcast-timer;
+				};
+			};
+
+			qcom,pm-cpu@1 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				qcom,psci-mode-shift = <0>;
+				qcom,psci-mode-mask = <0xf>;
+				qcom,ref-stddev = <100>;
+				qcom,tmr-add = <100>;
+				qcom,ref-premature-cnt = <3>;
+				qcom,cpu = <&CPU6 &CPU7>;
+
+				qcom,pm-cpu-level@0 { /* C1 */
+					reg = <0>;
+					label = "wfi";
+					qcom,psci-cpu-mode = <0x1>;
+					qcom,entry-latency-us = <55>;
+					qcom,exit-latency-us = <66>;
+					qcom,min-residency-us = <121>;
+				};
+
+				qcom,pm-cpu-level@1 {  /* C3 */
+					reg = <1>;
+					label = "pc";
+					qcom,psci-cpu-mode = <0x3>;
+					qcom,entry-latency-us = <523>;
+					qcom,exit-latency-us = <1244>;
+					qcom,min-residency-us = <2207>;
+					qcom,is-reset;
+					qcom,use-broadcast-timer;
+				};
+
+				qcom,pm-cpu-level@2 {  /* C4 */
+					reg = <2>;
+					label = "rail-pc";
+					qcom,psci-cpu-mode = <0x4>;
+					qcom,entry-latency-us = <526>;
+					qcom,exit-latency-us = <1854>;
+					qcom,min-residency-us = <5555>;
+					qcom,is-reset;
+					qcom,use-broadcast-timer;
+				};
+			};
+		};
+	};
+
+	qcom,rpm-stats@c300000 {
+		compatible = "qcom,rpm-stats";
+		reg = <0xc300000 0x1000>, <0xc3f0004 0x4>;
+		reg-names = "phys_addr_base", "offset_addr";
+		qcom,num-records = <3>;
+	};
+
+	qcom,rpmh-master-stats@b221200 {
+		compatible = "qcom,rpmh-master-stats-v1";
+		reg = <0xb221200 0x60>;
+	};
+};

arch/arm64/boot/dts/19721/atoll-qrd-overlay.dts

@@ -0,0 +1,23 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "atoll-qrd.dtsi"
+
+/ {
+	model = "QRD";
+	compatible = "qcom,atoll-qrd", "qcom,atoll", "qcom,qrd";
+	qcom,msm-id = <407 0x0>;
+	qcom,board-id = <0x1000B 0>;
+};

arch/arm64/boot/dts/19721/atoll-qrd.dts

@@ -0,0 +1,22 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll.dtsi"
+#include "atoll-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL PM6150 QRD";
+	compatible = "qcom,atoll-qrd", "qcom,atoll", "qcom,qrd";
+	qcom,board-id = <0x1000B 0>;
+};

arch/arm64/boot/dts/19721/atoll-qrd.dtsi

@@ -0,0 +1,504 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "atoll-audio-overlay.dtsi"
+#include "atoll-camera-sensor-qrd.dtsi"
+#include "atoll-sde-display.dtsi"
+#include "sdmmagpie-thermal-overlay.dtsi"
+
+&tlmm {
+	fpc_reset_int: fpc_reset_int {
+		fpc_reset_low: reset_low {
+			mux {
+				pins = "gpio91";
+				function = "gpio";
+			};
+			config {
+				pins = "gpio91";
+				drive-strength = <2>;
+				bias-disable;
+				output-low;
+			};
+		};
+
+		fpc_reset_high: reset_high {
+			mux {
+				pins = "gpio91";
+				function = "gpio";
+			};
+			config {
+				pins = "gpio91";
+				drive-strength = <2>;
+				bias-disable;
+				output-high;
+			};
+		};
+
+		fpc_int_low: int_low {
+			mux {
+				pins = "gpio90";
+				function = "gpio";
+			};
+			config {
+				pins = "gpio90";
+				drive-strength = <2>;
+				bias-pull-down;
+				input-enable;
+			};
+		};
+	};
+};
+
+&soc {
+	qrd_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+		#include "qg-batterydata-atl466271_3300mAh.dtsi"
+	};
+
+	fingerprint: fpc1020 {
+		compatible = "fpc,fpc1020";
+		interrupt-parent = <&tlmm>;
+		interrupts = <90 0>;
+		fpc,gpio_rst = <&tlmm 91 0>;
+		fpc,gpio_irq = <&tlmm 90 0>;
+		vcc_spi-supply = <&pm6150_l10>;
+		vdd_io-supply  = <&pm6150_l10>;
+		vdd_ana-supply = <&pm6150_l10>;
+		fpc,enable-on-boot;
+		pinctrl-names = "fpc1020_reset_reset",
+				"fpc1020_reset_active",
+				"fpc1020_irq_active";
+		pinctrl-0 = <&fpc_reset_low>;
+		pinctrl-1 = <&fpc_reset_high>;
+		pinctrl-2 = <&fpc_int_low>;
+	};
+};
+
+&pm6150a_amoled {
+	status = "ok";
+};
+
+&pm6150_qg {
+	qcom,battery-data = <&qrd_batterydata>;
+	qcom,qg-iterm-ma = <100>;
+	qcom,hold-soc-while-full;
+	qcom,linearize-soc;
+	qcom,cl-feedback-on;
+};
+
+&pm6150_charger {
+	io-channels = <&pm6150_vadc ADC_USB_IN_V_16>,
+		      <&pm6150_vadc ADC_USB_IN_I>,
+		      <&pm6150_vadc ADC_CHG_TEMP>,
+		      <&pm6150_vadc ADC_DIE_TEMP>,
+		      <&pm6150_vadc ADC_AMUX_THM3_PU2>,
+		      <&pm6150_vadc ADC_SBUx>,
+		      <&pm6150_vadc ADC_VPH_PWR>;
+	io-channel-names = "usb_in_voltage",
+			   "usb_in_current",
+			   "chg_temp",
+			   "die_temp",
+			   "conn_temp",
+			   "sbux_res",
+			   "vph_voltage";
+	qcom,battery-data = <&qrd_batterydata>;
+	qcom,auto-recharge-soc = <98>;
+	qcom,step-charging-enable;
+	qcom,sw-jeita-enable;
+	qcom,fcc-stepping-enable;
+	qcom,suspend-input-on-debug-batt;
+	qcom,sec-charger-config = <1>;
+	qcom,thermal-mitigation = <4200000 3500000 3000000
+			2500000 2000000 1500000 1000000 500000>;
+	dpdm-supply = <&qusb_phy0>;
+	qcom,charger-temp-max = <800>;
+	qcom,smb-temp-max = <800>;
+	qcom,fcc-step-delay-ms = <100>;
+	qcom,fcc-step-size-ua = <100000>;
+	qcom,disable-sw-thermal-regulation;
+	qcom,disable-fcc-restriction;
+	qcom,smb-internal-pull-kohm = <0>;
+};
+
+&usb0 {
+	extcon = <&pm6150_pdphy>, <&pm6150_charger>, <&eud>;
+};
+
+&qusb_phy0 {
+	qcom,qusb-phy-init-seq =
+		/* <value reg_offset> */
+		<0x23 0x210 /* PWR_CTRL1 */
+		 0x03 0x04  /* PLL_ANALOG_CONTROLS_TWO */
+		 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+		 0x80 0x2c  /* PLL_CMODE */
+		 0x0a 0x184 /* PLL_LOCK_DELAY */
+		 0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */
+		 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+		 0x18 0x198 /* PLL_BIAS_CONTROL_2 */
+		 0x21 0x214 /* PWR_CTRL2 */
+		 0x08 0x220 /* IMP_CTRL1 */
+		 0x58 0x224 /* IMP_CTRL2 */
+		 0x47 0x240 /* TUNE1 */
+		 0x28 0x244 /* TUNE2 */
+		 0xca 0x248 /* TUNE3 */
+		 0x04 0x24c /* TUNE4 */
+		 0x03 0x250 /* TUNE5 */
+		 0x30 0x23c /* CHG_CTRL2 */
+		 0x22 0x210>; /* PWR_CTRL1 */
+
+	qcom,qusb-phy-host-init-seq =
+		/* <value reg_offset> */
+		<0x23 0x210 /* PWR_CTRL1 */
+		0x03 0x04  /* PLL_ANALOG_CONTROLS_TWO */
+		0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+		0x80 0x2c  /* PLL_CMODE */
+		0x0a 0x184 /* PLL_LOCK_DELAY */
+		0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */
+		0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+		0x18 0x198 /* PLL_BIAS_CONTROL_2 */
+		0x21 0x214 /* PWR_CTRL2 */
+		0x08 0x220 /* IMP_CTRL1 */
+		0x58 0x224 /* IMP_CTRL2 */
+		0x47 0x240 /* TUNE1 */
+		0x28 0x244 /* TUNE2 */
+		0xca 0x248 /* TUNE3 */
+		0x04 0x24c /* TUNE4 */
+		0x03 0x250 /* TUNE5 */
+		0x30 0x23c /* CHG_CTRL2 */
+		0x22 0x210>; /* PWR_CTRL1 */
+};
+
+&usb_qmp_dp_phy {
+	extcon = <&pm6150_pdphy>;
+};
+
+&pm6150_gpios {
+	smb_stat {
+	smb_stat_default: smb_stat_default {
+			pins = "gpio3";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+			power-source = <0>;
+		};
+	};
+};
+
+&qupv3_se9_i2c {
+	status = "ok";
+	#include "smb1390.dtsi"
+};
+
+&smb1390 {
+	/delete-property/ interrupts;
+	interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&smb_stat_default>;
+	status = "ok";
+};
+
+&smb1390_charger {
+	compatible = "qcom,smb1390-charger-psy";
+	io-channels = <&pm6150_vadc ADC_AMUX_THM2>;
+	io-channel-names = "cp_die_temp";
+	qcom,parallel-input-mode = <1>; /* USBIN */
+	qcom,parallel-output-mode = <2>; /* VBAT */
+	qcom,min-ilim-ua = <750000>;
+	status = "ok";
+};
+
+&smb1390_slave {
+	status = "ok";
+};
+
+&smb1390_slave_charger {
+	status = "ok";
+};
+
+&pm6150l_gpios {
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio2";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			linux,can-disable;
+			debounce-interval = <15>;
+			gpio-key,wakeup;
+		};
+
+	};
+};
+
+&qupv3_se7_i2c {
+	status = "ok";
+
+	synaptics_tcm@20 {
+		compatible = "synaptics,tcm-i2c";
+		reg = <0x20>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <9 0x2008>;
+		pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+			"pmx_ts_release";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+		vdd-supply = <&pm6150_l10>;
+		avdd-supply = <&pm6150l_l7>;
+		synaptics,pwr-reg-name = "avdd";
+		synaptics,bus-reg-name = "vdd";
+		synaptics,irq-gpio = <&tlmm 9 0x2008>;
+		synaptics,irq-on-state = <0>;
+		synaptics,reset-gpio = <&tlmm 8 0x00>;
+		synaptics,reset-on-state = <0>;
+		synaptics,reset-active-ms = <20>;
+		synaptics,reset-delay-ms = <200>;
+		synaptics,power-delay-ms = <200>;
+		synaptics,ubl-i2c-addr = <0x20>;
+	};
+};
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v3";
+
+	vdda-phy-supply = <&pm6150_l4>; /* 0.9v */
+	vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */
+	vdda-phy-max-microamp = <62900>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&ufs_phy_gdsc>;
+	vdd-hba-fixed-regulator;
+	vcc-supply = <&pm6150_l19>;
+	vcc-voltage-level = <2960000 2960000>;
+	vcc-max-microamp = <600000>;
+	vccq2-supply = <&pm6150_l12>;
+	vccq2-voltage-level = <1750000 1950000>;
+	vccq2-max-microamp = <600000>;
+
+	qcom,vddp-ref-clk-supply = <&pm6150l_l3>; /* PX10 */
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	status = "ok";
+};
+
+&sdhc_1 {
+	vdd-supply = <&pm6150_l19>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&pm6150_l12>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+	status = "ok";
+};
+
+&sdhc_2 {
+	vdd-supply = <&pm6150l_l9>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&pm6150l_l6>;
+	qcom,vdd-io-voltage-level = <1800000 2950000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+	cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
+
+	status = "ok";
+};
+
+&atoll_snd {
+	qcom,model = "atoll-qrd-snd-card";
+	qcom,audio-routing =
+		"AMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Analog Mic1",
+		"AMIC2", "MIC BIAS2",
+		"MIC BIAS2", "Analog Mic2",
+		"AMIC3", "MIC BIAS3",
+		"MIC BIAS3", "Analog Mic3",
+		"AMIC4", "MIC BIAS1",
+		"MIC BIAS1", "Analog Mic4",
+		"TX DMIC0", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic0",
+		"TX DMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic1",
+		"TX DMIC2", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic2",
+		"TX DMIC3", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic3",
+		"TX DMIC4", "MIC BIAS4",
+		"MIC BIAS4", "Digital Mic4",
+		"IN1_HPHL", "HPHL_OUT",
+		"IN2_HPHR", "HPHR_OUT",
+		"IN3_AUX", "AUX_OUT",
+		"TX SWR_ADC0", "ADC1_OUTPUT",
+		"TX SWR_ADC1", "ADC2_OUTPUT",
+		"TX SWR_ADC2", "ADC3_OUTPUT",
+		"TX SWR_ADC3", "ADC4_OUTPUT",
+		"TX SWR_DMIC0", "DMIC1_OUTPUT",
+		"TX SWR_DMIC1", "DMIC2_OUTPUT",
+		"TX SWR_DMIC2", "DMIC3_OUTPUT",
+		"TX SWR_DMIC3", "DMIC4_OUTPUT",
+		"TX SWR_DMIC4", "DMIC5_OUTPUT",
+		"TX SWR_DMIC5", "DMIC6_OUTPUT",
+		"TX SWR_DMIC6", "DMIC7_OUTPUT",
+		"TX SWR_DMIC7", "DMIC8_OUTPUT",
+		"WSA SRC0_INP", "SRC0",
+		"WSA_TX DEC0_INP", "TX DEC0 MUX",
+		"WSA_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC0_INP", "TX DEC0 MUX",
+		"RX_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC2_INP", "TX DEC2 MUX",
+		"RX_TX DEC3_INP", "TX DEC3 MUX",
+		"SpkrLeft IN", "WSA_SPK1 OUT",
+		"SpkrRight IN", "WSA_SPK2 OUT",
+		"VA MIC BIAS3", "Digital Mic0",
+		"VA MIC BIAS3", "Digital Mic1",
+		"VA MIC BIAS1", "Digital Mic2",
+		"VA MIC BIAS1", "Digital Mic3",
+		"VA MIC BIAS4", "Digital Mic4",
+		"VA MIC BIAS4", "Digital Mic5",
+		"VA DMIC0", "VA MIC BIAS3",
+		"VA DMIC1", "VA MIC BIAS3",
+		"VA DMIC2", "VA MIC BIAS1",
+		"VA DMIC3", "VA MIC BIAS1",
+		"VA DMIC4", "VA MIC BIAS4",
+		"VA DMIC5", "VA MIC BIAS4",
+		"VA SWR_ADC0", "VA_SWR_CLK",
+		"VA SWR_ADC1", "VA_SWR_CLK",
+		"VA SWR_ADC2", "VA_SWR_CLK",
+		"VA SWR_ADC3", "VA_SWR_CLK",
+		"VA SWR_MIC0", "VA_SWR_CLK",
+		"VA SWR_MIC1", "VA_SWR_CLK",
+		"VA SWR_MIC2", "VA_SWR_CLK",
+		"VA SWR_MIC3", "VA_SWR_CLK",
+		"VA SWR_MIC4", "VA_SWR_CLK",
+		"VA SWR_MIC5", "VA_SWR_CLK",
+		"VA SWR_MIC6", "VA_SWR_CLK",
+		"VA SWR_MIC7", "VA_SWR_CLK",
+		"VA SWR_ADC0", "ADC1_OUTPUT",
+		"VA SWR_ADC1", "ADC2_OUTPUT",
+		"VA SWR_ADC2", "ADC3_OUTPUT",
+		"VA SWR_ADC3", "ADC4_OUTPUT",
+		"VA SWR_MIC0", "DMIC1_OUTPUT",
+		"VA SWR_MIC1", "DMIC2_OUTPUT",
+		"VA SWR_MIC2", "DMIC3_OUTPUT",
+		"VA SWR_MIC3", "DMIC4_OUTPUT",
+		"VA SWR_MIC4", "DMIC5_OUTPUT",
+		"VA SWR_MIC5", "DMIC6_OUTPUT",
+		"VA SWR_MIC6", "DMIC7_OUTPUT",
+		"VA SWR_MIC7", "DMIC8_OUTPUT";
+	qcom,wsa-max-devs = <1>;
+	qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>;
+	qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft";
+};
+
+&qupv3_se0_i2c {
+	status = "ok";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,nq-nci";
+		reg = <0x28>;
+		qcom,nq-irq = <&tlmm 37 0x00>;
+		qcom,nq-ven = <&tlmm 12 0x00>;
+		qcom,nq-firm = <&tlmm 36 0x00>;
+		qcom,nq-clkreq = <&tlmm 31 0x00>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <37 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active
+				&nfc_clk_req_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+				&nfc_clk_req_suspend>;
+	};
+};
+
+&dsi_rm69299_visionox_amoled_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <255>;
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+};
+
+&dsi_rm69299_visionox_amoled_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <255>;
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};
+
+&sde_dp{
+	pinctrl-names = "mdss_dp_active", "mdss_dp_sleep", "default";
+	pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
+	pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
+	pinctrl-2 = <&sde_dp_aux_suspend>;
+	qcom,aux-en-gpio = <&tlmm 55 0>;
+//#ifdef VENDOR_EDIT
+//lizhijie@BSP.CHG.Basic. 2020/02/25 add for charger
+	qcom,aux-sel-gpio = <&tlmm 93 0>;
+//#else
+//	qcom,aux-sel-gpio = <&tlmm 33 0>;
+//endif
+	qcom,dp-gpio-aux-switch;
+};
+
+&fsa4480{
+	status="disabled";
+};

arch/arm64/boot/dts/19721/atoll-qupv3.dtsi

@@ -0,0 +1,566 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+	/* QUPv3 North Instances
+	 * North 0 : SE 0
+	 * North 1 : SE 1
+	 * North 2 : SE 2
+	 * North 3 : SE 3
+	 * North 4 : SE 4
+	 * North 5 : SE 5
+	 */
+
+	qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0x8c0000 0x2000>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-bus-ids =
+			<MSM_BUS_MASTER_QUP_CORE_0 MSM_BUS_SLAVE_QUP_CORE_0>,
+			<MSM_BUS_MASTER_QUP_0 MSM_BUS_SLAVE_EBI_CH0>;
+		qcom,iommu-atomic-ctx;
+
+		iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {
+			compatible = "qcom,qupv3-geni-se-cb";
+			iommus = <&apps_smmu 0x43 0x0>;
+		};
+	};
+
+	/* GPI */
+	gpi_dma0: qcom,gpi-dma@800000 {
+		#dma-cells = <5>;
+		compatible = "qcom,gpi-dma";
+		reg = <0x800000 0x60000>;
+		reg-names = "gpi-top";
+		interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,
+			     <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,
+			     <0 252 0>, <0 253 0>;
+		qcom,max-num-gpii = <10>;
+		qcom,gpii-mask = <0x1f>;
+		qcom,ev-factor = <2>;
+		iommus = <&apps_smmu 0x56 0x0>;
+		qcom,smmu-cfg = <0x1>;
+		qcom,gpi-ee-offset = <0x10000>;
+		qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
+		status = "ok";
+	};
+
+	/* SPI */
+	qupv3_se0_spi: spi@880000 {
+		compatible = "qcom,spi-geni";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x880000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		//#ifndef OPLUS_ARCH_EXTENDS
+		//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.MACHINE, 2020/07/30, Delete for audio use gpio34/35 as i2c
+		/*
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se0_spi_active>;
+		pinctrl-1 = <&qupv3_se0_spi_sleep>;
+		*/
+		//#endif /* OPLUS_ARCH_EXTENDS */
+		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		dmas = <&gpi_dma0 0 0 1 64 0>,
+			<&gpi_dma0 1 0 1 64 0>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+	qupv3_se1_spi: spi@884000 {
+		compatible = "qcom,spi-geni";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x884000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se1_spi_active>;
+		pinctrl-1 = <&qupv3_se1_spi_sleep>;
+		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		dmas = <&gpi_dma0 0 1 1 64 0>,
+			<&gpi_dma0 1 1 1 64 0>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+	qupv3_se3_spi: spi@88c000 {
+		compatible = "qcom,spi-geni";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x88c000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se3_spi_active>;
+		pinctrl-1 = <&qupv3_se3_spi_sleep>;
+		interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		dmas = <&gpi_dma0 0 3 1 64 0>,
+			<&gpi_dma0 1 3 1 64 0>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+	qupv3_se5_spi: spi@894000 {
+		compatible = "qcom,spi-geni";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x894000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se5_spi_active>;
+		pinctrl-1 = <&qupv3_se5_spi_sleep>;
+		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		dmas = <&gpi_dma0 0 5 1 64 0>,
+			<&gpi_dma0 1 5 1 64 0>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+	/* I2C */
+	qupv3_se0_i2c: i2c@880000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x880000 0x4000>;
+		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		dmas = <&gpi_dma0 0 0 3 64 0>,
+			<&gpi_dma0 1 0 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se0_i2c_active>;
+		pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se1_i2c: i2c@884000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x884000 0x4000>;
+		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		dmas = <&gpi_dma0 0 1 3 64 0>,
+			<&gpi_dma0 1 1 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se1_i2c_active>;
+		pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se2_i2c: i2c@888000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x888000 0x4000>;
+		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		dmas = <&gpi_dma0 0 2 3 64 0>,
+			<&gpi_dma0 1 2 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se2_i2c_active>;
+		pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se3_i2c: i2c@88c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x88c000 0x4000>;
+		interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		dmas = <&gpi_dma0 0 3 3 64 0>,
+			<&gpi_dma0 1 3 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se3_i2c_active>;
+		pinctrl-1 = <&qupv3_se3_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se4_i2c: i2c@890000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x890000 0x4000>;
+		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		dmas = <&gpi_dma0 0 4 3 64 0>,
+			<&gpi_dma0 1 4 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se4_i2c_active>;
+		pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se5_i2c: i2c@894000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x894000 0x4000>;
+		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		dmas = <&gpi_dma0 0 5 3 64 0>,
+			<&gpi_dma0 1 5 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se5_i2c_active>;
+		pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	/* HSUART: BT used instance */
+	qupv3_se3_4uart: qcom,qup_uart@88c000 {
+		compatible = "qcom,msm-geni-serial-hs";
+		reg = <0x88c000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "active", "sleep";
+		pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>,
+				<&qupv3_se3_default_tx>;
+		pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
+				<&qupv3_se3_tx>;
+		pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
+				<&qupv3_se3_tx>;
+		interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+				<&tlmm 41 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,wrapper-core = <&qupv3_0>;
+		qcom,wakeup-byte = <0xFD>;
+		status = "disabled";
+	};
+
+	/* QUPv3 South Instances
+	 * South 0 : SE 6
+	 * South 1 : SE 7
+	 * South 2 : SE 8
+	 * South 3 : SE 9
+	 * South 4 : SE 10
+	 * South 5 : SE 11
+	 */
+
+	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0xac0000 0x2000>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-bus-ids =
+			<MSM_BUS_MASTER_QUP_CORE_1 MSM_BUS_SLAVE_QUP_CORE_1>,
+			<MSM_BUS_MASTER_QUP_1 MSM_BUS_SLAVE_EBI_CH0>;
+		qcom,iommu-atomic-ctx;
+
+		iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {
+			compatible = "qcom,qupv3-geni-se-cb";
+			iommus = <&apps_smmu 0x4c3 0x0>;
+		};
+	};
+
+	/* GPI */
+	gpi_dma1: qcom,gpi-dma@a00000 {
+		#dma-cells = <5>;
+		compatible = "qcom,gpi-dma";
+		reg = <0xa00000 0x60000>;
+		reg-names = "gpi-top";
+		interrupts = <0 645 0>, <0 646 0>, <0 647 0>, <0 648 0>,
+			     <0 649 0>, <0 650 0>, <0 651 0>, <0 652 0>,
+			     <0 653 0>, <0 654 0>;
+		qcom,max-num-gpii = <10>;
+		qcom,gpii-mask = <0x3f>;
+		qcom,ev-factor = <2>;
+		iommus = <&apps_smmu 0x4d6 0x0>;
+		qcom,smmu-cfg = <0x1>;
+		qcom,gpi-ee-offset = <0x10000>;
+		qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
+		status = "ok";
+	};
+
+	/* SPI */
+	qupv3_se6_spi: spi@a80000 {
+		compatible = "qcom,spi-geni";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0xa80000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se6_spi_active>;
+		pinctrl-1 = <&qupv3_se6_spi_sleep>;
+		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		dmas = <&gpi_dma1 0 0 1 64 0>,
+			<&gpi_dma1 1 0 1 64 0>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+	qupv3_se8_spi: spi@a88000 {
+		compatible = "qcom,spi-geni";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0xa88000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se8_spi_active>;
+		pinctrl-1 = <&qupv3_se8_spi_sleep>;
+		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		dmas = <&gpi_dma1 0 2 1 64 0>,
+			<&gpi_dma1 1 2 1 64 0>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+	qupv3_se10_spi: spi@a90000 {
+		compatible = "qcom,spi-geni";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0xa90000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se10_spi_active>;
+		pinctrl-1 = <&qupv3_se10_spi_sleep>;
+		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		dmas = <&gpi_dma1 0 4 1 64 0>,
+			<&gpi_dma1 1 4 1 64 0>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+	qupv3_se11_spi: spi@a94000 {
+		compatible = "qcom,spi-geni";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0xa94000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se11_spi_active>;
+		pinctrl-1 = <&qupv3_se11_spi_sleep>;
+		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		dmas = <&gpi_dma1 0 5 1 64 0>,
+			<&gpi_dma1 1 5 1 64 0>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+	/* I2C */
+	qupv3_se6_i2c: i2c@a80000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa80000 0x4000>;
+		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		dmas = <&gpi_dma1 0 0 3 64 0>,
+			<&gpi_dma1 1 0 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se6_i2c_active>;
+		pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se7_i2c: i2c@a84000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa84000 0x4000>;
+		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		dmas = <&gpi_dma1 0 1 3 64 0>,
+			<&gpi_dma1 1 1 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se7_i2c_active>;
+		pinctrl-1 = <&qupv3_se7_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se8_i2c: i2c@a88000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa88000 0x4000>;
+		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		dmas = <&gpi_dma1 0 2 3 64 0>,
+			<&gpi_dma1 1 2 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se8_i2c_active>;
+		pinctrl-1 = <&qupv3_se8_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se9_i2c: i2c@a8c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa8c000 0x4000>;
+		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		dmas = <&gpi_dma1 0 3 3 64 0>,
+			<&gpi_dma1 1 3 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se9_i2c_active>;
+		pinctrl-1 = <&qupv3_se9_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se10_i2c: i2c@a90000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa90000 0x4000>;
+		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		dmas = <&gpi_dma1 0 4 3 64 0>,
+			<&gpi_dma1 1 4 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se10_i2c_active>;
+		pinctrl-1 = <&qupv3_se10_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se11_i2c: i2c@a94000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa94000 0x4000>;
+		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		dmas = <&gpi_dma1 0 5 3 64 0>,
+			<&gpi_dma1 1 5 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se11_i2c_active>;
+		pinctrl-1 = <&qupv3_se11_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se8_2uart: qcom,qup_uart@a88000 {
+		compatible = "qcom,msm-geni-console";
+		reg = <0xa88000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se8_2uart_active>;
+		pinctrl-1 = <&qupv3_se8_2uart_sleep>;
+		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+};

arch/arm64/boot/dts/19721/atoll-regulator.dtsi

@@ -0,0 +1,854 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+&soc {
+	rpmh-regulator-cxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "cx.lvl";
+		pm6150l-s1-level-parent-supply = <&VDD_MX_LEVEL>;
+		pm6150l-s1-level_ao-parent-supply = <&VDD_MX_LEVEL_AO>;
+		VDD_CX_LEVEL:
+		S1C_LEVEL:
+		pm6150l_s1_level: regulator-pm6150l-s1-level {
+			regulator-name = "pm6150l_s1_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			qcom,min-dropout-voltage-level = <(-1)>;
+		};
+
+		VDD_CX_LEVEL_AO:
+		S1C_LEVEL_AO:
+		pm6150l_s1_level_ao: regulator-pm6150l-s1-level-ao {
+			regulator-name = "pm6150l_s1_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			qcom,min-dropout-voltage-level = <(-1)>;
+		};
+
+		cx_cdev: regulator-cdev {
+			compatible = "qcom,rpmh-reg-cdev";
+			mboxes = <&qmp_aop 0>;
+			qcom,reg-resource-name = "cx";
+			#cooling-cells = <2>;
+		};
+	};
+
+	rpmh-regulator-gfxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "gfx.lvl";
+		VDD_GFX_LEVEL:
+		S2A_LEVEL:
+		pm6150_s2_level: regulator-pm6150-s2-level {
+			regulator-name = "pm6150_s2_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-mxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "mx.lvl";
+		VDD_MX_LEVEL:
+		S3A_LEVEL:
+		pm6150_s3_level: regulator-pm6150-s3-level {
+			regulator-name = "pm6150_s3_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+
+		VDD_MX_LEVEL_AO:
+		S3A_LEVEL_AO:
+		pm6150_s3_level_ao: regulator-pm6150-s3-level-ao {
+			regulator-name = "pm6150_s3_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+
+		mx_cdev: mx-cdev-lvl {
+			compatible = "qcom,regulator-cooling-device";
+			regulator-cdev-supply = <&VDD_MX_LEVEL>;
+			regulator-levels = <RPMH_REGULATOR_LEVEL_NOM
+					RPMH_REGULATOR_LEVEL_OFF>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	rpmh-regulator-smpa1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "smpa1";
+		S1A:
+		pm6150_s1: regulator-pm6150-s1 {
+			regulator-name = "pm6150_s1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1128000>;
+			regulator-max-microvolt = <1128000>;
+			qcom,init-voltage = <1128000>;
+		};
+	};
+
+	rpmh-regulator-smpa4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "smpa4";
+		S4A:
+		pm6150_s4: regulator-pm6150-s4 {
+			regulator-name = "pm6150_s4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <824000>;
+			regulator-max-microvolt = <1120000>;
+			qcom,init-voltage = <824000>;
+		};
+	};
+
+	rpmh-regulator-smpa5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "smpa5";
+		S5A:
+		pm6150_s5: regulator-pm6150-s5 {
+			regulator-name = "pm6150_s5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1744000>;
+			regulator-max-microvolt = <2040000>;
+			qcom,init-voltage = <1744000>;
+		};
+	};
+
+	rpmh-regulator-ldoa1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L1A:
+		pm6150_l1: regulator-pm6150-l1 {
+			regulator-name = "pm6150_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1178000>;
+			regulator-max-microvolt = <1256000>;
+			qcom,init-voltage = <1178000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L2A:
+		pm6150_l2: regulator-pm6150-l2 {
+			regulator-name = "pm6150_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <944000>;
+			regulator-max-microvolt = <1056000>;
+			qcom,init-voltage = <944000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L3A:
+		pm6150_l3: regulator-pm6150-l3 {
+			regulator-name = "pm6150_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <968000>;
+			regulator-max-microvolt = <1064000>;
+			qcom,init-voltage = <968000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa4";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L4A:
+		pm6150_l4: regulator-pm6150-l4 {
+			regulator-name = "pm6150_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <824000>;
+			regulator-max-microvolt = <928000>;
+			qcom,init-voltage = <824000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa5";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L5A:
+		pm6150_l5: regulator-pm6150-l5 {
+			regulator-name = "pm6150_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa6";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L6A:
+		pm6150_l6: regulator-pm6150-l6 {
+			regulator-name = "pm6150_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <568000>;
+			regulator-max-microvolt = <648000>;
+			qcom,init-voltage = <568000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-lmxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "lmx.lvl";
+		L7A_LEVEL:
+		pm6150_l7_level: regulator-pm6150-l7-level {
+			regulator-name = "pm6150_l7_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-lcxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "lcx.lvl";
+		L8A_LEVEL:
+		pm6150_l8_level: regulator-pm6150-l8-level {
+			regulator-name = "pm6150_l8_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-ldoa9 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa9";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L9A:
+		pm6150_l9: regulator-pm6150-l9 {
+			regulator-name = "pm6150_l9";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <488000>;
+			regulator-max-microvolt = <800000>;
+			qcom,init-voltage = <488000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa10 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa10";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L10A:
+		pm6150_l10: regulator-pm6150-l10 {
+			regulator-name = "pm6150_l10";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1832000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa11 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa11";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L11A:
+		pm6150_l11: regulator-pm6150-l11 {
+			regulator-name = "pm6150_l11";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1904000>;
+			qcom,init-voltage = <1696000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa12 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa12";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L12A:
+		pm6150_l12: regulator-pm6150-l12 {
+			regulator-name = "pm6150_l12";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1952000>;
+			qcom,init-voltage = <1696000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa13 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa13";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L13A:
+		pm6150_l13: regulator-pm6150-l13 {
+			regulator-name = "pm6150_l13";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1904000>;
+			qcom,init-voltage = <1696000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa14 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa14";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L14A:
+		pm6150_l14: regulator-pm6150-l14 {
+			regulator-name = "pm6150_l14";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1728000>;
+			regulator-max-microvolt = <1832000>;
+			qcom,init-voltage = <1728000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa15 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa15";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L15A:
+		pm6150_l15: regulator-pm6150-l15 {
+			regulator-name = "pm6150_l15";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1696000>;
+			regulator-max-microvolt = <1904000>;
+			qcom,init-voltage = <1696000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa16 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa16";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L16A:
+		pm6150_l16: regulator-pm6150-l16 {
+			regulator-name = "pm6150_l16";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2496000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <2496000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa17 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa17";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L17A:
+		pm6150_l17: regulator-pm6150-l17 {
+			regulator-name = "pm6150_l17";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2920000>;
+			regulator-max-microvolt = <3232000>;
+			qcom,init-voltage = <2920000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa18 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa18";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L18A:
+		pm6150_l18: regulator-pm6150-l18 {
+			regulator-name = "pm6150_l18";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2496000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <2496000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa19 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoa19";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L19A:
+		pm6150_l19: regulator-pm6150-l19 {
+			regulator-name = "pm6150_l19";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2696000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <2696000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-msslvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "mss.lvl";
+		VDD_MSS_LEVEL:
+		S7C_LEVEL:
+		pm6150l_s7_level: regulator-pm6150l-s7-level {
+			regulator-name = "pm6150l_s7_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-smpc8 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "smpc8";
+		S8C:
+		pm6150l_s8: regulator-pm6150l-s8 {
+			regulator-name = "pm6150l_s8";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1120000>;
+			regulator-max-microvolt = <1408000>;
+			qcom,init-voltage = <1120000>;
+		};
+	};
+
+	rpmh-regulator-ldoc1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L1C:
+		pm6150l_l1: regulator-pm6150l-l1 {
+			regulator-name = "pm6150l_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1616000>;
+			regulator-max-microvolt = <1984000>;
+			qcom,init-voltage = <1616000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L2C:
+		pm6150l_l2: regulator-pm6150l-l2 {
+			regulator-name = "pm6150l_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1168000>;
+			regulator-max-microvolt = <1304000>;
+			qcom,init-voltage = <1168000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L3C:
+		pm6150l_l3: regulator-pm6150l-l3 {
+			regulator-name = "pm6150l_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1144000>;
+			regulator-max-microvolt = <1304000>;
+			qcom,init-voltage = <1144000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc4";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L4C:
+		pm6150l_l4: regulator-pm6150l-l4 {
+			regulator-name = "pm6150l_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <1648000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc5";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L5C:
+		pm6150l_l5: regulator-pm6150l-l5 {
+			regulator-name = "pm6150l_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <1648000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc6";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L6C:
+		pm6150l_l6: regulator-pm6150l-l6 {
+			regulator-name = "pm6150l_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <1648000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc7";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L7C:
+		pm6150l_l7: regulator-pm6150l-l7 {
+			regulator-name = "pm6150l_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3312000>;
+			qcom,init-voltage = <3300000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc8 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc8";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L8C:
+		pm6150l_l8: regulator-pm6150l-l8 {
+			regulator-name = "pm6150l_l8";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1904000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc9 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc9";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L9C:
+		pm6150l_l9: regulator-pm6150l-l9 {
+			regulator-name = "pm6150l_l9";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2952000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <2952000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc10 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc10";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L10C:
+		pm6150l_l10: regulator-pm6150l-l10 {
+			regulator-name = "pm6150l_l10";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3400000>;
+			qcom,init-voltage = <3000000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc11 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "ldoc11";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L11C:
+		pm6150l_l11: regulator-pm6150l-l11 {
+			regulator-name = "pm6150l_l11";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3400000>;
+			qcom,init-voltage = <3000000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-bobc1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		mboxes = <&apps_rsc 0>;
+		qcom,resource-name = "bobc1";
+		qcom,regulator-type = "pmic5-bob";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_PASS
+			RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1000000 2000000>;
+		qcom,send-defaults;
+		BOB:
+		pm6150l_bob: regulator-pm6150l-bob {
+			regulator-name = "pm6150l_bob";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			qcom,init-voltage = <3008000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_PASS>;
+		};
+
+		BOB_AO:
+		pm6150l_bob_ao: regulator-pm6150l-bob_ao {
+			regulator-name = "pm6150l_bob_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			qcom,init-voltage = <3008000>;
+			qcom,init-mode =
+				<RPMH_REGULATOR_MODE_AUTO>;
+		};
+	};
+
+	refgen: refgen-regulator@88e7000 {
+		compatible = "qcom,refgen-regulator";
+		reg = <0x88e7000 0x60>;
+		regulator-name = "refgen";
+		regulator-enable-ramp-delay = <5>;
+		proxy-supply = <&refgen>;
+		qcom,proxy-consumer-enable;
+	};
+};

arch/arm64/boot/dts/19721/atoll-rumi-overlay.dts

@@ -0,0 +1,25 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "atoll-rumi.dtsi"
+
+/ {
+	model = "RUMI";
+	compatible = "qcom,atoll-rumi", "qcom,atoll", "qcom,rumi";
+	qcom,msm-id = <407 0x0>;
+	qcom,board-id = <15 0>;
+};

arch/arm64/boot/dts/19721/atoll-rumi.dts

@@ -0,0 +1,22 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll.dtsi"
+#include "atoll-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL PM6150 RUMI";
+	compatible = "qcom,atoll-rumi", "qcom,atoll", "qcom,rumi";
+	qcom,board-id = <15 0>;
+};

arch/arm64/boot/dts/19721/atoll-rumi.dtsi

@@ -0,0 +1,166 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+
+	timer {
+		clock-frequency = <1000000>;
+	};
+
+	timer@17c20000 {
+		clock-frequency = <1000000>;
+	};
+
+	usb_emu_phy: usb_emu_phy@a720000 {
+		compatible = "qcom,usb-emu-phy";
+		reg = <0x0a720000 0x9500>,
+			<0x0a6f8800 0x100>;
+		reg-names = "base", "qcratch_base";
+
+		qcom,emu-init-seq = <0xfff0 0x4
+					0xfff3 0x4
+					0x40 0x4
+					0xfff3 0x4
+					0xfff0 0x4
+					0x100000 0x20
+					0x0 0x20
+					0x1a0 0x20
+					0x100000 0x3c
+					0x0 0x3c
+					0x10060 0x3c
+					0x0 0x4>;
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+	wdog: qcom,wdt@17c10000{
+		status = "disabled";
+	};
+
+	disp_rsc: mailbox@af20000 {
+		status = "disabled";
+	};
+};
+
+&sdhc_1 {
+	vdd-supply = <&pm6150_l19>;
+	qcom,vdd-voltage-level = <2950000 2950000>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&pm6150_l12>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+					&sdc1_rclk_on>;
+	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+					&sdc1_rclk_off>;
+
+	qcom,clk-rates = <400000 20000000 25000000 50000000>;
+	qcom,bus-speed-mode = "DDR_1p8v";
+
+	/delete-property/qcom,devfreq,freq-table;
+
+	status = "ok";
+};
+
+&sdhc_2 {
+	vdd-supply = <&pm6150l_l9>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&pm6150l_l6>;
+	qcom,vdd-io-voltage-level = <1800000 2950000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on>;
+	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
+
+	qcom,clk-rates = <400000 20000000 25000000 50000000>;
+	qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50";
+
+	/delete-property/qcom,devfreq,freq-table;
+
+	status = "ok";
+};
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qrbtc-sdm845";
+
+	vdda-phy-supply = <&pm6150_l4>; /* 0.88v */
+	vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */
+	vdda-phy-max-microamp = <62900>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	limit-tx-hs-gear = <1>;
+	limit-rx-hs-gear = <1>;
+	scsi-cmd-timeout = <300000>;
+
+	vdd-hba-supply = <&ufs_phy_gdsc>;
+	vdd-hba-fixed-regulator;
+	vcc-supply = <&pm6150_l19>;
+	vccq2-supply = <&pm6150_l12>;
+	vcc-max-microamp = <600000>;
+	vccq2-max-microamp = <600000>;
+
+	qcom,vddp-ref-clk-supply = <&pm6150l_l3>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+	qcom,vddp-ref-clk-min-uV = <1200000>;
+	qcom,vddp-ref-clk-max-uV = <1200000>;
+
+
+	qcom,disable-lpm;
+	rpm-level = <0>;
+	spm-level = <0>;
+	status = "ok";
+};
+
+&thermal_zones {
+	/delete-node/ aoss-0-lowf;
+};
+
+&usb0 {
+	dwc3@a600000 {
+		usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;
+		maximum-speed = "high-speed";
+	};
+	qcom,usbbam@a704000 {
+		status = "disabled";
+	};
+};
+
+&qusb_phy0 {
+	status = "disabled";
+};
+
+&usb_qmp_dp_phy {
+	status = "disabled";
+};
+
+&pm6150_pdphy {
+	status = "disabled";
+};
+/*
+&qupv3_se9_i2c {
+	status = "disabled";
+};
+*/

arch/arm64/boot/dts/19721/atoll-sde-display.dtsi

@@ -0,0 +1,494 @@
+/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "dsi-panel-rm69299-visionox-amoled-fhd-plus-video.dtsi"
+#include "dsi-panel-rm69299-visionox-amoled-fhd-plus-cmd.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include "dsi-panel-sim-cmd.dtsi"
+#include "dsi-panel-sim-dsc375-cmd.dtsi"
+#include "dsi-panel-nt36672c-fhd-plus-video.dtsi"
+//#ifdef VENDOR_EDIT
+//Jiasong.Zhong@PSW.MM.Display.LCD.Stable, 2020/02/24, Add for 19365 samsung cmd panel
+#include "dsi-panel-oppo19365samsung-ams644vk01-1080-2400-dsi-cmd.dtsi"
+#include "dsi-panel-oppo19365samsung-ams643xf01-1080-2400-dsi-cmd.dtsi"
+#include "dsi-panel-oppo19567samsung-amb655uv01-1080-2400-90fps.dtsi"
+#include "dsi-panel-oppo206B1samsung-ams643xy01-1080-2400-dsi-vid.dtsi"
+/* Shusheng.Bei@MULTIMEDIA.DISPLAY.LCD, 2020/10/27, add for bring up 19721 NT36672C JDI panel */
+#include "dsi-panel-nt36672c-jdi-fhd-plus-video.dtsi"
+#include "dsi-panel-nt36672c-boe-fhd-plus-video.dtsi"
+//#endif /* VENDOR_EDIT */
+#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
+
+&soc {
+	dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <1904000>;
+			qcom,supply-enable-load = <32000>;
+			qcom,supply-disable-load = <80>;
+		};
+
+		qcom,panel-supply-entry@1 {
+			reg = <1>;
+			qcom,supply-name = "lab";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <100000>;
+			qcom,supply-disable-load = <100>;
+		};
+
+		qcom,panel-supply-entry@2 {
+			reg = <2>;
+			qcom,supply-name = "ibb";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <100000>;
+			qcom,supply-disable-load = <100>;
+			qcom,supply-post-on-sleep = <10>;
+		};
+	};
+
+	dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <1904000>;
+			qcom,supply-enable-load = <32000>;
+			qcom,supply-disable-load = <80>;
+		};
+	};
+
+	dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <1904000>;
+			qcom,supply-enable-load = <32000>;
+			qcom,supply-disable-load = <80>;
+		};
+
+		qcom,panel-supply-entry@1 {
+			reg = <1>;
+			qcom,supply-name = "vdda-3p3";
+			qcom,supply-min-voltage = <3000000>;
+			qcom,supply-max-voltage = <3000000>;
+			qcom,supply-enable-load = <13200>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <12>;
+			qcom,supply-post-off-sleep = <12>;
+		};
+	};
+
+	dsi_rm69299_visionox_amoled_vid_display: qcom,dsi-display@0 {
+		label = "dsi_rm69299_visionox_amoled_vid_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+				"src_byte_clk0", "src_pixel_clk0",
+				"shadow_byte_clk0", "shadow_pixel_clk0";
+
+		qcom,dsi-panel = <&dsi_rm69299_visionox_amoled_video>;
+	};
+
+	dsi_rm69299_visionox_amoled_cmd_display: qcom,dsi-display@1 {
+		label = "dsi_rm69299_visionox_amoled_cmd_display";
+		qcom,display-type = "primary";
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+		qcom,dsi-panel = <&dsi_rm69299_visionox_amoled_cmd>;
+	};
+
+	dsi_sim_vid_display: qcom,dsi-display@2 {
+		label = "dsi_sim_vid_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+
+		qcom,dsi-panel = <&dsi_sim_vid>;
+	};
+
+	dsi_sim_cmd_display: qcom,dsi-display@3 {
+		label = "dsi_sim_cmd_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+
+		qcom,dsi-panel = <&dsi_sim_cmd>;
+	};
+
+	dsi_sim_dsc_375_cmd_display: qcom,dsi-display@4 {
+		label = "dsi_sim_dsc_375_cmd_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+
+		qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>;
+	};
+
+	dsi_nt36672c_video_display: qcom,dsi-display@5 {
+		label = "dsi_nt36672c_video_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+					"cphy_byte_clk0", "cphy_pixel_clk0",
+					"shadow_cphybyte_clk0",
+					"shadow_cphypixel_clk0";
+		qcom,dsi-panel = <&dsi_nt36672c_video>;
+	};
+
+//#ifdef VENDOR_EDIT
+//Jiasong.Zhong@PSW.MM.Display.LCD.Stable, 2020/02/24, Add for samsung cmd panel
+	dsi_oppo19365samsung_ams644vk01_1080_2400_cmd_display: qcom,dsi-display@6 {
+		label = "dsi_oppo19365samsung_ams644vk01_1080_2400_cmd_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+
+		qcom,dsi-panel = <&dsi_oppo19365samsung_ams644vk01_1080_2400_cmd>;
+	};
+
+	dsi_oppo19567samsung_amb655uv01_1080_2400_cmd_display: qcom,dsi-display@7 {
+	    label = "dsi_oppo19567samsung_amb655uv01_1080_2400_cmd_display";
+	    qcom,display-type = "primary";
+
+	    qcom,dsi-ctrl-num = <0>;
+	    qcom,dsi-phy-num = <0>;
+	    qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+
+	    qcom,dsi-panel = <&dsi_oppo19567samsung_amb655uv01_1080_2400_cmd>;
+	};
+
+	dsi_oppo19365samsung_ams643xf01_1080_2400_cmd_display: qcom,dsi-display@8 {
+		label = "dsi_oppo19365samsung_ams643xf01_1080_2400_cmd_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+
+		qcom,dsi-panel = <&dsi_oppo19365samsung_ams643xf01_1080_2400_cmd>;
+	};
+
+	dsi_oppo206B1samsung_ams643xy01_1080_2400_vid_display: qcom,dsi-display@9 {
+		label = "dsi_oppo206B1samsung_ams643xy01_1080_2400_vid_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+			"src_byte_clk0", "src_pixel_clk0",
+			"shadow_byte_clk0", "shadow_pixel_clk0";
+
+		qcom,dsi-panel = <&dsi_oppo206B1samsung_ams643xy01_1080_2400_vid>;
+	};
+//#endif /* VENDOR_EDIT */
+
+//#ifdef OPLUS_BUG_STABILITY
+/* Shusheng.Bei@MULTIMEDIA.DISPLAY.LCD, 2020/10/27, add for bring up 19721 NT36672C JDI panel */
+	dsi_nt36672c_jdi_video_display: qcom,dsi-display@10 {
+		label = "dsi_nt36672c_jdi_video_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+					"cphy_byte_clk0", "cphy_pixel_clk0";
+		qcom,dsi-panel = <&dsi_nt36672c_jdi_video>;
+	};
+	dsi_nt36672c_boe_video_display: qcom,dsi-display@11 {
+		label = "dsi_nt36672c_boe_video_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+
+		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+					"cphy_byte_clk0", "cphy_pixel_clk0";
+		qcom,dsi-panel = <&dsi_nt36672c_boe_video>;
+	};
+//#endif /* OPLUS_BUG_STABILITY */
+
+	sde_dsi: qcom,dsi-display {
+		compatible = "qcom,dsi-display";
+
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+
+		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+			 <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+			 <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+			<&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>,
+			<&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>,
+			 <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,
+			 <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>,
+			<&mdss_dsi0_pll SHADOW_CPHY_BYTECLK_SRC_0_CLK>,
+			<&mdss_dsi0_pll SHADOW_CPHY_PCLK_SRC_0_CLK>;
+		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+				"src_byte_clk0", "src_pixel_clk0",
+				"cphy_byte_clk0", "cphy_pixel_clk0",
+				"shadow_byte_clk0", "shadow_pixel_clk0",
+				"shadow_cphybyte_clk0", "shadow_cphypixel_clk0";
+
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&sde_te_active &disp_pins_default>;
+		pinctrl-1 = <&sde_te_suspend>;
+//#ifdef VENDOR_EDIT
+//Jiasong.Zhong@PSW.MM.Display.LCD.Stable, 2020/02/24, Add for 19365 samsung cmd panel
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+		qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+		qcom,panel-te-source = <0>;
+
+		vddio-supply = <&L13A>;
+
+		vdda-3p3-supply = <&L18A>;
+//#ifdef OPLUS_BUG_STABILITY
+/* Shusheng.Bei@MULTIMEDIA.DISPLAY.LCD, 2020/11/06, add for bring up 19721 NT36672C JDI panel */
+		lab-supply = <&lcdb_ldo_vreg>;
+		ibb-supply = <&lcdb_ncp_vreg>;
+//#endif /* OPLUS_BUG_STABILITY */
+//#endif /* VENDOR_EDIT */
+		qcom,dsi-display-list =
+			<&dsi_rm69299_visionox_amoled_vid_display
+			&dsi_rm69299_visionox_amoled_cmd_display
+			&dsi_sim_vid_display
+			&dsi_sim_cmd_display
+			&dsi_sim_dsc_375_cmd_display
+			&dsi_nt36672c_video_display
+			&dsi_oppo19365samsung_ams644vk01_1080_2400_cmd_display
+			&dsi_oppo19365samsung_ams643xf01_1080_2400_cmd_display
+			&dsi_oppo19567samsung_amb655uv01_1080_2400_cmd_display
+            &dsi_oppo206B1samsung_ams643xy01_1080_2400_vid_display
+            /*#ifdef OPLUS_BUG_STABILITY*/
+            /* Shusheng.Bei@MULTIMEDIA.DISPLAY.LCD, 2020/10/27, add for bring up 19721 NT36672C JDI panel */
+			&dsi_nt36672c_jdi_video_display
+			&dsi_nt36672c_boe_video_display>;
+            /*#endif OPLUS_BUG_STABILITY*/
+	};
+
+	sde_wb: qcom,wb-display@0 {
+		compatible = "qcom,wb-display";
+		cell-index = <0>;
+		label = "wb_display";
+	};
+	ext_disp: qcom,msm-ext-disp {
+		compatible = "qcom,msm-ext-disp";
+
+		ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
+			compatible = "qcom,msm-ext-disp-audio-codec-rx";
+		};
+	};
+
+};
+
+&sde_dp {
+	qcom,dp-usbpd-detection = <&pm6150_pdphy>;
+//#ifdef ODM_LQ_EDIT
+/*Hongbin.Chen@ODM_LQ.BSP.CHG 2019-11-25 close usb 3.0 */
+	status = "disabled";
+//#endif
+	qcom,ext-disp = <&ext_disp>;
+
+	qcom,usbplug-cc-gpio = <&tlmm 104 0>;
+
+	pinctrl-name = "mdss_dp_active", "mdss_dp_sleep";
+	pinctrl-0 = <&sde_dp_usbplug_cc_active>;
+	pinctrl-1 = <&sde_dp_usbplug_cc_suspend>;
+};
+
+&mdss_mdp {
+//#ifndef ODM_LQ_EDIT
+/*Hongbin.Chen@ODM_LQ.BSP.CHG 2019-11-25 close usb 3.0 */
+//	connectors = <&sde_wb &sde_dsi &sde_dp &sde_rscc>;
+//#else
+	connectors = <&sde_wb &sde_dsi &sde_rscc>;
+//#endif
+};
+
+&dsi_rm69299_visionox_amoled_video {
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,dsi-supported-dfps-list = <60 55 48>;
+	qcom,mdss-dsi-pan-enable-dynamic-fps;
+	qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+	qcom,dsi-dyn-clk-enable;
+	qcom,dsi-dyn-clk-list =
+		<950938560 935089584 939051832 943014072 946976320>;
+	qcom,mdss-dsi-t-clk-post = <0x0E>;
+	qcom,mdss-dsi-t-clk-pre = <0x31>;
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08
+				08 05 02 04 00];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_rm69299_visionox_amoled_cmd {
+	qcom,ulps-enabled;
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+	qcom,dsi-dyn-clk-enable;
+	qcom,dsi-dyn-clk-list =
+		<1034259840 1017022176 1021331592 1025641008 1029950424>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,mdss-dsi-t-clk-post = <0x0E>;
+	qcom,mdss-dsi-t-clk-pre = <0x31>;
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08
+				08 05 02 04 00];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_sim_vid {
+	qcom,mdss-dsi-t-clk-post = <0x0d>;
+	qcom,mdss-dsi-t-clk-pre = <0x2d>;
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
+				07 05 02 04 00];
+			qcom,display-topology = <1 0 1>,
+						<2 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_sim_cmd {
+	qcom,mdss-dsi-t-clk-post = <0x0c>;
+	qcom,mdss-dsi-t-clk-pre = <0x29>;
+	qcom,ulps-enabled;
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
+				07 04 02 04 00];
+			qcom,display-topology = <1 1 1>,
+						<2 2 1>;
+			qcom,default-topology-index = <1>;
+			qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+			qcom,partial-update-enabled = "single_roi";
+		};
+
+		timing@1{
+			qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
+				07 04 02 04 00];
+			qcom,display-topology = <1 1 1>,
+						<2 2 1>;
+			qcom,default-topology-index = <1>;
+			qcom,panel-roi-alignment = <540 40 540 40 540 40>;
+			qcom,partial-update-enabled = "single_roi";
+		};
+
+		timing@2{
+			qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
+				07 04 02 04 00];
+			qcom,display-topology = <1 1 1>,
+						<2 2 1>;
+			qcom,default-topology-index = <1>;
+			qcom,panel-roi-alignment = <360 40 360 40 360 40>;
+			qcom,partial-update-enabled = "single_roi";
+		};
+	};
+};
+
+&dsi_sim_dsc_375_cmd {
+	qcom,mdss-dsi-t-clk-post = <0x0d>;
+	qcom,mdss-dsi-t-clk-pre = <0x2d>;
+	qcom,ulps-enabled;
+	qcom,mdss-dsi-display-timings {
+		timing@0 { /* 1080p */
+			qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
+				07 04 02 04 00];
+			qcom,display-topology = <1 1 1>;
+			qcom,default-topology-index = <0>;
+		};
+		timing@1 { /* qhd */
+			qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
+				05 03 02 04 00];
+			qcom,display-topology = <1 1 1>,
+						<2 2 1>, /* dsc merge */
+						<2 1 1>; /* 3d mux */
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_nt36672c_video {
+	qcom,mdss-dsi-t-clk-post = <0x00>;
+	qcom,mdss-dsi-t-clk-pre = <0x00>;
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,dsi-supported-dfps-list = <60 90 50>;
+	qcom,mdss-dsi-pan-enable-dynamic-fps;
+	qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+	qcom,dsi-dyn-clk-enable;
+	qcom,dsi-dyn-clk-skip-timing-update;
+	qcom,dsi-dyn-clk-list =
+		<1052068500 1047684883 1043301259 1038917642 1034534025>;
+	qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp";
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09
+				09 09 06 02 04];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};

arch/arm64/boot/dts/19721/atoll-sde-pll.dtsi

@@ -0,0 +1,89 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+	mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94a00 {
+		compatible = "qcom,mdss_dsi_pll_10nm";
+		label = "MDSS DSI 0 PLL";
+		cell-index = <0>;
+		#clock-cells = <1>;
+		reg = <0xae94a00 0x1e0>,
+		      <0xae94400 0x800>,
+		      <0xaf03000 0x8>,
+		      <0xae94200 0x100>;
+		reg-names = "pll_base", "phy_base", "gdsc_base",
+			"dynamic_pll_base";
+		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
+		clock-names = "iface_clk";
+		clock-rate = <0>;
+		memory-region = <&dfps_data_memory>;
+		gdsc-supply = <&mdss_core_gdsc>;
+		qcom,dsi-pll-ssc-en;
+		//#ifdef VENDOR_EDIT
+		//Jiasong.Zhong@PSW.MM.Display.LCD.Stable, 2020/04/29, Add for ssc mode
+		//qcom,dsi-pll-ssc-mode = "down-spread";
+		qcom,dsi-pll-ssc-mode = "center-spread";
+		//#endif /* VENDOR_EDIT */
+		qcom,platform-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			qcom,platform-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "gdsc";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+
+	mdss_dp_pll: qcom,mdss_dp_pll@ae90000 {
+		compatible = "qcom,mdss_dp_pll_10nm";
+		label = "MDSS DP PLL";
+		cell-index = <0>;
+		#clock-cells = <1>;
+
+		reg = <0x088ea000 0x200>,
+		      <0x088eaa00 0x200>,
+		      <0x088ea200 0x200>,
+		      <0x088ea600 0x200>,
+		      <0xaf03000 0x8>;
+		reg-names = "pll_base", "phy_base", "ln_tx0_base",
+			"ln_tx1_base", "gdsc_base";
+
+		gdsc-supply = <&mdss_core_gdsc>;
+
+		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+			 <&clock_rpmh RPMH_CXO_CLK>,
+			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
+			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+		clock-names = "iface_clk", "ref_clk_src", "ref_clk",
+			"cfg_ahb_clk", "pipe_clk";
+		clock-rate = <0>;
+
+		qcom,platform-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,platform-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "gdsc";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/atoll-sde.dtsi

@@ -0,0 +1,621 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
+
+&soc {
+	mdss_mdp: qcom,mdss_mdp@ae00000 {
+		compatible = "qcom,sde-kms";
+		reg = <0xae00000 0x84208>,
+		      <0xaeb0000 0x2008>,
+		      <0xaeac000 0x214>,
+		      <0xae8f000 0x02c>;
+		reg-names = "mdp_phys",
+			"vbif_phys",
+			"regdma_phys",
+			"sid_phys";
+
+		clocks =
+			<&clock_gcc GCC_DISP_AHB_CLK>,
+			<&clock_gcc GCC_DISP_HF_AXI_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
+		clock-names = "gcc_iface", "gcc_bus", "iface_clk",
+				"core_clk", "vsync_clk",
+				"lut_clk", "rot_clk";
+		clock-rate = <0 0 0 300000000 19200000 200000000
+						200000000>;
+		clock-max-rate = <0 0 0 460000000 19200000 460000000
+						460000000>;
+
+		/* interrupt config */
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		iommus = <&apps_smmu 0x800 0x2>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		#power-domain-cells = <0>;
+
+		/* hw blocks */
+		qcom,sde-off = <0x1000>;
+		qcom,sde-len = <0x494>;
+
+		qcom,sde-ctl-off = <0x2000 0x2200 0x2400>;
+		qcom,sde-ctl-size = <0x1dc>;
+		qcom,sde-ctl-display-pref = "primary", "none", "none";
+
+		qcom,sde-mixer-off = <0x45000 0x46000>;
+		qcom,sde-mixer-size = <0x320>;
+		qcom,sde-mixer-display-pref = "primary", "none";
+
+		qcom,sde-mixer-cwb-pref = "none", "cwb";
+
+		qcom,sde-dspp-top-off = <0x1300>;
+		qcom,sde-dspp-top-size = <0x80>;
+		qcom,sde-dspp-off = <0x55000>;
+		qcom,sde-dspp-size = <0x1800>;
+
+		qcom,sde-wb-off = <0x66000>;
+		qcom,sde-wb-size = <0x2c8>;
+		qcom,sde-wb-xin-id = <6>;
+		qcom,sde-wb-id = <2>;
+		qcom,sde-wb-clk-ctrl = <0x3b8 24>;
+
+		qcom,sde-intf-off = <0x6b000 0x6b800>;
+		qcom,sde-intf-size = <0x2b8>;
+		qcom,sde-intf-type = "dp", "dsi";
+
+		qcom,sde-pp-off = <0x71000 0x71800>;
+		qcom,sde-pp-slave = <0x0 0x0>;
+		qcom,sde-pp-size = <0xd4>;
+		qcom,sde-pp-merge-3d-id = <0x0 0x0>;
+
+		qcom,sde-merge-3d-off = <0x84000>;
+		qcom,sde-merge-3d-size = <0x100>;
+
+		qcom,sde-te2-off = <0x2000 0x2000>;
+
+		qcom,sde-cdm-off = <0x7a200>;
+		qcom,sde-cdm-size = <0x224>;
+
+		qcom,sde-dither-off = <0x30e0 0x30e0>;
+		qcom,sde-dither-version = <0x00010000>;
+		qcom,sde-dither-size = <0x20>;
+
+		qcom,sde-sspp-type = "vig", "dma", "dma", "dma";
+
+		qcom,sde-sspp-off = <0x5000 0x25000 0x27000 0x29000>;
+		qcom,sde-sspp-src-size = <0x1f8>;
+
+		qcom,sde-sspp-xin-id = <0 1 5 9 >;
+		qcom,sde-sspp-excl-rect = <1 1 1 1>;
+		qcom,sde-sspp-smart-dma-priority = <4 1 2 3>;
+		qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+		qcom,sde-mixer-pair-mask = <2 1>;
+
+		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+						0xb0 0xc8 0xe0 0xf8 0x110>;
+
+		qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000
+						 2600000 2600000>;
+
+		qcom,sde-max-per-pipe-bw-high-kbps = <2600000 2600000
+						 2600000 2600000>;
+
+		/* offsets are relative to "mdp_phys + qcom,sde-off */
+		qcom,sde-sspp-clk-ctrl =
+				<0x2ac 0>, <0x2b4 8>,
+				 <0x2ac 8>, <0x2c4 8>;
+		qcom,sde-sspp-csc-off = <0x1a00>;
+		qcom,sde-csc-type = "csc-10bit";
+		qcom,sde-qseed-type = "qseedv3lite";
+		qcom,sde-sspp-qseed-off = <0xa00>;
+		qcom,sde-mixer-linewidth = <2560>;
+		qcom,sde-sspp-linewidth = <2160>;
+		qcom,sde-vig-sspp-linewidth = <4096>;
+		qcom,sde-wb-linewidth = <1920>;
+		qcom,sde-mixer-blendstages = <0x7>;
+		qcom,sde-highest-bank-bit = <0x1>;
+		qcom,sde-ubwc-version = <0x200>;
+		qcom,sde-ubwc-bw-calc-version = <0x1>;
+		qcom,sde-ubwc-static = <0x1E>;
+		qcom,sde-panic-per-pipe;
+		qcom,sde-smart-panel-align-mode = <0xc>;
+		qcom,sde-has-cdp;
+		qcom,sde-has-src-split;
+		qcom,sde-pipe-order-version = <0x1>;
+		qcom,sde-has-dim-layer;
+		qcom,sde-has-idle-pc;
+
+		qcom,sde-max-bw-low-kbps = <3900000>;
+		qcom,sde-max-bw-high-kbps = <5500000>;
+		qcom,sde-min-core-ib-kbps = <2400000>;
+		qcom,sde-min-llcc-ib-kbps = <800000>;
+		qcom,sde-min-dram-ib-kbps = <800000>;
+		qcom,sde-dram-channels = <2>;
+		qcom,sde-num-nrt-paths = <0>;
+
+		qcom,sde-vbif-off = <0>;
+		qcom,sde-vbif-size = <0x1040>;
+		qcom,sde-vbif-id = <0>;
+		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+		qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
+		qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;
+
+		/* macrotile & macrotile-qseed has the same configs */
+		qcom,sde-danger-lut = <0x000000ff 0x0000ffff
+			0x00000000 0x00000000 0x0000ffff>;
+
+		qcom,sde-safe-lut-linear = <0 0xfff0>;
+		qcom,sde-safe-lut-macrotile = <0 0xff00>;
+		/* same as safe-lut-macrotile */
+		qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
+		qcom,sde-safe-lut-nrt = <0 0xffff>;
+		qcom,sde-safe-lut-cwb = <0 0x3ff>;
+
+		qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
+		qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
+		qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
+		qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
+		qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>;
+
+		qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+		qcom,sde-qos-cpu-mask = <0x3>;
+		qcom,sde-qos-cpu-dma-latency = <300>;
+
+		/* offsets are relative to "mdp_phys + qcom,sde-off */
+
+		qcom,sde-reg-dma-off = <0>;
+		qcom,sde-reg-dma-version = <0x00010002>;
+		qcom,sde-reg-dma-trigger-off = <0x119c>;
+		qcom,sde-reg-dma-xin-id = <7>;
+		qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
+
+		qcom,sde-secure-sid-mask = <0x801>;
+
+		qcom,sde-sspp-vig-blocks {
+			qcom,sde-vig-csc-off = <0x1a00>;
+			qcom,sde-vig-qseed-off = <0xa00>;
+			qcom,sde-vig-qseed-size = <0xa0>;
+			qcom,sde-vig-gamut = <0x1d00 0x00060000>;
+			qcom,sde-vig-igc = <0x1d00 0x00060000>;
+			qcom,sde-vig-inverse-pma;
+		};
+
+		qcom,sde-sspp-dma-blocks {
+			dgm@0 {
+				qcom,sde-dma-igc = <0x400 0x00050000>;
+				qcom,sde-dma-gc = <0x600 0x00050000>;
+				qcom,sde-dma-inverse-pma;
+				qcom,sde-dma-csc-off = <0x200>;
+			};
+
+			dgm@1 {
+				qcom,sde-dma-igc = <0x1400 0x00050000>;
+				qcom,sde-dma-gc = <0x600 0x00050000>;
+				qcom,sde-dma-inverse-pma;
+				qcom,sde-dma-csc-off = <0x1200>;
+			};
+		};
+
+		qcom,sde-dspp-blocks {
+			qcom,sde-dspp-igc = <0x0 0x00030001>;
+			qcom,sde-dspp-hsic = <0x800 0x00010007>;
+			qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+			qcom,sde-dspp-hist = <0x800 0x00010007>;
+			qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+			qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+			qcom,sde-dspp-gamut = <0x1000 0x00040002>;
+			qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+			qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+			qcom,sde-dspp-dither = <0x82c 0x00010007>;
+		};
+
+		smmu_sde_sec: qcom,smmu_sde_sec_cb {
+			compatible = "qcom,smmu_sde_sec";
+			iommus = <&apps_smmu 0x801 0x0>;
+		};
+
+		/* data and reg bus scale settings */
+		qcom,sde-data-bus {
+			qcom,msm-bus,name = "mdss_sde";
+			qcom,msm-bus,num-cases = <3>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,vectors-KBps =
+				<22 512 0 0>,
+				<22 512 0 6400000>,
+				<22 512 0 6400000>;
+		};
+
+		qcom,sde-reg-bus {
+			qcom,msm-bus,name = "mdss_reg";
+			qcom,msm-bus,num-cases = <4>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,vectors-KBps =
+				<1 590 0 0>,
+				<1 590 0 76800>,
+				<1 590 0 150000>,
+				<1 590 0 300000>;
+		};
+
+		qcom,sde-limits {
+			qcom,sde-linewidth-limits{
+				qcom,sde-limit-name = "sspp_linewidth_usecases";
+				qcom,sde-limit-cases = "vig", "dma", "scale";
+				qcom,sde-limit-ids= <0x1 0x2 0x4>;
+				qcom,sde-limit-values = <0x1 4096>,
+							<0x5 2560>,
+							<0x2 2160>;
+			};
+			qcom,sde-bw-limits{
+				qcom,sde-limit-name = "sde_bwlimit_usecases";
+				qcom,sde-limit-cases = "per_vig_pipe",
+							"per_dma_pipe",
+							"total_max_bw",
+							"camera_concurrency",
+							"cwb_concurrency";
+				qcom,sde-limit-ids = <0x1 0x2 0x4 0x8 0x10>;
+				qcom,sde-limit-values = <0x1 2600000>,
+							<0x11 2600000>,
+							<0x9 2600000>,
+							<0x19 2600000>,
+							<0x2 2600000>,
+							<0x12 2600000>,
+							<0xa 2600000>,
+							<0x1a 2600000>,
+							<0x4 5800000>,
+							<0x14 5500000>,
+							<0xc 4400000>,
+							<0x1c 3900000>;
+			};
+		};
+	};
+
+	sde_rscc: qcom,sde_rscc@af20000 {
+		cell-index = <0>;
+		compatible = "qcom,sde-rsc";
+		reg = <0xaf20000 0x3c50>,
+			<0xaf30000 0x3fd4>;
+		reg-names = "drv", "wrapper";
+		qcom,sde-rsc-version = <3>;
+
+		qcom,sde-dram-channels = <2>;
+
+		mboxes = <&disp_rsc 0>;
+		mbox-names = "disp_rsc";
+
+		vdd-supply = <&mdss_core_gdsc>;
+		clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+		clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
+
+		/* data and reg bus scale settings */
+		qcom,sde-data-bus {
+			qcom,msm-bus,name = "disp_rsc_mnoc";
+			qcom,msm-bus,active-only;
+			qcom,msm-bus,num-cases = <3>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,vectors-KBps =
+			    <20003 20515 0 0>,
+			    <20003 20515 0 6400000>,
+			    <20003 20515 0 6400000>;
+		};
+
+		qcom,sde-llcc-bus {
+			qcom,msm-bus,name = "disp_rsc_llcc";
+			qcom,msm-bus,active-only;
+			qcom,msm-bus,num-cases = <3>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,vectors-KBps =
+			    <20001 20513 0 0>,
+			    <20001 20513 0 6400000>,
+			    <20001 20513 0 6400000>;
+		};
+
+		qcom,sde-ebi-bus {
+			qcom,msm-bus,name = "disp_rsc_ebi";
+			qcom,msm-bus,active-only;
+			qcom,msm-bus,num-cases = <3>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,vectors-KBps =
+			    <20000 20512 0 0>,
+			    <20000 20512 0 6400000>,
+			    <20000 20512 0 6400000>;
+		};
+	};
+
+	mdss_rotator: qcom,mdss_rotator@aea8800 {
+		compatible = "qcom,sde_rotator";
+		reg = <0xae00000 0xac000>,
+		      <0xaeb8000 0x3000>;
+		reg-names = "mdp_phys",
+			"rot_vbif_phys";
+
+		#list-cells = <1>;
+
+		qcom,mdss-rot-mode = <1>;
+		qcom,mdss-highest-bank-bit = <0x1>;
+
+		/* Bus Scale Settings */
+		qcom,msm-bus,name = "mdss_rotator";
+		qcom,msm-bus,num-cases = <3>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<25 512 0 0>,
+			<25 512 0 6400000>,
+			<25 512 0 6400000>;
+
+		rot-vdd-supply = <&mdss_core_gdsc>;
+		qcom,supply-names = "rot-vdd";
+
+		clocks =
+			<&clock_gcc GCC_DISP_AHB_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
+		clock-names = "gcc_iface", "iface_clk", "rot_clk";
+
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <2 0>;
+
+		power-domains = <&mdss_mdp>;
+
+		/* Offline rotator QoS setting */
+		qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
+		qcom,mdss-rot-vbif-memtype = <3 3>;
+		qcom,mdss-rot-cdp-setting = <1 1>;
+		qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
+		qcom,mdss-rot-danger-lut = <0x0 0x0>;
+		qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
+
+		qcom,mdss-default-ot-rd-limit = <32>;
+		qcom,mdss-default-ot-wr-limit = <32>;
+
+		qcom,mdss-sbuf-headroom = <20>;
+
+		/* reg bus scale settings */
+		rot_reg: qcom,rot-reg-bus {
+			qcom,msm-bus,name = "mdss_rot_reg";
+			qcom,msm-bus,num-cases = <2>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,vectors-KBps =
+				<1 590 0 0>,
+				<1 590 0 76800>;
+		};
+
+		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
+			compatible = "qcom,smmu_sde_rot_unsec";
+			iommus = <&apps_smmu 0xC1C 0x0>;
+		};
+
+		smmu_rot_sec: qcom,smmu_rot_sec_cb {
+			compatible = "qcom,smmu_sde_rot_sec";
+			iommus = <&apps_smmu 0xC1D 0x0>;
+		};
+	};
+
+	mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
+		compatible = "qcom,dsi-ctrl-hw-v2.4";
+		label = "dsi-ctrl-0";
+		cell-index = <0>;
+		reg =	<0xae94000 0x400>,
+			<0xaf08000 0x4>;
+		reg-names = "dsi_ctrl", "disp_cc_base";
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <4 0>;
+		vdda-1p2-supply = <&L3C>;
+		refgen-supply = <&refgen>;
+		clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+			<&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+			<&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
+		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+				"pixel_clk", "pixel_clk_rcg",
+				"esc_clk";
+
+// #ifdef OPLUS_BUG_STABILITY
+/* Shusheng.Bei@MULTIMEDIA.DISPLAY.LCD, 2020/11/10, modified for bring up NT36672C JDI panel */
+                oplus,scramble-switch = <1>;
+// #endif /*OPLUS_BUG_STABILITY*/
+
+		qcom,ctrl-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,ctrl-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-1p2";
+				qcom,supply-min-voltage = <1200000>;
+				qcom,supply-max-voltage = <1200000>;
+				qcom,supply-enable-load = <21800>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,core-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,core-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "refgen";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+
+	mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
+		compatible = "qcom,dsi-phy-v3.0";
+		label = "dsi-phy-0";
+		cell-index = <0>;
+		reg = <0xae94400 0x7c0>,
+		    <0xae94200 0x100>;
+		reg-names = "dsi_phy", "dyn_refresh_base";
+		vdda-0p9-supply = <&S3A_LEVEL>;
+		qcom,platform-strength-ctrl = [55 03
+						55 03
+						55 03
+						55 03
+						55 00];
+		qcom,platform-lane-config = [00 00 00 00
+						00 00 00 00
+						00 00 00 00
+						00 00 00 00
+						00 00 00 80];
+		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+		qcom,panel-allow-phy-poweroff;
+		qcom,phy-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			qcom,phy-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-0p9";
+				qcom,supply-min-voltage =
+					<RPM_SMD_REGULATOR_LEVEL_NOM>;
+				qcom,supply-max-voltage =
+					<RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR>;
+				qcom,supply-off-min-voltage =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+
+	sde_dp: qcom,dp_display@ae90000 {
+//#ifndef ODM_LQ_EDIT
+/*Hongbin.Chen@ODM_LQ.BSP.CHG 2019-11-25 close usb 3.0 */
+//		status = "ok";
+//#else
+		status = "disabled";
+//#endif
+		cell-index = <0>;
+		compatible = "qcom,dp-display";
+
+		vdda-1p2-supply = <&L3C>;
+		vdda-0p9-supply = <&L4A>;
+
+		reg =	<0xae90000 0x200>,
+			<0xae90200 0x200>,
+			<0xae90400 0xc00>,
+			<0xae91000 0x400>,
+			<0x88eaa00 0x200>,
+			<0x88ea200 0x200>,
+			<0x88ea600 0x200>,
+			<0xaf02000 0x2d0>,
+			<0x780000 0x6228>,
+			<0x88ea030 0x10>,
+			<0x88e8000 0x20>,
+			<0x0aee1000 0x2a>,
+			<0xae91400 0x400>;
+		reg-names =	"dp_ahb", "dp_aux", "dp_link",
+				"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+				"dp_mmss_cc", "qfprom_physical", "dp_pll",
+				"usb3_dp_com", "hdcp_physical", "dp_p1";
+
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <12 0>;
+
+		qcom,aux-cfg0-settings = [20 00];
+		qcom,aux-cfg1-settings = [24 13 23 1d];
+		qcom,aux-cfg2-settings = [28 24];
+		qcom,aux-cfg3-settings = [2c 00];
+		qcom,aux-cfg4-settings = [30 0a];
+		qcom,aux-cfg5-settings = [34 26];
+		qcom,aux-cfg6-settings = [38 0a];
+		qcom,aux-cfg7-settings = [3c 03];
+		qcom,aux-cfg8-settings = [40 bb];
+		qcom,aux-cfg9-settings = [44 03];
+
+		qcom,max-pclk-frequency-khz = <337500>;
+		qcom,max-hdisplay = <2560>;
+		qcom,max-vdisplay = <1600>;
+		qcom,no-mst-encoder;
+
+	clocks =	<&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+			<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+			<&clock_rpmh RPMH_CXO_CLK>,
+			<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
+			<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+			<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+			<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
+			<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+
+	clock-names =   "core_aux_clk", "core_usb_pipe_clk",
+			"core_usb_ref_clk_src",
+			"core_usb_ref_clk", "core_usb_pipe_clk",
+			"link_clk", "link_iface_clk",
+			"pixel_clk_rcg", "pixel_parent",
+			"strm0_pixel_clk";
+
+		qcom,ctrl-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,ctrl-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-1p2";
+				qcom,supply-min-voltage = <1200000>;
+				qcom,supply-max-voltage = <1200000>;
+				qcom,supply-enable-load = <21800>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,phy-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,phy-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-0p9";
+				qcom,supply-min-voltage = <880000>;
+				qcom,supply-max-voltage = <928000>;
+				qcom,supply-enable-load = <36000>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,core-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,core-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "refgen";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/atoll-stub-regulator.dtsi

@@ -0,0 +1,405 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR  PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+/* Stub regulators */
+
+/ {
+	/* pm6150l S1 - VDD_CX supply */
+	VDD_CX_LEVEL:
+	S1C_LEVEL: pm6150l_s1_level: regulator-pm6150l-s1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_s1_level";
+		qcom,hpm-min-load = <100000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	VDD_CX_LEVEL_AO:
+	S1C_LEVEL_AO: pm6150l_s1_level_ao: regulator-pm6150l-s1-level-ao {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_s1_level_ao";
+		qcom,hpm-min-load = <100000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	/* pm6150 S2 - VDD_GFX supply */
+	VDD_GFX_LEVEL:
+	S2A_LEVEL: pm6150_s2_level: regulator-pm6150-s2 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_s2_level";
+		qcom,hpm-min-load = <100000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	VDD_GFX_LEVEL_AO:
+	S2A_LEVEL_AO: pm6150_s2_level_ao: regulator-pm6150-s2-level-ao {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_s2_level_ao";
+		qcom,hpm-min-load = <100000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	/* pm6150 S3 - VDD_MX supply */
+	VDD_MX_LEVEL:
+	S3A_LEVEL: pm6150_s3_level: regulator-pm6150-s3 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_s3_level";
+		qcom,hpm-min-load = <100000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	VDD_MX_LEVEL_AO:
+	S3A_LEVEL_AO: pm6150_s3_level_ao: regulator-pm6150-s3-level-ao {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_s3_level_ao";
+		qcom,hpm-min-load = <100000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	S1A: pm6150_s1: regulator-pm6150-s1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_s1";
+		qcom,hpm-min-load = <100000>;
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1200000>;
+	};
+
+	/* pm6150l S7 - VDD_MSS supply */
+	VDD_MSS_LEVEL:
+	S7C_LEVEL: pm6150l_s7_level: regulator-pm6150l-s7 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_s7_level";
+		qcom,hpm-min-load = <100000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	S8C: pm6150l_s8: regulator-pm6150l-s8 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_s8";
+		qcom,hpm-min-load = <100000>;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1400000>;
+	};
+
+	L1A: pm6150_l1: regulator-pm6150-l1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l1";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1178000>;
+		regulator-max-microvolt = <1252000>;
+	};
+
+	L2A: pm6150_l2: regulator-pm6150-l2 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l2";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <1050000>;
+	};
+
+	L3A: pm6150_l3: regulator-pm6150-l3 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l3";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <970000>;
+		regulator-max-microvolt = <1060000>;
+	};
+
+	L4A: pm6150_l4: regulator-pm6150-l4 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l4";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <830000>;
+		regulator-max-microvolt = <920000>;
+	};
+
+	L5A: pm6150_l5: regulator-pm6150-l5 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l5";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <2600000>;
+		regulator-max-microvolt = <2800000>;
+	};
+
+	L6A: pm6150_l6: regulator-pm6150-l6 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l6";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <600000>;
+		regulator-max-microvolt = <650000>;
+	};
+
+	/* pm6150 L7 - LPI_MX supply */
+	L7A_LEVEL: pm6150_l7_level: regulator-pm6150-l7 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l7_level";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	/* pm6150 L8 - LPI_CX supply */
+	L8A_LEVEL: pm6150_l8_level: regulator-pm6150-l8 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l8_level";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	L9A: pm6150_l9: regulator-pm6150-l9 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l9";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <630000>;
+		regulator-max-microvolt = <760000>;
+	};
+
+	L10A: pm6150_l10: regulator-pm6150-l10 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l10";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1721000>;
+		regulator-max-microvolt = <1829000>;
+	};
+
+	L11A: pm6150_l11: regulator-pm6150-l11 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l11";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1620000>;
+		regulator-max-microvolt = <1980000>;
+	};
+
+	L12A: pm6150_l12: regulator-pm6150-l12 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l12";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1700000>;
+		regulator-max-microvolt = <1950000>;
+	};
+
+	L13A: pm6150_l13: regulator-pm6150-l13 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l13";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1700000>;
+		regulator-max-microvolt = <1900000>;
+	};
+
+	L14A: pm6150_l14: regulator-pm6150-l14 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l14";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1721000>;
+		regulator-max-microvolt = <1850000>;
+	};
+
+	L15A: pm6150_l15: regulator-pm6150-l15 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l15";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1700000>;
+		regulator-max-microvolt = <1900000>;
+	};
+
+	L16A: pm6150_l16: regulator-pm6150-l16 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l16";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <2430000>;
+		regulator-max-microvolt = <2970000>;
+	};
+
+	L17A: pm6150_l17: regulator-pm6150-l17 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l17";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3230000>;
+	};
+
+	L18A: pm6150_l18: regulator-pm6150-l18 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l18";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <4400000>;
+	};
+
+	L19A: pm6150_l19: regulator-pm6150-l19 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150_l19";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <2950000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	L1C: pm6150l_l1: regulator-pm6150l-l1 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l1";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1620000>;
+		regulator-max-microvolt = <1980000>;
+	};
+
+	L2C: pm6150l_l2: regulator-pm6150l-l2 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l2";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1350000>;
+	};
+
+	L3C: pm6150l_l3: regulator-pm6150l-l3 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l3";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1250000>;
+	};
+
+	L4C: pm6150l_l4: regulator-pm6150l-l4 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l4";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1650000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	L5C: pm6150l_l5: regulator-pm6150l-l5 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l5";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1650000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	L6C: pm6150l_l6: regulator-pm6150l-l6 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l6";
+		qcom,hpm-min-load = <5000>;
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <3600000>;
+	};
+
+	L7C: pm6150l_l7: regulator-pm6150l-l7 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l7";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3600000>;
+	};
+
+	L8C: pm6150l_l8: regulator-pm6150l-l8 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l8";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <1700000>;
+		regulator-max-microvolt = <1900000>;
+	};
+
+	L9C: pm6150l_l9: regulator-pm6150l-l9 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l9";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <2950000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	L10C: pm6150l_l10: regulator-pm6150l-l10 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l10";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3400000>;
+	};
+
+	L11C: pm6150l_l11: regulator-pm6150l-l11 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_l11";
+		qcom,hpm-min-load = <10000>;
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3400000>;
+	};
+
+	BOB: pm6150l_bob: regulator-pm6150l-bob {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_bob";
+		regulator-min-microvolt = <3200000>;
+		regulator-max-microvolt = <4200000>;
+	};
+
+	BOB_AO: pm6150l_bob_ao: regulator-pm6150l-bob-ao {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm6150l_bob_ao";
+		regulator-min-microvolt = <3200000>;
+		regulator-max-microvolt = <4200000>;
+	};
+
+	L1P: qcom,pm8008-l1@4000 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8008_l1";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1600000>;
+	};
+
+	L2P: qcom,pm8008-l2@4100 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8008_l2";
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1200000>;
+	};
+
+	L3P: qcom,pm8008-l3@4200 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8008_l3";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <2900000>;
+	};
+
+	L4P: qcom,pm8008-l4@4300 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8008_l4";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <2900000>;
+	};
+
+	L5P: qcom,pm8008-l5@4400 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8008_l5";
+		regulator-min-microvolt = <1700000>;
+		regulator-max-microvolt = <3400000>;
+	};
+
+	L6P: qcom,pm8008-l6@4500 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8008_l6";
+		regulator-min-microvolt = <2600000>;
+		regulator-max-microvolt = <3000000>;
+	};
+
+	L7P: qcom,pm8008-l7@4600 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8008_l7";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <3400000>;
+	};
+};

arch/arm64/boot/dts/19721/atoll-usb.dtsi

@@ -0,0 +1,394 @@
+/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-atoll.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/phy/qcom,atoll-qmp-usb3.h>
+
+&soc {
+	usb0: ssusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x0a600000 0x100000>;
+		reg-names = "core_base";
+
+		iommus = <&apps_smmu 0x540 0x0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		USB3_GDSC-supply = <&usb30_prim_gdsc>;
+		dpdm-supply = <&qusb_phy0>;
+		qcom,use-pdc-interrupts;
+
+		clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+			<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,
+			<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>;
+			clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+						"utmi_clk", "sleep_clk", "xo";
+
+		resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <133333333>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			 0x110 /* GSI_DBL_ADDR_L */
+			 0x120 /* GSI_DBL_ADDR_H */
+			 0x130 /* GSI_RING_BASE_ADDR_L */
+			 0x144 /* GSI_RING_BASE_ADDR_H */
+			 0x1a4>; /* GSI_IF_STS */
+		qcom,gsi-disable-io-coherency;
+		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
+
+		qcom,msm-bus,name = "usb0";
+		qcom,msm-bus,num-cases = <4>;
+		qcom,msm-bus,num-paths = <3>;
+		qcom,msm-bus,vectors-KBps =
+			/*  suspend vote */
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
+
+			/*  nominal vote */
+			<MSM_BUS_MASTER_USB3
+				MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>,
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+			/*  svs vote */
+			<MSM_BUS_MASTER_USB3
+				MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+			/*  min vote */
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
+
+		qcom,default-bus-vote = <2>; /* use svs bus voting */
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0x0a600000 0xcd00>;
+			interrupts = <0 133 0>;
+//#ifndef ODM_LQ_EDIT
+/*Hongbin.Chen@ODM_LQ.BSP.CHG 2019-11-25 close usb 3.0 */
+//			usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>;
+//#else
+			usb-phy = <&qusb_phy0>, <&usb_nop_phy>;
+//#endif
+			linux,sysdev_is_parent;
+			snps,disable-clk-gating;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_enblslpm_quirk;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x10>;
+			snps,usb3_lpm_capable;
+			usb-core-id = <0>;
+			tx-fifo-resize;
+//#ifndef ODM_LQ_EDIT
+/*Hongbin.Chen@ODM_LQ.BSP.CHG 2019-11-25 close usb 3.0 */
+//			maximum-speed = "super-speed";
+//#else
+			maximum-speed = "high-speed";
+//#endif
+			dr_mode = "otg";
+		};
+
+		qcom,usbbam@a704000 {
+			compatible = "qcom,usb-bam-msm";
+			reg = <0xa704000 0x17000>;
+			interrupts = <0 132 0>;
+
+			qcom,usb-bam-fifo-baseaddr = <0x146a6000>;
+			qcom,usb-bam-num-pipes = <4>;
+			qcom,disable-clk-gating;
+			qcom,usb-bam-override-threshold = <0x4001>;
+			qcom,usb-bam-max-mbps-highspeed = <400>;
+			qcom,usb-bam-max-mbps-superspeed = <3600>;
+			qcom,reset-bam-on-connect;
+
+			qcom,pipe0 {
+				label = "ssusb-qdss-in-0";
+				qcom,usb-bam-mem-type = <2>;
+				qcom,dir = <1>;
+				qcom,pipe-num = <0>;
+				qcom,peer-bam = <0>;
+				qcom,peer-bam-physical-address = <0x6064000>;
+				qcom,src-bam-pipe-index = <0>;
+				qcom,dst-bam-pipe-index = <0>;
+				qcom,data-fifo-offset = <0x0>;
+				qcom,data-fifo-size = <0x1800>;
+				qcom,descriptor-fifo-offset = <0x1800>;
+				qcom,descriptor-fifo-size = <0x800>;
+			};
+		};
+	};
+
+	/* Primary USB port related QUSB2 PHY */
+	qusb_phy0: qusb@88e3000 {
+		compatible = "qcom,qusb2phy-v2";
+		reg = <0x088e3000 0x400>,
+			<0x00780258 0x4>,
+			<0x088e7014 0x4>;
+		reg-names = "qusb_phy_base", "efuse_addr",
+				"refgen_north_bg_reg_addr";
+
+		qcom,efuse-bit-pos = <25>;
+		qcom,efuse-num-bits = <3>;
+		vdd-supply = <&pm6150_l4>;
+		vdda18-supply = <&pm6150_l11>;
+		vdda33-supply = <&pm6150_l17>;
+		qcom,vdd-voltage-level = <0 880000 900000>;
+		qcom,qusb-phy-reg-offset =
+			<0x240 /* QUSB2PHY_PORT_TUNE1 */
+			 0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */
+			 0x210 /* QUSB2PHY_PWR_CTRL1 */
+			 0x230 /* QUSB2PHY_INTR_CTRL */
+			 0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */
+			 0x254 /* QUSB2PHY_TEST1 */
+			 0x198 /* PLL_BIAS_CONTROL_2 */
+			 0x27c /* QUSB2PHY_DEBUG_CTRL1 */
+			 0x280 /* QUSB2PHY_DEBUG_CTRL2 */
+			 0x284 /* QUSB2PHY_DEBUG_CTRL3 */
+			 0x288 /* QUSB2PHY_DEBUG_CTRL4 */
+			 0x2a0>; /* QUSB2PHY_STAT5 */
+
+		qcom,qusb-phy-init-seq =
+			/* <value reg_offset> */
+			<0x23 0x210 /* PWR_CTRL1 */
+			 0x03 0x04  /* PLL_ANALOG_CONTROLS_TWO */
+			 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+			 0x80 0x2c  /* PLL_CMODE */
+			 0x0a 0x184 /* PLL_LOCK_DELAY */
+			 0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */
+			 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+			 0x17 0x198 /* PLL_BIAS_CONTROL_2 */
+			 0x21 0x214 /* PWR_CTRL2 */
+			 0x08 0x220 /* IMP_CTRL1 */
+			 0x58 0x224 /* IMP_CTRL2 */
+			 0x77 0x240 /* TUNE1 */
+			 0x28 0x244 /* TUNE2 */
+			 0xca 0x248 /* TUNE3 */
+			 0x04 0x24c /* TUNE4 */
+			 0x03 0x250 /* TUNE5 */
+			 0x30 0x23c /* CHG_CTRL2 */
+			 0x22 0x210>; /* PWR_CTRL1 */
+
+		qcom,qusb-phy-host-init-seq =
+			/* <value reg_offset> */
+			<0x23 0x210 /* PWR_CTRL1 */
+			0x03 0x04  /* PLL_ANALOG_CONTROLS_TWO */
+			0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+			0x80 0x2c  /* PLL_CMODE */
+			0x0a 0x184 /* PLL_LOCK_DELAY */
+			0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */
+			0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+			0x22 0x198 /* PLL_BIAS_CONTROL_2 */
+			0x21 0x214 /* PWR_CTRL2 */
+			0x08 0x220 /* IMP_CTRL1 */
+			0x58 0x224 /* IMP_CTRL2 */
+			0x47 0x240 /* TUNE1 */
+			0x28 0x244 /* TUNE2 */
+			0xca 0x248 /* TUNE3 */
+			0x04 0x24c /* TUNE4 */
+			0x03 0x250 /* TUNE5 */
+			0x30 0x23c /* CHG_CTRL2 */
+			0x22 0x210>; /* PWR_CTRL1 */
+
+		phy_type= "utmi";
+		clocks = <&clock_rpmh RPMH_CXO_CLK>,
+			<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+		clock-names = "ref_clk_src", "cfg_ahb_clk";
+
+		resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+	};
+//#ifdef ODM_LQ_EDIT
+/*Hongbin.Chen@ODM_LQ.BSP.CHG 2019-11-25 close usb 3.0 */
+	usb_nop_phy:usb_nop_phy{
+	status = "okay";
+	compatible = "usb-nop-xceiv";
+	};
+//#endif
+	/* Primary USB port related QMP USB DP Combo PHY */
+	usb_qmp_dp_phy: ssphy@88e8000 {
+		compatible = "qcom,usb-ssphy-qmp-dp-combo";
+		reg = <0x88e8000 0x3000>;
+		reg-names = "qmp_phy_base";
+//#ifndef ODM_LQ_EDIT
+/*Hongbin.Chen@ODM_LQ.BSP.CHG 2019-11-25 close usb 3.0 */
+		status = "disabled";
+//#endif
+		vdd-supply = <&pm6150_l4>;
+		qcom,vdd-voltage-level = <0 880000 900000>;
+		core-supply = <&pm6150l_l3>;
+		qcom,vbus-valid-override;
+		qcom,qmp-phy-init-seq =
+			/* <reg_offset, value, delay> */
+			<USB3_DP_QSERDES_COM_PLL_IVCO 0x07 0
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x14 0
+			USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x08 0
+			USB3_DP_QSERDES_COM_CLK_SELECT 0x30 0
+			USB3_DP_QSERDES_COM_SYS_CLK_CTRL 0x02 0
+			USB3_DP_QSERDES_COM_RESETSM_CNTRL2 0x08 0
+			USB3_DP_QSERDES_COM_CMN_CONFIG 0x16 0
+			USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x01 0
+			USB3_DP_QSERDES_COM_HSCLK_SEL 0x80 0
+			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
+			USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00 0
+			USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x3f 0
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x01 0
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0xc9 0
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE0  0x0a 0
+			USB3_DP_QSERDES_COM_LOCK_CMP3_MODE0 0x00 0
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x15 0
+			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
+			USB3_DP_QSERDES_COM_CORE_CLK_EN 0x00 0
+			USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x00 0
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x00 0
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
+			USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
+			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
+			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
+			USB3_DP_QSERDES_COM_SSC_ADJ_PER1 0x00 0
+			USB3_DP_QSERDES_COM_SSC_ADJ_PER2 0x00 0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1 0x85 0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2 0x07 0
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b 0
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e 0
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18 0
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+			USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x03 0
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x16 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00 0x05 0
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x03 0
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b 0
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e 0
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18 0
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+			USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x03 0
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x16 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00 0x05 0
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x03 0
+			USB3_DP_QSERDES_TXA_HIGHZ_DRVR_EN 0x10 0
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x16 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x06 0
+			USB3_DP_QSERDES_TXB_HIGHZ_DRVR_EN 0x10 0
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x16 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x06 0
+			USB3_DP_PCS_FLL_CNTRL2 0x83 0
+			USB3_DP_PCS_FLL_CNT_VAL_L 0x09 0
+			USB3_DP_PCS_FLL_CNT_VAL_H_TOL 0xa2 0
+			USB3_DP_PCS_FLL_MAN_CODE 0x40 0
+			USB3_DP_PCS_FLL_CNTRL1 0x02 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xd1 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x1f 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x47 0
+			USB3_DP_PCS_POWER_STATE_CONFIG2 0x1b 0
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75 0
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75 0
+			USB3_DP_PCS_RX_SIGDET_LVL 0xcc 0
+			USB3_DP_PCS_TXMGN_V0 0x9f 0
+			USB3_DP_PCS_TXMGN_V1 0x9f 0
+			USB3_DP_PCS_TXMGN_V2 0xb7 0
+			USB3_DP_PCS_TXMGN_V3 0x4e 0
+			USB3_DP_PCS_TXMGN_V4 0x65 0
+			USB3_DP_PCS_TXMGN_LS 0x6b 0
+			USB3_DP_PCS_TXDEEMPH_M6DB_V0 0x15 0
+			USB3_DP_PCS_TXDEEMPH_M3P5DB_V0 0x0d 0
+			USB3_DP_PCS_TXDEEMPH_M6DB_V1 0x15 0
+			USB3_DP_PCS_TXDEEMPH_M3P5DB_V1 0x0d 0
+			USB3_DP_PCS_TXDEEMPH_M6DB_V2 0x15 0
+			USB3_DP_PCS_TXDEEMPH_M3P5DB_V2 0x0d 0
+			USB3_DP_PCS_TXDEEMPH_M6DB_V3 0x15 0
+			USB3_DP_PCS_TXDEEMPH_M3P5DB_V3 0x1d 0
+			USB3_DP_PCS_TXDEEMPH_M6DB_V4 0x15 0
+			USB3_DP_PCS_TXDEEMPH_M3P5DB_V4 0x0d 0
+			USB3_DP_PCS_TXDEEMPH_M6DB_LS 0x15 0
+			USB3_DP_PCS_TXDEEMPH_M3P5DB_LS 0x0d 0
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
+			USB3_DP_PCS_REFGEN_REQ_CONFIG2 0x60 0
+			USB3_DP_PCS_RATE_SLEW_CNTRL 0x02 0
+			USB3_DP_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x04 0
+			USB3_DP_PCS_TSYNC_RSYNC_TIME 0x44 0
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
+			USB3_DP_PCS_RCVR_DTCT_DLY_U3_L 0x40 0
+			USB3_DP_PCS_RCVR_DTCT_DLY_U3_H 0x00 0
+			USB3_DP_PCS_RXEQTRAINING_WAIT_TIME 0x75 0
+			USB3_DP_PCS_LFPS_TX_ECSTART_EQTLOCK 0x86 0
+			USB3_DP_PCS_RXEQTRAINING_RUN_TIME 0x13 0
+			USB3_DP_PCS_LFPS_DET_HIGH_COUNT_VAL 0x04 0
+			0xffffffff 0xffffffff 0>;
+
+		qcom,qmp-phy-reg-offset =
+			<USB3_DP_PCS_PCS_STATUS
+			USB3_DP_PCS_AUTONOMOUS_MODE_CTRL
+			USB3_DP_PCS_LFPS_RXTERM_IRQ_CLEAR
+			USB3_DP_PCS_POWER_DOWN_CONTROL
+			USB3_DP_PCS_SW_RESET
+			USB3_DP_PCS_START_CONTROL
+			USB3_DP_PCS_MISC_TYPEC_CTRL
+			USB3_DP_PHY_DP_DP_PHY_PD_CTL
+			USB3_DP_COM_POWER_DOWN_CTRL
+			USB3_DP_COM_SW_RESET
+			USB3_DP_COM_RESET_OVRD_CTRL
+			USB3_DP_COM_PHY_MODE_CTRL
+			USB3_DP_COM_TYPEC_CTRL
+			USB3_DP_COM_SWI_CTRL
+			USB3_DP_PCS_MISC_CLAMP_ENABLE>;
+
+		clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+			<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+			<&clock_rpmh RPMH_CXO_CLK>,
+			<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
+			<&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+			<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
+				"ref_clk", "com_aux_clk", "cfg_ahb_clk";
+
+		resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+			<&clock_gcc GCC_USB3_PHY_PRIM_BCR>;
+		reset-names = "global_phy_reset", "phy_reset";
+	};
+
+	usb_audio_qmi_dev {
+		compatible = "qcom,usb-audio-qmi-dev";
+		iommus = <&apps_smmu 0x100f 0x0>;
+		qcom,usb-audio-stream-id = <0xf>;
+		qcom,usb-audio-intr-num = <2>;
+	};
+};

arch/arm64/boot/dts/19721/atoll-usbc-idp-overlay.dts

@@ -0,0 +1,30 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "atoll-idp.dtsi"
+#include "atoll-usbc-idp.dtsi"
+
+/ {
+	model = "USBC Audio IDP";
+	compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp";
+	qcom,msm-id = <407 0x0>;
+	qcom,board-id = <34 2>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};

arch/arm64/boot/dts/19721/atoll-usbc-idp.dts

@@ -0,0 +1,27 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll.dtsi"
+#include "atoll-idp.dtsi"
+#include "atoll-usbc-idp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL PM6150 USBC Audio IDP";
+	compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp";
+	qcom,board-id = <34 2>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};

arch/arm64/boot/dts/19721/atoll-usbc-idp.dtsi

@@ -0,0 +1,24 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "atoll-audio-overlay.dtsi"
+
+//#ifndef OPLUS_ARCH_EXTENDS
+//Suresh.Alla@MULTIMEDIA.AUDIODRIVER.HEADSETDET, 2020/07/30, Delete for headset detect
+/*
+&atoll_snd {
+	qcom,msm-mbhc-usbc-audio-supported = <1>;
+	qcom,msm-mbhc-hphl-swh = <0>;
+	qcom,msm-mbhc-gnd-swh = <0>;
+};
+*/
+//#endif /* OPLUS_ARCH_EXTENDS */

arch/arm64/boot/dts/19721/atoll-vidc.dtsi

@@ -0,0 +1,106 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/clock/qcom,videocc-atoll.h>
+
+&soc {
+	msm_vidc: qcom,vidc@aa00000 {
+		compatible = "qcom,msm-vidc", "qcom,atoll-vidc";
+		status = "ok";
+		reg = <0xaa00000 0x200000>;
+		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+		/* Supply */
+		venus-supply = <&venus_gdsc>;
+		venus-core0-supply = <&vcodec0_gdsc>;
+
+		/* Clocks */
+		clock-names = "core_clk", "iface_clk", "bus_clk",
+			"core0_clk", "core0_bus_clk";
+		clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
+			<&clock_videocc VIDEO_CC_VENUS_AHB_CLK>,
+			<&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
+			<&clock_videocc VIDEO_CC_VCODEC0_CORE_CLK>,
+			<&clock_videocc VIDEO_CC_VCODEC0_AXI_CLK>;
+		qcom,proxy-clock-names = "core_clk", "iface_clk",
+			"bus_clk", "core0_clk", "core0_bus_clk";
+		qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0>;
+		qcom,allowed-clock-rates = <150000000 270000000 340000000
+			434000000>;
+
+		/* Buses */
+		bus_cnoc {
+			compatible = "qcom,msm-vidc,bus";
+			label = "cnoc";
+			qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+			qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+			qcom,bus-governor = "performance";
+			qcom,bus-range-kbps = <1000 1000>;
+		};
+
+		venus_bus_ddr {
+			compatible = "qcom,msm-vidc,bus";
+			label = "venus-ddr";
+			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+			qcom,bus-governor = "vidc-ar50-ddr";
+			qcom,bus-range-kbps = <1000 2128000>;
+		};
+		arm9_bus_ddr {
+			compatible = "qcom,msm-vidc,bus";
+			label = "venus-arm9-ddr";
+			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+			qcom,bus-governor = "performance";
+			qcom,bus-range-kbps = <1000 1000>;
+		};
+
+		/* MMUs */
+		non_secure_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_ns";
+			iommus = <&apps_smmu 0xC00 0x60>;
+			buffer-types = <0xfff>;
+			virtual-addr-pool = <0x70800000 0x6f800000>;
+		};
+
+		secure_bitstream_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_sec_bitstream";
+			iommus = <&apps_smmu 0xC21 0x4>;
+			buffer-types = <0x241>;
+			virtual-addr-pool = <0x4b000000 0x25800000>;
+			qcom,secure-context-bank;
+		};
+
+		secure_pixel_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_sec_pixel";
+			iommus = <&apps_smmu 0xC23 0x0>;
+			buffer-types = <0x106>;
+			virtual-addr-pool = <0x25800000 0x25800000>;
+			qcom,secure-context-bank;
+		};
+
+		secure_non_pixel_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_sec_non_pixel";
+			iommus = <&apps_smmu 0xC04 0x60>;
+			buffer-types = <0x480>;
+			virtual-addr-pool = <0x1000000 0x24800000>;
+			qcom,secure-context-bank;
+		};
+	};
+};
+

arch/arm64/boot/dts/19721/atoll-wcd937x-idp-audio-overlay.dtsi

@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "atoll-audio-overlay.dtsi"
+
+&wcd937x_codec {
+	status = "ok";
+};
+
+&wcd938x_codec {
+	status = "disabled";
+};
+
+&wcd937x_rx_slave {
+	status = "ok";
+};
+
+&wcd937x_tx_slave {
+	status = "ok";
+};
+
+&wcd938x_rx_slave {
+	status = "disabled";
+};
+
+&wcd938x_tx_slave {
+	status = "disabled";
+};
+
+
+&atoll_snd {
+	qcom,model = "atoll-wcd937x-snd-card";
+	qcom,audio-routing =
+		"AMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Analog Mic1",
+		"AMIC2", "MIC BIAS2",
+		"MIC BIAS2", "Analog Mic2",
+		"AMIC3", "MIC BIAS3",
+		"MIC BIAS3", "Analog Mic3",
+		"TX DMIC0", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic0",
+		"TX DMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic1",
+		"TX DMIC2", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic2",
+		"TX DMIC3", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic3",
+		"IN1_HPHL", "HPHL_OUT",
+		"IN2_HPHR", "HPHR_OUT",
+		"IN3_AUX", "AUX_OUT",
+		"TX SWR_ADC0", "ADC1_OUTPUT",
+		"TX SWR_ADC2", "ADC2_OUTPUT",
+		"TX SWR_DMIC0", "DMIC1_OUTPUT",
+		"TX SWR_DMIC1", "DMIC2_OUTPUT",
+		"TX SWR_DMIC2", "DMIC3_OUTPUT",
+		"TX SWR_DMIC3", "DMIC4_OUTPUT",
+		"TX SWR_DMIC4", "DMIC5_OUTPUT",
+		"TX SWR_DMIC5", "DMIC6_OUTPUT",
+		"TX SWR_DMIC6", "DMIC7_OUTPUT",
+		"TX SWR_DMIC7", "DMIC8_OUTPUT",
+		"WSA SRC0_INP", "SRC0",
+		"WSA_TX DEC0_INP", "TX DEC0 MUX",
+		"WSA_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC0_INP", "TX DEC0 MUX",
+		"RX_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC2_INP", "TX DEC2 MUX",
+		"RX_TX DEC3_INP", "TX DEC3 MUX",
+		"SpkrLeft IN", "WSA_SPK1 OUT",
+		"SpkrRight IN", "WSA_SPK2 OUT",
+		"VA_AIF1 CAP", "VA_SWR_CLK",
+		"VA_AIF2 CAP", "VA_SWR_CLK",
+		"VA_AIF3 CAP", "VA_SWR_CLK",
+		"VA MIC BIAS1", "Digital Mic0",
+		"VA MIC BIAS1", "Digital Mic1",
+		"VA MIC BIAS3", "Digital Mic2",
+		"VA MIC BIAS3", "Digital Mic3",
+		"VA DMIC0", "VA MIC BIAS1",
+		"VA DMIC1", "VA MIC BIAS1",
+		"VA DMIC2", "VA MIC BIAS3",
+		"VA DMIC3", "VA MIC BIAS3",
+		"VA SWR_ADC0", "VA_SWR_CLK",
+		"VA SWR_ADC1", "VA_SWR_CLK",
+		"VA SWR_ADC2", "VA_SWR_CLK",
+		"VA SWR_ADC3", "VA_SWR_CLK",
+		"VA SWR_MIC0", "VA_SWR_CLK",
+		"VA SWR_MIC1", "VA_SWR_CLK",
+		"VA SWR_MIC2", "VA_SWR_CLK",
+		"VA SWR_MIC3", "VA_SWR_CLK",
+		"VA SWR_MIC4", "VA_SWR_CLK",
+		"VA SWR_MIC5", "VA_SWR_CLK",
+		"VA SWR_MIC6", "VA_SWR_CLK",
+		"VA SWR_MIC7", "VA_SWR_CLK",
+		"VA SWR_ADC0", "ADC1_OUTPUT",
+		"VA SWR_ADC2", "ADC2_OUTPUT",
+		"VA SWR_MIC0", "DMIC1_OUTPUT",
+		"VA SWR_MIC1", "DMIC2_OUTPUT",
+		"VA SWR_MIC2", "DMIC3_OUTPUT",
+		"VA SWR_MIC3", "DMIC4_OUTPUT",
+		"VA SWR_MIC4", "DMIC5_OUTPUT",
+		"VA SWR_MIC5", "DMIC6_OUTPUT",
+		"VA SWR_MIC6", "DMIC7_OUTPUT",
+		"VA SWR_MIC7", "DMIC8_OUTPUT";
+	qcom,codec-aux-devs = <&wcd937x_codec>;
+};
+

arch/arm64/boot/dts/19721/atoll-wcd937x-idp-overlay.dts

@@ -0,0 +1,36 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "atoll-idp.dtsi"
+#include "atoll-wcd937x-idp-audio-overlay.dtsi"
+
+/ {
+	model = "wcd937x Audio Codec IDP";
+	compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp";
+	qcom,msm-id = <407 0x0>;
+	qcom,board-id = <34 1>;
+};
+//#ifdef OPLUS_BUG_STABILITY
+/* Shusheng.Bei@MULTIMEDIA.DISPLAY.LCD, 2020/11/12, add for bring up 19721 NT36672C BOE panel */
+/*&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};*/
+
+&dsi_nt36672c_boe_video_display {
+    qcom,dsi-display-active;
+};
+/*#endif OPLUS_BUG_STABILITY*/
+

arch/arm64/boot/dts/19721/atoll-wcd937x-idp.dts

@@ -0,0 +1,27 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll.dtsi"
+#include "atoll-idp.dtsi"
+#include "atoll-wcd937x-idp-audio-overlay.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL PM6150 wcd937x Audio Codec IDP";
+	compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp";
+	qcom,board-id = <34 1>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};

arch/arm64/boot/dts/19721/atoll.dts

@@ -0,0 +1,23 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atoll.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLL SoC";
+	compatible = "qcom,atoll";
+	qcom,pmic-name = "PM6150";
+	qcom,board-id = <0 0>;
+	oppo,dtsi_no = <19721>;
+};

arch/arm64/boot/dts/19721/atollp-atp-overlay.dts

@@ -0,0 +1,25 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "atoll-atp.dtsi"
+
+/ {
+	model = "ATP";
+	compatible = "qcom,atollp-atp", "qcom,atollp", "qcom,atp";
+	qcom,msm-id = <424 0x0>;
+	qcom,board-id = <33 0>;
+};

arch/arm64/boot/dts/19721/atollp-atp.dts

@@ -0,0 +1,22 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atollp.dtsi"
+#include "atoll-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLLP PM6150 ATP";
+	compatible = "qcom,atollp-idp", "qcom,atollp", "qcom,idp", "qcom,atp";
+	qcom,board-id = <33 0>;
+};

arch/arm64/boot/dts/19721/atollp-idp-overlay.dts

@@ -0,0 +1,30 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "atoll-idp.dtsi"
+#include "atoll-audio-overlay.dtsi"
+
+/ {
+	model = "IDP";
+	compatible = "qcom,atollp-idp", "qcom,atollp", "qcom,idp";
+	qcom,msm-id = <424 0x0>;
+	qcom,board-id = <34 0>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};

arch/arm64/boot/dts/19721/atollp-idp.dts

@@ -0,0 +1,26 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atollp.dtsi"
+#include "atoll-idp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLLP PM6150 IDP";
+	compatible = "qcom,atollp-idp", "qcom,atollp", "qcom,idp";
+	qcom,board-id = <34 0>;
+};
+
+&dsi_rm69299_visionox_amoled_vid_display {
+	qcom,dsi-display-active;
+};

arch/arm64/boot/dts/19721/atollp-qrd-overlay.dts

@@ -0,0 +1,23 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "atoll-qrd.dtsi"
+
+/ {
+	model = "QRD";
+	compatible = "qcom,atollp-qrd", "qcom,atollp", "qcom,qrd";
+	qcom,msm-id = <424 0>;
+	qcom,board-id = <0x1000B 0>;
+};

arch/arm64/boot/dts/19721/atollp-qrd.dts

@@ -0,0 +1,22 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atollp.dtsi"
+#include "atoll-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLLP PM6150 QRD";
+	compatible = "qcom,atollp-qrd", "qcom,atollp", "qcom,qrd";
+	qcom,board-id = <0x1000B 0>;
+};

arch/arm64/boot/dts/19721/atollp.dts

@@ -0,0 +1,22 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "atollp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLLP SoC";
+	compatible = "qcom,atoll";
+	qcom,pmic-name = "PM6150";
+	qcom,board-id = <0 0>;
+};

arch/arm64/boot/dts/19721/atollp.dtsi

@@ -0,0 +1,29 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "atoll.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ATOLLP";
+	qcom,msm-name = "ATOLLP";
+	qcom,msm-id = <424 0>;
+};
+
+&soc {
+	qcom,rmnet-ipa {
+		status="disabled";
+	};
+};
+
+&ipa_hw {
+	status="disabled";
+};

arch/arm64/boot/dts/19721/dsi-panel-ext-bridge-1080p.dtsi

@@ -0,0 +1,52 @@
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p {
+		qcom,mdss-dsi-panel-name = "ext video mode dsi bridge";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-t-clk-post = <0x03>;
+		qcom,mdss-dsi-t-clk-pre = <0x24>;
+		qcom,mdss-dsi-force-clock-lane-hs;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1920>;
+				qcom,mdss-dsi-panel-height = <1080>;
+				qcom,mdss-dsi-h-front-porch = <88>;
+				qcom,mdss-dsi-h-back-porch = <148>;
+				qcom,mdss-dsi-h-pulse-width = <44>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <36>;
+				qcom,mdss-dsi-v-front-porch = <4>;
+				qcom,mdss-dsi-v-pulse-width = <5>;
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,display-topology = <1 0 1>;
+				qcom,default-topology-index = <0>;
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-ext-bridge-hdmi-1080p.dtsi

@@ -0,0 +1,52 @@
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_ext_bridge_hdmi_1080p: qcom,mdss_dsi_ext_bridge_hdmi_1080p {
+		qcom,mdss-dsi-panel-name = "ext bridge video mode hdmi 1080p";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-t-clk-post = <0x18>;
+		qcom,mdss-dsi-t-clk-pre = <0x1b>;
+		qcom,mdss-dsi-force-clock-lane-hs;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1920>;
+				qcom,mdss-dsi-panel-height = <1080>;
+				qcom,mdss-dsi-h-front-porch = <88>;
+				qcom,mdss-dsi-h-back-porch = <148>;
+				qcom,mdss-dsi-h-pulse-width = <44>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <36>;
+				qcom,mdss-dsi-v-front-porch = <4>;
+				qcom,mdss-dsi-v-pulse-width = <5>;
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,display-topology = <1 0 1>;
+				qcom,default-topology-index = <0>;
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi

@@ -0,0 +1,159 @@
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_hx83112a_truly_video: qcom,mdss_dsi_hx83112a_truly_video {
+		qcom,mdss-dsi-panel-name =
+			"hx83112a video mode dsi truly panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-h-left-border = <0>;
+		qcom,mdss-dsi-h-right-border = <0>;
+		qcom,mdss-dsi-v-top-border = <0>;
+		qcom,mdss-dsi-v-bottom-border = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-lp11-init;
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+		qcom,mdss-dsi-bl-min-level = <1>;
+		qcom,mdss-dsi-bl-max-level = <4095>;
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-pan-physical-width-dimension = <65>;
+		qcom,mdss-pan-physical-height-dimension = <129>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0 {
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2160>;
+				qcom,mdss-dsi-h-front-porch = <42>;
+				qcom,mdss-dsi-h-back-porch = <42>;
+				qcom,mdss-dsi-h-pulse-width = <10>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <15>;
+				qcom,mdss-dsi-v-front-porch = <10>;
+				qcom,mdss-dsi-v-pulse-width = <3>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+				  39 01 00 00 00 00 04 B9 83 11 2A
+				  39 01 00 00 00 00 09 B1 08 29 29 00 00 4F 54
+				     33
+				  39 01 00 00 00 00 11 B2 00 02 00 80 70 00 08
+				     26 FC 01 00 03 15 A3 87 09
+				  39 01 00 00 00 00 02 BD 02
+				  39 01 00 00 00 00 02 BD 00
+				  39 01 00 00 00 00 03 D2 2C 2C
+				  39 01 00 00 00 00 1C B4 01 CE 01 CE 01 CE 0A
+				     CE 0A CE 0A CE 00 FF 00 FF 00 00 22 23 00
+				     28 0A 13 14 00 8A
+				  39 01 00 00 00 00 02 BD 02
+				  39 01 00 00 00 00 0A B4 00 92 12 22 88 12 12
+				     00 53
+				  39 01 00 00 00 00 02 BD 00
+				  39 01 00 00 00 00 04 B6 82 82 E3
+				  39 01 00 00 00 00 02 CC 08
+				  39 01 00 00 00 00 2B D3 40 00 00 00 00 01 01
+				     0A 0A 07 07 00 08 09 09 09 09 32 10 09 00
+				     09 32 21 0A 00 0A 32 10 08 00 00 00 00 00
+				     00 00 00 00 0B 08 82
+				  39 01 00 00 00 00 02 BD 01
+				  39 01 00 00 00 00 09 D3 00 00 19 00 00 0A 00
+				     81
+				  39 01 00 00 00 00 02 BD 00
+				  39 01 00 00 00 00 31 D5 18 18 18 18 18 18 18
+				     18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0
+				     18 40 40 01 00 07 06 05 04 03 02 21 20 18
+				     18 19 19 18 18 03 03 18 18 18 18 18 18
+				  39 01 00 00 00 00 31 D6 18 18 18 18 18 18 18
+				     18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0
+				     18 40 40 02 03 04 05 06 07 00 01 20 21 18
+				     18 18 18 19 19 20 20 18 18 18 18 18 18
+				  39 01 00 00 00 00 19 D8 00 00 00 00 00 00 00
+				     00 00 00 00 00 00 00 00 00 00 00 00 00 00
+				     00 00 00
+				  39 01 00 00 00 00 02 BD 01
+				  39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA
+				     AA AA AA AA AA AA AA AA AA AA AA AA AA AA
+				     AA AA AA
+				  39 01 00 00 00 00 02 BD 02
+				  39 01 00 00 00 00 0D D8 AF FF FA AA BA AA AA
+				     FF FA AA BA AA
+				  39 01 00 00 00 00 02 BD 03
+				  39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA
+				     AA AA AA AA AA AA AA AA AA AA AA AA AA AA
+				     AA AA AA
+				  39 01 00 00 00 00 02 BD 00
+				  39 01 00 00 00 00 18 E7 0E 0E 1E 6A 1D 6A 00
+				     32 02 02 00 00 02 02 02 05 14 14 32 B9 23
+				     B9 08
+				  39 01 00 00 00 00 02 BD 01
+				  39 01 00 00 00 00 0A E7 02 00 98 01 9A 0D A8
+				     0E 01
+				  39 01 00 00 00 00 02 BD 02
+				  39 01 00 00 00 00 1E E7 00 00 08 00 01 00 00
+				     00 00 00 00 00 00 00 00 00 00 00 00 00 00
+				     00 04 00 00 00 00 02 00
+				  39 01 00 00 00 00 02 BD 00
+				  39 01 00 00 00 00 02 C1 01
+				  39 01 00 00 00 00 02 BD 01
+				  39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+				     C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+				     6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+				     1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+				     C6 B8 9C 37 43 3D E5 00
+				  39 01 00 00 00 00 02 BD 02
+				  39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+				     C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+				     6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+				     1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+				     C6 B8 9C 37 43 3D E5 00
+				  39 01 00 00 00 00 02 BD 03
+				  39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+				     C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+				     6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+				     1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+				     C6 B8 9C 37 43 3D E5 00
+				  39 01 00 00 00 00 02 BD 00
+				  39 01 00 00 00 00 02 E9 C3
+				  39 01 00 00 00 00 03 CB 92 01
+				  39 01 00 00 00 00 02 E9 3F
+				  39 01 00 00 00 00 07 C7 70 00 04 E0 33 00
+				  39 01 00 00 00 00 03 51 0F FF
+				  39 01 00 00 00 00 02 53 24
+				  39 01 00 00 00 00 02 55 00
+				  15 01 00 00 00 00 02 35 00
+				  05 01 00 00 96 00 02 11 00
+				  05 01 00 00 32 00 02 29 00];
+				qcom,mdss-dsi-off-command = [
+				  05 01 00 00 32 00 02 28 00
+				  05 01 00 00 96 00 02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-hx8394d-720p-video.dtsi

@@ -0,0 +1,99 @@
+/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_hx8394d_720_vid: qcom,mdss_dsi_hx8394d_720p_video {
+		qcom,mdss-dsi-panel-name = "hx8394d 720p video mode dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-panel-framerate = <60>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <720>;
+		qcom,mdss-dsi-panel-height = <1280>;
+		qcom,mdss-dsi-h-front-porch = <52>;
+		qcom,mdss-dsi-h-back-porch = <100>;
+		qcom,mdss-dsi-h-pulse-width = <24>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <20>;
+		qcom,mdss-dsi-v-front-porch = <8>;
+		qcom,mdss-dsi-v-pulse-width = <4>;
+		qcom,mdss-dsi-h-left-border = <0>;
+		qcom,mdss-dsi-h-right-border = <0>;
+		qcom,mdss-dsi-v-top-border = <0>;
+		qcom,mdss-dsi-v-bottom-border = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-on-command = [
+			39 01 00 00 00 00 04 b9 ff 83 94
+			39 01 00 00 00 00 03 ba 33 83
+			39 01 00 00 00 00 10 b1 6c 12 12
+				37 04 11 f1 80 ec 94 23 80 c0
+				d2 18
+			39 01 00 00 00 00 0c b2 00 64 0e
+				0d 32 23 08 08 1c 4d 00
+			39 01 00 00 00 00 0d b4 00 ff 03
+				50 03 50 03 50 01 6a 01 6a
+			39 01 00 00 00 00 02 bc 07
+			39 01 00 00 00 00 04 bf 41 0e 01
+			39 01 00 00 00 00 1f d3 00 07 00
+				00 00 10 00 32 10 05 00 00 32
+				10 00 00 00 32 10 00 00 00 36
+				03 09 09 37 00 00 37
+			39 01 00 00 00 00 2d d5 02 03 00
+				01 06 07 04 05 20 21 22 23 18
+				18 18 18 18 18 18 18 18 18 18
+				18 18 18 18 18 18 18 18 18 18
+				18 18 18 18 18 24 25 18 18 19
+				19
+			39 01 00 00 00 00 2d d6 05 04 07
+				06 01 00 03 02 23 22 21 20 18
+				18 18 18 18 18 58 58 18 18 18
+				18 18 18 18 18 18 18 18 18 18
+				18 18 18 18 18 25 24 19 19 18
+				18
+			39 01 00 00 00 00 02 cc 09
+			39 01 00 00 00 00 03 c0 30 14
+			39 01 00 00 00 00 05 c7 00 c0 40 c0
+			39 01 00 00 00 00 03 b6 43 43
+			05 01 00 00 c8 00 02 11 00
+			05 01 00 00 0a 00 02 29 00
+			];
+		qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00
+				05 01 00 00 00 00 02 10 00];
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-h-sync-pulse = <1>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-panel-timings = [
+			79 1a 12 00 3e 42
+			16 1e 15 03 04 00
+			];
+		qcom,mdss-dsi-t-clk-post = <0x04>;
+		qcom,mdss-dsi-t-clk-pre = <0x1b>;
+		qcom,mdss-dsi-bl-min-level = <1>;
+		qcom,mdss-dsi-bl-max-level = <4095>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+		qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+		qcom,mdss-pan-physical-width-dimension = <59>;
+		qcom,mdss-pan-physical-height-dimension = <104>;
+
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-hx8399c-fhd-plus-video.dtsi

@@ -0,0 +1,132 @@
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_hx8399c_truly_vid: qcom,mdss_dsi_hx8399_truly_fhd_video {
+		qcom,mdss-dsi-panel-name =
+			"hx8399c video mode dsi truly panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-panel-framerate = <60>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <1080>;
+		qcom,mdss-dsi-panel-height = <2160>;
+		qcom,mdss-dsi-h-front-porch = <42>;
+		qcom,mdss-dsi-h-back-porch = <42>;
+		qcom,mdss-dsi-h-pulse-width = <10>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <15>;
+		qcom,mdss-dsi-v-front-porch = <10>;
+		qcom,mdss-dsi-v-pulse-width = <3>;
+		qcom,mdss-dsi-h-left-border = <0>;
+		qcom,mdss-dsi-h-right-border = <0>;
+		qcom,mdss-dsi-v-top-border = <0>;
+		qcom,mdss-dsi-v-bottom-border = <0>;
+		qcom,mdss-pan-physical-width-dimension = <65>;
+		qcom,mdss-pan-physical-height-dimension = <129>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-on-command = [
+			39 01 00 00 00 00 04
+				b9 ff 83 99
+			39 01 00 00 00 00 02
+				d2 88
+			39 01 00 00 00 00 0c
+				b1 02 04 72 92 01
+				32 aa 11 11 52 57
+			39 01 00 00 00 00 10
+				b2 00 80 80 cc 05 07 5a
+				11 10 10 00 1e 70 03 d4
+			39 01 00 00 00 00 2d
+				b4 00 ff 59 59 01 ab 00
+				00 09 00 03 05 00 28 03
+				0b 0d 21 03 02 00 0c a3
+				80 59 59 02 ab 00 00 09
+				00 03 05 00 28 03 0b 0d
+				02 00 0c a3 01
+			39 01 00 00 05 00 22
+				d3 00 0c 03 03 00 00 10
+				10 00 00 03 00 03 00 08
+				78 08 78 00 00 00 00 00
+				24 02 05 05 03 00 00 00
+				05 40
+			39 01 00 00 05 00 21
+				d5 20 20 19 19 18 18 02
+				03 00 01 24 24 18 18 18
+				18 24 24 00 00 00 00 00
+				00 00 00 2f 2f 30 30 31
+				31
+			39 01 00 00 05 00 21
+				d6 24 24 18 18 19 19 01
+				00 03 02 24 24 18 18 18
+				18 20 20 40 40 40 40 40
+				40 40 40 2f 2f 30 30 31
+				31
+			39 01 00 00 00 00 02
+				bd 00
+			39 01 00 00 00 00 11
+				d8 aa aa aa aa aa aa aa
+				aa aa ba aa aa aa ba aa
+				aa
+			39 01 00 00 00 00 02
+				bd 01
+			39 01 00 00 00 00 11
+				d8 00 00 00 00 00 00 00
+				00 82 ea aa aa 82 ea aa
+				aa
+			39 01 00 00 00 00 02
+				bd 02
+			39 01 00 00 00 00 09
+				d8 ff ff c0 3f ff ff c0
+				3f
+			39 01 00 00 00 00 02
+				bd 00
+			39 01 00 00 05 00 37
+				e0 01 21 31 2d 66 6f 7b
+				75 7a 81 86 89 8c 90 95
+				97 9a a1 a2 aa 9e ad b0
+				5b 57 63 7a 01 21 31 2d
+				66 6f 7b 75 7a 81 86 89
+				8c 90 95 97 9a a1 a2 aa
+				9e ad b0 5b 57 63 7a
+			39 01 00 00 00 00 03
+				b6 7e 7e
+			39 01 00 00 00 00 02
+				cc 08
+			05 01 00 00 96 00 02 11 00
+			05 01 00 00 32 00 02 29 00];
+		qcom,mdss-dsi-off-command = [
+			05 01 00 00 32 00 02 28 00
+			05 01 00 00 96 00 02 10 00];
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-t-clk-post = <0x0e>;
+		qcom,mdss-dsi-t-clk-pre = <0x31>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-lp11-init;
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+	};
+};
+

arch/arm64/boot/dts/19721/dsi-panel-lgd-incell-sw49106-fhd-video.dtsi

@@ -0,0 +1,115 @@
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_lgd_incell_sw49106_fhd_video:
+		qcom,mdss_dsi_lgd_incell_sw49106_fhd_video {
+			qcom,mdss-dsi-panel-name =
+				"lgd incell sw49106 fhd video";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-panel-framerate = <60>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <1080>;
+		qcom,mdss-dsi-panel-height = <2160>;
+		qcom,mdss-dsi-h-front-porch = <8>;
+		qcom,mdss-dsi-h-back-porch = <8>;
+		qcom,mdss-dsi-h-pulse-width = <4>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <92>;
+		qcom,mdss-dsi-v-front-porch = <170>;
+		qcom,mdss-dsi-v-pulse-width = <1>;
+		qcom,mdss-dsi-h-left-border = <0>;
+		qcom,mdss-dsi-h-right-border = <0>;
+		qcom,mdss-dsi-v-top-border = <0>;
+		qcom,mdss-dsi-v-bottom-border = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-panel-timings = [F8 3C 28 00 6E 72 2E
+				40 30 03 04 00];
+		qcom,mdss-dsi-t-clk-post = <0x02>;
+		qcom,mdss-dsi-t-clk-pre = <0x2D>;
+		qcom,mdss-dsi-bl-min-level = <1>;
+		qcom,mdss-dsi-bl-max-level = <4095>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-on-command = [05 01 00 00 0B 00 02 35 00
+			15 01 00 00 00 00 02 36 00
+			15 01 00 00 00 00 02 51 FF
+			15 01 00 00 00 00 02 53 24
+			15 01 00 00 00 00 02 55 80
+			39 01 00 00 00 00 02 B0 AC
+			39 01 00 00 00 00 06 B1 46 00 80 14 85
+			39 01 00 00 00 00 08 B3 05 08 14 00 1C 00 02
+			39 01 00 00 00 00 10 B4 83 08 00 04 04 04 04 00
+				00 00 00 00 00 00 00
+			39 01 00 00 00 00 13 B5 03 1E 0B 02 29 00 00 00
+				00 04 00 24 00 10 10 10 10 00
+			39 01 00 00 00 00 0A B6 00 72 39 13 08 67 00 60 46
+			39 01 00 00 00 00 05 B7 00 50 37 04
+			39 01 00 00 00 00 0C B8 70 38 14 ED 08 04 00 01
+				0A A0 00
+			39 01 00 00 00 00 06 C0 8A 8F 18 C1 12
+			39 01 00 00 00 00 07 C1 01 00 30 C2 C7 0F
+			39 01 00 00 00 00 03 C2 2A 00
+			39 01 00 00 00 00 07 C3 05 0E 0E 50 88 09
+			39 01 00 00 00 00 04 C4 A2 E8 F4
+			39 01 00 00 00 00 05 C5 C2 2A 4E 08
+			39 01 00 00 00 00 03 C6 15 01
+			39 01 00 00 00 00 07 CA 00 00 03 84 55 F5
+			39 01 00 00 00 00 03 CB 3F A0
+			39 01 00 00 00 00 09 CC F0 03 10 55 11 FC 34 34
+			39 01 00 00 00 00 07 CD 11 50 50 90 00 F3
+			39 01 00 00 00 00 07 CE A0 28 28 34 00 AB
+			39 01 00 00 00 00 10 D0 10 1B 22 2A 35 42 4A 53 4D
+				44 34 23 10 03 81
+			39 01 00 00 00 00 10 D1 09 15 1C 25 31 3F 47 52 4F
+				45 34 22 0E 01 83
+			39 01 00 00 00 00 10 D2 10 1B 22 29 34 41 49 52 4E
+				44 34 23 10 03 81
+			39 01 00 00 00 00 10 D3 09 15 1C 24 30 3E 46 51 50
+				45 34 22 0E 01 83
+			39 01 00 00 00 00 10 D4 10 1B 22 2A 35 42 4A 53 4D
+				44 34 23 10 03 81
+			39 01 00 00 00 00 10 D5 09 15 1C 25 31 3F 47 52 4F
+				45 34 22 0E 01 83
+			39 01 00 00 00 00 0D E5 24 23 11 10 00 0A 08 06 04
+				11 0E 23
+			39 01 00 00 00 00 0D E6 24 23 11 10 01 0B 09 07 05
+				11 0E 23
+			39 01 00 00 00 00 07 E7 15 16 17 18 19 1A
+			39 01 00 00 00 00 07 E8 1B 1C 1D 1E 1F 20
+			39 01 00 00 00 00 05 ED 00 01 53 0C
+			39 01 00 00 00 00 03 F0 B2 00
+			39 01 00 00 00 00 05 F2 01 00 17 00
+			39 01 00 00 64 00 07 F3 00 50 90 C9 00 01
+			05 01 00 00 78 00 02 11 00
+			05 01 00 00 05 00 02 29 00];
+		qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00
+			05 01 00 00 64 00 02 10 00];
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+		qcom,mdss-dsi-reset-sequence = <1 400>, <0 400>, <1 400>;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-dsi-post-init-delay = <1>;
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi

@@ -0,0 +1,105 @@
+/* Copyright (c) 2015-2017, 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_dual_nt35597_cmd: qcom,mdss_dsi_nt35597_wqxga_cmd{
+		qcom,mdss-dsi-panel-name =
+			"Dual nt35597 cmd mode dsi panel without DSC";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-panel-framerate = <60>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <720>;
+		qcom,mdss-dsi-panel-height = <2560>;
+		qcom,mdss-dsi-h-front-porch = <100>;
+		qcom,mdss-dsi-h-back-porch = <32>;
+		qcom,mdss-dsi-h-pulse-width = <16>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <7>;
+		qcom,mdss-dsi-v-front-porch = <8>;
+		qcom,mdss-dsi-v-pulse-width = <1>;
+		qcom,mdss-dsi-h-left-border = <0>;
+		qcom,mdss-dsi-h-right-border = <0>;
+		qcom,mdss-dsi-v-top-border = <0>;
+		qcom,mdss-dsi-v-bottom-border = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-panel-timings = [cd 32 22 00 60 64 26 34 29 03
+									04 00];
+		qcom,adjust-timer-wakeup-ms = <1>;
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-pan-physical-width-dimension = <74>;
+		qcom,mdss-pan-physical-height-dimension = <131>;
+		qcom,mdss-dsi-t-clk-post = <0x0d>;
+		qcom,mdss-dsi-t-clk-pre = <0x2d>;
+		qcom,mdss-dsi-bl-max-level = <4095>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,ulps-enabled;
+		qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 10
+			15 01 00 00 10 00 02 fb 01
+			15 01 00 00 10 00 02 ba 03
+			15 01 00 00 10 00 02 e5 01
+			15 01 00 00 10 00 02 35 00
+			15 01 00 00 10 00 02 bb 10
+			15 01 00 00 10 00 02 b0 03
+			15 01 00 00 10 00 02 ff e0
+			15 01 00 00 10 00 02 fb 01
+			15 01 00 00 10 00 02 6b 3d
+			15 01 00 00 10 00 02 6c 3d
+			15 01 00 00 10 00 02 6d 3d
+			15 01 00 00 10 00 02 6e 3d
+			15 01 00 00 10 00 02 6f 3d
+			15 01 00 00 10 00 02 35 02
+			15 01 00 00 10 00 02 36 72
+			15 01 00 00 10 00 02 37 10
+			15 01 00 00 10 00 02 08 c0
+			15 01 00 00 10 00 02 ff 24
+			15 01 00 00 10 00 02 fb 01
+			15 01 00 00 10 00 02 c6 06
+			15 01 00 00 10 00 02 ff 10
+			05 01 00 00 a0 00 02 11 00
+			05 01 00 00 a0 00 02 29 00];
+
+		qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00
+			05 01 00 00 3c 00 02 10 00];
+
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+		qcom,config-select = <&dsi_dual_nt35597_cmd_config0>;
+
+		dsi_dual_nt35597_cmd_config0: config0 {
+			qcom,split-mode = "dualctl-split";
+		};
+
+		dsi_dual_nt35597_cmd_config1: config1 {
+			qcom,split-mode = "pingpong-split";
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt35597-dualmipi-wqxga-video.dtsi

@@ -0,0 +1,96 @@
+/* Copyright (c) 2015-2017, 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_dual_nt35597_video: qcom,mdss_dsi_nt35597_wqxga_video {
+		qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi
+			panel without DSC";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-panel-framerate = <60>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <720>;
+		qcom,mdss-dsi-panel-height = <2560>;
+		qcom,mdss-dsi-h-front-porch = <100>;
+		qcom,mdss-dsi-h-back-porch = <32>;
+		qcom,mdss-dsi-h-pulse-width = <16>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <7>;
+		qcom,mdss-dsi-v-front-porch = <8>;
+		qcom,mdss-dsi-v-pulse-width = <1>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0x3ff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+			17000 15500 30000 8000 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+		qcom,mdss-dsi-panel-blackness-level = <3230>;
+		qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10
+			15 01 00 00 00 00 02 fb 01
+			15 01 00 00 00 00 02 ba 03
+			15 01 00 00 00 00 02 e5 01
+			15 01 00 00 00 00 02 35 00
+			15 01 00 00 00 00 02 bb 03
+			15 01 00 00 00 00 02 b0 03
+			39 01 00 00 00 00 06 3b 03 08 08 64 9a
+			15 01 00 00 00 00 02 ff e0
+			15 01 00 00 00 00 02 fb 01
+			15 01 00 00 00 00 02 6b 3d
+			15 01 00 00 00 00 02 6c 3d
+			15 01 00 00 00 00 02 6d 3d
+			15 01 00 00 00 00 02 6e 3d
+			15 01 00 00 00 00 02 6f 3d
+			15 01 00 00 00 00 02 35 02
+			15 01 00 00 00 00 02 36 72
+			15 01 00 00 00 00 02 37 10
+			15 01 00 00 00 00 02 08 c0
+			15 01 00 00 00 00 02 ff 10
+			05 01 00 00 78 00 02 11 00
+			05 01 00 00 32 00 02 29 00];
+		qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00
+				 05 01 00 00 3c 00 02 10 00];
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-panel-timings = [e2 36 24 00 66 6a 28 38 2a
+			03 04 00];
+		qcom,mdss-dsi-t-clk-post = <0x0d>;
+		qcom,mdss-dsi-t-clk-pre = <0x2d>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-pan-physical-width-dimension = <74>;
+		qcom,mdss-pan-physical-height-dimension = <131>;
+		qcom,mdss-dsi-min-refresh-rate = <55>;
+		qcom,mdss-dsi-max-refresh-rate = <60>;
+		qcom,mdss-dsi-pan-enable-dynamic-fps;
+		qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+
+		qcom,config-select = <&dsi_dual_nt35597_video_config0>;
+
+		dsi_dual_nt35597_video_config0: config0 {
+			qcom,split-mode = "dualctl-split";
+		};
+
+		dsi_dual_nt35597_video_config1: config1 {
+			qcom,split-mode = "pingpong-split";
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi

@@ -0,0 +1,258 @@
+/* Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_nt35597_truly_dsc_cmd: qcom,mdss_dsi_nt35597_dsc_cmd_truly {
+		qcom,mdss-dsi-panel-name =
+			"nt35597 cmd mode dsi truly panel with DSC";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-pan-physical-width-dimension = <74>;
+		qcom,mdss-pan-physical-height-dimension = <131>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+			17000 15500 30000 8000 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+		qcom,mdss-dsi-panel-blackness-level = <3230>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-bl-max-level = <4095>;
+		qcom,adjust-timer-wakeup-ms = <1>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-panel-width = <1440>;
+				qcom,mdss-dsi-panel-height = <2560>;
+				qcom,mdss-dsi-h-front-porch = <100>;
+				qcom,mdss-dsi-h-back-porch = <32>;
+				qcom,mdss-dsi-h-pulse-width = <16>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <8>;
+				qcom,mdss-dsi-v-front-porch = <10>;
+				qcom,mdss-dsi-v-pulse-width = <2>;
+				qcom,mdss-dsi-h-left-border = <0>;
+				qcom,mdss-dsi-h-right-border = <0>;
+				qcom,mdss-dsi-v-top-border = <0>;
+				qcom,mdss-dsi-v-bottom-border = <0>;
+				qcom,mdss-dsi-panel-jitter = <0x1 0x1>;
+				qcom,mdss-dsi-on-command = [
+					/* CMD2_P0 */
+					15 01 00 00 00 00 02 ff 20
+					15 01 00 00 00 00 02 fb 01
+					15 01 00 00 00 00 02 00 01
+					15 01 00 00 00 00 02 01 55
+					15 01 00 00 00 00 02 02 45
+					15 01 00 00 00 00 02 05 40
+					15 01 00 00 00 00 02 06 19
+					15 01 00 00 00 00 02 07 1e
+					15 01 00 00 00 00 02 0b 73
+					15 01 00 00 00 00 02 0c 73
+					15 01 00 00 00 00 02 0e b0
+					15 01 00 00 00 00 02 0f ae
+					15 01 00 00 00 00 02 11 b8
+					15 01 00 00 00 00 02 13 00
+					15 01 00 00 00 00 02 58 80
+					15 01 00 00 00 00 02 59 01
+					15 01 00 00 00 00 02 5a 00
+					15 01 00 00 00 00 02 5b 01
+					15 01 00 00 00 00 02 5c 80
+					15 01 00 00 00 00 02 5d 81
+					15 01 00 00 00 00 02 5e 00
+					15 01 00 00 00 00 02 5f 01
+					15 01 00 00 00 00 02 72 31
+					15 01 00 00 00 00 02 68 03
+					/* CMD2_P4 */
+					15 01 00 00 00 00 02 ff 24
+					15 01 00 00 00 00 02 fb 01
+					15 01 00 00 00 00 02 00 1c
+					15 01 00 00 00 00 02 01 0b
+					15 01 00 00 00 00 02 02 0c
+					15 01 00 00 00 00 02 03 01
+					15 01 00 00 00 00 02 04 0f
+					15 01 00 00 00 00 02 05 10
+					15 01 00 00 00 00 02 06 10
+					15 01 00 00 00 00 02 07 10
+					15 01 00 00 00 00 02 08 89
+					15 01 00 00 00 00 02 09 8a
+					15 01 00 00 00 00 02 0a 13
+					15 01 00 00 00 00 02 0b 13
+					15 01 00 00 00 00 02 0c 15
+					15 01 00 00 00 00 02 0d 15
+					15 01 00 00 00 00 02 0e 17
+					15 01 00 00 00 00 02 0f 17
+					15 01 00 00 00 00 02 10 1c
+					15 01 00 00 00 00 02 11 0b
+					15 01 00 00 00 00 02 12 0c
+					15 01 00 00 00 00 02 13 01
+					15 01 00 00 00 00 02 14 0f
+					15 01 00 00 00 00 02 15 10
+					15 01 00 00 00 00 02 16 10
+					15 01 00 00 00 00 02 17 10
+					15 01 00 00 00 00 02 18 89
+					15 01 00 00 00 00 02 19 8a
+					15 01 00 00 00 00 02 1a 13
+					15 01 00 00 00 00 02 1b 13
+					15 01 00 00 00 00 02 1c 15
+					15 01 00 00 00 00 02 1d 15
+					15 01 00 00 00 00 02 1e 17
+					15 01 00 00 00 00 02 1f 17
+					/* STV */
+					15 01 00 00 00 00 02 20 40
+					15 01 00 00 00 00 02 21 01
+					15 01 00 00 00 00 02 22 00
+					15 01 00 00 00 00 02 23 40
+					15 01 00 00 00 00 02 24 40
+					15 01 00 00 00 00 02 25 6d
+					15 01 00 00 00 00 02 26 40
+					15 01 00 00 00 00 02 27 40
+					/* Vend */
+					15 01 00 00 00 00 02 e0 00
+					15 01 00 00 00 00 02 dc 21
+					15 01 00 00 00 00 02 dd 22
+					15 01 00 00 00 00 02 de 07
+					15 01 00 00 00 00 02 df 07
+					15 01 00 00 00 00 02 e3 6D
+					15 01 00 00 00 00 02 e1 07
+					15 01 00 00 00 00 02 e2 07
+					/* UD */
+					15 01 00 00 00 00 02 29 d8
+					15 01 00 00 00 00 02 2a 2a
+					/* CLK */
+					15 01 00 00 00 00 02 4b 03
+					15 01 00 00 00 00 02 4c 11
+					15 01 00 00 00 00 02 4d 10
+					15 01 00 00 00 00 02 4e 01
+					15 01 00 00 00 00 02 4f 01
+					15 01 00 00 00 00 02 50 10
+					15 01 00 00 00 00 02 51 00
+					15 01 00 00 00 00 02 52 80
+					15 01 00 00 00 00 02 53 00
+					15 01 00 00 00 00 02 56 00
+					15 01 00 00 00 00 02 54 07
+					15 01 00 00 00 00 02 58 07
+					15 01 00 00 00 00 02 55 25
+					/* Reset XDONB */
+					15 01 00 00 00 00 02 5b 43
+					15 01 00 00 00 00 02 5c 00
+					15 01 00 00 00 00 02 5f 73
+					15 01 00 00 00 00 02 60 73
+					15 01 00 00 00 00 02 63 22
+					15 01 00 00 00 00 02 64 00
+					15 01 00 00 00 00 02 67 08
+					15 01 00 00 00 00 02 68 04
+					/* Resolution:1440x2560*/
+					15 01 00 00 00 00 02 72 02
+					/* mux */
+					15 01 00 00 00 00 02 7a 80
+					15 01 00 00 00 00 02 7b 91
+					15 01 00 00 00 00 02 7c D8
+					15 01 00 00 00 00 02 7d 60
+					15 01 00 00 00 00 02 7f 15
+					15 01 00 00 00 00 02 75 15
+					/* ABOFF */
+					15 01 00 00 00 00 02 b3 C0
+					15 01 00 00 00 00 02 b4 00
+					15 01 00 00 00 00 02 b5 00
+					/* Source EQ */
+					15 01 00 00 00 00 02 78 00
+					15 01 00 00 00 00 02 79 00
+					15 01 00 00 00 00 02 80 00
+					15 01 00 00 00 00 02 83 00
+					/* FP BP */
+					15 01 00 00 00 00 02 93 0a
+					15 01 00 00 00 00 02 94 0a
+					/* Inversion Type */
+					15 01 00 00 00 00 02 8a 00
+					15 01 00 00 00 00 02 9b ff
+					/* IMGSWAP =1 @PortSwap=1 */
+					15 01 00 00 00 00 02 9d b0
+					15 01 00 00 00 00 02 9f 63
+					15 01 00 00 00 00 02 98 10
+					/* FRM */
+					15 01 00 00 00 00 02 ec 00
+					/* CMD1 */
+					15 01 00 00 00 00 02 ff 10
+					/* VESA DSC PPS settings
+					 *  (1440x2560 slide 16H)
+					 */
+					39 01 00 00 00 00 11 c1 09
+					20 00 10 02 00 02 68 01 bb
+					00 0a 06 67 04 c5
+
+					39 01 00 00 00 00 03 c2 10 f0
+					/* C0h = 0x0(2 Port SDC)
+					 * 0x01(1 PortA FBC)
+					 * 0x02(MTK) 0x03(1 PortA VESA)
+					 */
+					15 01 00 00 00 00 02 c0 03
+					/* VBP+VSA=,VFP = 10H */
+					15 01 00 00 00 00 04 3b 03 0a 0a
+					/* FTE on */
+					15 01 00 00 00 00 02 35 00
+					/* EN_BK =1(auto black) */
+					15 01 00 00 00 00 02 e5 01
+					/* CMD mode(10) VDO mode(03) */
+					15 01 00 00 00 00 02 bb 10
+					/* Non Reload MTP */
+					15 01 00 00 00 00 02 fb 01
+					/* SlpOut + DispOn */
+					05 01 00 00 78 00 02 11 00
+					05 01 00 00 78 00 02 29 00
+					];
+				qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+					02 28 00 05 01 00 00 78 00 02 10 00];
+
+				qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,compression-mode = "dsc";
+				qcom,mdss-dsc-slice-height = <16>;
+				qcom,mdss-dsc-slice-width = <720>;
+				qcom,mdss-dsc-slice-per-pkt = <2>;
+				qcom,mdss-dsc-bit-per-component = <8>;
+				qcom,mdss-dsc-bit-per-pixel = <8>;
+				qcom,mdss-dsc-block-prediction-enable;
+			};
+		};
+		dsi_nt35597_truly_dsc_cmd_config2: config2 {
+			qcom,lm-split = <720 720>;
+			qcom,mdss-dsc-encoders = <2>; /* DSC Merge */
+			qcom,mdss-dsc-slice-height = <16>;
+			qcom,mdss-dsc-slice-width = <720>;
+			qcom,mdss-dsc-slice-per-pkt = <2>;
+
+			qcom,mdss-dsc-bit-per-component = <8>;
+			qcom,mdss-dsc-bit-per-pixel = <8>;
+			qcom,mdss-dsc-block-prediction-enable;
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi

@@ -0,0 +1,244 @@
+/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_nt35597_truly_dsc_video: qcom,mdss_dsi_nt35597_dsc_video_truly {
+		qcom,mdss-dsi-panel-name =
+			"nt35597 video mode dsi truly panel with DSC";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+			17000 15500 30000 8000 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+		qcom,mdss-dsi-panel-blackness-level = <3230>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-pan-physical-width-dimension = <74>;
+		qcom,mdss-pan-physical-height-dimension = <131>;
+		qcom,mdss-dsi-dma-schedule-line = <5>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1440>;
+				qcom,mdss-dsi-panel-height = <2560>;
+				qcom,mdss-dsi-h-front-porch = <100>;
+				qcom,mdss-dsi-h-back-porch = <32>;
+				qcom,mdss-dsi-h-pulse-width = <16>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <8>;
+				qcom,mdss-dsi-v-front-porch = <10>;
+				qcom,mdss-dsi-v-pulse-width = <2>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+					/* CMD2_P0 */
+					15 01 00 00 00 00 02 ff 20
+					15 01 00 00 00 00 02 fb 01
+					15 01 00 00 00 00 02 00 01
+					15 01 00 00 00 00 02 01 55
+					15 01 00 00 00 00 02 02 45
+					15 01 00 00 00 00 02 05 40
+					15 01 00 00 00 00 02 06 19
+					15 01 00 00 00 00 02 07 1e
+					15 01 00 00 00 00 02 0b 73
+					15 01 00 00 00 00 02 0c 73
+					15 01 00 00 00 00 02 0e b0
+					15 01 00 00 00 00 02 0f aE
+					15 01 00 00 00 00 02 11 b8
+					15 01 00 00 00 00 02 13 00
+					15 01 00 00 00 00 02 58 80
+					15 01 00 00 00 00 02 59 01
+					15 01 00 00 00 00 02 5a 00
+					15 01 00 00 00 00 02 5b 01
+					15 01 00 00 00 00 02 5c 80
+					15 01 00 00 00 00 02 5d 81
+					15 01 00 00 00 00 02 5e 00
+					15 01 00 00 00 00 02 5f 01
+					15 01 00 00 00 00 02 72 31
+					15 01 00 00 00 00 02 68 03
+					/* CMD2_P4 */
+					15 01 00 00 00 00 02 ff 24
+					15 01 00 00 00 00 02 fb 01
+					15 01 00 00 00 00 02 00 1c
+					15 01 00 00 00 00 02 01 0b
+					15 01 00 00 00 00 02 02 0c
+					15 01 00 00 00 00 02 03 01
+					15 01 00 00 00 00 02 04 0f
+					15 01 00 00 00 00 02 05 10
+					15 01 00 00 00 00 02 06 10
+					15 01 00 00 00 00 02 07 10
+					15 01 00 00 00 00 02 08 89
+					15 01 00 00 00 00 02 09 8a
+					15 01 00 00 00 00 02 0a 13
+					15 01 00 00 00 00 02 0b 13
+					15 01 00 00 00 00 02 0c 15
+					15 01 00 00 00 00 02 0d 15
+					15 01 00 00 00 00 02 0e 17
+					15 01 00 00 00 00 02 0f 17
+					15 01 00 00 00 00 02 10 1c
+					15 01 00 00 00 00 02 11 0b
+					15 01 00 00 00 00 02 12 0c
+					15 01 00 00 00 00 02 13 01
+					15 01 00 00 00 00 02 14 0f
+					15 01 00 00 00 00 02 15 10
+					15 01 00 00 00 00 02 16 10
+					15 01 00 00 00 00 02 17 10
+					15 01 00 00 00 00 02 18 89
+					15 01 00 00 00 00 02 19 8a
+					15 01 00 00 00 00 02 1a 13
+					15 01 00 00 00 00 02 1b 13
+					15 01 00 00 00 00 02 1c 15
+					15 01 00 00 00 00 02 1d 15
+					15 01 00 00 00 00 02 1e 17
+					15 01 00 00 00 00 02 1f 17
+					/* STV */
+					15 01 00 00 00 00 02 20 40
+					15 01 00 00 00 00 02 21 01
+					15 01 00 00 00 00 02 22 00
+					15 01 00 00 00 00 02 23 40
+					15 01 00 00 00 00 02 24 40
+					15 01 00 00 00 00 02 25 6d
+					15 01 00 00 00 00 02 26 40
+					15 01 00 00 00 00 02 27 40
+					/* Vend */
+					15 01 00 00 00 00 02 e0 00
+					15 01 00 00 00 00 02 dc 21
+					15 01 00 00 00 00 02 dd 22
+					15 01 00 00 00 00 02 de 07
+					15 01 00 00 00 00 02 df 07
+					15 01 00 00 00 00 02 e3 6d
+					15 01 00 00 00 00 02 e1 07
+					15 01 00 00 00 00 02 e2 07
+					/* UD */
+					15 01 00 00 00 00 02 29 d8
+					15 01 00 00 00 00 02 2a 2a
+					/* CLK */
+					15 01 00 00 00 00 02 4b 03
+					15 01 00 00 00 00 02 4c 11
+					15 01 00 00 00 00 02 4d 10
+					15 01 00 00 00 00 02 4e 01
+					15 01 00 00 00 00 02 4f 01
+					15 01 00 00 00 00 02 50 10
+					15 01 00 00 00 00 02 51 00
+					15 01 00 00 00 00 02 52 80
+					15 01 00 00 00 00 02 53 00
+					15 01 00 00 00 00 02 56 00
+					15 01 00 00 00 00 02 54 07
+					15 01 00 00 00 00 02 58 07
+					15 01 00 00 00 00 02 55 25
+					/* Reset XDONB */
+					15 01 00 00 00 00 02 5b 43
+					15 01 00 00 00 00 02 5c 00
+					15 01 00 00 00 00 02 5f 73
+					15 01 00 00 00 00 02 60 73
+					15 01 00 00 00 00 02 63 22
+					15 01 00 00 00 00 02 64 00
+					15 01 00 00 00 00 02 67 08
+					15 01 00 00 00 00 02 68 04
+					/* Resolution:1440x2560*/
+					15 01 00 00 00 00 02 72 02
+					/* mux */
+					15 01 00 00 00 00 02 7a 80
+					15 01 00 00 00 00 02 7b 91
+					15 01 00 00 00 00 02 7c d8
+					15 01 00 00 00 00 02 7d 60
+					15 01 00 00 00 00 02 7f 15
+					15 01 00 00 00 00 02 75 15
+					/* ABOFF */
+					15 01 00 00 00 00 02 b3 c0
+					15 01 00 00 00 00 02 b4 00
+					15 01 00 00 00 00 02 b5 00
+					/* Source EQ */
+					15 01 00 00 00 00 02 78 00
+					15 01 00 00 00 00 02 79 00
+					15 01 00 00 00 00 02 80 00
+					15 01 00 00 00 00 02 83 00
+					/* FP BP */
+					15 01 00 00 00 00 02 93 0a
+					15 01 00 00 00 00 02 94 0a
+					/* Inversion Type */
+					15 01 00 00 00 00 02 8a 00
+					15 01 00 00 00 00 02 9b ff
+					/* IMGSWAP =1 @PortSwap=1 */
+					15 01 00 00 00 00 02 9d b0
+					15 01 00 00 00 00 02 9f 63
+					15 01 00 00 00 00 02 98 10
+					/* FRM */
+					15 01 00 00 00 00 02 ec 00
+					/* CMD1 */
+					15 01 00 00 00 00 02 ff 10
+					/* VESA DSC PPS settings
+					 * (1440x2560 slide 16H)
+					 */
+					39 01 00 00 00 00 11 c1 09
+					20 00 10 02 00 02 68 01	bb
+					00 0a 06 67 04 c5
+
+					39 01 00 00 00 00 03 c2 10 f0
+					/* C0h = 0x00(2 Port SDC);
+					 * 0x01(1 PortA FBC);
+					 * 0x02(MTK); 0x03(1 PortA VESA)
+					 */
+					15 01 00 00 00 00 02 c0 03
+					/* VBP+VSA=,VFP = 10H */
+					39 01 00 00 00 00 04 3b 03 0a 0a
+					/* FTE on */
+					15 01 00 00 00 00 02 35 00
+					/* EN_BK =1(auto black) */
+					15 01 00 00 00 00 02 e5 01
+					/* CMD mode(10) VDO mode(03) */
+					15 01 00 00 00 00 02 bb 03
+					/* Non Reload MTP */
+					15 01 00 00 00 00 02 fb 01
+					/* SlpOut + DispOn */
+					05 01 00 00 78 00 02 11 00
+					05 01 00 00 78 00 02 29 00
+					];
+				qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+					02 28 00 05 01 00 00 78 00 02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,compression-mode = "dsc";
+				qcom,mdss-dsc-slice-height = <16>;
+				qcom,mdss-dsc-slice-width = <720>;
+				qcom,mdss-dsc-slice-per-pkt = <2>;
+				qcom,mdss-dsc-bit-per-component = <8>;
+				qcom,mdss-dsc-bit-per-pixel = <8>;
+				qcom,mdss-dsc-block-prediction-enable;
+			};
+		};
+		dsi_nt35597_truly_dsc_video_config2: config2 {
+			qcom,lm-split = <720 720>;
+			qcom,mdss-dsc-encoders = <2>; /* DSC Merge */
+			qcom,mdss-dsc-slice-height = <16>;
+			qcom,mdss-dsc-slice-width = <720>;
+			qcom,mdss-dsc-slice-per-pkt = <2>;
+
+			qcom,mdss-dsc-bit-per-component = <8>;
+			qcom,mdss-dsc-bit-per-pixel = <8>;
+			qcom,mdss-dsc-block-prediction-enable;
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi

@@ -0,0 +1,226 @@
+/* Copyright (c) 2016-2017, 2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_dual_nt35597_truly_cmd: qcom,mdss_dsi_nt35597_truly_wqxga_cmd{
+		qcom,mdss-dsi-panel-name =
+			"Dual nt35597 cmd mode dsi truly panel without DSC";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,adjust-timer-wakeup-ms = <1>;
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-pan-physical-width-dimension = <74>;
+		qcom,mdss-pan-physical-height-dimension = <131>;
+		qcom,mdss-dsi-bl-max-level = <4095>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+			17000 15500 30000 8000 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+		qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-panel-width = <720>;
+				qcom,mdss-dsi-panel-height = <2560>;
+				qcom,mdss-dsi-h-front-porch = <100>;
+				qcom,mdss-dsi-h-back-porch = <32>;
+				qcom,mdss-dsi-h-pulse-width = <16>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <7>;
+				qcom,mdss-dsi-v-front-porch = <8>;
+				qcom,mdss-dsi-v-pulse-width = <1>;
+				qcom,mdss-dsi-h-left-border = <0>;
+				qcom,mdss-dsi-h-right-border = <0>;
+				qcom,mdss-dsi-v-top-border = <0>;
+				qcom,mdss-dsi-v-bottom-border = <0>;
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,mdss-dsi-panel-jitter = <0x1 0x1>;
+				qcom,mdss-dsi-on-command = [
+					/* CMD2_P0 */
+					15 01 00 00 00 00 02 FF 20
+					15 01 00 00 00 00 02 fb 01
+					15 01 00 00 00 00 02 00 01
+					15 01 00 00 00 00 02 01 55
+					15 01 00 00 00 00 02 02 45
+					15 01 00 00 00 00 02 05 40
+					15 01 00 00 00 00 02 06 19
+					15 01 00 00 00 00 02 07 1E
+					15 01 00 00 00 00 02 0B 73
+					15 01 00 00 00 00 02 0C 73
+					15 01 00 00 00 00 02 0E B0
+					15 01 00 00 00 00 02 0F AE
+					15 01 00 00 00 00 02 11 B8
+					15 01 00 00 00 00 02 13 00
+					15 01 00 00 00 00 02 58 80
+					15 01 00 00 00 00 02 59 01
+					15 01 00 00 00 00 02 5A 00
+					15 01 00 00 00 00 02 5B 01
+					15 01 00 00 00 00 02 5C 80
+					15 01 00 00 00 00 02 5D 81
+					15 01 00 00 00 00 02 5E 00
+					15 01 00 00 00 00 02 5F 01
+					15 01 00 00 00 00 02 72 31
+					15 01 00 00 00 00 02 68 03
+					/* CMD2_P4 */
+					15 01 00 00 00 00 02 ff 24
+					15 01 00 00 00 00 02 fb 01
+					15 01 00 00 00 00 02 00 1C
+					15 01 00 00 00 00 02 01 0B
+					15 01 00 00 00 00 02 02 0C
+					15 01 00 00 00 00 02 03 01
+					15 01 00 00 00 00 02 04 0F
+					15 01 00 00 00 00 02 05 10
+					15 01 00 00 00 00 02 06 10
+					15 01 00 00 00 00 02 07 10
+					15 01 00 00 00 00 02 08 89
+					15 01 00 00 00 00 02 09 8A
+					15 01 00 00 00 00 02 0A 13
+					15 01 00 00 00 00 02 0B 13
+					15 01 00 00 00 00 02 0C 15
+					15 01 00 00 00 00 02 0D 15
+					15 01 00 00 00 00 02 0E 17
+					15 01 00 00 00 00 02 0F 17
+					15 01 00 00 00 00 02 10 1C
+					15 01 00 00 00 00 02 11 0B
+					15 01 00 00 00 00 02 12 0C
+					15 01 00 00 00 00 02 13 01
+					15 01 00 00 00 00 02 14 0F
+					15 01 00 00 00 00 02 15 10
+					15 01 00 00 00 00 02 16 10
+					15 01 00 00 00 00 02 17 10
+					15 01 00 00 00 00 02 18 89
+					15 01 00 00 00 00 02 19 8A
+					15 01 00 00 00 00 02 1A 13
+					15 01 00 00 00 00 02 1B 13
+					15 01 00 00 00 00 02 1C 15
+					15 01 00 00 00 00 02 1D 15
+					15 01 00 00 00 00 02 1E 17
+					15 01 00 00 00 00 02 1F 17
+					/* STV */
+					15 01 00 00 00 00 02 20 40
+					15 01 00 00 00 00 02 21 01
+					15 01 00 00 00 00 02 22 00
+					15 01 00 00 00 00 02 23 40
+					15 01 00 00 00 00 02 24 40
+					15 01 00 00 00 00 02 25 6D
+					15 01 00 00 00 00 02 26 40
+					15 01 00 00 00 00 02 27 40
+					/* Vend */
+					15 01 00 00 00 00 02 E0 00
+					15 01 00 00 00 00 02 DC 21
+					15 01 00 00 00 00 02 DD 22
+					15 01 00 00 00 00 02 DE 07
+					15 01 00 00 00 00 02 DF 07
+					15 01 00 00 00 00 02 E3 6D
+					15 01 00 00 00 00 02 E1 07
+					15 01 00 00 00 00 02 E2 07
+					/* UD */
+					15 01 00 00 00 00 02 29 D8
+					15 01 00 00 00 00 02 2A 2A
+					/* CLK */
+					15 01 00 00 00 00 02 4B 03
+					15 01 00 00 00 00 02 4C 11
+					15 01 00 00 00 00 02 4D 10
+					15 01 00 00 00 00 02 4E 01
+					15 01 00 00 00 00 02 4F 01
+					15 01 00 00 00 00 02 50 10
+					15 01 00 00 00 00 02 51 00
+					15 01 00 00 00 00 02 52 80
+					15 01 00 00 00 00 02 53 00
+					15 01 00 00 00 00 02 56 00
+					15 01 00 00 00 00 02 54 07
+					15 01 00 00 00 00 02 58 07
+					15 01 00 00 00 00 02 55 25
+					/* Reset XDONB */
+					15 01 00 00 00 00 02 5B 43
+					15 01 00 00 00 00 02 5C 00
+					15 01 00 00 00 00 02 5F 73
+					15 01 00 00 00 00 02 60 73
+					15 01 00 00 00 00 02 63 22
+					15 01 00 00 00 00 02 64 00
+					15 01 00 00 00 00 02 67 08
+					15 01 00 00 00 00 02 68 04
+					/* Resolution:1440x2560*/
+					15 01 00 00 00 00 02 72 02
+					/* mux */
+					15 01 00 00 00 00 02 7A 80
+					15 01 00 00 00 00 02 7B 91
+					15 01 00 00 00 00 02 7C D8
+					15 01 00 00 00 00 02 7D 60
+					15 01 00 00 00 00 02 7F 15
+					15 01 00 00 00 00 02 75 15
+					/* ABOFF */
+					15 01 00 00 00 00 02 B3 C0
+					15 01 00 00 00 00 02 B4 00
+					15 01 00 00 00 00 02 B5 00
+					/* Source EQ */
+					15 01 00 00 00 00 02 78 00
+					15 01 00 00 00 00 02 79 00
+					15 01 00 00 00 00 02 80 00
+					15 01 00 00 00 00 02 83 00
+					/* FP BP */
+					15 01 00 00 00 00 02 93 0A
+					15 01 00 00 00 00 02 94 0A
+					/* Inversion Type */
+					15 01 00 00 00 00 02 8A 00
+					15 01 00 00 00 00 02 9B FF
+					/* IMGSWAP =1 @PortSwap=1 */
+					15 01 00 00 00 00 02 9D B0
+					15 01 00 00 00 00 02 9F 63
+					15 01 00 00 00 00 02 98 10
+					/* FRM */
+					15 01 00 00 00 00 02 EC 00
+					/* CMD1 */
+					15 01 00 00 00 00 02 ff 10
+					/* VBP+VSA=,VFP = 10H */
+					15 01 00 00 00 00 04 3B 03 0A 0A
+					/* FTE on */
+					15 01 00 00 00 00 02 35 00
+					/* EN_BK =1(auto black) */
+					15 01 00 00 00 00 02 E5 01
+					/* CMD mode(10) VDO mode(03) */
+					15 01 00 00 00 00 02 BB 10
+					/* Non Reload MTP */
+					15 01 00 00 00 00 02 FB 01
+					/* SlpOut + DispOn */
+					05 01 00 00 78 00 02 11 00
+					05 01 00 00 78 00 02 29 00
+					];
+				qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+					02 28 00 05 01 00 00 78 00 02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi

@@ -0,0 +1,215 @@
+/* Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_dual_nt35597_truly_video: qcom,mdss_dsi_nt35597_wqxga_video_truly {
+		qcom,mdss-dsi-panel-name =
+			"Dual nt35597 video mode dsi truly panel without DSC";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-panel-framerate = <60>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <720>;
+		qcom,mdss-dsi-panel-height = <2560>;
+		qcom,mdss-dsi-h-front-porch = <100>;
+		qcom,mdss-dsi-h-back-porch = <32>;
+		qcom,mdss-dsi-h-pulse-width = <16>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <7>;
+		qcom,mdss-dsi-v-front-porch = <8>;
+		qcom,mdss-dsi-v-pulse-width = <1>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0x3ff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-on-command = [
+			/* CMD2_P0 */
+			15 01 00 00 00 00 02 FF 20
+			15 01 00 00 00 00 02 FB 01
+			15 01 00 00 00 00 02 00 01
+			15 01 00 00 00 00 02 01 55
+			15 01 00 00 00 00 02 02 45
+			15 01 00 00 00 00 02 05 40
+			15 01 00 00 00 00 02 06 19
+			15 01 00 00 00 00 02 07 1E
+			15 01 00 00 00 00 02 0B 73
+			15 01 00 00 00 00 02 0C 73
+			15 01 00 00 00 00 02 0E B0
+			15 01 00 00 00 00 02 0F AE
+			15 01 00 00 00 00 02 11 B8
+			15 01 00 00 00 00 02 13 00
+			15 01 00 00 00 00 02 58 80
+			15 01 00 00 00 00 02 59 01
+			15 01 00 00 00 00 02 5A 00
+			15 01 00 00 00 00 02 5B 01
+			15 01 00 00 00 00 02 5C 80
+			15 01 00 00 00 00 02 5D 81
+			15 01 00 00 00 00 02 5E 00
+			15 01 00 00 00 00 02 5F 01
+			15 01 00 00 00 00 02 72 11
+			15 01 00 00 00 00 02 68 03
+			/* CMD2_P4 */
+			15 01 00 00 00 00 02 FF 24
+			15 01 00 00 00 00 02 FB 01
+			15 01 00 00 00 00 02 00 1C
+			15 01 00 00 00 00 02 01 0B
+			15 01 00 00 00 00 02 02 0C
+			15 01 00 00 00 00 02 03 01
+			15 01 00 00 00 00 02 04 0F
+			15 01 00 00 00 00 02 05 10
+			15 01 00 00 00 00 02 06 10
+			15 01 00 00 00 00 02 07 10
+			15 01 00 00 00 00 02 08 89
+			15 01 00 00 00 00 02 09 8A
+			15 01 00 00 00 00 02 0A 13
+			15 01 00 00 00 00 02 0B 13
+			15 01 00 00 00 00 02 0C 15
+			15 01 00 00 00 00 02 0D 15
+			15 01 00 00 00 00 02 0E 17
+			15 01 00 00 00 00 02 0F 17
+			15 01 00 00 00 00 02 10 1C
+			15 01 00 00 00 00 02 11 0B
+			15 01 00 00 00 00 02 12 0C
+			15 01 00 00 00 00 02 13 01
+			15 01 00 00 00 00 02 14 0F
+			15 01 00 00 00 00 02 15 10
+			15 01 00 00 00 00 02 16 10
+			15 01 00 00 00 00 02 17 10
+			15 01 00 00 00 00 02 18 89
+			15 01 00 00 00 00 02 19 8A
+			15 01 00 00 00 00 02 1A 13
+			15 01 00 00 00 00 02 1B 13
+			15 01 00 00 00 00 02 1C 15
+			15 01 00 00 00 00 02 1D 15
+			15 01 00 00 00 00 02 1E 17
+			15 01 00 00 00 00 02 1F 17
+			/* STV */
+			15 01 00 00 00 00 02 20 40
+			15 01 00 00 00 00 02 21 01
+			15 01 00 00 00 00 02 22 00
+			15 01 00 00 00 00 02 23 40
+			15 01 00 00 00 00 02 24 40
+			15 01 00 00 00 00 02 25 6D
+			15 01 00 00 00 00 02 26 40
+			15 01 00 00 00 00 02 27 40
+			/* Vend */
+			15 01 00 00 00 00 02 E0 00
+			15 01 00 00 00 00 02 DC 21
+			15 01 00 00 00 00 02 DD 22
+			15 01 00 00 00 00 02 DE 07
+			15 01 00 00 00 00 02 DF 07
+			15 01 00 00 00 00 02 E3 6D
+			15 01 00 00 00 00 02 E1 07
+			15 01 00 00 00 00 02 E2 07
+			/* UD */
+			15 01 00 00 00 00 02 29 D8
+			15 01 00 00 00 00 02 2A 2A
+			/* CLK */
+			15 01 00 00 00 00 02 4B 03
+			15 01 00 00 00 00 02 4C 11
+			15 01 00 00 00 00 02 4D 10
+			15 01 00 00 00 00 02 4E 01
+			15 01 00 00 00 00 02 4F 01
+			15 01 00 00 00 00 02 50 10
+			15 01 00 00 00 00 02 51 00
+			15 01 00 00 00 00 02 52 80
+			15 01 00 00 00 00 02 53 00
+			15 01 00 00 00 00 02 56 00
+			15 01 00 00 00 00 02 54 07
+			15 01 00 00 00 00 02 58 07
+			15 01 00 00 00 00 02 55 25
+			/* Reset XDONB */
+			15 01 00 00 00 00 02 5B 43
+			15 01 00 00 00 00 02 5C 00
+			15 01 00 00 00 00 02 5F 73
+			15 01 00 00 00 00 02 60 73
+			15 01 00 00 00 00 02 63 22
+			15 01 00 00 00 00 02 64 00
+			15 01 00 00 00 00 02 67 08
+			15 01 00 00 00 00 02 68 04
+			/* Resolution:1440x2560*/
+			15 01 00 00 00 00 02 72 02
+			/* mux */
+			15 01 00 00 00 00 02 7A 80
+			15 01 00 00 00 00 02 7B 91
+			15 01 00 00 00 00 02 7C D8
+			15 01 00 00 00 00 02 7D 60
+			15 01 00 00 00 00 02 7F 15
+			15 01 00 00 00 00 02 75 15
+			/* ABOFF */
+			15 01 00 00 00 00 02 B3 C0
+			15 01 00 00 00 00 02 B4 00
+			15 01 00 00 00 00 02 B5 00
+			/* Source EQ */
+			15 01 00 00 00 00 02 78 00
+			15 01 00 00 00 00 02 79 00
+			15 01 00 00 00 00 02 80 00
+			15 01 00 00 00 00 02 83 00
+			/* FP BP */
+			15 01 00 00 00 00 02 93 0A
+			15 01 00 00 00 00 02 94 0A
+			/* Inversion Type */
+			15 01 00 00 00 00 02 8A 00
+			15 01 00 00 00 00 02 9B FF
+			/* IMGSWAP =1 @PortSwap=1 */
+			15 01 00 00 00 00 02 9D B0
+			15 01 00 00 00 00 02 9F 63
+			15 01 00 00 00 00 02 98 10
+			/* FRM */
+			15 01 00 00 00 00 02 EC 00
+			/* CMD1 */
+			15 01 00 00 00 00 02 FF 10
+			/* VBP+VSA=,VFP = 10H */
+			15 01 00 00 00 00 04 3B 03 0A 0A
+			/* FTE on */
+			15 01 00 00 00 00 02 35 00
+			/* EN_BK =1(auto black) */
+			15 01 00 00 00 00 02 E5 01
+			/* CMD mode(10) VDO mode(03) */
+			15 01 00 00 00 00 02 BB 03
+			/* Non Reload MTP */
+			15 01 00 00 00 00 02 FB 01
+			/* SlpOut + DispOn */
+			05 01 00 00 78 00 02 11 00
+			05 01 00 00 78 00 02 29 00
+			];
+		qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00
+				 05 01 00 00 78 00 02 10 00];
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-panel-timings = [e2 36 24 00 66 6a 28 38 2a 03
+				04 00];
+		qcom,mdss-dsi-t-clk-post = <0x0d>;
+		qcom,mdss-dsi-t-clk-pre = <0x2d>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-pan-physical-width-dimension = <74>;
+		qcom,mdss-pan-physical-height-dimension = <131>;
+
+		qcom,config-select = <&dsi_dual_nt35597_truly_video_config0>;
+
+		dsi_dual_nt35597_truly_video_config0: config0 {
+			qcom,split-mode = "dualctl-split";
+		};
+
+
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt35695b-truly-fhd-cmd.dtsi

@@ -0,0 +1,188 @@
+/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_nt35695b_truly_fhd_cmd: qcom,mdss_dsi_nt35695b_truly_fhd_cmd {
+		qcom,mdss-dsi-panel-name =
+				"nt35695b truly fhd command mode dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-dsi-post-init-delay = <1>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <1920>;
+				qcom,mdss-dsi-h-front-porch = <120>;
+				qcom,mdss-dsi-h-back-porch = <60>;
+				qcom,mdss-dsi-h-pulse-width = <12>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <2>;
+				qcom,mdss-dsi-v-front-porch = <12>;
+				qcom,mdss-dsi-v-pulse-width = <2>;
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,mdss-dsi-h-left-border = <0>;
+				qcom,mdss-dsi-h-right-border = <0>;
+				qcom,mdss-dsi-v-top-border = <0>;
+				qcom,mdss-dsi-v-bottom-border = <0>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command =
+					[15 01 00 00 10 00 02 ff 20
+					15 01 00 00 00 00 02 fb 01
+					15 01 00 00 00 00 02 00 01
+					15 01 00 00 00 00 02 01 55
+					15 01 00 00 00 00 02 02 45
+					15 01 00 00 00 00 02 03 55
+					15 01 00 00 00 00 02 05 50
+					15 01 00 00 00 00 02 06 a8
+					15 01 00 00 00 00 02 07 ad
+					15 01 00 00 00 00 02 08 0c
+					15 01 00 00 00 00 02 0b aa
+					15 01 00 00 00 00 02 0c aa
+					15 01 00 00 00 00 02 0e b0
+					15 01 00 00 00 00 02 0f b3
+					15 01 00 00 00 00 02 11 28
+					15 01 00 00 00 00 02 12 10
+					15 01 00 00 00 00 02 13 01
+					15 01 00 00 00 00 02 14 4a
+					15 01 00 00 00 00 02 15 12
+					15 01 00 00 00 00 02 16 12
+					15 01 00 00 00 00 02 30 01
+					15 01 00 00 00 00 02 72 11
+					15 01 00 00 00 00 02 58 82
+					15 01 00 00 00 00 02 59 00
+					15 01 00 00 00 00 02 5a 02
+					15 01 00 00 00 00 02 5b 00
+					15 01 00 00 00 00 02 5c 82
+					15 01 00 00 00 00 02 5d 80
+					15 01 00 00 00 00 02 5e 02
+					15 01 00 00 00 00 02 5f 00
+					15 01 00 00 00 00 02 ff 24
+					15 01 00 00 00 00 02 fb 01
+					15 01 00 00 00 00 02 00 01
+					15 01 00 00 00 00 02 01 0b
+					15 01 00 00 00 00 02 02 0c
+					15 01 00 00 00 00 02 03 89
+					15 01 00 00 00 00 02 04 8a
+					15 01 00 00 00 00 02 05 0f
+					15 01 00 00 00 00 02 06 10
+					15 01 00 00 00 00 02 07 10
+					15 01 00 00 00 00 02 08 1c
+					15 01 00 00 00 00 02 09 00
+					15 01 00 00 00 00 02 0a 00
+					15 01 00 00 00 00 02 0b 00
+					15 01 00 00 00 00 02 0c 00
+					15 01 00 00 00 00 02 0d 13
+					15 01 00 00 00 00 02 0e 15
+					15 01 00 00 00 00 02 0f 17
+					15 01 00 00 00 00 02 10 01
+					15 01 00 00 00 00 02 11 0b
+					15 01 00 00 00 00 02 12 0c
+					15 01 00 00 00 00 02 13 89
+					15 01 00 00 00 00 02 14 8a
+					15 01 00 00 00 00 02 15 0f
+					15 01 00 00 00 00 02 16 10
+					15 01 00 00 00 00 02 17 10
+					15 01 00 00 00 00 02 18 1c
+					15 01 00 00 00 00 02 19 00
+					15 01 00 00 00 00 02 1a 00
+					15 01 00 00 00 00 02 1b 00
+					15 01 00 00 00 00 02 1c 00
+					15 01 00 00 00 00 02 1d 13
+					15 01 00 00 00 00 02 1e 15
+					15 01 00 00 00 00 02 1f 17
+					15 01 00 00 00 00 02 20 00
+					15 01 00 00 00 00 02 21 01
+					15 01 00 00 00 00 02 22 00
+					15 01 00 00 00 00 02 23 40
+					15 01 00 00 00 00 02 24 40
+					15 01 00 00 00 00 02 25 6d
+					15 01 00 00 00 00 02 26 40
+					15 01 00 00 00 00 02 27 40
+					15 01 00 00 00 00 02 29 d8
+					15 01 00 00 00 00 02 2a 2a
+					15 01 00 00 00 00 02 4b 03
+					15 01 00 00 00 00 02 4c 11
+					15 01 00 00 00 00 02 4d 10
+					15 01 00 00 00 00 02 4e 01
+					15 01 00 00 00 00 02 4f 01
+					15 01 00 00 00 00 02 50 10
+					15 01 00 00 00 00 02 51 00
+					15 01 00 00 00 00 02 52 80
+					15 01 00 00 00 00 02 53 00
+					15 01 00 00 00 00 02 54 07
+					15 01 00 00 00 00 02 55 25
+					15 01 00 00 00 00 02 56 00
+					15 01 00 00 00 00 02 58 07
+					15 01 00 00 00 00 02 5b 43
+					15 01 00 00 00 00 02 5c 00
+					15 01 00 00 00 00 02 5f 73
+					15 01 00 00 00 00 02 60 73
+					15 01 00 00 00 00 02 63 22
+					15 01 00 00 00 00 02 64 00
+					15 01 00 00 00 00 02 67 08
+					15 01 00 00 00 00 02 68 04
+					15 01 00 00 00 00 02 7a 80
+					15 01 00 00 00 00 02 7b 91
+					15 01 00 00 00 00 02 7c d8
+					15 01 00 00 00 00 02 7d 60
+					15 01 00 00 00 00 02 93 06
+					15 01 00 00 00 00 02 94 06
+					15 01 00 00 00 00 02 8a 00
+					15 01 00 00 00 00 02 9b 0f
+					15 01 00 00 00 00 02 b3 c0
+					15 01 00 00 00 00 02 b4 00
+					15 01 00 00 00 00 02 b5 00
+					15 01 00 00 00 00 02 b6 21
+					15 01 00 00 00 00 02 b7 22
+					15 01 00 00 00 00 02 b8 07
+					15 01 00 00 00 00 02 b9 07
+					15 01 00 00 00 00 02 ba 22
+					15 01 00 00 00 00 02 bd 20
+					15 01 00 00 00 00 02 be 07
+					15 01 00 00 00 00 02 bf 07
+					15 01 00 00 00 00 02 c1 6d
+					15 01 00 00 00 00 02 c4 24
+					15 01 00 00 00 00 02 e3 00
+					15 01 00 00 00 00 02 ec 00
+					15 01 00 00 00 00 02 ff 10
+					15 01 00 00 00 00 02 bb 10
+					15 01 00 00 00 00 02 35 00
+					05 01 00 00 78 00 02 11 00
+					05 01 00 00 78 00 02 29 00];
+				qcom,mdss-dsi-off-command = [05 01 00 00 14
+					00 02 28 00 05 01 00 00 78 00 02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt35695b-truly-fhd-video.dtsi

@@ -0,0 +1,184 @@
+/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_nt35695b_truly_fhd_video: qcom,mdss_dsi_nt35695b_truly_fhd_video {
+		qcom,mdss-dsi-panel-name =
+				"nt35695b truly fhd video mode dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-dsi-post-init-delay = <1>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <1920>;
+				qcom,mdss-dsi-h-front-porch = <120>;
+				qcom,mdss-dsi-h-back-porch = <60>;
+				qcom,mdss-dsi-h-pulse-width = <12>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,mdss-dsi-v-back-porch = <2>;
+				qcom,mdss-dsi-v-front-porch = <12>;
+				qcom,mdss-dsi-v-pulse-width = <2>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-h-left-border = <0>;
+				qcom,mdss-dsi-h-right-border = <0>;
+				qcom,mdss-dsi-v-top-border = <0>;
+				qcom,mdss-dsi-v-bottom-border = <0>;
+				qcom,mdss-dsi-on-command =
+					[15 01 00 00 10 00 02 ff 20
+					15 01 00 00 00 00 02 fb 01
+					15 01 00 00 00 00 02 00 01
+					15 01 00 00 00 00 02 01 55
+					15 01 00 00 00 00 02 02 45
+					15 01 00 00 00 00 02 03 55
+					15 01 00 00 00 00 02 05 50
+					15 01 00 00 00 00 02 06 a8
+					15 01 00 00 00 00 02 07 ad
+					15 01 00 00 00 00 02 08 0c
+					15 01 00 00 00 00 02 0b aa
+					15 01 00 00 00 00 02 0c aa
+					15 01 00 00 00 00 02 0e b0
+					15 01 00 00 00 00 02 0f b3
+					15 01 00 00 00 00 02 11 28
+					15 01 00 00 00 00 02 12 10
+					15 01 00 00 00 00 02 13 01
+					15 01 00 00 00 00 02 14 4a
+					15 01 00 00 00 00 02 15 12
+					15 01 00 00 00 00 02 16 12
+					15 01 00 00 00 00 02 30 01
+					15 01 00 00 00 00 02 72 11
+					15 01 00 00 00 00 02 58 82
+					15 01 00 00 00 00 02 59 00
+					15 01 00 00 00 00 02 5a 02
+					15 01 00 00 00 00 02 5b 00
+					15 01 00 00 00 00 02 5c 82
+					15 01 00 00 00 00 02 5d 80
+					15 01 00 00 00 00 02 5e 02
+					15 01 00 00 00 00 02 5f 00
+					15 01 00 00 00 00 02 ff 24
+					15 01 00 00 00 00 02 fb 01
+					15 01 00 00 00 00 02 00 01
+					15 01 00 00 00 00 02 01 0b
+					15 01 00 00 00 00 02 02 0c
+					15 01 00 00 00 00 02 03 89
+					15 01 00 00 00 00 02 04 8a
+					15 01 00 00 00 00 02 05 0f
+					15 01 00 00 00 00 02 06 10
+					15 01 00 00 00 00 02 07 10
+					15 01 00 00 00 00 02 08 1c
+					15 01 00 00 00 00 02 09 00
+					15 01 00 00 00 00 02 0a 00
+					15 01 00 00 00 00 02 0b 00
+					15 01 00 00 00 00 02 0c 00
+					15 01 00 00 00 00 02 0d 13
+					15 01 00 00 00 00 02 0e 15
+					15 01 00 00 00 00 02 0f 17
+					15 01 00 00 00 00 02 10 01
+					15 01 00 00 00 00 02 11 0b
+					15 01 00 00 00 00 02 12 0c
+					15 01 00 00 00 00 02 13 89
+					15 01 00 00 00 00 02 14 8a
+					15 01 00 00 00 00 02 15 0f
+					15 01 00 00 00 00 02 16 10
+					15 01 00 00 00 00 02 17 10
+					15 01 00 00 00 00 02 18 1c
+					15 01 00 00 00 00 02 19 00
+					15 01 00 00 00 00 02 1a 00
+					15 01 00 00 00 00 02 1b 00
+					15 01 00 00 00 00 02 1c 00
+					15 01 00 00 00 00 02 1d 13
+					15 01 00 00 00 00 02 1e 15
+					15 01 00 00 00 00 02 1f 17
+					15 01 00 00 00 00 02 20 00
+					15 01 00 00 00 00 02 21 01
+					15 01 00 00 00 00 02 22 00
+					15 01 00 00 00 00 02 23 40
+					15 01 00 00 00 00 02 24 40
+					15 01 00 00 00 00 02 25 6d
+					15 01 00 00 00 00 02 26 40
+					15 01 00 00 00 00 02 27 40
+					15 01 00 00 00 00 02 29 d8
+					15 01 00 00 00 00 02 2a 2a
+					15 01 00 00 00 00 02 4b 03
+					15 01 00 00 00 00 02 4c 11
+					15 01 00 00 00 00 02 4d 10
+					15 01 00 00 00 00 02 4e 01
+					15 01 00 00 00 00 02 4f 01
+					15 01 00 00 00 00 02 50 10
+					15 01 00 00 00 00 02 51 00
+					15 01 00 00 00 00 02 52 80
+					15 01 00 00 00 00 02 53 00
+					15 01 00 00 00 00 02 54 07
+					15 01 00 00 00 00 02 55 25
+					15 01 00 00 00 00 02 56 00
+					15 01 00 00 00 00 02 58 07
+					15 01 00 00 00 00 02 5b 43
+					15 01 00 00 00 00 02 5c 00
+					15 01 00 00 00 00 02 5f 73
+					15 01 00 00 00 00 02 60 73
+					15 01 00 00 00 00 02 63 22
+					15 01 00 00 00 00 02 64 00
+					15 01 00 00 00 00 02 67 08
+					15 01 00 00 00 00 02 68 04
+					15 01 00 00 00 00 02 7a 80
+					15 01 00 00 00 00 02 7b 91
+					15 01 00 00 00 00 02 7c d8
+					15 01 00 00 00 00 02 7d 60
+					15 01 00 00 00 00 02 93 06
+					15 01 00 00 00 00 02 94 06
+					15 01 00 00 00 00 02 8a 00
+					15 01 00 00 00 00 02 9b 0f
+					15 01 00 00 00 00 02 b3 c0
+					15 01 00 00 00 00 02 b4 00
+					15 01 00 00 00 00 02 b5 00
+					15 01 00 00 00 00 02 b6 21
+					15 01 00 00 00 00 02 b7 22
+					15 01 00 00 00 00 02 b8 07
+					15 01 00 00 00 00 02 b9 07
+					15 01 00 00 00 00 02 ba 22
+					15 01 00 00 00 00 02 bd 20
+					15 01 00 00 00 00 02 be 07
+					15 01 00 00 00 00 02 bf 07
+					15 01 00 00 00 00 02 c1 6d
+					15 01 00 00 00 00 02 c4 24
+					15 01 00 00 00 00 02 e3 00
+					15 01 00 00 00 00 02 ec 00
+					15 01 00 00 00 00 02 ff 10
+					15 01 00 00 00 00 02 bb 03
+					05 01 00 00 78 00 02 11 00
+					05 01 00 00 78 00 02 29 00];
+				qcom,mdss-dsi-off-command = [05 01 00 00
+					14 00 02 28 00 05 01 00 00 78 00
+					02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt36672-truly-fhd-video.dtsi

@@ -0,0 +1,282 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_nt36672_truly_video: qcom,mdss_dsi_nt36672_truly_video {
+		qcom,mdss-dsi-panel-name =
+				"nt36672 truly fhd video mode dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-dsi-post-init-delay = <1>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2520>;
+				qcom,mdss-dsi-h-front-porch = <28>;
+				qcom,mdss-dsi-h-back-porch = <176>;
+				qcom,mdss-dsi-h-pulse-width = <12>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <10>;
+				qcom,mdss-dsi-v-front-porch = <12>;
+				qcom,mdss-dsi-v-pulse-width = <4>;
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,mdss-dsi-h-left-border = <0>;
+				qcom,mdss-dsi-h-right-border = <0>;
+				qcom,mdss-dsi-v-top-border = <0>;
+				qcom,mdss-dsi-v-bottom-border = <0>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+					29 01 00 00 00 00 02 FF 10
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 FF 20
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 0E B0
+					29 01 00 00 00 00 02 0F AE
+					29 01 00 00 00 00 02 62 93
+					29 01 00 00 00 00 02 6D 44
+					29 01 00 00 00 00 02 78 01
+					29 01 00 00 00 00 02 95 B9
+					29 01 00 00 00 00 02 96 B9
+					29 01 00 00 00 00 02 97 B9
+					29 01 00 00 00 00 02 98 B9
+					29 01 00 00 00 00 02 FF 24
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 00 1C
+					29 01 00 00 00 00 02 01 1C
+					29 01 00 00 00 00 02 02 1C
+					29 01 00 00 00 00 02 03 1C
+					29 01 00 00 00 00 02 04 20
+					29 01 00 00 00 00 02 05 00
+					29 01 00 00 00 00 02 06 09
+					29 01 00 00 00 00 02 07 0A
+					29 01 00 00 00 00 02 08 1E
+					29 01 00 00 00 00 02 09 0D
+					29 01 00 00 00 00 02 0A 0D
+					29 01 00 00 00 00 02 0B 25
+					29 01 00 00 00 00 02 0C 24
+					29 01 00 00 00 00 02 0D 01
+					29 01 00 00 00 00 02 0E 04
+					29 01 00 00 00 00 02 0F 04
+					29 01 00 00 00 00 02 10 03
+					29 01 00 00 00 00 02 11 03
+					29 01 00 00 00 00 02 12 14
+					29 01 00 00 00 00 02 13 14
+					29 01 00 00 00 00 02 14 12
+					29 01 00 00 00 00 02 15 12
+					29 01 00 00 00 00 02 16 10
+					29 01 00 00 00 00 02 17 1C
+					29 01 00 00 00 00 02 18 1C
+					29 01 00 00 00 00 02 19 1C
+					29 01 00 00 00 00 02 1A 1C
+					29 01 00 00 00 00 02 1B 20
+					29 01 00 00 00 00 02 1C 0D
+					29 01 00 00 00 00 02 1D 09
+					29 01 00 00 00 00 02 1E 0A
+					29 01 00 00 00 00 02 1F 1E
+					29 01 00 00 00 00 02 20 0D
+					29 01 00 00 00 00 02 21 0D
+					29 01 00 00 00 00 02 22 25
+					29 01 00 00 00 00 02 23 24
+					29 01 00 00 00 00 02 24 01
+					29 01 00 00 00 00 02 25 04
+					29 01 00 00 00 00 02 26 04
+					29 01 00 00 00 00 02 27 03
+					29 01 00 00 00 00 02 28 03
+					29 01 00 00 00 00 02 29 14
+					29 01 00 00 00 00 02 2A 14
+					29 01 00 00 00 00 02 2B 12
+					29 01 00 00 00 00 02 2D 12
+					29 01 00 00 00 00 02 2F 10
+					29 01 00 00 00 00 02 31 02
+					29 01 00 00 00 00 02 32 03
+					29 01 00 00 00 00 02 33 04
+					29 01 00 00 00 00 02 34 02
+					29 01 00 00 00 00 02 37 09
+					29 01 00 00 00 00 02 38 6A
+					29 01 00 00 00 00 02 39 6A
+					29 01 00 00 00 00 02 3F 6A
+					29 01 00 00 00 00 02 41 02
+					29 01 00 00 00 00 02 42 03
+					29 01 00 00 00 00 02 4C 10
+					29 01 00 00 00 00 02 4D 10
+					29 01 00 00 00 00 02 60 90
+					29 01 00 00 00 00 02 61 D8
+					29 01 00 00 00 00 02 72 00
+					29 01 00 00 00 00 02 73 00
+					29 01 00 00 00 00 02 74 00
+					29 01 00 00 00 00 02 75 00
+					29 01 00 00 00 00 02 79 23
+					29 01 00 00 00 00 02 7A 0D
+					29 01 00 00 00 00 02 7B 98
+					29 01 00 00 00 00 02 7C 80
+					29 01 00 00 00 00 02 7D 09
+					29 01 00 00 00 00 02 80 42
+					29 01 00 00 00 00 02 82 11
+					29 01 00 00 00 00 02 83 22
+					29 01 00 00 00 00 02 84 33
+					29 01 00 00 00 00 02 85 00
+					29 01 00 00 00 00 02 86 00
+					29 01 00 00 00 00 02 87 00
+					29 01 00 00 00 00 02 88 11
+					29 01 00 00 00 00 02 89 22
+					29 01 00 00 00 00 02 8A 33
+					29 01 00 00 00 00 02 8B 00
+					29 01 00 00 00 00 02 8C 00
+					29 01 00 00 00 00 02 8D 00
+					29 01 00 00 00 00 02 92 6D
+					29 01 00 00 00 00 02 9D B6
+					29 01 00 00 00 00 02 B3 02
+					29 01 00 00 00 00 02 B4 00
+					29 01 00 00 00 00 02 DC 44
+					29 01 00 00 00 00 02 DD 03
+					29 01 00 00 00 00 02 DF 3E
+					29 01 00 00 00 00 02 E0 3E
+					29 01 00 00 00 00 02 E1 22
+					29 01 00 00 00 00 02 E2 24
+					29 01 00 00 00 00 02 E3 09
+					29 01 00 00 00 00 02 E4 09
+					29 01 00 00 00 00 02 EB 0F
+					29 01 00 00 00 00 02 FF 25
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 21 18
+					29 01 00 00 00 00 02 22 18
+					29 01 00 00 00 00 02 24 6D
+					29 01 00 00 00 00 02 25 6D
+					29 01 00 00 00 00 02 2F 10
+					29 01 00 00 00 00 02 30 2D
+					29 01 00 00 00 00 02 38 2D
+					29 01 00 00 00 00 02 3F 21
+					29 01 00 00 00 00 02 40 65
+					29 01 00 00 00 00 02 4B 21
+					29 01 00 00 00 00 02 4C 65
+					29 01 00 00 00 00 02 58 22
+					29 01 00 00 00 00 02 59 04
+					29 01 00 00 00 00 02 5A 09
+					29 01 00 00 00 00 02 5B 09
+					29 01 00 00 00 00 02 5C 25
+					29 01 00 00 00 00 02 5E FF
+					29 01 00 00 00 00 02 5F 28
+					29 01 00 00 00 00 02 66 D8
+					29 01 00 00 00 00 02 67 2B
+					29 01 00 00 00 00 02 68 58
+					29 01 00 00 00 00 02 6B 00
+					29 01 00 00 00 00 02 6C 6D
+					29 01 00 00 00 00 02 77 72
+					29 01 00 00 00 00 02 BF 00
+					29 01 00 00 00 00 02 C3 01
+					29 01 00 00 00 00 02 FF 26
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 06 FF
+					29 01 00 00 00 00 02 0C 11
+					29 01 00 00 00 00 02 0F 09
+					29 01 00 00 00 00 02 10 0A
+					29 01 00 00 00 00 02 12 8C
+					29 01 00 00 00 00 02 1A 28
+					29 01 00 00 00 00 02 1C AF
+					29 01 00 00 00 00 02 1E AB
+					29 01 00 00 00 00 02 98 F1
+					29 01 00 00 00 00 02 A9 12
+					29 01 00 00 00 00 02 AA 10
+					29 01 00 00 00 00 02 AE 6A
+					29 01 00 00 00 00 02 FF 27
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 13 00
+					29 01 00 00 00 00 02 1E 24
+					29 01 00 00 00 00 02 FF F0
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 A2 00
+					29 01 00 00 00 00 02 FF 20
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 11 B0 00 00 00 3D 00
+						74 00 9A 00 B9 00 D1 00 E6 00 F8
+					29 01 00 00 00 00 11 B1 01 08 01 3B 01
+						5E 01 95 01 BB 01 F8 02 23 02 25
+					29 01 00 00 00 00 11 B2 02 51 02 84 02
+						AB 02 E1 02 FB 03 30 03 3E 03 4D
+					29 01 00 00 00 00 0D B3 03 5F 03 72 03
+						8A 03 A9 03 C9 03 FF
+					29 01 00 00 00 00 11 B4 00 00 00 3D 00
+						74 00 9A 00 B9 00 D1 00 E6 00 F8
+					29 01 00 00 00 00 11 B5 01 08 01 3B 01
+						5E 01 95 01 BB 01 F8 02 23 02 25
+					29 01 00 00 00 00 11 B6 02 51 02 84 02
+						AB 02 E1 02 FB 03 30 03 3E 03 4D
+					29 01 00 00 00 00 0D B7 03 5F 03 72 03
+						8A 03 A9 03 C9 03 FF
+					29 01 00 00 00 00 11 B8 00 00 00 3D 00
+						74 00 9A 00 B9 00 D1 00 E6 00 F8
+					29 01 00 00 00 00 11 B9 01 08 01 3B 01
+						5E 01 95 01 BB 01 F8 02 23 02 25
+					29 01 00 00 00 00 11 BA 02 51 02 84 02
+						AB 02 E1 02 FB 03 30 03 3E 03 4D
+					29 01 00 00 00 00 0D BB 03 5F 03 72 03
+						8A 03 A9 03 C9 03 FF
+					29 01 00 00 00 00 02 FF 21
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 11 B0 00 00 00 3D 00
+						74 00 9A 00 B9 00 D1 00 E6 00 F8
+					29 01 00 00 00 00 11 B1 01 08 01 3B 01
+						5E 01 95 01 BB 01 F8 02 23 02 25
+					29 01 00 00 00 00 11 B2 02 51 02 84 02
+						AB 02 E1 02 FB 03 30 03 3E 03 4D
+					29 01 00 00 00 00 0D B3 03 5F 03 72 03
+						8A 03 A9 03 C9 03 FF
+					29 01 00 00 00 00 11 B4 00 00 00 3D 00
+						74 00 9A 00 B9 00 D1 00 E6 00 F8
+					29 01 00 00 00 00 11 B5 01 08 01 3B 01
+						5E 01 95 01 BB 01 F8 02 23 02 25
+					29 01 00 00 00 00 11 B6 02 51 02 84 02
+						AB 02 E1 02 FB 03 30 03 3E 03 4D
+					29 01 00 00 00 00 0D B7 03 5F 03 72 03
+						8A 03 A9 03 C9 03 FF
+					29 01 00 00 00 00 11 B8 00 00 00 3D 00
+						74 00 9A 00 B9 00 D1 00 E6 00 F8
+					29 01 00 00 00 00 11 B9 01 08 01 3B 01
+						5E 01 95 01 BB 01 F8 02 23 02 25
+					29 01 00 00 00 00 11 BA 02 51 02 84 02
+						AB 02 E1 02 FB 03 30 03 3E 03 4D
+					29 01 00 00 00 00 0D BB 03 5F 03 72 03
+						8A 03 A9 03 C9 03 FF
+					29 01 00 00 00 00 02 FF 10
+					29 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 51 FF
+					39 01 00 00 00 00 02 53 2C
+					05 01 00 00 78 00 02 11 00
+					05 01 00 00 32 00 02 29 00];
+				qcom,mdss-dsi-off-command = [05 01 00 00 14
+					00 02 28 00 05 01 00 00 78 00 02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt36672c-boe-fhd-plus-video.dtsi

@@ -0,0 +1,291 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_nt36672c_boe_video: qcom,mdss_dsi_nt36672c_boe_video {
+		qcom,mdss-dsi-panel-name =
+			"nt36672c fhd plus video mode dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 3>, <1 0>;
+		qcom,mdss-pan-physical-width-dimension = <69>;
+		qcom,mdss-pan-physical-height-dimension = <152>;
+		qcom,mdss-dsi-dma-schedule-line = <5>;
+
+		qcom,mdss-dsi-lp11-init;
+		qcom,dsi-supported-dfps-list = <60 90 45>;
+		qcom,mdss-dsi-pan-enable-dynamic-fps;
+		qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+
+		qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+		qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+
+		oplus,is_19696_lcd;
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+		qcom,mdss-dsi-bl-min-level = <1>;
+		qcom,mdss-dsi-bl-max-level = <4095>;
+                qcom,mdss-dsi-bl-normal-max-level = <2047>;
+		qcom,mdss-brightness-max-level =<2047>;
+		qcom,mdss-dsi-bl-default-level = <1024>;
+		oppo,dsi-brightness-remapping = <1    1>,
+							<2    18>,
+							<20   44>,
+							<50   58>,
+							<121  84>,
+							<200  118>,
+							<277  152>,
+							<355  190>,
+							<452  242>,
+							<605  348>,
+							<803  528>,
+							<1024 786>,
+							<1224 1116>,
+							<1425 1570>,
+							<1625 2170>,
+							<1823 2962>,
+							<2047 4095>;
+
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15000 15500 34000
+		       16000 13250 34500 7500 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4300000>;
+		qcom,mdss-dsi-panel-blackness-level = <1023>;
+		qcom,panel-cphy-mode;
+		oppo,bl_interpolate_nosub;
+		oppo,mdss-dsi-vendor-name = "nt36672c";
+		oppo,mdss-dsi-manufacture = "boe vdo mode";
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2400>;
+				qcom,mdss-dsi-h-front-porch = <202>;
+				qcom,mdss-dsi-h-back-porch = <56>;
+				qcom,mdss-dsi-h-pulse-width = <12>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <10>;
+				qcom,mdss-dsi-v-front-porch = <1291>;
+				qcom,mdss-dsi-v-pulse-width = <10>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-pre-on-command=[
+						29 01 00 00 00 00 02 FF C0   /*modified for VDD_TP power*/
+						29 01 00 00 0A 00 02 48 1F
+						29 01 00 00 00 00 02 FF C0
+						29 01 00 00 00 00 02 4B 0E];
+				qcom,mdss-dsi-on-command = [
+						29 01 00 00 00 00 02 FF 10
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 B0 10
+						29 01 00 00 00 00 02 C0 00       /*VESA off for C-PHY*/
+						29 01 00 00 00 00 03 C2 1B A0
+
+						29 01 00 00 00 00 02 FF 25
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 18 20     /*60hz :21 ; 90hz:20*/
+
+						15 01 00 00 00 00 02 FF 2A  /*for switch 60hz TP*/
+						15 01 00 00 00 00 02 FB 01
+						15 01 00 00 00 00 02 27 80
+						15 01 00 00 00 00 02 28 FD
+
+						/*#ifdef ODM_LQ_EDIT*/
+						/*qujiong@ODM_LQ@BSP.touch,2019/10/30,modified for TP self-test*/
+						29 01 00 00 00 00 02 FF F0
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 5A 00
+						29 01 00 00 00 00 02 A0 08
+						29 01 00 00 00 00 02 FF D0
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 09 AD
+						/*endif ODM_LQ_EDIT*/
+
+						/*#ifdef ODM_LQ_EDIT*/
+						/*zhangjialong@ODM_LQ@Multimedia.Dispaly,2019/11/21,add cabc function */
+						15 01 00 00 00 00 02 FF 10
+						15 01 00 00 00 00 02 FB 01
+						15 01 00 00 00 00 02 51 FF   /*keep pwm high when cabc off*/
+						15 01 00 00 00 00 02 53 24
+						15 01 00 00 00 00 02 FF 23
+						15 01 00 00 00 00 02 FB 01
+
+						15 01 00 00 00 00 02 0A 00
+						15 01 00 00 00 00 02 0B 00
+						15 01 00 00 00 00 02 0C 00
+						15 01 00 00 00 00 02 0D 00
+
+						15 01 00 00 00 00 02 11 01
+						15 01 00 00 00 00 02 12 95
+						15 01 00 00 00 00 02 15 68
+						15 01 00 00 00 00 02 16 0B
+						15 01 00 00 00 00 02 6F 00
+						15 01 00 00 00 00 02 70 00
+						15 01 00 00 00 00 02 71 00
+						15 01 00 00 00 00 02 A0 11
+						15 01 00 00 00 00 02 FF  F0
+						15 01 00 00 00 00 02 FB 01
+						15 01 00 00 00 00 02 D2 52
+						/*#endif ODM_LQ_EDIT*/
+
+						29 01 00 00 00 00 02 FF 24
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 E3 02
+						29 01 00 00 00 00 02 FF D0
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 53 22
+						29 01 00 00 00 00 02 54 02
+
+						29 01 00 00 00 00 02 FF 23
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 07 20
+						29 01 00 00 00 00 02 08 07
+						29 01 00 00 00 00 02 09 04
+
+						29 01 00 00 00 00 02 FF 10
+						29 01 00 00 00 00 02 35 00
+						05 01 00 00 46 00 02 11 00
+						05 01 00 00 1E 00 02 29 00
+					];
+				qcom,mdss-dsi-off-command =[
+					29 01 00 00 00 00 02 FF 10
+					29 01 00 00 00 00 02 FB 01
+					05 01 00 00 14 00 02 28 00
+					05 01 00 00 78 00 02 10 00
+					];
+				/*#ifdef ODM_LQ_EDIT*/
+				/*zhangjialong@ODM_LQ@Multimedia.Dispaly,2019/11/21,add cabc function */
+				qcom,mdss-dsi-cabc-off-command = [
+					15 01 00 00 00 00 02 FF 10
+					15 01 00 00 00 00 02 55 00
+					];
+				qcom,mdss-dsi-cabc-ui-command = [
+					15 01 00 00 00 00 02 FF 23
+					15 00 00 00 00 00 02 FB 01
+					/*UI_PWM DUTY*/
+					15 01 00 00 00 00 02 30 FF
+					15 00 00 00 00 00 02 31 FC
+					15 00 00 00 00 00 02 32 F8
+					15 00 00 00 00 00 02 33 F4
+					15 00 00 00 00 00 02 34 F3
+					15 00 00 00 00 00 02 35 F3
+					15 00 00 00 00 00 02 36 F3
+					15 00 00 00 00 00 02 37 F2
+					15 00 00 00 00 00 02 38 F1
+					15 00 00 00 00 00 02 39 F0
+					15 01 00 00 00 00 02 3A EE
+					15 00 00 00 00 00 02 3B EC
+					15 00 00 00 00 00 02 3D EA
+					15 00 00 00 00 00 02 3F E8
+					15 00 00 00 00 00 02 40 E6
+					15 00 00 00 10 00 02 41 E4
+					15 01 00 00 00 00 02 FF 10
+					15 00 00 00 00 00 02 FB 01
+					15 00 00 00 00 00 02 51 FF
+					15 00 00 00 00 00 02 53 2C
+					15 01 00 00 00 00 02 55 01   /*mode switch*/
+					];
+				qcom,mdss-dsi-cabc-still-image-command = [
+					15 01 00 00 00 00 02 FF 23
+					15 00 00 00 00 00 02 FB 01
+					/*Still_PWM DUTY*/
+					15 01 00 00 00 00 02 45 E7
+					15 00 00 00 00 00 02 46 E0
+					15 00 00 00 00 00 02 47 D8
+					15 00 00 00 00 00 02 48 CE
+					15 00 00 00 00 00 02 49 CD
+					15 00 00 00 00 00 02 4A CC
+					15 00 00 00 00 00 02 4B CA
+					15 00 00 00 00 00 02 4C C4
+					15 00 00 00 00 00 02 4D C0
+					15 00 00 00 00 00 02 4E BF
+					15 01 00 00 00 00 02 4F BF
+					15 00 00 00 00 00 02 50 BF
+					15 00 00 00 00 00 02 51 BF
+					15 00 00 00 00 00 02 52 BF
+					15 00 00 00 00 00 02 53 BF
+					15 00 00 00 00 00 02 54 BE
+					15 01 00 00 00 00 02 FF 10
+					15 00 00 00 00 00 02 FB 01
+					15 00 00 00 00 00 02 51 FF
+					15 00 00 00 00 00 02 53 2C
+					15 01 00 00 00 00 02 55 02   /*mode switch*/
+					];
+				qcom,mdss-dsi-cabc-video-command = [
+					15 01 00 00 00 00 02 FF 23
+					15 00 00 00 00 00 02 FB 01
+					/*MOV_PWM DUTY*/
+					15 01 00 00 00 00 02 58 D9
+					15 00 00 00 00 00 02 59 CC
+					15 00 00 00 00 00 02 5A C0
+					15 00 00 00 00 00 02 5B B3
+					15 00 00 00 00 00 02 5C B2
+					15 00 00 00 00 00 02 5D B2
+					15 00 00 00 00 00 02 5E B2
+					15 00 00 00 00 00 02 5F A6
+					15 00 00 00 00 00 02 60 A5
+					15 00 00 00 00 00 02 61 A1
+					15 01 00 00 00 00 02 62 A0
+					15 00 00 00 00 00 02 63 98
+					15 00 00 00 00 00 02 64 90
+					15 00 00 00 00 00 02 65 8A
+					15 00 00 00 00 00 02 66 80
+					15 00 00 00 00 00 02 67 72
+					15 01 00 00 00 00 02 FF 10
+					15 00 00 00 00 00 02 FB 01
+					15 00 00 00 00 00 02 51 FF
+					15 00 00 00 00 00 02 53 2C
+					15 01 00 00 00 00 02 55 03   /*mode switch*/
+					];
+				qcom,mdss-dsi-cabc-off-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-cabc-ui-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-cabc-still-image-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-cabc-video-command-state = "dsi_lp_mode";
+				/*#endif ODM_LQ_EDIT*/
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+			};
+		};
+	};
+};
+
+&dsi_nt36672c_boe_video {
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0a 00];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9C>;
+	qcom,mdss-dsi-panel-on-check-value = <0x9C>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,mdss-dsi-panel-max-error-count = <3>;
+	qcom,mdss-dsi-t-clk-post = <0x00>;
+	qcom,mdss-dsi-t-clk-pre = <0x00>;
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09 09
+				09 06 02 04];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt36672c-fhd-plus-video.dtsi

@@ -0,0 +1,113 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_nt36672c_video: qcom,mdss_dsi_nt36672c_video {
+		qcom,mdss-dsi-panel-name =
+			"nt36672c fhd plus video mode dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>;
+		qcom,mdss-pan-physical-width-dimension = <74>;
+		qcom,mdss-pan-physical-height-dimension = <131>;
+
+		qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+		qcom,mdss-dsi-panel-blackness-level = <3230>;
+		qcom,panel-cphy-mode;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2400>;
+				qcom,mdss-dsi-h-front-porch = <202>;
+				qcom,mdss-dsi-h-back-porch = <56>;
+				qcom,mdss-dsi-h-pulse-width = <12>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <10>;
+				qcom,mdss-dsi-v-front-porch = <1291>;
+				qcom,mdss-dsi-v-pulse-width = <10>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+					29 01 00 00 00 00 02 FF 10
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 B0 00
+					29 01 00 00 00 00 02 C0 00
+					29 01 00 00 00 00 03 C2 1B A0
+
+					29 01 00 00 00 00 02 FF 25
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 18 20
+
+					15 01 00 00 00 00 02 FF 2A
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 27 80
+					15 01 00 00 00 00 02 28 FD
+
+					29 01 00 00 00 00 02 FF F0
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 5A 00
+					29 01 00 00 00 00 02 A0 08
+					29 01 00 00 00 00 02 FF D0
+					29 01 00 00 00 00 02 FB 01
+					29 01 00 00 00 00 02 09 AD
+
+					15 01 00 00 00 00 02 FF 10
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 51 FF
+					15 01 00 00 00 00 02 53 2C
+					15 01 00 00 00 00 02 FF 23
+					15 01 00 00 00 00 02 FB 01
+
+					15 01 00 00 00 00 02 0A 00
+					15 01 00 00 00 00 02 0B 00
+					15 01 00 00 00 00 02 0C 00
+					15 01 00 00 00 00 02 0D 00
+
+					15 01 00 00 00 00 02 11 01
+					15 01 00 00 00 00 02 12 95
+					15 01 00 00 00 00 02 15 68
+					15 01 00 00 00 00 02 16 0B
+					15 01 00 00 00 00 02 6F 00
+					15 01 00 00 00 00 02 70 00
+					15 01 00 00 00 00 02 71 00
+					15 01 00 00 00 00 02 A0 11
+					15 01 00 00 00 00 02 FF F0
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 D2 52
+
+					29 01 00 00 00 00 02 FF 10
+					29 01 00 00 00 00 02 35 00
+					05 01 00 00 78 00 02 11 00
+					05 01 00 00 14 00 02 29 00
+				];
+				qcom,mdss-dsi-off-command =[
+					05 01 00 00 14 00 02 28 00
+					05 01 00 00 78 00 02 10 00
+				];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt36672c-jdi-fhd-plus-video.dtsi

@@ -0,0 +1,290 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_nt36672c_jdi_video: qcom,mdss_dsi_nt36672c_jdi_video {
+		qcom,mdss-dsi-panel-name =
+			"nt36672c jdi fhd plus video mode dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 3>, <1 0>;
+		qcom,mdss-pan-physical-width-dimension = <69>;
+		qcom,mdss-pan-physical-height-dimension = <152>;
+		qcom,mdss-dsi-dma-schedule-line = <5>;
+
+		qcom,mdss-dsi-lp11-init;
+		qcom,dsi-supported-dfps-list = <60 90 45>;
+		qcom,mdss-dsi-pan-enable-dynamic-fps;
+		qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+
+		qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+		qcom,platform-te-gpio = <&tlmm 10 0>;
+		qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+
+		oplus,is_19696_lcd;
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+		qcom,mdss-dsi-bl-min-level = <1>;
+		qcom,mdss-dsi-bl-max-level = <4095>;
+                qcom,mdss-dsi-bl-normal-max-level = <2047>;
+		qcom,mdss-brightness-max-level =<2047>;
+		qcom,mdss-dsi-bl-default-level = <1024>;
+		oppo,dsi-brightness-remapping = <1    1>,
+							<2    18>,
+							<20   44>,
+							<50   58>,
+							<121  84>,
+							<200  118>,
+							<277  152>,
+							<355  190>,
+							<452  242>,
+							<605  348>,
+							<803  528>,
+							<1024 786>,
+							<1224 1116>,
+							<1425 1570>,
+							<1625 2170>,
+							<1823 2962>,
+							<2047 4095>;
+
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15000 15500 34000
+		       16000 13250 34500 7500 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4300000>;
+		qcom,mdss-dsi-panel-blackness-level = <1023>;
+		qcom,panel-cphy-mode;
+		oppo,bl_interpolate_nosub;
+		oppo,mdss-dsi-vendor-name = "nt36672c";
+		oppo,mdss-dsi-manufacture = "jdi vdo mode";
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2400>;
+				qcom,mdss-dsi-h-front-porch = <202>;
+				qcom,mdss-dsi-h-back-porch = <56>;
+				qcom,mdss-dsi-h-pulse-width = <12>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <10>;
+				qcom,mdss-dsi-v-front-porch = <1291>;
+				qcom,mdss-dsi-v-pulse-width = <10>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-pre-on-command=[
+						29 01 00 00 00 00 02 FF C0   /*modified for VDD_TP power*/
+						29 01 00 00 0A 00 02 48 1F
+						29 01 00 00 00 00 02 FF C0
+						29 01 00 00 00 00 02 4B 0E];
+				qcom,mdss-dsi-on-command = [
+
+						29 01 00 00 00 00 02 FF 10
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 B0 10
+						29 01 00 00 00 00 02 C0 00       /*VESA off for C-PHY*/
+						29 01 00 00 00 00 03 C2 1B A0
+
+						29 01 00 00 00 00 02 FF 25
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 18 20     /*60hz :21 ; 90hz:20*/
+
+						15 01 00 00 00 00 02 FF 2A  /*for switch 60hz TP*/
+						15 01 00 00 00 00 02 FB 01
+						15 01 00 00 00 00 02 27 80
+						15 01 00 00 00 00 02 28 0A
+
+
+						29 01 00 00 00 00 02 FF F0		/*modified for TP self-test*/
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 5A 00
+						29 01 00 00 00 00 02 A0 08
+						29 01 00 00 00 00 02 FF D0
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 09 AD
+
+						/*#ifdef ODM_LQ_EDIT*/
+						/*zhangjialong@ODM_LQ@Multimedia.Dispaly,2019/11/21,add cabc function */
+						15 01 00 00 00 00 02 FF 10
+						15 01 00 00 00 00 02 FB 01
+						15 01 00 00 00 00 02 51 FF   /*keep pwm high when cabc off*/
+						15 01 00 00 00 00 02 53 24
+						15 01 00 00 00 00 02 FF 23
+						15 01 00 00 00 00 02 FB 01
+
+						15 01 00 00 00 00 02 0A 00
+						15 01 00 00 00 00 02 0B 00
+						15 01 00 00 00 00 02 0C 00
+						15 01 00 00 00 00 02 0D 00
+
+						15 01 00 00 00 00 02 11 01
+						15 01 00 00 00 00 02 12 95
+						15 01 00 00 00 00 02 15 68
+						15 01 00 00 00 00 02 16 0B
+						15 01 00 00 00 00 02 6F 00
+						15 01 00 00 00 00 02 70 00
+						15 01 00 00 00 00 02 71 00
+						15 01 00 00 00 00 02 A0 11
+						15 01 00 00 00 00 02 FF  F0
+						15 01 00 00 00 00 02 FB 01
+						15 01 00 00 00 00 02 D2 52
+						/*#endif ODM_LQ_EDIT*/
+
+						29 01 00 00 00 00 02 FF 24
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 E3 02
+						29 01 00 00 00 00 02 FF D0
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 53 22
+						29 01 00 00 00 00 02 54 02
+
+						29 01 00 00 00 00 02 FF 23
+						29 01 00 00 00 00 02 FB 01
+						29 01 00 00 00 00 02 07 20
+						29 01 00 00 00 00 02 08 07
+						29 01 00 00 00 00 02 09 04
+
+						29 01 00 00 00 00 02 FF 10
+						29 01 00 00 00 00 02 35 00
+						05 01 00 00 46 00 02 11 00
+						05 01 00 00 1E 00 02 29 00
+					];
+				qcom,mdss-dsi-off-command =[
+					29 01 00 00 00 00 02 FF 10
+					29 01 00 00 00 00 02 FB 01
+					05 01 00 00 14 00 02 28 00
+					05 01 00 00 78 00 02 10 00
+					];
+				/*#ifdef ODM_LQ_EDIT*/
+				/*zhangjialong@ODM_LQ@Multimedia.Dispaly,2019/11/21,add cabc function */
+				qcom,mdss-dsi-cabc-off-command = [
+					15 01 00 00 00 00 02 FF 10
+					15 01 00 00 00 00 02 55 00
+					];
+				qcom,mdss-dsi-cabc-ui-command = [
+					15 01 00 00 00 00 02 FF 23
+					15 00 00 00 00 00 02 FB 01
+					/*UI_PWM DUTY*/
+					15 01 00 00 00 00 02 30 FF
+					15 00 00 00 00 00 02 31 FC
+					15 00 00 00 00 00 02 32 F8
+					15 00 00 00 00 00 02 33 F4
+					15 00 00 00 00 00 02 34 F3
+					15 00 00 00 00 00 02 35 F3
+					15 00 00 00 00 00 02 36 F3
+					15 00 00 00 00 00 02 37 F2
+					15 00 00 00 00 00 02 38 F1
+					15 00 00 00 00 00 02 39 F0
+					15 01 00 00 00 00 02 3A EE
+					15 00 00 00 00 00 02 3B EC
+					15 00 00 00 00 00 02 3D EA
+					15 00 00 00 00 00 02 3F E8
+					15 00 00 00 00 00 02 40 E6
+					15 00 00 00 10 00 02 41 E4
+					15 01 00 00 00 00 02 FF 10
+					15 00 00 00 00 00 02 FB 01
+					15 00 00 00 00 00 02 51 FF
+					15 00 00 00 00 00 02 53 2C
+					15 01 00 00 00 00 02 55 01   /*mode switch*/
+					];
+				qcom,mdss-dsi-cabc-still-image-command = [
+					15 01 00 00 00 00 02 FF 23
+					15 00 00 00 00 00 02 FB 01
+					/*Still_PWM DUTY*/
+					15 01 00 00 00 00 02 45 E7
+					15 00 00 00 00 00 02 46 E0
+					15 00 00 00 00 00 02 47 D8
+					15 00 00 00 00 00 02 48 CE
+					15 00 00 00 00 00 02 49 CD
+					15 00 00 00 00 00 02 4A CC
+					15 00 00 00 00 00 02 4B CA
+					15 00 00 00 00 00 02 4C C4
+					15 00 00 00 00 00 02 4D C0
+					15 00 00 00 00 00 02 4E BF
+					15 01 00 00 00 00 02 4F BF
+					15 00 00 00 00 00 02 50 BF
+					15 00 00 00 00 00 02 51 BF
+					15 00 00 00 00 00 02 52 BF
+					15 00 00 00 00 00 02 53 BF
+					15 00 00 00 00 00 02 54 BE
+					15 01 00 00 00 00 02 FF 10
+					15 00 00 00 00 00 02 FB 01
+					15 00 00 00 00 00 02 51 FF
+					15 00 00 00 00 00 02 53 2C
+					15 01 00 00 00 00 02 55 02   /*mode switch*/
+					];
+				qcom,mdss-dsi-cabc-video-command = [
+					15 01 00 00 00 00 02 FF 23
+					15 00 00 00 00 00 02 FB 01
+					/*MOV_PWM DUTY*/
+					15 01 00 00 00 00 02 58 D9
+					15 00 00 00 00 00 02 59 CC
+					15 00 00 00 00 00 02 5A C0
+					15 00 00 00 00 00 02 5B B3
+					15 00 00 00 00 00 02 5C B2
+					15 00 00 00 00 00 02 5D B2
+					15 00 00 00 00 00 02 5E B2
+					15 00 00 00 00 00 02 5F A6
+					15 00 00 00 00 00 02 60 A5
+					15 00 00 00 00 00 02 61 A1
+					15 01 00 00 00 00 02 62 A0
+					15 00 00 00 00 00 02 63 98
+					15 00 00 00 00 00 02 64 90
+					15 00 00 00 00 00 02 65 8A
+					15 00 00 00 00 00 02 66 80
+					15 00 00 00 00 00 02 67 72
+					15 01 00 00 00 00 02 FF 10
+					15 00 00 00 00 00 02 FB 01
+					15 00 00 00 00 00 02 51 FF
+					15 00 00 00 00 00 02 53 2C
+					15 01 00 00 00 00 02 55 03   /*mode switch*/
+					];
+				qcom,mdss-dsi-cabc-off-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-cabc-ui-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-cabc-still-image-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-cabc-video-command-state = "dsi_lp_mode";
+				/*#endif ODM_LQ_EDIT*/
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+			};
+		};
+	};
+};
+
+&dsi_nt36672c_jdi_video {
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0a 00];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9C>;
+	qcom,mdss-dsi-panel-on-check-value = <0x9C>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,mdss-dsi-panel-max-error-count = <3>;
+	qcom,mdss-dsi-t-clk-post = <0x00>;
+	qcom,mdss-dsi-t-clk-pre = <0x00>;
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09 09
+				09 06 02 04];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi

@@ -0,0 +1,416 @@
+/* Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_dual_nt36850_truly_cmd: qcom,mdss_dsi_nt36850_truly_wqhd_cmd{
+		qcom,mdss-dsi-panel-name =
+			"Dual nt36850 cmd mode dsi truly panel without DSC";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-panel-framerate = <60>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <720>;
+		qcom,mdss-dsi-panel-height = <2560>;
+		qcom,mdss-dsi-h-front-porch = <120>;
+		qcom,mdss-dsi-h-back-porch = <140>;
+		qcom,mdss-dsi-h-pulse-width = <20>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <20>;
+		qcom,mdss-dsi-v-front-porch = <8>;
+		qcom,mdss-dsi-v-pulse-width = <4>;
+		qcom,mdss-dsi-h-left-border = <0>;
+		qcom,mdss-dsi-h-right-border = <0>;
+		qcom,mdss-dsi-v-top-border = <0>;
+		qcom,mdss-dsi-v-bottom-border = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-on-command = [
+				15 01 00 00 00 00 02 ff 24
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 00 19
+				15 01 00 00 00 00 02 01 03
+				15 01 00 00 00 00 02 02 04
+				15 01 00 00 00 00 02 03 1b
+				15 01 00 00 00 00 02 04 1d
+				15 01 00 00 00 00 02 05 01
+				15 01 00 00 00 00 02 06 0c
+				15 01 00 00 00 00 02 07 0f
+				15 01 00 00 00 00 02 08 1f
+				15 01 00 00 00 00 02 09 00
+				15 01 00 00 00 00 02 0a 00
+				15 01 00 00 00 00 02 0b 13
+				15 01 00 00 00 00 02 0c 16
+				15 01 00 00 00 00 02 0d 14
+				15 01 00 00 00 00 02 0e 15
+				15 01 00 00 00 00 02 0f 00
+				15 01 00 00 00 00 02 10 19
+				15 01 00 00 00 00 02 11 03
+				15 01 00 00 00 00 02 12 04
+				15 01 00 00 00 00 02 13 1b
+				15 01 00 00 00 00 02 14 1d
+				15 01 00 00 00 00 02 15 01
+				15 01 00 00 00 00 02 16 0c
+				15 01 00 00 00 00 02 17 0f
+				15 01 00 00 00 00 02 18 1f
+				15 01 00 00 00 00 02 19 00
+				15 01 00 00 00 00 02 1a 00
+				15 01 00 00 00 00 02 1b 13
+				15 01 00 00 00 00 02 1c 16
+				15 01 00 00 00 00 02 1d 14
+				15 01 00 00 00 00 02 1e 15
+				15 01 00 00 00 00 02 1f 00
+				15 01 00 00 00 00 02 21 01
+				15 01 00 00 00 00 02 22 10
+				15 01 00 00 00 00 02 23 28
+				15 01 00 00 00 00 02 24 28
+				15 01 00 00 00 00 02 25 5d
+				15 01 00 00 00 00 02 26 28
+				15 01 00 00 00 00 02 27 28
+				15 01 00 00 00 00 02 29 d8
+				15 01 00 00 00 00 02 2a 15
+				15 01 00 00 00 00 02 2b 00
+				15 01 00 00 00 00 02 2d 00
+				15 01 00 00 00 00 02 2f 02
+				15 01 00 00 00 00 02 30 02
+				15 01 00 00 00 00 02 31 00
+				15 01 00 00 00 00 02 32 23
+				15 01 00 00 00 00 02 33 01
+				15 01 00 00 00 00 02 34 03
+				15 01 00 00 00 00 02 35 49
+				15 01 00 00 00 00 02 36 00
+				15 01 00 00 00 00 02 37 1d
+				15 01 00 00 00 00 02 38 08
+				15 01 00 00 00 00 02 39 03
+				15 01 00 00 00 00 02 3a 49
+				15 01 00 00 00 00 02 42 01
+				15 01 00 00 00 00 02 43 8c
+				15 01 00 00 00 00 02 44 a3
+				15 01 00 00 00 00 02 48 8c
+				15 01 00 00 00 00 02 49 a3
+				15 01 00 00 00 00 02 5b 00
+				15 01 00 00 00 00 02 5f 4d
+				15 01 00 00 00 00 02 63 00
+				15 01 00 00 00 00 02 67 04
+				15 01 00 00 00 00 02 6e 10
+				15 01 00 00 00 00 02 72 02
+				15 01 00 00 00 00 02 73 00
+				15 01 00 00 00 00 02 74 04
+				15 01 00 00 00 00 02 75 1b
+				15 01 00 00 00 00 02 76 05
+				15 01 00 00 00 00 02 77 01
+				15 01 00 00 00 00 02 78 00
+				15 01 00 00 00 00 02 79 00
+				15 01 00 00 00 00 02 7a 00
+				15 01 00 00 00 00 02 7b 91
+				15 01 00 00 00 00 02 7c da
+				15 01 00 00 00 00 02 7d 10
+				15 01 00 00 00 00 02 7e 04
+				15 01 00 00 00 00 02 7f 1b
+				15 01 00 00 00 00 02 80 00
+				15 01 00 00 00 00 02 81 05
+				15 01 00 00 00 00 02 82 01
+				15 01 00 00 00 00 02 83 00
+				15 01 00 00 00 00 02 84 05
+				15 01 00 00 00 00 02 85 05
+				15 01 00 00 00 00 02 86 1b
+				15 01 00 00 00 00 02 87 1b
+				15 01 00 00 00 00 02 88 1b
+				15 01 00 00 00 00 02 89 1b
+				15 01 00 00 00 00 02 8a 00
+				15 01 00 00 00 00 02 8b f0
+				15 01 00 00 00 00 02 8c 00
+				15 01 00 00 00 00 02 8f 63
+				15 01 00 00 00 00 02 90 51
+				15 01 00 00 00 00 02 91 40
+				15 01 00 00 00 00 02 92 51
+				15 01 00 00 00 00 02 93 08
+				15 01 00 00 00 00 02 94 08
+				15 01 00 00 00 00 02 95 51
+				15 01 00 00 00 00 02 96 51
+				15 01 00 00 00 00 02 97 00
+				15 01 00 00 00 00 02 98 00
+				15 01 00 00 00 00 02 99 33
+				15 01 00 00 00 00 02 9b ff
+				15 01 00 00 00 00 02 9c 01
+				15 01 00 00 00 00 02 9d 30
+				15 01 00 00 00 00 02 a5 10
+				15 01 00 00 00 00 02 a6 01
+				15 01 00 00 00 00 02 a9 21
+				15 01 00 00 00 00 02 b3 2a
+				15 01 00 00 00 00 02 b4 da
+				15 01 00 00 00 00 02 ba 83
+				15 01 00 00 00 00 02 c4 24
+				15 01 00 00 00 00 02 c5 aa
+				15 01 00 00 00 00 02 c6 09
+				15 01 00 00 00 00 02 c7 00
+				15 01 00 00 00 00 02 c9 c0
+				15 01 00 00 00 00 02 ca 04
+				15 01 00 00 00 00 02 d5 3f
+				15 01 00 00 00 00 02 d6 10
+				15 01 00 00 00 00 02 d7 3f
+				15 01 00 00 00 00 02 d8 10
+				15 01 00 00 00 00 02 d9 ee
+				15 01 00 00 00 00 02 da 49
+				15 01 00 00 00 00 02 db 94
+				15 01 00 00 00 00 02 e9 33
+				15 01 00 00 00 00 02 eb 28
+				15 01 00 00 00 00 02 ec 00
+				15 01 00 00 00 00 02 ee 00
+				15 01 00 00 00 00 02 ef 06
+				15 01 00 00 00 00 02 f0 01
+				15 01 00 00 00 00 02 f1 01
+				15 01 00 00 00 00 02 f2 0d
+				15 01 00 00 00 00 02 f3 48
+				15 01 00 00 00 00 02 f6 00
+				15 01 00 00 00 00 02 f7 00
+				15 01 00 00 00 00 02 f8 00
+				15 01 00 00 00 00 02 f9 00
+				15 01 00 00 00 00 02 ff 26
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 00 ab
+				15 01 00 00 00 00 02 01 00
+				15 01 00 00 00 00 02 02 80
+				15 01 00 00 00 00 02 03 08
+				15 01 00 00 00 00 02 04 01
+				15 01 00 00 00 00 02 05 32
+				15 01 00 00 00 00 02 06 4c
+				15 01 00 00 00 00 02 07 26
+				15 01 00 00 00 00 02 08 09
+				15 01 00 00 00 00 02 09 02
+				15 01 00 00 00 00 02 0a 32
+				15 01 00 00 00 00 02 0b 55
+				15 01 00 00 00 00 02 0c 14
+				15 01 00 00 00 00 02 0d 28
+				15 01 00 00 00 00 02 0e 40
+				15 01 00 00 00 00 02 0f 80
+				15 01 00 00 00 00 02 10 00
+				15 01 00 00 00 00 02 11 22
+				15 01 00 00 00 00 02 12 0a
+				15 01 00 00 00 00 02 13 20
+				15 01 00 00 00 00 02 14 06
+				15 01 00 00 00 00 02 15 00
+				15 01 00 00 00 00 02 16 40
+				15 01 00 00 00 00 02 19 43
+				15 01 00 00 00 00 02 1a 03
+				15 01 00 00 00 00 02 1b 25
+				15 01 00 00 00 00 02 1c 11
+				15 01 00 00 00 00 02 1d 00
+				15 01 00 00 00 00 02 1e 80
+				15 01 00 00 00 00 02 1f 00
+				15 01 00 00 00 00 02 20 03
+				15 01 00 00 00 00 02 21 03
+				15 01 00 00 00 00 02 22 25
+				15 01 00 00 00 00 02 23 25
+				15 01 00 00 00 00 02 24 00
+				15 01 00 00 00 00 02 25 a7
+				15 01 00 00 00 00 02 26 80
+				15 01 00 00 00 00 02 27 a5
+				15 01 00 00 00 00 02 28 06
+				15 01 00 00 00 00 02 29 85
+				15 01 00 00 00 00 02 2a 30
+				15 01 00 00 00 00 02 2b 97
+				15 01 00 00 00 00 02 2f 25
+				15 01 00 00 00 00 02 30 26
+				15 01 00 00 00 00 02 31 41
+				15 01 00 00 00 00 02 32 04
+				15 01 00 00 00 00 02 33 04
+				15 01 00 00 00 00 02 34 2b
+				15 01 00 00 00 00 02 35 00
+				15 01 00 00 00 00 02 36 00
+				15 01 00 00 00 00 02 37 c8
+				15 01 00 00 00 00 02 38 26
+				15 01 00 00 00 00 02 39 25
+				15 01 00 00 00 00 02 3a 26
+				15 01 00 00 00 00 02 3f eb
+				15 01 00 00 00 00 02 41 21
+				15 01 00 00 00 00 02 42 03
+				15 01 00 00 00 00 02 43 00
+				15 01 00 00 00 00 02 44 11
+				15 01 00 00 00 00 02 45 00
+				15 01 00 00 00 00 02 46 00
+				15 01 00 00 00 00 02 47 00
+				15 01 00 00 00 00 02 48 03
+				15 01 00 00 00 00 02 49 03
+				15 01 00 00 00 00 02 4a 00
+				15 01 00 00 00 00 02 4b 00
+				15 01 00 00 00 00 02 4c 01
+				15 01 00 00 00 00 02 4d 4e
+				15 01 00 00 00 00 02 4e 01
+				15 01 00 00 00 00 02 4f 4c
+				15 01 00 00 00 00 02 50 0d
+				15 01 00 00 00 00 02 51 0e
+				15 01 00 00 00 00 02 52 20
+				15 01 00 00 00 00 02 53 97
+				15 01 00 00 00 00 02 54 4b
+				15 01 00 00 00 00 02 55 4c
+				15 01 00 00 00 00 02 56 20
+				15 01 00 00 00 00 02 58 04
+				15 01 00 00 00 00 02 59 04
+				15 01 00 00 00 00 02 5a 09
+				15 01 00 00 00 00 02 5b 00
+				15 01 00 00 00 00 02 5c 00
+				15 01 00 00 00 00 02 5d c8
+				15 01 00 00 00 00 02 5e 4c
+				15 01 00 00 00 00 02 5f 4b
+				15 01 00 00 00 00 02 60 00
+				15 01 00 00 00 00 02 80 2b
+				15 01 00 00 00 00 02 81 43
+				15 01 00 00 00 00 02 82 03
+				15 01 00 00 00 00 02 83 25
+				15 01 00 00 00 00 02 84 11
+				15 01 00 00 00 00 02 85 00
+				15 01 00 00 00 00 02 86 80
+				15 01 00 00 00 00 02 87 00
+				15 01 00 00 00 00 02 88 00
+				15 01 00 00 00 00 02 89 03
+				15 01 00 00 00 00 02 8a 22
+				15 01 00 00 00 00 02 8b 25
+				15 01 00 00 00 00 02 8c 00
+				15 01 00 00 00 00 02 8d a4
+				15 01 00 00 00 00 02 8e 00
+				15 01 00 00 00 00 02 8f a2
+				15 01 00 00 00 00 02 90 06
+				15 01 00 00 00 00 02 91 63
+				15 01 00 00 00 00 02 92 30
+				15 01 00 00 00 00 02 93 97
+				15 01 00 00 00 00 02 94 25
+				15 01 00 00 00 00 02 95 26
+				15 01 00 00 00 00 02 96 41
+				15 01 00 00 00 00 02 97 04
+				15 01 00 00 00 00 02 98 04
+				15 01 00 00 00 00 02 99 f0
+				15 01 00 00 00 00 02 9a 00
+				15 01 00 00 00 00 02 9b 00
+				15 01 00 00 00 00 02 9c c8
+				15 01 00 00 00 00 02 9d 50
+				15 01 00 00 00 00 02 9e 26
+				15 01 00 00 00 00 02 9f 25
+				15 01 00 00 00 00 02 a0 26
+				15 01 00 00 00 00 02 a2 00
+				15 01 00 00 00 00 02 a3 33
+				15 01 00 00 00 00 02 a5 40
+				15 01 00 00 00 00 02 a6 40
+				15 01 00 00 00 00 02 ac 91
+				15 01 00 00 00 00 02 ad 66
+				15 01 00 00 00 00 02 ae 66
+				15 01 00 00 00 00 02 b1 40
+				15 01 00 00 00 00 02 b2 40
+				15 01 00 00 00 00 02 b4 40
+				15 01 00 00 00 00 02 b5 40
+				15 01 00 00 00 00 02 b7 40
+				15 01 00 00 00 00 02 b8 40
+				15 01 00 00 00 00 02 ba 22
+				15 01 00 00 00 00 02 bb 00
+				15 01 00 00 00 00 02 c2 01
+				15 01 00 00 00 00 02 c3 01
+				15 01 00 00 00 00 02 c4 01
+				15 01 00 00 00 00 02 c5 01
+				15 01 00 00 00 00 02 c6 01
+				15 01 00 00 00 00 02 c8 00
+				15 01 00 00 00 00 02 c9 00
+				15 01 00 00 00 00 02 ca 00
+				15 01 00 00 00 00 02 cd 00
+				15 01 00 00 00 00 02 ce 00
+				15 01 00 00 00 00 02 d6 04
+				15 01 00 00 00 00 02 d7 00
+				15 01 00 00 00 00 02 d8 0d
+				15 01 00 00 00 00 02 d9 00
+				15 01 00 00 00 00 02 da 00
+				15 01 00 00 00 00 02 db 00
+				15 01 00 00 00 00 02 dc 00
+				15 01 00 00 00 00 02 dd 00
+				15 01 00 00 00 00 02 de 00
+				15 01 00 00 00 00 02 df 01
+				15 01 00 00 00 00 02 e0 00
+				15 01 00 00 00 00 02 e1 00
+				15 01 00 00 00 00 02 e2 19
+				15 01 00 00 00 00 02 e3 04
+				15 01 00 00 00 00 02 e4 00
+				15 01 00 00 00 00 02 e5 04
+				15 01 00 00 00 00 02 e6 00
+				15 01 00 00 00 00 02 e7 12
+				15 01 00 00 00 00 02 e8 00
+				15 01 00 00 00 00 02 e9 50
+				15 01 00 00 00 00 02 ea 10
+				15 01 00 00 00 00 02 eb 02
+				15 01 00 00 00 00 02 ff 27
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 ff 28
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 60 0a
+				15 01 00 00 00 00 02 63 32
+				15 01 00 00 00 00 02 64 01
+				15 01 00 00 00 00 02 68 da
+				15 01 00 00 00 00 02 69 00
+				15 01 00 00 00 00 02 ff 29
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 60 0a
+				15 01 00 00 00 00 02 63 32
+				15 01 00 00 00 00 02 64 01
+				15 01 00 00 00 00 02 68 da
+				15 01 00 00 00 00 02 69 00
+				15 01 00 00 00 00 02 ff e0
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 35 40
+				15 01 00 00 00 00 02 36 40
+				15 01 00 00 00 00 02 37 00
+				15 01 00 00 00 00 02 89 c6
+				15 01 00 00 00 00 02 ff f0
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 ea 40
+				15 01 00 00 00 00 02 ff 10
+				15 01 00 00 00 00 02 36 00
+				15 01 00 00 00 00 02 35 00
+				39 01 00 00 00 00 03 44 03 e8
+				15 01 00 00 00 00 02 51 ff
+				15 01 00 00 00 00 02 53 2c
+				15 01 00 00 00 00 02 55 01
+				05 01 00 00 0a 00 02 20 00
+				15 01 00 00 00 00 02 bb 10
+				05 01 00 00 78 00 02 11 00
+				05 01 00 00 14 00 02 29 00];
+		qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+				05 01 00 00 78 00 02 10 00];
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,cmd-sync-wait-broadcast;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-panel-timings =
+			[da 34 24 00 64 68 28 38 2a 03 04 00];
+		qcom,mdss-dsi-t-clk-pre = <0x29>;
+		qcom,mdss-dsi-t-clk-post = <0x03>;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-lp11-init;
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+		qcom,mdss-dsi-bl-min-level = <1>;
+		qcom,mdss-dsi-bl-max-level = <4095>;
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-oppo19365samsung-ams643xf01-1080-2400-dsi-cmd.dtsi

@@ -0,0 +1,324 @@
+&mdss_mdp {
+	dsi_oppo19365samsung_ams643xf01_1080_2400_cmd: qcom,mdss_dsi_oppo19365samsung_ams643xf01_1080_2400_cmd {
+		qcom,mdss-dsi-panel-name =
+		  "samsung ams643xf01 amoled fhd+ panel without DSC";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15000 15500 34000
+			16000 13250 34500 7500 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4300000>;
+		qcom,mdss-dsi-panel-blackness-level = <1023>;
+		qcom,mdss-pan-physical-width-dimension = <68>;
+		qcom,mdss-pan-physical-height-dimension = <152>;
+		qcom,esd-check-enabled;
+		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+		qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00];
+		qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-panel-status-value = <0x9C>;
+		qcom,mdss-dsi-panel-status-read-length = <1>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-clockrate = <1107000000>;
+				qcom,mdss-mdp-transfer-time-us = <9000>;
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2400>;
+				qcom,mdss-dsi-h-front-porch = <8>;
+				qcom,mdss-dsi-h-back-porch = <8>;
+				qcom,mdss-dsi-h-pulse-width = <24>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <6>;
+				qcom,mdss-dsi-v-front-porch = <8>;
+				qcom,mdss-dsi-v-pulse-width = <4>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				//qcom,mdss-dsi-panel-phy-timings = [00 22 05 09 25 23 09 09 06 03 04 00];
+				qcom,display-topology = <1 0 1>;
+				qcom,default-topology-index = <0>;
+				oppo,fod-on-vblank = <2>;
+				oppo,fod-off-vblank = <0>;
+
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 03 FC 5A 5A
+					39 01 00 00 00 00 02 B0 0C
+					39 01 00 00 00 00 02 FF 10
+					39 01 00 00 00 00 02 B0 22
+					39 01 00 00 00 00 02 D1 1E
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 0A 00 03 FC A5 A5
+					05 01 00 00 15 00 01 11
+					/* TE vsync ON */
+					39 01 00 00 00 00 03 9F A5 A5
+					15 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 03 9F 5A 5A
+					/* CASET/PASET Setting */
+					39 01 00 00 00 00 05 2A 00 00 04 37
+					39 01 00 00 00 00 05 2B 00 00 09 5F
+					/* Err_FG Setting */
+					//39 01 00 00 00 00 03 F0 5A 5A
+					//39 01 00 00 00 00 03 FC 5A 5A
+					//39 01 00 00 00 00 07 E1 00 00 02 02 42 02
+					//39 01 00 00 00 00 07 E2 00 00 00 00 00 00
+					//15 01 00 00 00 00 02 B0 0C
+					//15 01 00 00 00 00 02 E1 19
+					//39 01 00 00 00 00 03 F0 A5 A5
+					//39 01 00 00 00 00 03 FC A5 A5
+					/* FD Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 06
+					15 01 00 00 00 00 02 D5 20
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* TSP H_sync ON */
+					//39 01 00 00 00 00 03 F0 5A 5A
+					//15 01 00 00 00 00 02 B0 09
+					//39 01 00 00 00 00 03 E8 10 30
+					//39 01 00 00 00 00 03 F0 A5 A5
+					/* ESD Setting */
+					//39 01 00 00 00 00 03 FC 5A 5A
+					//15 01 00 00 00 00 02 B0 01
+					//15 01 00 00 00 00 02 E3 A8
+					//15 01 00 00 00 00 02 B0 07
+					//15 01 00 00 00 00 02 ED 67
+					//39 01 00 00 3C 00 03 FC A5 A5
+					/* Backlight Dimming Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 B0 07
+					39 01 00 00 00 00 02 B7 16
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 02 53 20
+					/* ACL off */
+					15 01 00 00 00 00 02 55 00
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 DD
+					15 01 00 00 00 00 02 B9 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* FFC Setting 90.25M*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 0C E9 11 65 A5 68 2C A9 12 8C 00 1A B8
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* SPR Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 03 B6 00 1A
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Seed CRC mode enable */
+					39 01 00 00 00 00 03 81 92 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E8 00 04 00 FF 02 00 00 FF 14 FF DE FD 00 DE FF ED 00 FF FF FF
+					39 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Seed Tcs On */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 22
+					15 01 00 00 00 00 02 B3 91
+					15 01 00 00 00 00 02 83 00
+					15 01 00 00 00 00 02 B3 C0
+					39 01 00 00 6F 00 03 F0 A5 A5
+					/* Display On*/
+					//39 01 00 00 6F 00 03 9F A5 A5
+					//05 01 00 00 00 00 01 29
+					//39 01 00 00 00 00 03 9F 5A 5A
+					];
+				qcom,mdss-dsi-post-on-backlight = [
+					/* Display On*/
+					39 01 00 00 00 00 03 9F A5 A5
+					05 01 00 00 00 00 01 29
+					05 01 00 00 00 00 01 13
+					39 01 00 00 00 00 03 9F 5A 5A
+				];
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 16 00 01 28
+					05 01 00 00 96 00 01 10
+				];
+				qcom,mdss-dsi-lp1-command = [
+					/*AOD on */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 60 00
+					39 01 00 00 00 00 02 53 22
+					39 01 00 00 00 00 02 B0 A3
+					39 01 00 00 00 00 02 C7 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-nolp-command = [
+					/* AOD off to normal*/
+					//05 01 00 00 22 00 01 28
+					15 01 00 00 00 00 02 53 20
+					39 01 00 00 00 00 03 9F 5A 5A
+					05 01 00 00 00 00 01 29
+					39 01 00 00 00 00 03 9F A5 A5
+				];
+				qcom,mdss-dsi-aod-hbm-on-command = [
+					/* HBM Mode ON */
+					39 01 00 00 00 00 02 53 E0
+					/* 0xE0 Normal transition */
+					39 01 00 00 00 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-aod-hbm-off-command = [
+					15 01 00 00 00 00 02 53 22
+					39 01 00 00 00 00 03 51 00 01
+				];
+				qcom,mdss-dsi-hbm-on-command = [
+					15 01 00 00 00 00 02 53 E0
+					39 01 00 00 22 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-hbm-off-command = [
+					15 01 00 00 00 00 02 53 20
+				];
+				qcom,mdss-dsi-normal-hbm-on-command = [
+					15 01 00 00 00 00 02 53 E0
+					39 01 00 00 00 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-aod-high-mode-command = [
+					/* AOD 50nit */
+					15 01 00 00 00 00 02 53 22
+				];
+				qcom,mdss-dsi-aod-low-mode-command = [
+					/* AOD 10nit */
+					15 01 00 00 00 00 02 53 23
+				];
+				qcom,mdss-dsi-seed-off-command = [
+					/* TCS OFF */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B3 C1
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* CRC OFF */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 81 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-0-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 92 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC DCI-P3 */
+					39 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E8 00 04 00 FF 02 00 00 FF 14 FF DE FD 00 DE FF ED 00 FF FF FF
+					/* SEED CRC ON */
+					39 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-1-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 90 00
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC sRGB */
+					39 01 00 00 00 00 02 B0 01
+					39 01 00 00 00 00 16 B1 BB 01 05 39 D5 15 06 07 C1 47 F2 D5 CB 0B C1 F4 E8 1D FF FF FF
+					/* SEED CRC ON */
+					39 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-2-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 92 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC DCI-P3 */
+					39 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E8 00 04 00 FF 02 00 00 FF 14 FF DE FD 00 DE FF ED 00 FF FF FF
+					/* SEED CRC ON */
+					39 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-osc-clk-mode0-command = [
+					/* 90.25Mhz */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 0C E9 11 65 A5 68 2C A9 12 8C 00 1A B8
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-osc-clk-mode1-command = [
+					/* 88.9Mhz */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 0C E9 11 65 A5 68 2C AB A3 D2 00 1A B8
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-enter-command = [
+					/*ENTER*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 B0 1E
+					39 01 00 00 00 00 08 B7 05 05 05 05 05 05 05
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-exit-command = [
+					/*EXIT*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 B0 1E
+					39 01 00 00 00 00 08 B7 05 04 03 03 01 00 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-aod-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-aod-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-0-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-1-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-2-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-osc-clk-mode0-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-osc-clk-mode1-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-seed-enter-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-exit-command-state = "dsi_hs_mode";
+			};
+
+		};
+	};
+};
+
+&dsi_oppo19365samsung_ams643xf01_1080_2400_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-normal-max-level = <1023>;
+	qcom,mdss-dsi-bl-max-level = <2047>;
+	qcom,mdss-brightness-normal-max-level = <1023>;
+	qcom,mdss-brightness-max-level = <2047>;
+	qcom,mdss-dsi-bl-default-level = <400>;
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+	oppo,mdss-dsi-vendor-name = "ams643xf01";
+	oppo,mdss-dsi-manufacture = "samsung1024";
+
+	qcom,ulps-enabled;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+				"src_byte_clk0", "src_pixel_clk0",
+				"shadow_byte_clk0", "shadow_pixel_clk0";
+	qcom,mdss-dsi-t-clk-post = <0x1A>;
+	qcom,mdss-dsi-t-clk-pre = <0x1F>;
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			//qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 06 04 02 04 00];
+			qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 09 02 04 00];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-oppo19365samsung-ams644vk01-1080-2400-dsi-cmd.dtsi

@@ -0,0 +1,309 @@
+&mdss_mdp {
+	dsi_oppo19365samsung_ams644vk01_1080_2400_cmd: qcom,mdss_dsi_oppo19365samsung_ams644vk01_1080_2400_cmd {
+		qcom,mdss-dsi-panel-name =
+		  "samsung ams644vk01 amoled fhd+ panel without DSC";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15000 15500 34000
+			16000 13250 34500 7500 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4300000>;
+		qcom,mdss-dsi-panel-blackness-level = <1023>;
+		qcom,mdss-pan-physical-width-dimension = <68>;
+		qcom,mdss-pan-physical-height-dimension = <152>;
+		//qcom,esd-check-enabled;
+		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+		qcom,mdss-dsi-panel-status-command = [
+						06 01 00 01 05 00 02 0A 00
+						];
+		qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-panel-status-value = <0x9C>;
+		qcom,mdss-dsi-panel-status-read-length = <1>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-clockrate = <1107800000>;
+				//qcom,mdss-mdp-transfer-time-us = <9000>;
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2400>;
+				qcom,mdss-dsi-h-front-porch = <8>;
+				qcom,mdss-dsi-h-back-porch = <8>;
+				qcom,mdss-dsi-h-pulse-width = <24>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <6>;
+				qcom,mdss-dsi-v-front-porch = <8>;
+				qcom,mdss-dsi-v-pulse-width = <4>;
+				qcom,mdss-dsi-panel-framerate = <61>;
+				//qcom,mdss-dsi-panel-phy-timings = [00 22 05 09 25 23 09 09 06 03 04 00];
+				qcom,display-topology = <1 0 1>;
+				qcom,default-topology-index = <0>;
+				oppo,fod-on-vblank = <1>;
+				oppo,fod-off-vblank = <1>;
+
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 03 9F A5 A5
+					05 01 00 00 0A 00 01 11
+					39 01 00 00 00 00 03 9F 5A 5A
+					/* FD setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 03
+					15 01 00 00 14 00 02 CD 04
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* TE vsync ON */
+					39 01 00 00 00 00 03 9F A5 A5
+					15 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 03 9F 5A 5A
+					/* MIC setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 08 EB 17 41 92 0E 10 82 5A
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* CASET/PASET Setting */
+					39 01 00 00 00 00 05 2A 00 00 04 37
+					39 01 00 00 00 00 05 2B 00 00 09 5F
+					/* TSP H_sync ON */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 09
+					39 01 00 00 00 00 03 E8 10 30
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* ESD Setting */
+					39 01 00 00 00 00 03 FC 5A 5A
+					15 01 00 00 00 00 02 B0 01
+					15 01 00 00 00 00 02 E3 A8
+					15 01 00 00 00 00 02 B0 07
+					15 01 00 00 00 00 02 ED 67
+					39 01 00 00 3C 00 03 FC A5 A5
+					/* Backlight Dimming Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 07
+					15 01 00 00 00 00 02 B7 01
+					15 01 00 00 00 00 02 B0 08
+					15 01 00 00 00 00 02 B7 12
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 02 53 28
+					/* ACL off */
+					15 01 00 00 00 00 02 55 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Normal mode */
+					15 01 00 00 00 00 02 53 20
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 DE
+					15 01 00 00 00 00 02 B9 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Seed CRC mode enable */
+					15 01 00 00 00 00 02 81 90
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 02
+					39 01 00 00 00 00 16 B1 CA 00 00 1B D6 00 0C 0A E8 2C FD E0 F0 0C E3 F2 ED 01 FF FF FF
+					39 01 00 00 00 00 03 B1 00 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Seed Tcs On */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 23
+					15 01 00 00 00 00 02 B3 91
+					15 01 00 00 00 00 02 83 80
+					39 01 00 00 00 00 03 B3 00 C0
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Display On*/
+					39 01 00 00 00 00 03 9F A5 A5
+					05 01 00 00 00 00 01 29
+					39 01 00 00 00 00 03 9F 5A 5A
+					];
+				qcom,mdss-dsi-post-on-backlight = [
+					05 01 00 00 00 00 01 29
+				];
+				qcom,mdss-dsi-off-command = [
+					//39 01 00 00 00 00 03 9F A5 A5
+					//05 01 00 00 14 00 01 29
+					05 01 00 00 14 00 01 28
+					05 01 00 00 96 00 01 10
+					//39 01 00 00 96 00 03 9F 5a 5a
+				];
+				qcom,mdss-dsi-lp1-command = [
+					39 01 00 00 00 00 03 9F 5A 5A
+					15 01 00 00 25 00 01 28
+					39 01 00 00 00 00 03 9F A5 A5
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 60 00
+					39 01 00 00 00 00 02 53 23
+					39 01 00 00 00 00 02 B0 32
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 B0 07
+					39 01 00 00 00 00 02 F4 5B
+					39 01 00 00 00 00 03 F0 A5 A5
+					];
+				qcom,mdss-dsi-nolp-command = [
+					/* 90hz Transition */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 53 20
+					39 01 00 00 00 00 02 B0 32
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 03 9F 5A 5A
+					15 01 00 00 00 00 01 13
+					15 01 00 00 00 00 01 29
+					39 01 00 00 00 00 03 9F A5 A5
+					];
+				qcom,mdss-dsi-aod-hbm-on-command = [
+					/* HBM Mode ON */
+					39 01 00 00 00 00 02 53 E0
+					/* 0xE0 Normal transition */
+					39 01 00 00 00 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-aod-hbm-off-command = [
+					15 01 00 00 00 00 02 53 23
+					39 01 00 00 00 00 03 51 00 01
+				];
+				qcom,mdss-dsi-hbm-on-command = [
+					15 01 00 00 00 00 02 53 E0
+					39 01 00 00 22 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-hbm-off-command = [
+					15 01 00 00 00 00 02 53 20
+				];
+				qcom,mdss-dsi-normal-hbm-on-command = [
+					15 01 00 00 00 00 02 53 E0
+					39 01 00 00 00 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-aod-high-mode-command = [
+					/* AOD 50nit */
+					15 01 00 00 00 00 02 53 22
+				];
+				qcom,mdss-dsi-aod-low-mode-command = [
+					/* AOD 10nit */
+					15 01 00 00 00 00 02 53 23
+				];
+				qcom,mdss-dsi-seed-off-command = [
+					/* TCS OFF */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B2 83
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* CRC OFF */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B1 01
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-0-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC P3 */
+					15 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E4 05 00 07 E0 01 0C 02 F0 18 FA E3 FB 0A DF F9 F5 01 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-1-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 00
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC SRGB RGB */
+					15 01 00 00 00 00 02 B0 01
+					39 01 00 00 00 00 16 B1 B2 0D 04 37 D5 13 0C 02 C8 49 F3 DC D1 14 CA EB EA 18 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-2-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC P3 */
+					15 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E4 05 00 07 E0 01 0C 02 F0 18 FA E3 FB 0A DF F9 F5 01 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-osc-clk-mode0-command = [
+					/* 139.6Mhz */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 C4
+					15 01 00 00 00 00 02 B0 04
+					39 01 00 00 00 00 06 F8 41 45 22 2C 2C
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 CC
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-osc-clk-mode1-command = [
+					/* 136.3Mhz */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 C4
+					15 01 00 00 00 00 02 B0 04
+					39 01 00 00 00 00 06 F8 41 69 22 5B 5B
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 CC
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-aod-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-aod-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-0-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-1-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-2-command-state = "dsi_hs_mode";
+			};
+
+		};
+	};
+};
+
+&dsi_oppo19365samsung_ams644vk01_1080_2400_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <2047>;
+	qcom,mdss-brightness-max-level = <2047>;
+	qcom,mdss-brightness-default-level = <400>;
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+	oppo,mdss-dsi-vendor-name = "ams644vk01";
+	oppo,mdss-dsi-manufacture = "samsung1024";
+
+	qcom,ulps-enabled;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+				"src_byte_clk0", "src_pixel_clk0",
+				"shadow_byte_clk0", "shadow_pixel_clk0";
+	qcom,mdss-dsi-t-clk-post = <0x0E>;
+	qcom,mdss-dsi-t-clk-pre = <0x35>;
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 06 04 02 04 00];
+
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-oppo19567samsung-amb655uv01-1080-2400-90fps.dtsi

@@ -0,0 +1,609 @@
+&mdss_mdp {
+	dsi_oppo19567samsung_amb655uv01_1080_2400_cmd: qcom,mdss_dsi_oppo19567samsung_amb655uv01_1080_2400_cmd {
+		qcom,mdss-dsi-panel-name =
+		  "samsung amb655uv01 amoled fhd+ panel no DSC";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15000 15500 34000
+			16000 13250 34500 7500 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4300000>;
+		qcom,mdss-dsi-panel-blackness-level = <1023>;
+		qcom,mdss-pan-physical-width-dimension = <68>;
+		qcom,mdss-pan-physical-height-dimension = <152>;
+		qcom,esd-check-enabled;
+		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+		qcom,mdss-dsi-panel-status-command = [
+						06 01 00 01 05 00 02 EA 00
+						06 01 00 01 05 00 02 EE 00
+						06 01 00 01 05 00 02 0A 00
+						];
+		qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-panel-status-value = <
+						0x00 0x00 0x9C
+						0x00 0x80 0x9C
+						0x80 0x00 0x9C
+						0x80 0x80 0x9C
+						>;
+		qcom,mdss-dsi-panel-status-read-length = <1 1 1>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-clockrate = <1702800000>;
+				qcom,mdss-mdp-transfer-time-us = <9000>;
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2400>;
+				qcom,mdss-dsi-h-front-porch = <8>;
+				qcom,mdss-dsi-h-back-porch = <8>;
+				qcom,mdss-dsi-h-pulse-width = <24>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <6>;
+				qcom,mdss-dsi-v-front-porch = <8>;
+				qcom,mdss-dsi-v-pulse-width = <4>;
+				qcom,mdss-dsi-panel-framerate = <90>;
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 03 9f 5A 5A
+					05 01 00 00 14 00 01 11
+					/* TE ON */
+					15 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 03 9F A5 A5
+					/* CASET/PASET Setting */
+					39 01 00 00 00 00 05 2A 00 00 04 37
+					39 01 00 00 00 00 05 2B 00 00 09 5F
+					/* TSP SYNC ON */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 05
+					39 01 00 00 00 00 04 D7 07 02 40
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Driver-IC Initial Code */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 03 F1 5A 5A
+					39 01 00 00 00 00 04 E5 13 E8 FC
+					39 01 00 00 00 00 02 ED 97
+					39 01 00 00 00 00 02 B0 1A
+					39 01 00 00 00 00 02 F9 20
+					39 01 00 00 00 00 03 F1 A5 A5
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Dimming Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 06
+					15 01 00 00 00 00 02 B7 00
+					15 01 00 00 00 00 02 B0 05
+					15 01 00 00 00 00 02 B7 13
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* ACL Mode */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 55 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* SEED LP ON */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 29 BD
+					   00 FF FF 09 15 00 73 18
+					   00 00 09 15 43 92 00 44
+					   44 00 09 15 43 92 00 22
+					   22 09 15 43 92 00 11 11
+					   00 09 15 43 92 00 00 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* LP Disable */
+					15 01 00 00 00 00 02 8B 00
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC P3 */
+					15 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E4 05 00 07 E0 01 0C 02 F0 18 FA E3 FB 0A DF F9 F5 01 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/*FB_Delay*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 B0 3B
+					39 01 00 00 00 00 02 F5 25
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* 90hz Transition */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 60 10
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* T2M Clk Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 F5 85
+					15 01 00 00 00 00 02 B0 01
+					15 01 00 00 00 00 02 F5 77
+					15 01 00 00 00 00 02 B0 03
+					39 01 00 00 00 00 05 F5 10 40 10 40
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Normal mode */
+					15 01 00 00 6E 00 02 53 20
+					/* Display ON */
+					39 01 00 00 00 00 03 9F 5A 5A
+					15 01 00 00 00 00 01 13
+					15 01 00 00 00 00 01 29
+					39 01 00 00 00 00 03 9F A5 A5
+				];
+				qcom,mdss-dsi-post-on-backlight = [
+					/* T2M Clk Fixed Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 F5 87
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 03 9F 5A 5A
+					05 01 00 00 00 00 01 29
+					05 01 00 00 00 00 01 13
+					39 01 00 00 00 00 03 9F A5 A5
+				];
+				qcom,mdss-dsi-timing-switch-command = [
+					/* 90hz Transition */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 60 10
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-off-command = [
+					39 01 00 00 00 00 03 9F 5A 5A
+					05 01 00 00 14 00 01 29
+					05 01 00 00 14 00 01 28
+					05 01 00 00 00 00 01 10
+					39 01 00 00 96 00 03 9F A5 A5
+				];
+				qcom,mdss-dsi-lp1-command = [
+					39 01 00 00 00 00 03 9F 5A 5A
+					15 01 00 00 25 00 01 28
+					39 01 00 00 00 00 03 9F A5 A5
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 60 00
+					39 01 00 00 00 00 02 53 23
+					39 01 00 00 00 00 02 B0 32
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 B0 07
+					39 01 00 00 00 00 02 F4 5B
+					39 01 00 00 00 00 03 F0 A5 A5
+					];
+				qcom,mdss-dsi-nolp-command = [
+					/* 90hz Transition */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 60 10
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 53 20
+					39 01 00 00 00 00 02 B0 32
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 03 9F 5A 5A
+					15 01 00 00 00 00 01 13
+					15 01 00 00 00 00 01 29
+					39 01 00 00 00 00 03 9F A5 A5
+					];
+				qcom,mdss-dsi-aod-hbm-on-command = [
+					/* HBM Mode ON */
+					39 01 00 00 00 00 02 53 E0
+					/* 0xE0 Normal transition */
+					39 01 00 00 00 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-aod-hbm-off-command = [
+					15 01 00 00 00 00 02 53 23
+					39 01 00 00 00 00 03 51 00 01
+				];
+				qcom,mdss-dsi-hbm-on-command = [
+					15 01 00 00 00 00 02 53 E0
+					39 01 00 00 22 00 03 51 07 FF
+				];
+				com,mdss-dsi-hbm-off-command = [
+					15 01 00 00 00 00 02 53 20
+				];
+				qcom,mdss-dsi-normal-hbm-on-command = [
+					15 01 00 00 00 00 02 53 E0
+					39 01 00 00 00 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-aod-high-mode-command = [
+					/* AOD 50nit */
+					15 01 00 00 00 00 02 53 22
+				];
+				qcom,mdss-dsi-aod-low-mode-command = [
+					/* AOD 10nit */
+					15 01 00 00 00 00 02 53 23
+				];
+				qcom,mdss-dsi-seed-off-command = [
+					/* TCS OFF */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B2 83
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* CRC OFF */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B1 01
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-0-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC P3 */
+					15 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E4 05 00 07 E0 01 0C 02 F0 18 FA E3 FB 0A DF F9 F5 01 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-1-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 00
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC SRGB RGB */
+					15 01 00 00 00 00 02 B0 01
+					39 01 00 00 00 00 16 B1 B2 0D 04 37 D5 13 0C 02 C8 49 F3 DC D1 14 CA EB EA 18 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-2-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC P3 */
+					15 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E4 05 00 07 E0 01 0C 02 F0 18 FA E3 FB 0A DF F9 F5 01 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-osc-clk-mode0-command = [
+					/* 139.6Mhz */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 C4
+					15 01 00 00 00 00 02 B0 04
+					39 01 00 00 00 00 06 F8 41 45 22 2C 2C
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 CC
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-osc-clk-mode1-command = [
+					/* 136.3Mhz */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 C4
+					15 01 00 00 00 00 02 B0 04
+					39 01 00 00 00 00 06 F8 41 69 22 5B 5B
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 CC
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-aod-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-aod-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-0-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-1-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-2-command-state = "dsi_hs_mode";
+			};
+
+			timing@1{
+				qcom,mdss-dsi-panel-clockrate = <1202800000>;
+				qcom,mdss-mdp-transfer-time-us = <14000>;
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2400>;
+				qcom,mdss-dsi-h-front-porch = <8>;
+				qcom,mdss-dsi-h-back-porch = <8>;
+				qcom,mdss-dsi-h-pulse-width = <24>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <6>;
+				qcom,mdss-dsi-v-front-porch = <8>;
+				qcom,mdss-dsi-v-pulse-width = <4>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 03 9f 5A 5A
+					05 01 00 00 14 00 01 11
+					/* TE ON */
+					15 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 03 9F A5 A5
+					/* CASET/PASET Setting */
+					39 01 00 00 00 00 05 2A 00 00 04 37
+					39 01 00 00 00 00 05 2B 00 00 09 5F
+					/* TSP SYNC ON */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 05
+					39 01 00 00 00 00 04 D7 07 02 40
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Driver-IC Initial Code */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 03 F1 5A 5A
+					39 01 00 00 00 00 04 E5 13 E8 FC
+					39 01 00 00 00 00 02 ED 97
+					39 01 00 00 00 00 02 B0 1A
+					39 01 00 00 00 00 02 F9 20
+					39 01 00 00 00 00 03 F1 A5 A5
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Dimming Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 06
+					15 01 00 00 00 00 02 B7 00
+					15 01 00 00 00 00 02 B0 05
+					15 01 00 00 00 00 02 B7 13
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* ACL Mode */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 55 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* SEED LP ON */
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 29 BD
+					   00 FF FF 09 15 00 73 18
+					   00 00 09 15 43 92 00 44
+					   44 00 09 15 43 92 00 22
+					   22 09 15 43 92 00 11 11
+					   00 09 15 43 92 00 00 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* LP Disable */
+					15 01 00 00 00 00 02 8B 00
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC P3 */
+					15 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E4 05 00 07 E0 01 0C 02 F0 18 FA E3 FB 0A DF F9 F5 01 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/*FB_Delay*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 B0 3B
+					39 01 00 00 00 00 02 F5 25
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* 60hz Transition */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 60 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* T2M Clk Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 F5 85
+					15 01 00 00 00 00 02 B0 01
+					15 01 00 00 00 00 02 F5 77
+					15 01 00 00 00 00 02 B0 03
+					39 01 00 00 00 00 05 F5 10 40 10 40
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* Normal mode */
+					15 01 00 00 6E 00 02 53 20
+					/* Display ON */
+					39 01 00 00 00 00 03 9F 5A 5A
+					15 01 00 00 00 00 01 13
+					15 01 00 00 00 00 01 29
+					39 01 00 00 00 00 03 9F A5 A5
+				];
+				qcom,mdss-dsi-post-on-backlight = [
+					/* T2M Clk Fixed Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 F5 87
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 03 9F 5A 5A
+					05 01 00 00 00 00 01 29
+					05 01 00 00 00 00 01 13
+					39 01 00 00 00 00 03 9F A5 A5
+				];
+				qcom,mdss-dsi-timing-switch-command = [
+					/* 60hz Transition */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 60 00
+					39 01 00 00 10 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-off-command = [
+					39 01 00 00 00 00 03 9F 5A 5A
+					05 01 00 00 14 00 01 29
+					05 01 00 00 14 00 01 28
+					05 01 00 00 00 00 01 10
+					39 01 00 00 96 00 03 9F A5 A5
+				];
+				qcom,mdss-dsi-lp1-command = [
+					39 01 00 00 00 00 03 9F 5A 5A
+					15 01 00 00 25 00 01 28
+					39 01 00 00 00 00 03 9F A5 A5
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 60 00
+					39 01 00 00 00 00 02 53 23
+					39 01 00 00 00 00 02 B0 32
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 B0 07
+					39 01 00 00 00 00 02 F4 5B
+					39 01 00 00 00 00 03 F0 A5 A5
+					];
+				qcom,mdss-dsi-nolp-command = [
+					/* 60hz Transition */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 60 00
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 03 f0 5a 5a
+					15 01 00 00 00 00 02 53 20
+					15 01 00 00 00 00 02 b0 32
+					39 01 00 00 00 00 03 f0 a5 a5
+					39 01 00 00 00 00 03 9F 5A 5A
+					15 01 00 00 00 00 01 13
+					15 01 00 00 00 00 01 29
+					39 01 00 00 00 00 03 9F A5 A5
+					];
+				qcom,mdss-dsi-aod-hbm-on-command = [
+					/* HBM Mode ON */
+					39 01 00 00 00 00 02 53 E0
+					/* 0xE0 Normal transition */
+					39 01 00 00 00 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-aod-hbm-off-command = [
+					15 01 00 00 00 00 02 53 23
+					39 01 00 00 00 00 03 51 00 01
+				];
+				qcom,mdss-dsi-hbm-on-command = [
+					15 01 00 00 00 00 02 53 E0
+					39 01 00 00 22 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-hbm-off-command = [
+					15 01 00 00 00 00 02 53 20
+				];
+				qcom,mdss-dsi-normal-hbm-on-command = [
+					15 01 00 00 00 00 02 53 E0
+					39 01 00 00 00 00 03 51 07 FF
+				];
+				qcom,mdss-dsi-aod-high-mode-command = [
+					/* AOD 50nit */
+					15 01 00 00 00 00 02 53 22
+				];
+				qcom,mdss-dsi-aod-low-mode-command = [
+					/* AOD 10nit */
+					15 01 00 00 00 00 02 53 23
+				];
+				qcom,mdss-dsi-seed-off-command = [
+					/* TCS OFF */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B2 83
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* CRC OFF */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B1 01
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-0-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC P3 */
+					15 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E4 05 00 07 E0 01 0C 02 F0 18 FA E3 FB 0A DF F9 F5 01 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-1-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 00
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC SRGB RGB */
+					15 01 00 00 00 00 02 B0 01
+					39 01 00 00 00 00 16 B1 B2 0D 04 37 D5 13 0C 02 C8 49 F3 DC D1 14 CA EB EA 18 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-seed-2-command = [
+					/* SEED CRC Setting */
+					39 01 00 00 00 00 03 81 31 02
+					39 01 00 00 00 00 03 F0 5A 5A
+					/* SEED CRC P3 */
+					15 01 00 00 00 00 02 B0 2B
+					39 01 00 00 00 00 16 B1 E4 05 00 07 E0 01 0C 02 F0 18 FA E3 FB 0A DF F9 F5 01 FF FF FF
+					/* SEED CRC ON */
+					15 01 00 00 00 00 02 B1 00
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-osc-clk-mode0-command = [
+					/* 139.6Mhz */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 C4
+					15 01 00 00 00 00 02 B0 04
+					39 01 00 00 00 00 06 F8 41 45 22 2C 2C
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 CC
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-osc-clk-mode1-command = [
+					/* 136.3Mhz */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 C4
+					15 01 00 00 00 00 02 B0 04
+					39 01 00 00 00 00 06 F8 41 69 22 5B 5B
+					15 01 00 00 00 00 02 B0 02
+					15 01 00 00 00 00 02 F8 CC
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,mdss-dsi-aod-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-aod-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-0-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-1-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-2-command-state = "dsi_hs_mode";
+			};
+
+		};
+	};
+};
+
+&dsi_oppo19567samsung_amb655uv01_1080_2400_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <2047>;
+	qcom,mdss-brightness-max-level = <2047>;
+	qcom,mdss-brightness-default-level = <400>;
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+	//qcom,platform-vddr-gpio = <&tlmm 4 0>;  //1.25v
+	qcom,panel-mode-gpio = <&pm6150_gpios 4 0>;  //1.25v
+	oppo,mdss-dsi-vendor-name = "AMB655UV01";
+	oppo,mdss-dsi-manufacture = "samsung1024";
+
+	oppo,dsi-fod-brightness = <0 0xff>,
+				<1 0xee>,
+				<2 0xea>,
+				<3 0xe9>,
+				<4 0xe8>,
+				<6 0xe6>,
+				<10 0xe3>,
+				<20 0xd9>,
+				<30 0xd3>,
+				<45 0xcb>,
+				<70 0xc0>,
+				<100 0xb5>,
+				<150 0xa6>,
+				<227 0x96>,
+				<300 0x88>,
+				<400 0x78>,
+				<500 0x6c>,
+				<600 0x5d>,
+				<800 0x46>,
+				<1023 0x2A>;
+
+	qcom,ulps-enabled;
+	qcom,mdss-dsi-t-clk-post = <0x0E>;
+	qcom,mdss-dsi-t-clk-pre = <0x35>;
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
+				06 04 02 04 00];
+
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+		timing@1{
+			qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
+				06 04 02 04 00];
+
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-oppo206B1samsung-ams643xy01-1080-2400-dsi-vid.dtsi

@@ -0,0 +1,673 @@
+&mdss_mdp {
+	dsi_oppo206B1samsung_ams643xy01_1080_2400_vid: qcom,dsi_oppo206B1samsung_ams643xy01_1080_2400_vid {
+		qcom,mdss-dsi-panel-name =
+		"samsung ams643xy01 amoled fhd+ panel without DSC";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 5>;
+		//qcom,mdss-dsi-lp11-init;
+		qcom,mdss-pan-physical-width-dimension = <67>;
+		qcom,mdss-pan-physical-height-dimension = <149>;
+		qcom,dsi-dyn-clk-enable;
+		qcom,dsi-dyn-clk-list = <1199870976 1190035968>;
+		qcom,mdss-dsi-panel-mode-switch;
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				//qcom,mdss-dsi-panel-clockrate = <1199870976>;
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2400>;
+				qcom,mdss-dsi-h-front-porch = <50>;
+				qcom,mdss-dsi-h-back-porch = <198>;
+				qcom,mdss-dsi-h-pulse-width = <20>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <9>;
+				qcom,mdss-dsi-v-front-porch = <21>;
+				qcom,mdss-dsi-v-pulse-width = <2>;
+				qcom,mdss-dsi-panel-framerate = <61>;
+
+				qcom,mdss-dsi-on-command = [
+					05 01 00 00 16 00 01 11
+					15 01 00 00 00 00 02 35 00
+					/* Fast Discharge setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 01
+					15 01 00 00 00 00 02 CD 01
+					39 01 00 00 10 00 03 F0 A5 A5
+					/*FAIL SAFE Setting */
+					39 01 00 00 00 00 03 FC 5A 5A
+					15 01 00 00 00 00 02 B0 03
+					39 01 00 00 00 00 0B ED 40 FF 08 87 A4 4A 73 E2 9F 00
+					39 01 00 00 00 00 03 FC A5 A5
+					/* ELVSS Dim Setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 05
+					15 01 00 00 00 00 02 B3 07
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* PCD setting*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 EA 4C
+					39 01 00 00 00 00 03 F0 A5 A5
+					/*Curve Setting*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 3C
+					15 01 00 00 00 00 02 B5 00
+					15 01 00 00 00 00 02 B0 15
+					39 01 00 00 00 00 12 B5 00 B4 10 E1 74 1B E1 FC 26 22 B8 36 43 B8 40 64 4C
+					15 01 00 00 00 00 02 B0 2E
+					39 01 00 00 00 00 0C B3 44 C0 B4 10 31 74 1F C2 B8 3B 80
+					39 01 00 00 00 00 03 F0 A5 A5
+					/*11 bit Dimming Setting*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 01
+					15 01 00 00 00 00 02 B3 7F
+					39 01 00 00 00 00 03 F0 A5 A5
+					/*ACL Mode */
+					39 01 00 00 00 00 02 55 00
+					39 01 00 00 00 00 02 53 20
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 F2 0F
+					39 01 00 00 00 00 03 F0 A5 A5
+					];
+
+				qcom,mdss-dsi-post-on-backlight = [
+					05 01 00 00 00 00 01 29
+					];
+
+				qcom,mdss-dsi-pre-off-command = [
+					05 01 00 00 14 00 01 28
+					05 01 00 00 78 00 01 10];
+				qcom,mdss-dsi-aod-high-mode-command = [
+					39 01 00 00 00 00 02 53 22];
+				qcom,mdss-dsi-aod-low-mode-command = [
+					39 01 00 00 00 00 02 53 23];
+				qcom,mdss-dsi-hbm-on-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 51 05 FF
+					15 00 00 00 00 00 02 53 E0
+					15 00 00 00 00 00 02 B7 00
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-hbm-off-command = [
+					/*HBM_670 OFF*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 B7 02
+					39 00 00 00 00 00 03 F0 A5 A5
+					/*HBM mode OFF*/
+					15 01 00 00 00 00 02 53 20];
+				qcom,mdss-dsi-aod-hbm-on-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 51 05 FF
+					15 00 00 00 00 00 02 53 E0
+					15 00 00 00 00 00 02 B7 00
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-aod-hbm-off-command = [
+					/*HBM_670 OFF*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 B7 02
+					39 00 00 00 00 00 03 F0 A5 A5
+					/*HBM mode OFF*/
+					15 01 00 00 00 00 02 53 20];
+				qcom,mdss-dsi-normal-hbm-on-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 51 03 FF
+					15 00 00 00 00 00 02 53 E0
+					15 00 00 00 00 00 02 B7 02
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-nolp-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 B7 02
+					39 00 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 02 53 20];
+				qcom,mdss-dsi-failsafe-on-command = [
+					39 00 00 00 00 00 03 FC 5A 5A
+					39 00 00 00 00 00 02 B0 03
+					39 00 00 00 00 00 0B ED 40 FF 08 87 A4 4A 73 E2 9F 00
+					39 01 00 00 00 00 03 FC A5 A5];
+				qcom,mdss-dsi-failsafe-off-command = [
+					39 00 00 00 00 00 03 FC 5A 5A
+					39 00 00 00 00 00 02 B0 03
+					39 00 00 00 00 00 0B ED 40 04 08 87 84 4A 73 E2 1F 00
+					39 01 00 00 00 00 03 FC A5 A5];
+				qcom,mdss-dsi-seed-0-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 80 92
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 2B B1
+					39 00 00 00 00 00 16 B1 E0 00 06 0D D3 02 09 08 E8 1C F8 D7 F5 00 DA E6 E1 03 FF FF FF
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-seed-1-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 80 90
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 01 B1
+					39 00 00 00 00 00 16 B1 A4 00 04 3C D3 15 04 06 B0 4F F0 D2 C2 05 BB E9 E5 1D FF FB E0
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-seed-2-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 80 92
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 2B B1
+					39 00 00 00 00 00 16 B1 E0 00 06 10 FF 00 00 00 FF 2A FF E2 FF 00 EE FF F1 00 FF FF FF
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-seed-4-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 80 91
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 16 B1
+					39 00 00 00 00 00 16 B1 E0 00 06 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-video-mode;
+				qcom,video-to-cmd-mode-switch-commands = [
+					39 01 00 00 0A 00 01 28
+					05 01 00 00 78 00 01 10
+					/* Internal VDO Packet generation enable*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 FC 5A 5A
+					39 00 00 00 00 00 03 B0 14 FE
+					39 00 00 00 00 00 02 FE 12
+					39 00 00 00 00 00 03 F0 A5 A5
+					39 00 00 00 00 00 03 FC A5 A5
+					/*Sleep out*/
+					39 01 00 00 0A 00 01 11
+					/* MIPI Mode cmd */
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 F2 03
+					39 00 00 00 00 00 03 F0 A5 A5
+					/* TE vsync ON */
+					39 01 00 00 0A 00 02 35 00
+					/* PCD setting off */
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 EA 48
+					39 00 00 00 00 00 03 F0 A5 A5
+					/* AOD AMP ON */
+					39 00 00 00 00 00 03 FC 5A 5A
+					39 00 00 00 00 00 03 B0 06 FD
+					39 00 00 00 00 00 02 FD 85
+					39 00 00 00 00 00 03 FC A5 A5
+					39 00 00 00 00 00 02 53 22
+					/* Internal VDO Packet generation enable*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 FC 5A 5A
+					39 00 00 00 00 00 03 B0 14 FE
+					39 00 00 00 00 00 02 FE 10
+					39 00 00 00 00 00 03 F0 A5 A5
+					39 00 00 00 00 00 03 FC A5 A5
+					/*AOD IP Setting*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 B0 03 C2
+					39 00 00 00 00 00 02 C2 04
+					39 00 00 00 00 00 03 F0 A5 A5
+					/*seed setting*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 80 92
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 2B B1
+					39 00 00 00 00 00 16 B1 E0 00 06 0D D3 02 09 08 E8 1C F8 D7 F5 00 DA E6 E1 03 FF FF FF
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 64 00 03 F0 A5 A5];
+				qcom,video-to-cmd-mode-post-switch-commands = [
+					/* Display on */
+					39 01 00 00 00 00 01 29
+					39 00 00 00 00 00 03 51 00 02
+					/* MIPI Video cmd*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 F2 03
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,cmd-to-video-mode-switch-commands = [
+					05 00 00 00 00 00 01 28
+					39 00 00 00 00 00 02 53 E0
+					/* TE vsync ON */
+					39 01 00 00 0A 00 02 35 00
+					//39 00 00 00 00 00 03 51 07 FF
+					//05 01 00 00 00 00 01 29
+				];
+				qcom,cmd-to-video-mode-post-switch-commands = [
+					05 01 00 00 00 00 01 28
+					39 00 00 00 00 00 02 81 00
+					/*Curve Setting*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 B0 3C
+					15 00 00 00 00 00 02 B5 00
+					15 00 00 00 00 00 02 B0 15
+					39 00 00 00 00 00 12 B5 00 B4 10 E1 74 1B E1 FC 26 22 B8 36 43 B8 40 64 4C
+					15 00 00 00 00 00 02 B0 2E
+					39 00 00 00 00 00 0C B3 44 C0 B4 10 31 74 1F C2 B8 3B 80
+					39 00 00 00 00 00 03 F0 A5 A5
+					/*11 bit Dimming Setting*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 B0 01
+					15 00 00 00 00 00 02 B3 7F
+					39 00 00 00 00 00 03 F0 A5 A5
+					05 01 00 00 00 00 01 29
+				];
+				/*close fingerprint hbm off*/
+				qcom,mdss-dsi-fingerprint-hbm-off-command = [
+					39 00 00 00 00 00 03 51 08 00
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 53 20
+					15 00 00 00 00 00 02 B7 02
+					39 01 00 00 00 00 03 F0 A5 A5];
+				/*elvss seed enter*/
+				qcom,mdss-dsi-seed-enter-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 B0 1E
+					39 00 00 00 00 00 08 B3 05 05 05 05 05 05 05
+					39 01 00 00 00 00 03 F0 A5 A5];
+				/*elvss seed exit*/
+				qcom,mdss-dsi-seed-exit-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 B0 1E
+					39 00 00 00 00 00 08 B3 05 05 05 05 05 05 05
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-hbm-setbacklight-command = [
+					39 00 00 00 00 00 03 51 08 00
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 53 E0
+					15 00 00 00 00 00 02 B7 02
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-setbacklight-seed0-command = [
+					39 00 00 00 00 00 03 51 08 00
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 B0 1E
+					39 00 00 00 00 00 08 B3 05 05 05 05 05 05 05
+					15 00 00 00 00 00 02 53 20
+					15 00 00 00 00 00 02 B7 02
+					39 00 00 00 00 00 02 80 92
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 2B B1
+					39 00 00 00 00 00 16 B1 E0 00 06 0D D3 02 09 08 E8 1C F8 D7 F5 00 DA E6 E1 03 FF FF FF
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-setbacklight-seed1-command = [
+					39 00 00 00 00 00 03 51 08 00
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 B0 1E
+					39 00 00 00 00 00 08 B3 05 05 05 05 05 05 05
+					15 00 00 00 00 00 02 53 20
+					15 00 00 00 00 00 02 B7 02
+					39 00 00 00 00 00 02 80 90
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 01 B1
+					39 00 00 00 00 00 16 B1 A4 00 04 3C D3 15 04 06 B0 4F F0 D2 C2 05 BB E9 E5 1D FF FB E0
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-setbacklight-seed4-command = [
+					39 00 00 00 00 00 03 51 08 00
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 B0 1E
+					39 00 00 00 00 00 08 B3 05 05 05 05 05 05 05
+					15 00 00 00 00 00 02 53 20
+					15 00 00 00 00 00 02 B7 02
+					39 00 00 00 00 00 02 80 91
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 16 B1
+					39 00 00 00 00 00 16 B1 E0 00 06 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-pre-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-aod-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-aod-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-normal-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-0-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-nolp-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-lp1-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-failsafe-on-command-state="dsi_hs_mode";
+				qcom,mdss-dsi-failsafe-off-command-state="dsi_hs_mode";
+				qcom,mdss-dsi-seed-enter-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-seed-exit-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-fingerprint-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-setbacklight-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-setbacklight-seed0-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-setbacklight-seed1-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-setbacklight-seed4-command-state = "dsi_hs_mode";
+			};
+			timing@1{
+				qcom,mdss-dsi-panel-clockrate = <1199870976>;
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2400>;
+				qcom,mdss-dsi-h-front-porch = <50>;
+				qcom,mdss-dsi-h-back-porch = <198>;
+				qcom,mdss-dsi-h-pulse-width = <20>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <9>;
+				qcom,mdss-dsi-v-front-porch = <21>;
+				qcom,mdss-dsi-v-pulse-width = <2>;
+				qcom,mdss-dsi-panel-framerate = <30>;
+
+				qcom,mdss-dsi-on-command = [
+					05 01 00 00 16 00 01 11
+					15 01 00 00 00 00 02 35 00
+					/* Fast Discharge setting */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 01
+					15 01 00 00 00 00 02 CD 01
+					39 01 00 00 10 00 03 F0 A5 A5
+					/*FAIL SAFE Setting on*/
+					39 01 00 00 00 00 03 FC 5A 5A
+					15 01 00 00 00 00 02 B0 03
+					39 01 00 00 00 00 0B ED 40 FF 08 87 A4 4A 73 E2 9F 00
+					39 01 00 00 00 00 03 FC A5 A5
+					/* ELVSS Dim Setting off */
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 05
+					15 01 00 00 00 00 02 B3 07
+					39 01 00 00 00 00 03 F0 A5 A5
+					/* PCD setting on*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 02 EA 4C
+					39 01 00 00 00 00 03 F0 A5 A5
+					/*Curve Setting*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 3C
+					15 01 00 00 00 00 02 B5 00
+					15 01 00 00 00 00 02 B0 15
+					39 01 00 00 00 00 12 B5 00 B4 10 E1 74 1B E1 FC 26 22 B8 36 43 B8 40 64 4C
+					15 01 00 00 00 00 02 B0 2E
+					39 01 00 00 00 00 0C B3 44 C0 B4 10 31 74 1F C2 B8 3B 80
+					39 01 00 00 00 00 03 F0 A5 A5
+					/*11 bit Dimming Setting*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B0 01
+					15 01 00 00 00 00 02 B3 7F
+					39 01 00 00 00 00 03 F0 A5 A5
+					/*ACL Mode */
+					39 01 00 00 00 00 02 55 00
+					39 01 00 00 00 00 02 53 20
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 F2 0F
+					39 01 00 00 00 00 03 F0 A5 A5
+					];
+				qcom,mdss-dsi-post-on-backlight = [
+					05 01 00 00 00 00 01 29
+					];
+				qcom,mdss-dsi-pre-off-command = [
+					05 01 00 00 14 00 01 28
+					05 01 00 00 78 00 01 10];
+
+				qcom,mdss-dsi-aod-high-mode-command = [
+					39 01 00 00 00 00 02 53 22];
+				qcom,mdss-dsi-aod-low-mode-command = [
+					39 01 00 00 00 00 02 53 23];
+				qcom,mdss-dsi-hbm-on-command = [
+					39 01 00 00 00 00 03 F0 5A 5A
+					39 01 00 00 00 00 03 51 05 FF
+					15 01 00 00 00 00 02 53 E0
+					15 01 00 00 00 00 02 B7 00
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-hbm-off-command = [
+					/*HBM_670 OFF*/
+					39 01 00 00 00 00 03 F0 5A 5A
+					15 01 00 00 00 00 02 B7 02
+					39 01 00 00 00 00 03 F0 A5 A5
+					/*HBM mode OFF*/
+					15 01 00 00 00 00 02 53 20];
+				qcom,mdss-dsi-aod-hbm-on-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 51 05 FF
+					15 00 00 00 00 00 02 53 E0
+					15 00 00 00 00 00 02 B7 00
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-aod-hbm-off-command = [
+					/*HBM_670 OFF*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					15 00 00 00 00 00 02 B7 02
+					39 00 00 00 00 00 03 F0 A5 A5
+					/*HBM mode OFF*/
+					15 01 00 00 00 00 02 53 20];
+				qcom,mdss-dsi-normal-hbm-on-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 51 03 FF
+					15 00 00 00 00 00 02 53 E0
+					15 00 00 00 00 00 02 B7 02
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-nolp-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 B7 02
+					39 00 00 00 00 00 03 F0 A5 A5
+					39 01 00 00 00 00 02 53 20];
+				qcom,mdss-dsi-seed-0-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 80 92
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 2B B1
+					39 00 00 00 00 00 16 B1 E0 00 06 0D D3 02 09 08 E8 1C F8 D7 F5 00 DA E6 E1 03 FF FF FF
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-seed-1-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 80 90
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 01 B1
+					39 00 00 00 00 00 16 B1 A4 00 04 3C D3 15 04 06 B0 4F F0 D2 C2 05 BB E9 E5 1D FF FB E0
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-seed-4-command = [
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 80 91
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 16 B1
+					39 00 00 00 00 00 16 B1 E0 00 06 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 00 00 03 F0 A5 A5];
+				qcom,mdss-dsi-cmd-mode;
+				qcom,video-to-cmd-mode-switch-commands = [
+					39 01 00 00 0A 00 01 28
+					05 01 00 00 78 00 01 10
+					/* Internal VDO Packet generation enable*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 FC 5A 5A
+					39 00 00 00 00 00 03 B0 14 FE
+					39 00 00 00 00 00 02 FE 12
+					39 00 00 00 00 00 03 F0 A5 A5
+					39 00 00 00 00 00 03 FC A5 A5
+					/*Sleep out*/
+					39 01 00 00 0A 00 01 11
+					/* MIPI Mode cmd */
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 F2 03
+					39 00 00 00 00 00 03 F0 A5 A5
+					/* TE vsync ON */
+					39 01 00 00 0A 00 02 35 00
+					/* PCD setting off */
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 EA 48
+					39 00 00 00 00 00 03 F0 A5 A5
+					/* AOD AMP ON */
+					39 00 00 00 00 00 03 FC 5A 5A
+					39 00 00 00 00 00 03 B0 06 FD
+					39 00 00 00 00 00 02 FD 85
+					39 00 00 00 00 00 03 FC A5 A5
+					39 00 00 00 00 00 02 53 22
+					/* Internal VDO Packet generation enable*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 FC 5A 5A
+					39 00 00 00 00 00 03 B0 14 FE
+					39 00 00 00 00 00 02 FE 10
+					39 00 00 00 00 00 03 F0 A5 A5
+					39 00 00 00 00 00 03 FC A5 A5
+					/*AOD IP Setting*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 03 B0 03 C2
+					39 00 00 00 00 00 02 C2 04
+					39 00 00 00 00 00 03 F0 A5 A5
+					/*seed setting*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 80 92
+					39 00 00 00 00 00 02 B1 00
+					39 00 00 00 00 00 03 B0 2B B1
+					39 01 00 00 00 00 16 B1 E0 00 06 0D D3 02 09 08 E8 1C F8 D7 F5 00 DA E6 E1 03 FF FF FF
+					39 00 00 00 00 00 03 B0 55 B1
+					39 00 00 00 00 00 02 B1 80
+					39 01 00 00 64 00 03 F0 A5 A5];
+				qcom,video-to-cmd-mode-post-switch-commands = [
+					/* Display on */
+					39 00 00 00 00 00 01 29
+					39 00 00 00 00 00 03 51 00 02
+					/* MIPI Video cmd*/
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 F2 03
+					39 01 00 00 00 00 03 F0 A5 A5
+				];
+				qcom,cmd-to-video-mode-switch-commands = [
+					05 00 00 00 00 00 01 28
+					39 00 00 00 00 00 03 F0 5A 5A
+					39 00 00 00 00 00 02 F2 0F
+					39 01 00 00 00 00 03 F0 A5 A5
+					39 00 00 00 00 00 02 53 E0
+					/* TE vsync ON */
+					39 01 00 00 00 00 02 35 00
+					//39 00 00 00 00 00 03 51 07 FF
+					//05 01 00 00 00 00 01 29
+				];
+
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-pre-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-aod-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-aod-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-normal-hbm-on-command-state = "dsi_hs_mode";
+			};
+
+		};
+	};
+};
+
+&dsi_oppo206B1samsung_ams643xy01_1080_2400_vid {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-dsi-bl-normal-max-level = <2047>;
+	qcom,mdss-brightness-normal-max-level = <2047>;
+	qcom,mdss-brightness-max-level = <4095>;
+	qcom,mdss-brightness-default-level = <400>;
+		//qcom,bl-map-size = <128>;
+		/*qcom,bl-map = <36 16
+				    16 22
+				    17 21
+				    19 20
+				    19 20
+				    20 17
+				    22 15
+				    22 14
+				    24 10
+				    24 8
+				    26 4
+				    27 0
+				    29 9
+				    29 9
+				    30 14
+				    33 25
+				    34 30
+				    36 44
+				    37 49
+				    40 65
+				    40 69
+				    43 88
+				    46 109
+				    47 112
+				    50 135
+				    53 161
+				    53 163
+				    60 220
+				    60 223
+				    64 257
+				    63 255
+				    71 334
+				    71 331
+				    75 375
+				    80 422
+				    84 473
+				    89 529
+				    88 518
+				    99 653
+				    98 640
+				    103 707
+				    117 878
+				    115 862
+				    122 947
+				    128 1039
+				    135 1138
+				    132 1102
+				    149 1355
+				    157 1478
+				    166 1611
+				    163 1563
+				    183 1900
+				    180 1844
+				    203 2232
+				    199 2169
+				    209 2344
+				    236 2821
+				    232 2742
+				    243 2958
+				    255 3188
+				    268 3433
+				    282 3705
+				    317 4400
+				    176 1555>;*/
+	qcom,platform-te-gpio = <&tlmm 10 0>;
+	qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>;
+	oppo,mdss-dsi-vendor-name = "ams643xy01";
+	oppo,mdss-dsi-manufacture = "samsung1024";
+	oppo,aod_ramless;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+				"src_byte_clk0", "src_pixel_clk0",
+				"shadow_byte_clk0", "shadow_pixel_clk0";
+	qcom,mdss-dsi-t-clk-post = <0x10>;
+	qcom,mdss-dsi-t-clk-pre = <0x3E>;
+	qcom,mdss-dsi-display-timings {
+		timing@0{
+			qcom,mdss-dsi-panel-phy-timings = [00 27 0A 0A 27 25 0A 0B 0A 02 04 00]; 
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+		timing@1{
+            qcom,mdss-dsi-panel-phy-timings = [00 27 0A 0A 27 25 0A 0B 0A 02 04 00];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-rm67195-amoled-fhd-cmd.dtsi

@@ -0,0 +1,131 @@
+/* Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_rm67195_amoled_fhd_cmd: qcom,mdss_dsi_rm67195_amoled_fhd_cmd{
+		qcom,mdss-dsi-panel-name =
+			"rm67195 amoled fhd cmd mode dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-panel-framerate = <60>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <1080>;
+		qcom,mdss-dsi-panel-height = <1920>;
+		qcom,mdss-dsi-h-front-porch = <120>;
+		qcom,mdss-dsi-h-back-porch = <60>;
+		qcom,mdss-dsi-h-pulse-width = <12>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <12>;
+		qcom,mdss-dsi-v-front-porch = <8>;
+		qcom,mdss-dsi-v-pulse-width = <4>;
+		qcom,mdss-dsi-h-left-border = <0>;
+		qcom,mdss-dsi-h-right-border = <0>;
+		qcom,mdss-dsi-v-top-border = <0>;
+		qcom,mdss-dsi-v-bottom-border = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-on-command = [
+				15 01 00 00 00 00 02 fe 0d
+				15 01 00 00 00 00 02 0b c0
+				15 01 00 00 00 00 02 42 00
+				15 01 00 00 00 00 02 18 08
+				15 01 00 00 00 00 02 08 41
+				15 01 00 00 00 00 02 46 02
+				15 01 00 00 00 00 02 1e 04
+				15 01 00 00 02 00 02 1e 00
+				15 01 00 00 00 00 02 fe 0a
+				15 01 00 00 00 00 02 24 17
+				15 01 00 00 00 00 02 04 07
+				15 01 00 00 00 00 02 1a 0c
+				15 01 00 00 02 00 02 0f 44
+				15 01 00 00 00 00 02 fe 0b
+				15 01 00 00 00 00 02 28 40
+				15 01 00 00 02 00 02 29 4f
+				15 01 00 00 00 00 02 fe 04
+				15 01 00 00 00 00 02 0a d8
+				15 01 00 00 00 00 02 0c e6
+				15 01 00 00 00 00 02 4e 20
+				15 01 00 00 00 00 02 4f 1b
+				15 01 00 00 00 00 02 50 2f
+				15 01 00 00 02 00 02 51 08
+				15 01 00 00 00 00 02 fe 09
+				15 01 00 00 00 00 02 00 08
+				15 01 00 00 00 00 02 01 08
+				15 01 00 00 00 00 02 02 00
+				15 01 00 00 00 00 02 03 00
+				15 01 00 00 00 00 02 04 10
+				15 01 00 00 00 00 02 05 00
+				15 01 00 00 00 00 02 06 08
+				15 01 00 00 00 00 02 07 08
+				15 01 00 00 00 00 02 08 00
+				15 01 00 00 00 00 02 12 24
+				15 01 00 00 00 00 02 13 49
+				15 01 00 00 00 00 02 14 92
+				15 01 00 00 00 00 02 15 49
+				15 01 00 00 00 00 02 16 92
+				15 01 00 00 00 00 02 17 24
+				15 01 00 00 00 00 02 18 24
+				15 01 00 00 00 00 02 19 49
+				15 01 00 00 00 00 02 1a 92
+				15 01 00 00 00 00 02 1b 49
+				15 01 00 00 00 00 02 1c 92
+				15 01 00 00 00 00 02 1d 24
+				15 01 00 00 00 00 02 1e 24
+				15 01 00 00 00 00 02 1f 49
+				15 01 00 00 00 00 02 20 92
+				15 01 00 00 00 00 02 21 49
+				15 01 00 00 00 00 02 22 92
+				15 01 00 00 00 00 02 23 24
+				15 01 00 00 00 00 02 9b 07
+				15 01 00 00 02 00 02 9c a5
+				15 01 00 00 00 00 02 fe 00
+				15 01 00 00 00 00 02 c2 08
+				15 01 00 00 02 00 02 35 00
+				39 01 00 00 00 00 03 44 03 e8
+				05 01 00 00 82 00 02 11 00
+				05 01 00 00 14 00 02 29 00];
+
+		qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+				05 01 00 00 82 00 02 10 00];
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-t-clk-post = <0x0d>;
+		qcom,mdss-dsi-t-clk-pre = <0x2f>;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-lp11-init;
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+		qcom,mdss-dsi-bl-min-level = <1>;
+		qcom,mdss-dsi-bl-max-level = <255>;
+		qcom,mdss-pan-physical-width-dimension = <70>;
+		qcom,mdss-pan-physical-height-dimension = <125>;
+		qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>;
+		qcom,mdss-dsi-panel-orientation = "180";
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-rm69298-truly-amoled-fhd-plus-cmd.dtsi

@@ -0,0 +1,330 @@
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_rm69298_truly_amoled_cmd: qcom,mdss_dsi_rm69298_truly_amoled_cmd {
+		qcom,mdss-dsi-panel-name =
+			"rm69298 amoled fhd+ cmd mode dsi truly panel";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-lp11-init;
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0 {
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2160>;
+				qcom,mdss-dsi-h-front-porch = <30>;
+				qcom,mdss-dsi-h-back-porch = <40>;
+				qcom,mdss-dsi-h-pulse-width = <10>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <16>;
+				qcom,mdss-dsi-v-front-porch = <8>;
+				qcom,mdss-dsi-v-pulse-width = <4>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+					15 01 00 00 00 00 02 FE 40
+					15 01 00 00 00 00 02 0A 15
+					15 01 00 00 00 00 02 0B CC
+					15 01 00 00 00 00 02 0C 15
+					15 01 00 00 00 00 02 0D 80
+					15 01 00 00 00 00 02 0F 87
+					15 01 00 00 00 00 02 05 08
+					15 01 00 00 00 00 02 06 08
+					15 01 00 00 00 00 02 08 08
+					15 01 00 00 00 00 02 09 08
+					15 01 00 00 00 00 02 16 15
+					15 01 00 00 00 00 02 20 8D
+					15 01 00 00 00 00 02 21 8D
+					15 01 00 00 00 00 02 24 55
+					15 01 00 00 00 00 02 26 55
+					15 01 00 00 00 00 02 28 55
+					15 01 00 00 00 00 02 2A 55
+					15 01 00 00 00 00 02 2D 28
+					15 01 00 00 00 00 02 2F 28
+					15 01 00 00 00 00 02 30 1E
+					15 01 00 00 00 00 02 31 1E
+					15 01 00 00 00 00 02 37 80
+					15 01 00 00 00 00 02 38 40
+					15 01 00 00 00 00 02 39 90
+					15 01 00 00 00 00 02 46 43
+					15 01 00 00 00 00 02 47 43
+					15 01 00 00 00 00 02 64 02
+					15 01 00 00 00 00 02 6F 02
+					15 01 00 00 00 00 02 74 2F
+					15 01 00 00 00 00 02 80 16
+					15 01 00 00 00 00 02 4E 01
+					15 01 00 00 00 00 02 FE A0
+					15 01 00 00 00 00 02 2B 22
+					15 01 00 00 00 00 02 16 00
+					15 01 00 00 00 00 02 2F 35
+					15 01 00 00 00 00 02 FE 60
+					15 01 00 00 00 00 02 00 AC
+					15 01 00 00 00 00 02 01 0F
+					15 01 00 00 00 00 02 02 FF
+					15 01 00 00 00 00 02 03 05
+					15 01 00 00 00 00 02 04 00
+					15 01 00 00 00 00 02 05 06
+					15 01 00 00 00 00 02 06 00
+					15 01 00 00 00 00 02 07 00
+					15 01 00 00 00 00 02 09 C0
+					15 01 00 00 00 00 02 0A 00
+					15 01 00 00 00 00 02 0B 02
+					15 01 00 00 00 00 02 0C 00
+					15 01 00 00 00 00 02 0E 00
+					15 01 00 00 00 00 02 0E 04
+					15 01 00 00 00 00 02 0F 0E
+					15 01 00 00 00 00 02 10 A2
+					15 01 00 00 00 00 02 12 C0
+					15 01 00 00 00 00 02 13 00
+					15 01 00 00 00 00 02 14 02
+					15 01 00 00 00 00 02 15 00
+					15 01 00 00 00 00 02 16 00
+					15 01 00 00 00 00 02 17 05
+					15 01 00 00 00 00 02 18 0E
+					15 01 00 00 00 00 02 19 A2
+					15 01 00 00 00 00 02 1b C0
+					15 01 00 00 00 00 02 1c 00
+					15 01 00 00 00 00 02 1d 04
+					15 01 00 00 00 00 02 1E 01
+					15 01 00 00 00 00 02 1F 00
+					15 01 00 00 00 00 02 20 04
+					15 01 00 00 00 00 02 21 24
+					15 01 00 00 00 00 02 22 99
+					15 01 00 00 00 00 02 24 C0
+					15 01 00 00 00 00 02 25 00
+					15 01 00 00 00 00 02 26 04
+					15 01 00 00 00 00 02 27 01
+					15 01 00 00 00 00 02 28 00
+					15 01 00 00 00 00 02 29 06
+					15 01 00 00 00 00 02 2a 24
+					15 01 00 00 00 00 02 2b 99
+					15 01 00 00 00 00 02 83 CA
+					15 01 00 00 00 00 02 84 0F
+					15 01 00 00 00 00 02 85 FF
+					15 01 00 00 00 00 02 86 0A
+					15 01 00 00 00 00 02 87 00
+					15 01 00 00 00 00 02 88 08
+					15 01 00 00 00 00 02 89 00
+					15 01 00 00 00 00 02 8A 00
+					15 01 00 00 00 00 02 8B 80
+					15 01 00 00 00 00 02 C7 1F
+					15 01 00 00 00 00 02 C8 00
+					15 01 00 00 00 00 02 C9 01
+					15 01 00 00 00 00 02 CA 1F
+					15 01 00 00 00 00 02 CB 02
+					15 01 00 00 00 00 02 CC 1F
+					15 01 00 00 00 00 02 CD 1F
+					15 01 00 00 00 00 02 CE 1F
+					15 01 00 00 00 00 02 CF 1F
+					15 01 00 00 00 00 02 D0 1F
+					15 01 00 00 00 00 02 D1 1F
+					15 01 00 00 00 00 02 D2 1F
+					15 01 00 00 00 00 02 D3 1F
+					15 01 00 00 00 00 02 D4 1F
+					15 01 00 00 00 00 02 D5 1F
+					15 01 00 00 00 00 02 D6 1F
+					15 01 00 00 00 00 02 D7 1F
+					15 01 00 00 00 00 02 D8 1F
+					15 01 00 00 00 00 02 D9 1F
+					15 01 00 00 00 00 02 DA 1F
+					15 01 00 00 00 00 02 DB 1F
+					15 01 00 00 00 00 02 DC 00
+					15 01 00 00 00 00 02 DD 0E
+					15 01 00 00 00 00 02 DE 1F
+					15 01 00 00 00 00 02 DF 03
+					15 01 00 00 00 00 02 E0 04
+					15 01 00 00 00 00 02 E1 1F
+					15 01 00 00 00 00 02 E2 01
+					15 01 00 00 00 00 02 E3 02
+					15 01 00 00 00 00 02 E4 1F
+					15 01 00 00 00 00 02 E5 1F
+					15 01 00 00 00 00 02 E6 1F
+					15 01 00 00 00 00 02 E7 1F
+					15 01 00 00 00 00 02 E8 1F
+					15 01 00 00 00 00 02 E9 1F
+					15 01 00 00 00 00 02 EA 1F
+					15 01 00 00 00 00 02 EB 1F
+					15 01 00 00 00 00 02 EC 1F
+					15 01 00 00 00 00 02 ED 1F
+					15 01 00 00 00 00 02 EE 1F
+					15 01 00 00 00 00 02 EF 03
+					15 01 00 00 00 00 02 FE E0
+					15 01 00 00 00 00 02 C6 15
+					15 01 00 00 00 00 02 C9 9E
+					15 01 00 00 00 00 02 CB 3F
+					15 01 00 00 00 00 02 D1 0F
+					15 01 00 00 00 00 02 D3 15
+					15 01 00 00 00 00 02 D4 15
+					15 01 00 00 00 00 02 D5 00
+					15 01 00 00 00 00 02 FE 90
+					15 01 00 00 00 00 02 C8 00
+					15 01 00 00 00 00 02 FE E0
+					15 01 00 00 00 00 02 09 00
+					15 01 00 00 00 00 02 FE 70
+					15 01 00 00 00 00 02 A9 40
+					15 01 00 00 00 00 02 CB 05
+					15 01 00 00 00 00 02 FE 70
+					15 01 00 00 00 00 02 5A FF
+					15 01 00 00 00 00 02 5C FF
+					15 01 00 00 00 00 02 5D 0A
+					15 01 00 00 00 00 02 7D 31
+					15 01 00 00 00 00 02 7E 4A
+					15 01 00 00 00 00 02 52 80
+					15 01 00 00 00 00 02 49 05
+					15 01 00 00 00 00 02 4A 2E
+					15 01 00 00 00 00 02 4B 58
+					15 01 00 00 00 00 02 4C 77
+					15 01 00 00 00 00 02 4D A1
+					15 01 00 00 00 00 02 4E DE
+					15 01 00 00 00 00 02 4F 2C
+					15 01 00 00 00 00 02 50 97
+					15 01 00 00 00 00 02 51 2A
+					15 01 00 00 00 00 02 AD EC
+					15 01 00 00 00 00 02 AE 80
+					15 01 00 00 00 00 02 AF 00
+					15 01 00 00 00 00 02 B0 50
+					15 01 00 00 00 00 02 B1 3A
+					15 01 00 00 00 00 02 FE 90
+					15 01 00 00 00 00 02 56 91
+					15 01 00 00 00 00 02 58 04
+					15 01 00 00 00 00 02 59 24
+					15 01 00 00 00 00 02 5A 05
+					15 01 00 00 00 00 02 5B C6
+					15 01 00 00 00 00 02 5C 05
+					15 01 00 00 00 00 02 5D 66
+					15 01 00 00 00 00 02 5E 06
+					15 01 00 00 00 00 02 5F 17
+					15 01 00 00 00 00 02 60 07
+					15 01 00 00 00 00 02 61 CF
+					15 01 00 00 00 00 02 62 07
+					15 01 00 00 00 00 02 63 98
+					15 01 00 00 00 00 02 64 08
+					15 01 00 00 00 00 02 65 65
+					15 01 00 00 00 00 02 66 09
+					15 01 00 00 00 00 02 67 37
+					15 01 00 00 00 00 02 68 0A
+					15 01 00 00 00 00 02 6B 02
+					15 01 00 00 00 00 02 6C 0C
+					15 01 00 00 00 00 02 71 02
+					15 01 00 00 00 00 02 72 0F
+					15 01 00 00 00 00 02 73 93
+					15 01 00 00 00 00 02 74 0F
+					15 01 00 00 00 00 02 FE 20
+					15 01 00 00 00 00 02 98 CF
+					15 01 00 00 00 00 02 FE 20
+					15 01 00 00 00 00 02 72 11
+					15 01 00 00 00 00 02 B4 31
+					15 01 00 00 00 00 02 B7 42
+					15 01 00 00 00 00 02 AA 03
+					15 01 00 00 00 00 02 09 13
+					15 01 00 00 00 00 02 FE 20
+					15 01 00 00 00 00 02 01 41
+					15 01 00 00 00 00 02 02 00
+					15 01 00 00 00 00 02 03 00
+					15 01 00 00 00 00 02 04 FF
+					15 01 00 00 00 00 02 05 00
+					15 01 00 00 00 00 02 06 C0
+					15 01 00 00 00 00 02 07 40
+					15 01 00 00 00 00 02 08 20
+					15 01 00 00 00 00 02 19 E0
+					15 01 00 00 00 00 02 1A 40
+					15 01 00 00 00 00 02 1B 00
+					15 01 00 00 00 00 02 1C 80
+					15 01 00 00 00 00 02 60 40
+					15 01 00 00 00 00 02 61 40
+					15 01 00 00 00 00 02 62 40
+					15 01 00 00 00 00 02 63 40
+					15 01 00 00 00 00 02 64 40
+					15 01 00 00 00 00 02 65 40
+					15 01 00 00 00 00 02 72 11
+					15 01 00 00 00 00 02 73 00
+					15 01 00 00 00 00 02 74 02
+					15 01 00 00 00 00 02 75 10
+					15 01 00 00 00 00 02 76 14
+					15 01 00 00 00 00 02 77 1C
+					15 01 00 00 00 00 02 78 20
+					15 01 00 00 00 00 02 79 0A
+					15 01 00 00 00 00 02 7A 00
+					15 01 00 00 00 00 02 7B 00
+					15 01 00 00 00 00 02 7C 00
+					15 01 00 00 00 00 02 7D 00
+					15 01 00 00 00 00 02 7E 00
+					15 01 00 00 00 00 02 7F 00
+					15 01 00 00 00 00 02 80 00
+					15 01 00 00 00 00 02 81 00
+					15 01 00 00 00 00 02 82 00
+					15 01 00 00 00 00 02 83 00
+					15 01 00 00 00 00 02 84 00
+					15 01 00 00 00 00 02 85 00
+					15 01 00 00 00 00 02 86 20
+					15 01 00 00 00 00 02 87 0A
+					15 01 00 00 00 00 02 88 02
+					15 01 00 00 00 00 02 89 2B
+					15 01 00 00 00 00 02 8A 14
+					15 01 00 00 00 00 02 8B 01
+					15 01 00 00 00 00 02 8C 00
+					15 01 00 00 00 00 02 8D 00
+					15 01 00 00 00 00 02 8E 00
+					15 01 00 00 00 00 02 8F 00
+					15 01 00 00 00 00 02 90 00
+					15 01 00 00 00 00 02 91 00
+					15 01 00 00 00 00 02 92 00
+					15 01 00 00 00 00 02 93 00
+					15 01 00 00 00 00 02 94 00
+					15 01 00 00 00 00 02 95 00
+					15 01 00 00 00 00 02 96 00
+					15 01 00 00 00 00 02 B2 40
+					15 01 00 00 00 00 02 B7 42
+					15 01 00 00 00 00 02 B8 D0
+					15 01 00 00 00 00 02 B9 06
+					15 01 00 00 00 00 02 BA 00
+					15 01 00 00 00 00 02 FE 00
+					39 01 00 00 00 00 05 51 00 00 FF FF
+					15 01 00 00 00 00 02 C2 08
+					15 01 00 00 00 00 02 35 00
+					05 01 00 00 96 00 01 11
+					05 01 00 00 32 00 01 29];
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 32 00 02 28 00
+					05 01 00 00 96 00 02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-rm69298-truly-amoled-fhd-plus-video.dtsi

@@ -0,0 +1,330 @@
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_rm69298_truly_amoled_video:
+			qcom,mdss_dsi_rm69298_truly_amoled_video {
+		qcom,mdss-dsi-panel-name =
+			"rm69298 amoled fhd+ video mode dsi truly panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-lp11-init;
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0 {
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2160>;
+				qcom,mdss-dsi-h-front-porch = <30>;
+				qcom,mdss-dsi-h-back-porch = <40>;
+				qcom,mdss-dsi-h-pulse-width = <10>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <16>;
+				qcom,mdss-dsi-v-front-porch = <8>;
+				qcom,mdss-dsi-v-pulse-width = <4>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+					15 01 00 00 00 00 02 FE 40
+					15 01 00 00 00 00 02 0A 15
+					15 01 00 00 00 00 02 0B CC
+					15 01 00 00 00 00 02 0C 15
+					15 01 00 00 00 00 02 0D 80
+					15 01 00 00 00 00 02 0F 87
+					15 01 00 00 00 00 02 05 08
+					15 01 00 00 00 00 02 06 08
+					15 01 00 00 00 00 02 08 08
+					15 01 00 00 00 00 02 09 08
+					15 01 00 00 00 00 02 16 15
+					15 01 00 00 00 00 02 20 8D
+					15 01 00 00 00 00 02 21 8D
+					15 01 00 00 00 00 02 24 55
+					15 01 00 00 00 00 02 26 55
+					15 01 00 00 00 00 02 28 55
+					15 01 00 00 00 00 02 2A 55
+					15 01 00 00 00 00 02 2D 28
+					15 01 00 00 00 00 02 2F 28
+					15 01 00 00 00 00 02 30 1E
+					15 01 00 00 00 00 02 31 1E
+					15 01 00 00 00 00 02 37 80
+					15 01 00 00 00 00 02 38 40
+					15 01 00 00 00 00 02 39 90
+					15 01 00 00 00 00 02 46 43
+					15 01 00 00 00 00 02 47 43
+					15 01 00 00 00 00 02 64 02
+					15 01 00 00 00 00 02 6F 02
+					15 01 00 00 00 00 02 74 2F
+					15 01 00 00 00 00 02 80 16
+					15 01 00 00 00 00 02 4E 01
+					15 01 00 00 00 00 02 FE A0
+					15 01 00 00 00 00 02 2B 22
+					15 01 00 00 00 00 02 16 00
+					15 01 00 00 00 00 02 2F 35
+					15 01 00 00 00 00 02 FE 60
+					15 01 00 00 00 00 02 00 AC
+					15 01 00 00 00 00 02 01 0F
+					15 01 00 00 00 00 02 02 FF
+					15 01 00 00 00 00 02 03 05
+					15 01 00 00 00 00 02 04 00
+					15 01 00 00 00 00 02 05 06
+					15 01 00 00 00 00 02 06 00
+					15 01 00 00 00 00 02 07 00
+					15 01 00 00 00 00 02 09 C0
+					15 01 00 00 00 00 02 0A 00
+					15 01 00 00 00 00 02 0B 02
+					15 01 00 00 00 00 02 0C 00
+					15 01 00 00 00 00 02 0E 00
+					15 01 00 00 00 00 02 0E 04
+					15 01 00 00 00 00 02 0F 0E
+					15 01 00 00 00 00 02 10 A2
+					15 01 00 00 00 00 02 12 C0
+					15 01 00 00 00 00 02 13 00
+					15 01 00 00 00 00 02 14 02
+					15 01 00 00 00 00 02 15 00
+					15 01 00 00 00 00 02 16 00
+					15 01 00 00 00 00 02 17 05
+					15 01 00 00 00 00 02 18 0E
+					15 01 00 00 00 00 02 19 A2
+					15 01 00 00 00 00 02 1b C0
+					15 01 00 00 00 00 02 1c 00
+					15 01 00 00 00 00 02 1d 04
+					15 01 00 00 00 00 02 1E 01
+					15 01 00 00 00 00 02 1F 00
+					15 01 00 00 00 00 02 20 04
+					15 01 00 00 00 00 02 21 24
+					15 01 00 00 00 00 02 22 99
+					15 01 00 00 00 00 02 24 C0
+					15 01 00 00 00 00 02 25 00
+					15 01 00 00 00 00 02 26 04
+					15 01 00 00 00 00 02 27 01
+					15 01 00 00 00 00 02 28 00
+					15 01 00 00 00 00 02 29 06
+					15 01 00 00 00 00 02 2a 24
+					15 01 00 00 00 00 02 2b 99
+					15 01 00 00 00 00 02 83 CA
+					15 01 00 00 00 00 02 84 0F
+					15 01 00 00 00 00 02 85 FF
+					15 01 00 00 00 00 02 86 0A
+					15 01 00 00 00 00 02 87 00
+					15 01 00 00 00 00 02 88 08
+					15 01 00 00 00 00 02 89 00
+					15 01 00 00 00 00 02 8A 00
+					15 01 00 00 00 00 02 8B 80
+					15 01 00 00 00 00 02 C7 1F
+					15 01 00 00 00 00 02 C8 00
+					15 01 00 00 00 00 02 C9 01
+					15 01 00 00 00 00 02 CA 1F
+					15 01 00 00 00 00 02 CB 02
+					15 01 00 00 00 00 02 CC 1F
+					15 01 00 00 00 00 02 CD 1F
+					15 01 00 00 00 00 02 CE 1F
+					15 01 00 00 00 00 02 CF 1F
+					15 01 00 00 00 00 02 D0 1F
+					15 01 00 00 00 00 02 D1 1F
+					15 01 00 00 00 00 02 D2 1F
+					15 01 00 00 00 00 02 D3 1F
+					15 01 00 00 00 00 02 D4 1F
+					15 01 00 00 00 00 02 D5 1F
+					15 01 00 00 00 00 02 D6 1F
+					15 01 00 00 00 00 02 D7 1F
+					15 01 00 00 00 00 02 D8 1F
+					15 01 00 00 00 00 02 D9 1F
+					15 01 00 00 00 00 02 DA 1F
+					15 01 00 00 00 00 02 DB 1F
+					15 01 00 00 00 00 02 DC 00
+					15 01 00 00 00 00 02 DD 0E
+					15 01 00 00 00 00 02 DE 1F
+					15 01 00 00 00 00 02 DF 03
+					15 01 00 00 00 00 02 E0 04
+					15 01 00 00 00 00 02 E1 1F
+					15 01 00 00 00 00 02 E2 01
+					15 01 00 00 00 00 02 E3 02
+					15 01 00 00 00 00 02 E4 1F
+					15 01 00 00 00 00 02 E5 1F
+					15 01 00 00 00 00 02 E6 1F
+					15 01 00 00 00 00 02 E7 1F
+					15 01 00 00 00 00 02 E8 1F
+					15 01 00 00 00 00 02 E9 1F
+					15 01 00 00 00 00 02 EA 1F
+					15 01 00 00 00 00 02 EB 1F
+					15 01 00 00 00 00 02 EC 1F
+					15 01 00 00 00 00 02 ED 1F
+					15 01 00 00 00 00 02 EE 1F
+					15 01 00 00 00 00 02 EF 03
+					15 01 00 00 00 00 02 FE E0
+					15 01 00 00 00 00 02 C6 15
+					15 01 00 00 00 00 02 C9 9E
+					15 01 00 00 00 00 02 CB 3F
+					15 01 00 00 00 00 02 D1 0F
+					15 01 00 00 00 00 02 D3 15
+					15 01 00 00 00 00 02 D4 15
+					15 01 00 00 00 00 02 D5 00
+					15 01 00 00 00 00 02 FE 90
+					15 01 00 00 00 00 02 C8 00
+					15 01 00 00 00 00 02 FE E0
+					15 01 00 00 00 00 02 09 00
+					15 01 00 00 00 00 02 FE 70
+					15 01 00 00 00 00 02 A9 40
+					15 01 00 00 00 00 02 CB 05
+					15 01 00 00 00 00 02 FE 70
+					15 01 00 00 00 00 02 5A FF
+					15 01 00 00 00 00 02 5C FF
+					15 01 00 00 00 00 02 5D 0A
+					15 01 00 00 00 00 02 7D 31
+					15 01 00 00 00 00 02 7E 4A
+					15 01 00 00 00 00 02 52 80
+					15 01 00 00 00 00 02 49 05
+					15 01 00 00 00 00 02 4A 2E
+					15 01 00 00 00 00 02 4B 58
+					15 01 00 00 00 00 02 4C 77
+					15 01 00 00 00 00 02 4D A1
+					15 01 00 00 00 00 02 4E DE
+					15 01 00 00 00 00 02 4F 2C
+					15 01 00 00 00 00 02 50 97
+					15 01 00 00 00 00 02 51 2A
+					15 01 00 00 00 00 02 AD EC
+					15 01 00 00 00 00 02 AE 80
+					15 01 00 00 00 00 02 AF 00
+					15 01 00 00 00 00 02 B0 50
+					15 01 00 00 00 00 02 B1 3A
+					15 01 00 00 00 00 02 FE 90
+					15 01 00 00 00 00 02 56 91
+					15 01 00 00 00 00 02 58 04
+					15 01 00 00 00 00 02 59 24
+					15 01 00 00 00 00 02 5A 05
+					15 01 00 00 00 00 02 5B C6
+					15 01 00 00 00 00 02 5C 05
+					15 01 00 00 00 00 02 5D 66
+					15 01 00 00 00 00 02 5E 06
+					15 01 00 00 00 00 02 5F 17
+					15 01 00 00 00 00 02 60 07
+					15 01 00 00 00 00 02 61 CF
+					15 01 00 00 00 00 02 62 07
+					15 01 00 00 00 00 02 63 98
+					15 01 00 00 00 00 02 64 08
+					15 01 00 00 00 00 02 65 65
+					15 01 00 00 00 00 02 66 09
+					15 01 00 00 00 00 02 67 37
+					15 01 00 00 00 00 02 68 0A
+					15 01 00 00 00 00 02 6B 02
+					15 01 00 00 00 00 02 6C 0C
+					15 01 00 00 00 00 02 71 02
+					15 01 00 00 00 00 02 72 0F
+					15 01 00 00 00 00 02 73 93
+					15 01 00 00 00 00 02 74 0F
+					15 01 00 00 00 00 02 FE 20
+					15 01 00 00 00 00 02 98 CF
+					15 01 00 00 00 00 02 FE 20
+					15 01 00 00 00 00 02 72 11
+					15 01 00 00 00 00 02 B4 31
+					15 01 00 00 00 00 02 B7 42
+					15 01 00 00 00 00 02 AA 03
+					15 01 00 00 00 00 02 09 13
+					15 01 00 00 00 00 02 FE 20
+					15 01 00 00 00 00 02 01 41
+					15 01 00 00 00 00 02 02 00
+					15 01 00 00 00 00 02 03 00
+					15 01 00 00 00 00 02 04 FF
+					15 01 00 00 00 00 02 05 00
+					15 01 00 00 00 00 02 06 C0
+					15 01 00 00 00 00 02 07 40
+					15 01 00 00 00 00 02 08 20
+					15 01 00 00 00 00 02 19 E0
+					15 01 00 00 00 00 02 1A 40
+					15 01 00 00 00 00 02 1B 00
+					15 01 00 00 00 00 02 1C 80
+					15 01 00 00 00 00 02 60 40
+					15 01 00 00 00 00 02 61 40
+					15 01 00 00 00 00 02 62 40
+					15 01 00 00 00 00 02 63 40
+					15 01 00 00 00 00 02 64 40
+					15 01 00 00 00 00 02 65 40
+					15 01 00 00 00 00 02 72 11
+					15 01 00 00 00 00 02 73 00
+					15 01 00 00 00 00 02 74 02
+					15 01 00 00 00 00 02 75 10
+					15 01 00 00 00 00 02 76 14
+					15 01 00 00 00 00 02 77 1C
+					15 01 00 00 00 00 02 78 20
+					15 01 00 00 00 00 02 79 0A
+					15 01 00 00 00 00 02 7A 00
+					15 01 00 00 00 00 02 7B 00
+					15 01 00 00 00 00 02 7C 00
+					15 01 00 00 00 00 02 7D 00
+					15 01 00 00 00 00 02 7E 00
+					15 01 00 00 00 00 02 7F 00
+					15 01 00 00 00 00 02 80 00
+					15 01 00 00 00 00 02 81 00
+					15 01 00 00 00 00 02 82 00
+					15 01 00 00 00 00 02 83 00
+					15 01 00 00 00 00 02 84 00
+					15 01 00 00 00 00 02 85 00
+					15 01 00 00 00 00 02 86 20
+					15 01 00 00 00 00 02 87 0A
+					15 01 00 00 00 00 02 88 02
+					15 01 00 00 00 00 02 89 2B
+					15 01 00 00 00 00 02 8A 14
+					15 01 00 00 00 00 02 8B 01
+					15 01 00 00 00 00 02 8C 00
+					15 01 00 00 00 00 02 8D 00
+					15 01 00 00 00 00 02 8E 00
+					15 01 00 00 00 00 02 8F 00
+					15 01 00 00 00 00 02 90 00
+					15 01 00 00 00 00 02 91 00
+					15 01 00 00 00 00 02 92 00
+					15 01 00 00 00 00 02 93 00
+					15 01 00 00 00 00 02 94 00
+					15 01 00 00 00 00 02 95 00
+					15 01 00 00 00 00 02 96 00
+					15 01 00 00 00 00 02 B2 40
+					15 01 00 00 00 00 02 B7 42
+					15 01 00 00 00 00 02 B8 D0
+					15 01 00 00 00 00 02 B9 06
+					15 01 00 00 00 00 02 BA 00
+					15 01 00 00 00 00 02 FE 00
+					39 01 00 00 00 00 05 51 00 00 FF FF
+					15 01 00 00 00 00 02 C2 09
+					05 01 00 00 96 00 01 11
+					05 01 00 00 32 00 01 29];
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 32 00 02 28 00
+					05 01 00 00 96 00 02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-rm69299-visionox-amoled-fhd-plus-cmd.dtsi

@@ -0,0 +1,73 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_rm69299_visionox_amoled_cmd:
+		qcom,mdss_dsi_rm69299_visionox_amoled_cmd {
+		qcom,mdss-dsi-panel-name =
+		"rm69299 amoled fhd+ cmd mode dsi visionox panel";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-lp11-init;
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-display-timings {
+			timing@0 {
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2248>;
+				qcom,mdss-dsi-h-front-porch = <26>;
+				qcom,mdss-dsi-h-back-porch = <36>;
+				qcom,mdss-dsi-h-pulse-width = <2>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <4>;
+				qcom,mdss-dsi-v-front-porch = <56>;
+				qcom,mdss-dsi-v-pulse-width = <4>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 02 FE 00
+					39 01 00 00 00 00 02 C2 08
+					39 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 02 51 FF
+					05 01 00 00 96 00 02 11 00
+					05 01 00 00 32 00 02 29 00];
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 32 00 02 28 00
+					05 01 00 00 96 00 02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-rm69299-visionox-amoled-fhd-plus-video.dtsi

@@ -0,0 +1,75 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_rm69299_visionox_amoled_video:
+			qcom,mdss_dsi_rm69299_visionox_amoled_video {
+		qcom,mdss-dsi-panel-name =
+			"rm69299 amoled fhd+ video mode dsi visionox panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-lp11-init;
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0 {
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2248>;
+				qcom,mdss-dsi-h-front-porch = <26>;
+				qcom,mdss-dsi-h-back-porch = <36>;
+				qcom,mdss-dsi-h-pulse-width = <2>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <4>;
+				qcom,mdss-dsi-v-front-porch = <56>;
+				qcom,mdss-dsi-v-pulse-width = <4>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 02 FE 00
+					39 01 00 00 00 00 02 C2 08
+					39 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 02 51 FF
+					05 01 00 00 96 00 02 11 00
+					05 01 00 00 32 00 02 29 00];
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 32 00 02 28 00
+					05 01 00 00 96 00 02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi

@@ -0,0 +1,141 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_dual_s6e3ha3_amoled_cmd: qcom,mdss_dsi_s6e3ha3_amoled_wqhd_cmd{
+		qcom,mdss-dsi-panel-name =
+			"Dual s6e3ha3 amoled cmd mode dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-panel-framerate = <60>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <720>;
+		qcom,mdss-dsi-panel-height = <2560>;
+		qcom,mdss-dsi-h-front-porch = <100>;
+		qcom,mdss-dsi-h-back-porch = <100>;
+		qcom,mdss-dsi-h-pulse-width = <40>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <31>;
+		qcom,mdss-dsi-v-front-porch = <30>;
+		qcom,mdss-dsi-v-pulse-width = <8>;
+		qcom,mdss-dsi-h-left-border = <0>;
+		qcom,mdss-dsi-h-right-border = <0>;
+		qcom,mdss-dsi-v-top-border = <0>;
+		qcom,mdss-dsi-v-bottom-border = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-on-command = [05 01 00 00 05 00 02 11 00
+					39 01 00 00 00 00 05 2a 00 00 05 9f
+					39 01 00 00 00 00 05 2b 00 00 09 ff
+					39 01 00 00 00 00 03 f0 5a 5a
+					39 01 00 00 00 00 02 b0 10
+					39 01 00 00 00 00 02 b5 a0
+					39 01 00 00 00 00 02 c4 03
+					39 01 00 00 00 00 0a
+						f6 42 57 37 00 aa cc d0 00 00
+					39 01 00 00 00 00 02 f9 03
+					39 01 00 00 00 00 14
+						c2 00 00 d8 d8 00 80 2b 05 08
+						0e 07 0b 05 0d 0a 15 13 20 1e
+					39 01 00 00 78 00 03 f0 a5 a5
+					39 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 02 53 20
+					39 01 00 00 00 00 02 51 60
+					05 01 00 00 05 00 02 29 00];
+		qcom,mdss-dsi-off-command = [05 01 00 00 3c 00 02 28 00
+					05 01 00 00 b4 00 02 10 00];
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-lp-mode-on = [39 00 00 00 05 00 03 f0 5a 5a
+					39 00 00 00 05 00 03 f1 5a 5a
+					39 00 00 00 05 00 03 fc 5a 5a
+					39 00 00 00 05 00 02 b0 17
+					39 00 00 00 05 00 02 cb 10
+					39 00 00 00 05 00 02 b0 2d
+					39 00 00 00 05 00 02 cb cd
+					39 00 00 00 05 00 02 b0 0e
+					39 00 00 00 05 00 02 cb 02
+					39 00 00 00 05 00 02 b0 0f
+					39 00 00 00 05 00 02 cb 09
+					39 00 00 00 05 00 02 b0 02
+					39 00 00 00 05 00 02 f2 c9
+					39 00 00 00 05 00 02 b0 03
+					39 00 00 00 05 00 02 f2 c0
+					39 00 00 00 05 00 02 b0 03
+					39 00 00 00 05 00 02 f4 aa
+					39 00 00 00 05 00 02 b0 08
+					39 00 00 00 05 00 02 b1 30
+					39 00 00 00 05 00 02 b0 09
+					39 00 00 00 05 00 02 b1 0a
+					39 00 00 00 05 00 02 b0 0d
+					39 00 00 00 05 00 02 b1 10
+					39 00 00 00 05 00 02 b0 00
+					39 00 00 00 05 00 02 f7 03
+					39 00 00 00 05 00 02 fe 30
+					39 01 00 00 05 00 02 fe b0];
+		qcom,mdss-dsi-lp-mode-off = [39 00 00 00 05 00 03 f0 5a 5a
+					39 00 00 00 05 00 03 f1 5a 5a
+					39 00 00 00 05 00 03 fc 5a 5a
+					39 00 00 00 05 00 02 b0 2d
+					39 00 00 00 05 00 02 cb 4d
+					39 00 00 00 05 00 02 b0 17
+					39 00 00 00 05 00 02 cb 04
+					39 00 00 00 05 00 02 b0 0e
+					39 00 00 00 05 00 02 cb 06
+					39 00 00 00 05 00 02 b0 0f
+					39 00 00 00 05 00 02 cb 05
+					39 00 00 00 05 00 02 b0 02
+					39 00 00 00 05 00 02 f2 b8
+					39 00 00 00 05 00 02 b0 03
+					39 00 00 00 05 00 02 f2 80
+					39 00 00 00 05 00 02 b0 03
+					39 00 00 00 05 00 02 f4 8a
+					39 00 00 00 05 00 02 b0 08
+					39 00 00 00 05 00 02 b1 10
+					39 00 00 00 05 00 02 b0 09
+					39 00 00 00 05 00 02 b1 0a
+					39 00 00 00 05 00 02 b0 0d
+					39 00 00 00 05 00 02 b1 80
+					39 00 00 00 05 00 02 b0 00
+					39 00 00 00 05 00 02 f7 03
+					39 00 00 00 05 00 02 fe 30
+					39 01 00 00 05 00 02 fe b0];
+		qcom,mdss-dsi-h-sync-pulse = <0>;
+		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,dcs-cmd-by-left;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-lp11-init;
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+		qcom,mdss-dsi-bl-min-level = <1>;
+		qcom,mdss-dsi-bl-max-level = <255>;
+		qcom,mdss-pan-physical-width-dimension = <68>;
+		qcom,mdss-pan-physical-height-dimension = <122>;
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-sharp-1080p-cmd.dtsi

@@ -0,0 +1,86 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_sharp_1080_cmd: qcom,mdss_dsi_sharp_1080p_cmd {
+		qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel";
+		qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-panel-destination = "display_1";
+		qcom,mdss-dsi-panel-clockrate = <850000000>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-pan-physical-width-dimension = <64>;
+		qcom,mdss-pan-physical-height-dimension = <117>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <1920>;
+				qcom,mdss-dsi-h-front-porch = <0>;
+				qcom,mdss-dsi-h-back-porch = <0>;
+				qcom,mdss-dsi-h-pulse-width = <0>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <0>;
+				qcom,mdss-dsi-v-front-porch = <0>;
+				qcom,mdss-dsi-v-pulse-width = <0>;
+				qcom,mdss-dsi-h-left-border = <0>;
+				qcom,mdss-dsi-h-right-border = <0>;
+				qcom,mdss-dsi-v-top-border = <0>;
+				qcom,mdss-dsi-v-bottom-border = <0>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+					15 01 00 00 00 00 02 bb 10
+					15 01 00 00 00 00 02 b0 03
+					05 01 00 00 78 00 01 11
+					15 01 00 00 00 00 02 51 ff
+					15 01 00 00 00 00 02 53 24
+					15 01 00 00 00 00 02 ff 23
+					15 01 00 00 00 00 02 08 05
+					15 01 00 00 00 00 02 46 90
+					15 01 00 00 00 00 02 ff 10
+					15 01 00 00 00 00 02 ff f0
+					15 01 00 00 00 00 02 92 01
+					15 01 00 00 00 00 02 ff 10
+					/* enable TE generation */
+					15 01 00 00 00 00 02 35 00
+					05 01 00 00 28 00 01 29];
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 10 00 01 28
+					05 01 00 00 40 00 01 10];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-sharp-dsc-4k-cmd.dtsi

@@ -0,0 +1,103 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd {
+		qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
+		qcom,mdss-pan-physical-width-dimension = <71>;
+		qcom,mdss-pan-physical-height-dimension = <129>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-wr-mem-start = <0x2c>;
+		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,dcs-cmd-by-left;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,adjust-timer-wakeup-ms = <1>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+			17000 15500 30000 8000 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+		qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <3840>;
+				qcom,mdss-dsi-h-front-porch = <30>;
+				qcom,mdss-dsi-h-back-porch = <100>;
+				qcom,mdss-dsi-h-pulse-width = <4>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <7>;
+				qcom,mdss-dsi-v-front-porch = <8>;
+				qcom,mdss-dsi-v-pulse-width = <1>;
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-panel-jitter = <0x8 0xa>;
+
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 11 91 09 20 00 20 02
+					00 03 1c 04 21 00
+					0f 03 19 01 97
+					39 01 00 00 00 00 03 92 10 f0
+					15 01 00 00 00 00 02 90 03
+					15 01 00 00 00 00 02 03 01
+					39 01 00 00 00 00 06 f0 55 aa 52 08 04
+					15 01 00 00 00 00 02 c0 03
+					39 01 00 00 00 00 06 f0 55 aa 52 08 07
+					15 01 00 00 00 00 02 ef 01
+					39 01 00 00 00 00 06 f0 55 aa 52 08 00
+					15 01 00 00 00 00 02 b4 01
+					15 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 06 f0 55 aa 52 08 01
+					39 01 00 00 00 00 05 ff aa 55 a5 80
+					15 01 00 00 00 00 02 6f 01
+					15 01 00 00 00 00 02 f3 10
+					39 01 00 00 00 00 05 ff aa 55 a5 00
+					/* sleep out + delay 120ms */
+					05 01 00 00 78 00 01 11
+					/* display on + delay 120ms */
+					05 01 00 00 78 00 01 29
+					];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command =
+					[05 01 00 00 78 00 02 28 00
+					 05 01 00 00 78 00 02 10 00];
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+				qcom,compression-mode = "dsc";
+				qcom,mdss-dsc-slice-height = <32>;
+				qcom,mdss-dsc-slice-width = <1080>;
+				qcom,mdss-dsc-slice-per-pkt = <1>;
+				qcom,mdss-dsc-bit-per-component = <8>;
+				qcom,mdss-dsc-bit-per-pixel = <8>;
+				qcom,mdss-dsc-block-prediction-enable;
+			};
+		};
+	};
+};

arch/arm64/boot/dts/19721/dsi-panel-sharp-dsc-4k-video.dtsi

@@ -0,0 +1,96 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&mdss_mdp {
+	dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video {
+		qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
+		qcom,mdss-pan-physical-width-dimension = <71>;
+		qcom,mdss-pan-physical-height-dimension = <129>;
+		qcom,mdss-dsi-tx-eot-append;
+
+		qcom,adjust-timer-wakeup-ms = <1>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+			17000 15500 30000 8000 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+		qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0{
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <3840>;
+				qcom,mdss-dsi-h-front-porch = <30>;
+				qcom,mdss-dsi-h-back-porch = <100>;
+				qcom,mdss-dsi-h-pulse-width = <4>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <7>;
+				qcom,mdss-dsi-v-front-porch = <8>;
+				qcom,mdss-dsi-v-pulse-width = <1>;
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 11 91 09 20 00 20 02
+					00 03 1c 04 21 00
+					0f 03 19 01 97
+					39 01 00 00 00 00 03 92 10 f0
+					15 01 00 00 00 00 02 90 03
+					15 01 00 00 00 00 02 03 01
+					39 01 00 00 00 00 06 f0 55 aa 52 08 04
+					15 01 00 00 00 00 02 c0 03
+					39 01 00 00 00 00 06 f0 55 aa 52 08 07
+					15 01 00 00 00 00 02 ef 01
+					39 01 00 00 00 00 06 f0 55 aa 52 08 00
+					15 01 00 00 00 00 02 b4 10
+					15 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 06 f0 55 aa 52 08 01
+					39 01 00 00 00 00 05 ff aa 55 a5 80
+					15 01 00 00 00 00 02 6f 01
+					15 01 00 00 00 00 02 f3 10
+					39 01 00 00 00 00 05 ff aa 55 a5 00
+					/* sleep out + delay 120ms */
+					05 01 00 00 78 00 01 11
+					/* display on + delay 120ms */
+					05 01 00 00 78 00 01 29
+					];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command =
+					[05 01 00 00 78 00 02 28 00
+					 05 01 00 00 78 00 02 10 00];
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+				qcom,compression-mode = "dsc";
+				qcom,mdss-dsc-slice-height = <32>;
+				qcom,mdss-dsc-slice-width = <1080>;
+				qcom,mdss-dsc-slice-per-pkt = <1>;
+				qcom,mdss-dsc-bit-per-component = <8>;
+				qcom,mdss-dsc-bit-per-pixel = <8>;
+				qcom,mdss-dsc-block-prediction-enable;
+			};
+		};
+	};
+};