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Import from SM-A715F_EUR_13_Opensource

Browse Source 
* Taken from A715FXXUADWE1 source.

Change-Id: Ife88f79141085bddd4537434c451245b52ac71ad
This commit is contained in:
Haky86
2024-05-13 18:30:34 +02:00
parent 4f23255a48
commit 1a16e98230
2953 changed files with 1882026 additions and 30995 deletions
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18
AndroidKernel.mk
View File

@@ -13,6 +13,16 @@ endif
MAKE_ARGS := $(strip $(TARGET_KERNEL_MAKE_ARGS))
KERNEL_DISABLE_DEBUGFS := $(TARGET_KERNEL_DISABLE_DEBUGFS)
# Samsung specific Kconfig
ifeq ( ,$(findstring VARIANT_DEFCONFIG, $(KERNEL_DEFCONFIG)))
KERNEL_DEFCONFIG += VARIANT_DEFCONFIG=$(VARIANT_DEFCONFIG) \
DEBUG_DEFCONFIG=$(DEBUG_DEFCONFIG) \
SELINUX_DEFCONFIG=$(SELINUX_DEFCONFIG) \
SELINUX_LOG_DEFCONFIG=$(SELINUX_LOG_DEFCONFIG) \
DMVERITY_DEFCONFIG=$(DMVERITY_DEFCONFIG) \
KASLR_DEFCONFIG=$(KASLR_DEFCONFIG)
endif
TARGET_KERNEL_MAKE_ENV := $(strip $(TARGET_KERNEL_MAKE_ENV))
ifeq ($(TARGET_KERNEL_MAKE_ENV),)
KERNEL_MAKE_ENV :=
@@ -35,9 +45,9 @@ $(warning Forcing kernel header generation only for '$(TARGET_KERNEL_HEADER_ARCH
KERNEL_HEADER_ARCH := $(TARGET_KERNEL_HEADER_ARCH)
endif
ifeq ($(shell echo $(KERNEL_DEFCONFIG) | grep vendor),)
KERNEL_DEFCONFIG := vendor/$(KERNEL_DEFCONFIG)
endif
#ifeq ($(shell echo $(KERNEL_DEFCONFIG) | grep vendor),)
#KERNEL_DEFCONFIG := vendor/$(KERNEL_DEFCONFIG)
#endif
KERNEL_HEADER_DEFCONFIG := $(strip $(KERNEL_HEADER_DEFCONFIG))
ifeq ($(KERNEL_HEADER_DEFCONFIG),)
@@ -147,7 +157,7 @@ KERNEL_MODULES_OUT ?= $(PRODUCT_OUT)/$(KERNEL_MODULES_INSTALL)/lib/modules
TARGET_PREBUILT_KERNEL := $(TARGET_PREBUILT_INT_KERNEL)
BOARD_VENDOR_KERNEL_MODULES += $(wildcard $(KERNEL_MODULES_OUT)/*.ko)
#BOARD_VENDOR_KERNEL_MODULES += $(shell ls $(KERNEL_MODULES_OUT)/*.ko)
define mv-modules
mdpath=`find $(KERNEL_MODULES_OUT) -type f -name modules.dep`;\

2
Androidbp
View File

@@ -40,6 +40,6 @@ cc_library_headers {
export_generated_headers: ["qti_generate_kernel_headers_arm64"],
},
},
vendor: true,
vendor_available: true,
recovery_available: true,
}

116
Documentation/devicetree/bindings/extcon/extcon-tacna.txt Normal file
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@@ -0,0 +1,116 @@
Cirrus Logic Tacna class audio codecs extcon driver
The extcon configuration settings are a child node of the parent MFD driver
binding.
See Documentation/devicetree/bindings/mfd/tacna.txt
This node contains one or more child nodes to describe the configuration for
each accessory detect.
Mandatory properties:
- compatible : must be "cirrus,tacna-extcon"
- #address-cells : must be 1
- #size-cells : must be 0
Optional properties:
- cirrus,gpsw : Settings for the general purpose switches, set as per the
SWn_MODE bits in the GP_SWITCH register. If given must be 2 cells.
First cell is the value for the GPSW1_MODE
Second cell is the value for the GPSW2_MODE
Child node mandatory properties:
- reg : output number this configuration applies to, must be 1
Child node optional properties:
- cirrus,micd-detect-debounce-ms : Additional software microphone detection
debounce specified in milliseconds
- cirrus,micd-manual-debounce : Additional software button detection
debounce specified as a number
- cirrus,micd-bias-start-time : Time allowed for MICBIAS to startup prior to
performing microphone detection, specified as per the MICDn_DELAY
bits in the register MICDET_CONTROL1
- cirrus,micd-pol-gpio : GPIO specifier for the GPIO controlling the headset
polarity if one exists
- cirrus,micd-rate : Delay between successive microphone detection
measurements, specified as per the MICDn_RATE bits in the register
MICDETn_CONTROL1
- cirrus,micd-dbtime : Microphone detection hardware debounce level, specified
as per the MICDn_DBTIME bits in the register MICDET_CONTROL1
- cirrus,micd-timeout-ms : Timeout for microphone detection, specified in
milliseconds
- cirrus,micd-software-compare : Use a software comparison to determine mic
presence
- cirrus,fixed-hpdet-imp : Do not perform any headphone detection, just use
the fixed value specified here as the headphone impedance. Value is in
hundredths-of-an-ohm (ohms * 100)
- cirrus,hpdet-ext-res : Impedance of external series resistor on hpdet.
Value is in hundredths-of-an-ohm (ohms * 100)
- cirrus,hpdet-short-circuit-imp : Specifies the maximum impedance in ohms
that will be considered as a short circuit
- cirrus,hpdet-channel : Set which channel is used for headphone impedance
measurement. 0 = left, 1 = right
- cirrus,micd-clamp-mode : Specifies the logic of the micdetect clamp block
- cirrus,hpd-pins : 4 cells specifying the clamp and sense pins to use.
<clamp_left sense_left clamp_right sense_right>
where clamp_x is the clamp pin for channel x and sense_x is the impedance
sense pin for channel x, as per the HPD_OUT_SEL field of HPDET1_CONTROL1
register. A value >0xFFFF means use the default.
- cirrus,micd-configs : Headset polarity configurations, variable length but
must be a multiple of 5 cells, each 5-cell group represents one
polarity configuration
first cell is the value of MICDn_SENSE_SEL register field
second cell is the accessory detection ground as per the MICDn_GND_SEL
register field
the third cell is the MICBIAS to be used as per the MICDn_BIAS_SRC register
field
fourth cell is the value of the micd-pol-gpio pin, a non-zero value
indicates this should be on
fifth cell is the value of HPn_GND_SEL register field
- cirrus,accdet-dbtime : Set accessory detection hardware debounce level,
as per the ACCDET_DBTIME bits in the register TACNA_ACCDET_DEBOUNCE
Example:
codec: cs47l96@0 {
compatible = "cirrus,cs47l96";
accdet {
compatible = "cirrus,tacna-extcon";
#address-cells = <1>;
#size-cells = <0>;
cirrus,gpsw = <3 0>;
cirrus,micd-pol-gpios = <&gpio 0>
acc@1 {
reg = <1>;
cirrus,micd-detect-debounce-ms = <10>;
cirrus,micd-bias-start-time = <0x1>;
cirrus,micd-rate = <0x1>;
cirrus,micd-dbtime = <0x1>;
cirrus,micd-timeout-ms = <10>;
cirrus,micd-configs = <
0x1 0 1 0 2
0x0 0 2 1 2
>;
cirrus,accdet-dbtime =<0x1>;
};
};
};

141
Documentation/devicetree/bindings/mfd/tacna.txt Normal file
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@@ -0,0 +1,141 @@
Cirrus Logic Tacna class audio codecs multi-function device
These devices are audio SoCs with extensive digital capabilities and a range
of analogue I/O.
See also the child driver bindings in:
bindings/extcon/extcon-tacna.txt
bindings/gpio/gpio-tacna.txt
bindings/pinctrl/cirrus,tacna-pinctrl.txt
bindings/regulator/arizona-regulator.txt
bindings/sound/tacna.txt
Required properties:
- compatible : One of the following chip-specific strings:
"cirrus,cs47l96"
"cirrus,cs47l97"
- reg : I2C slave address when connected using I2C, chip select number when
using SPI.
- VDD_D-supply : Power supply for the device as defined in
bindings/regulator/regulator.txt
- VDD_A-supply, VDD_IO1-supply, VDD_IO2-supply,
VDD1_CP-supply, VDD2_CP-supply, VDD3_CP-supply:
Power supplies for the device
- interrupt-controller : Indicates that this device is an interrupt controller
- #interrupt-cells: the number of cells to describe an IRQ, must be 2.
The first cell is the IRQ number.
The second cell is the flags, encoded as the trigger masks from
bindings/interrupt-controller/interrupts.txt
- interrupt-parent : The parent interrupt controller.
- interrupts : The interrupt line the /IRQ signal for the device is
connected to.
- gpio-controller : Indicates this device is a GPIO controller.
- #gpio-cells : Must be 2. The first cell is the pin number. The second cell
is reserved for future use and must be zero
Optional properties:
- reset-gpios : One entry specifying the GPIO controlling RESET_B.
As defined in bindings/gpio.txt.
- pinctrl-names : Name of pinctrl configurations. Each of these is optional.
Legal names are:
"probe" - external pinctrl dependencies required to probe this codec,
typically these are for the reset GPIO and IRQ pin, though
could include clocks. Do NOT include configuration of this
codec's own GPIO pins because these can't be applied until
after the mfd probe has completed.
"active" - full set of external and local pinctrl configurations to
apply after probe including all the configuration of the GPIO
pins on this codec (bindings/pinctrl/cirrus,tacna-pinctrl.txt).
This must include the external dependencies in the "probe"
configuration, since they will still be required after probe.
Do not use "default" since it is applied too early before the mfd has
fully probed the codec.
- pinctrl-0, pinctrl-1 : handle to pinctrl configurations matching the
entries in pinctrl-names
- cirrus,clk32k-src : set the input source for the codec 32kHz clock.
See the TACNA_32KZ_* macros in include/dt-bindings/mfd/tacna.h for
valid options.
cs48l32 will default to MCLK1, all other codecs will default to MCLK2.
Optional child nodes:
- MICBIASx : Initial data for the MICBIAS regulators, as covered in
Documentation/devicetree/bindings/regulator/regulator.txt.
One for each MICBIAS generator (MICBIAS1, MICBIAS2, ...)
One for each output pin (MICBIAS1A, MIBCIAS1B, MICBIAS2A, ...)
The following property is supported for all nodes:
- regulator-active-discharge:
0: Disable active discharge.
1: Enable active discharge.
The following following additional property is supported for the generator
nodes:
- cirrus,ext-cap : Set to 1 if the MICBIAS has external decoupling
capacitors attached.
Example:
codec: cs47l96@0 {
compatible = "cirrus,cs47l96";
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&main_pic>;
interrupts = <1 0>;
gpio-controller;
#gpio-cells = <2>;
VDD_A-supply = <&regulator_dummy>;
VDD_IO1-supply = <&regulator_dummy>;
VDD1_CP-supply = <&regulator_dummy>;
VDD2_CP-supply = <&regulator_dummy>;
VDD3_CP-supply = <&regulator_dummy>;
VDD_D-supply = <&regulator_dummy_dcvdd>;
reset-gpios = <&gpio 0>;
pinctrl-names = "probe", "active";
pinctrl-0 = <&gpio_0_enable_state>;
pinctrl-1 = <&gpio_0_enable_state &cs47l96_gpio_config>;
cs47l96_gpio_config: cs47l96-gpio-config {
asp2 {
groups = "asp2";
function = "asp2";
bias-bus-hold;
};
opclk {
groups = "gpio1";
function = "opclk";
bias-pull-up;
drive-strength = <8>;
};
};
MICBIAS1 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3300000>;
cirrus,ext-cap = <1>;
};
};

98
Documentation/devicetree/bindings/pinctrl/cirrus,tacna-pinctrl.txt Normal file
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@@ -0,0 +1,98 @@
Cirrus Logic Tacna class audio codecs pinctrl driver
The Cirrus Logic Tacna codecs provide a number of GPIO functions for
interfacing to external hardware and to provide logic outputs to other devices.
Certain groups of GPIO pins also have an alternate function, normally as an
audio interface.
The set of available GPIOs, functions and alternate function groups differs
between codecs so refer to the datasheet for the codec for further information
on what is supported on that device.
The properties for this driver must exist within the parent MFD driver node.
See bindings/mfd/tacna.txt.
See also
the core bindings for the parent MFD driver:
Documentation/devicetree/bindings/mfd/tacna.txt
the generic pinmix bindings:
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Required properties of configuration subnodes:
- groups : name of one pin group to configure. One of:
asp2, asp3, asp4, dsd1, in1-pdm, in2-pdm, in3-pdm, in4-pdm, out5-pdm,
gpio1, gpio2, ..., gpio23
The gpioN groups select the single pin of this name for configuration
Optional properties of configuration subnodes:
Any configuration option not explicitly listed in the dts will be left at
chip default setting.
- function : name of function to assign to this group. One of (actual
available will differ from codec to codec, refer to the datasheet for
more information):
asp1, asp2, asp3, asp4, asp1ao, dsd1, in1-pdm, in2-pdm, in3-pdm,
in4-pdm, out5-pdm, io, dsp-gpio, irq1,
fll1-clk, fll1-lock, fll2-clk, fll2-lock, fll3-clk, fll3-lock,
opclk, opclk-async, opclk-dsp,
pwm1-out, pwm2-out,
input-path-signal-detect,
ultrasonic-in1-activity-detect, ultrasonic-in2-activity-detect,
asrc1-in1-lock, asrc1-in2-lock,
dfc1-saturate,
dma-ch0-programmable-transfer-complete,
dma-ch1-programmable-transfer-complete,
dma-ch2-programmable-transfer-complete,
dma-ch3-programmable-transfer-complete,
dma-ch4-programmable-transfer-complete,
dma-ch5-programmable-transfer-complete,
dma-ch6-programmable-transfer-complete,
dma-ch7-programmable-transfer-complete,
out1r-hp1-enable-disable-sequence, out1l-hp1-enable-disable-sequence,
out1r-hp2-enable-disable-sequence, out1l-hp2-enable-disable-sequence,
out2r-enable-disable-sequence, out2l-enable-disable-sequence,
outh-enable-disable-sequence,
sample-rate-change-trigger-a, sample-rate-change-trigger-b,
sample-rate-change-trigger-c, sample-rate-change-trigger-d,
timer1-irq-ch1, timer1-irq-ch2, timer1-irq-ch3, timer1-irq-ch4,
timer2-irq-ch1, timer2-irq-ch2, timer2-irq-ch3, timer2-irq-ch4,
timer3-irq-ch1, timer3-irq-ch2, timer3-irq-ch3, timer3-irq-ch4,
timer4-irq-ch1, timer4-irq-ch2, timer4-irq-ch3, timer4-irq-ch4,
timer5-irq-ch1, timer5-irq-ch2, timer5-irq-ch3, timer5-irq-ch4,
timer-1, timer-2, timer-3, timer-4, timer-5
- bias-disable : disable pull-up and pull-down
- bias-bus-hold : enable buskeeper
- bias-pull-up : output is pulled-up
- bias-pull-down : output is pulled-down
- drive-push-pull : CMOS output
- drive-open-drain : open-drain output
- drive-strength : drive strength in mA. See the datasheet for a list of valid
values for your codec.
- output-low : set the pin to output mode with low level
- output-high : set the pin to output mode with high level
Example:
codec: cs47l96@0 {
compatible = "cirrus,cs47l96";
pinctrl-names = "active";
pinctrl-0 = <&cs47l96_gpio_config>;
cs47l96_gpio_config: cs47l96-gpio-config {
asp2 {
groups = "asp2";
function = "asp2";
bias-bus-hold;
};
opclk {
groups = "gpio1";
function = "opclk";
bias-pull-up;
drive-strength = <8>;
};
};
};

66
Documentation/devicetree/bindings/sound/tacna.txt Normal file
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@@ -0,0 +1,66 @@
Cirrus Logic Tacna class audio codecs
This describes audio configuration bindings for these codecs.
See also the core bindings for the parent MFD driver:
See Documentation/devicetree/bindings/mfd/tacna.txt
and defines for values used in these bindings:
include/dt-bindings/sound/tacna.h
These properties are all contained in the parent MFD node.
Optional properties:
- cirrus,in-type : A list of input type settings for each input.
Maximum of 16 cells, with four cells per input in the order
INnL_1, INnR_1 INnL_2 INnR_2.
For non-muxed inputs the first two cells for that input set the mode for
the left and right channel and the second two cells must be 0.
For muxed inputs the first two cells for that input set the mode of the
left and right _1 inputs and the second two cells set the mode of the left
and right _2 inputs.
Valid mode values are one of the TACNA_IN_TYPE_xxx. If the array is shorter
than the number of inputs the unspecified inputs default to
TACNA_IN_TYPE_DIFF.
- cirrus,out-mono : Mono bit for each output. A non-zero value indicates the
corresponding output is mono.
Cells are:
<OUT1_HP1 OUT1_HP2> (cs47l96, cs47l97)
<OUT1 OUT2 OUT3 ...> (all other codecs)
- cirrus,max-channels-clocked : Maximum number of channels that I2S clocks
will be generated for. Useful when clock master for systems where the I2S
bus has multiple data lines.
One cell for each AIF, use a value of zero for AIFs that should be handled
normally.
- cirrus,pdm-fmt : PDM speaker data format, must contain 2 cells
(OUT5 and OUT6). One of the TACNA_PDM_FMT_MODE_x values.
The second cell is ignored for codecs that do not have OUT6.
- cirrus,pdm-mute : PDM mute format sequence, must contain 2 cells
(OUT5 and OUT6).
The second cell is ignored for codecs that do not have OUT6.
See datasheet for a description of the OUTnPDM_MUTE_SEQ field.
- cirrus,pdm-sup : Indicates how the MICBIAS pins have been externally
connected to DMICs on each input, one cell per input.
<IN1 IN2 IN3 ...>
A value of 0 indicates VOUT_MIC and is the default, other values depend on
the value of the INn_PDM_SUP field.
See the datasheet for a description of the INn_PDM_SUP field.
Example:
cs47l96@0 {
compatible = "cirrus,cs47l96";
cirrus,in-type = <
TACNA_IN_TYPE_DIFF TACNA_IN_TYPE_DIFF /* IN1[LR]_1 differential */
TACNA_IN_TYPE_SE TACNA_IN_TYPE_SE /* IN1[LR]_2 single-ended */
TACNA_IN_TYPE_DIFF TACNA_IN_TYPE_DIFF /* IN2[LR]_1 differential */
>;
cirrus,out-mono = <0 0 0 0>;
cirrus,max-channels-clocked = <2 0 0>;
};

45
Documentation/devicetree/bindings/sound/tas2562.txt Normal file
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@@ -0,0 +1,45 @@
Texas Instruments TAS2562 Smart PA
Required properties:
- compatible: Should contain "ti,tas2562".
- reg: The i2c address. Should contain <0x4c>, <0x4d>,
<0x4e>, or <0x4f>.
Optional properties:
- ti,left-channel: The i2c address of left device.
- ti,right-channel: The i2c address of right device.
It can be NULL for mono design.
- ti,channels: This property is channels number from 1 to 2.
If given 1, it is mono design.
If given 2, it is stereo design.
- ti,reset-gpio: Reset GPIO number of left device.
- ti,reset-gpio2: Reset GPIO number of right device.
It can be NULL for mono design.
- irq-gpio: IRQ GPIO number of left device.
- irq-gpio2: IRQ GPIO number of right device.
It can be NULL for mono design.
Examples:
tas2562:tas2562@4c {
#sound-dai-cells = <0>;
compatible = "ti,tas2562";
reg = <0x4c>;
ti,left-channel = <0x4c>;
ti,right-channel = <0x4d>;
ti,channels = <2>; /* channel number */
ti,reset-gpio = <&gpio1 17 0>;
ti,reset-gpio2 = <&gpio1 16 0>;
ti,irq-gpio = <&gpio1 15 0>;
ti,irq-gpio2 = <&gpio1 14 0>;
status = "ok";
};

6
MAINTAINERS
View File

@@ -6201,12 +6201,6 @@ F: drivers/hid/
F: include/linux/hid*
F: include/uapi/linux/hid*
HID PLAYSTATION DRIVER
M: Roderick Colenbrander <roderick.colenbrander@sony.com>
L: linux-input@vger.kernel.org
S: Supported
F: drivers/hid/hid-playstation.c
HID SENSOR HUB DRIVERS
M: Jiri Kosina <jikos@kernel.org>
M: Jonathan Cameron <jic23@kernel.org>

26
Makefile
View File

@@ -1018,6 +1018,28 @@ ifeq ($(CONFIG_RELR),y)
LDFLAGS_vmlinux += --pack-dyn-relocs=relr
endif
USE_SECGETSPF := $(shell echo $(PATH))
ifneq ($(findstring buildscript/build_common/core/bin, $(USE_SECGETSPF)),)
ifneq ($(shell secgetspf SEC_PRODUCT_FEATURE_BIOAUTH_CONFIG_FINGERPRINT_TZ), false)
ifeq ($(CONFIG_SENSORS_FINGERPRINT), y)
ifndef CONFIG_SEC_FACTORY
export KBUILD_FP_SENSOR_CFLAGS := -DENABLE_SENSORS_FPRINT_SECURE
endif
endif
endif
else
ifeq ($(CONFIG_SENSORS_FINGERPRINT), y)
ifndef CONFIG_SEC_FACTORY
export KBUILD_FP_SENSOR_CFLAGS := -DENABLE_SENSORS_FPRINT_SECURE
endif
endif
endif
ifneq ($(shell secgetspf SEC_PRODUCT_FEATURE_COMMON_CONFIG_SEP_VERSION),)
SEP_MAJOR_VERSION := $(shell secgetspf SEC_PRODUCT_FEATURE_COMMON_CONFIG_SEP_VERSION | cut -f1 -d.)
SEP_MINOR_VERSION := $(shell secgetspf SEC_PRODUCT_FEATURE_COMMON_CONFIG_SEP_VERSION | cut -f2 -d.)
export KBUILD_SEP_VERSION := -DSEP_KVERSION=$(SEP_MAJOR_VERSION)$(SEP_MINOR_VERSION)
endif
# Default kernel image to build when no specific target is given.
# KBUILD_IMAGE may be overruled on the command line or
# set in the environment
@@ -1392,7 +1414,7 @@ headers_install: __headers
$(error Headers not exportable for the $(SRCARCH) architecture))
$(Q)$(MAKE) $(hdr-inst)=include/uapi dst=include
$(Q)$(MAKE) $(hdr-inst)=arch/$(hdr-arch)/include/uapi $(hdr-dst)
$(Q)$(MAKE) $(hdr-inst)=techpack
$(Q)$(MAKE) $(hdr-inst)=techpack/audio/include/uapi dst=techpack/audio/include
PHONY += headers_check_all
headers_check_all: headers_install_all
@@ -1402,7 +1424,7 @@ PHONY += headers_check
headers_check: headers_install
$(Q)$(MAKE) $(hdr-inst)=include/uapi dst=include HDRCHECK=1
$(Q)$(MAKE) $(hdr-inst)=arch/$(hdr-arch)/include/uapi $(hdr-dst) HDRCHECK=1
$(Q)$(MAKE) $(hdr-inst)=techpack HDRCHECK=1
$(Q)$(MAKE) $(hdr-inst)=techpack/audio/include/uapi dst=techpack/audio/include HDRCHECK=1
# ---------------------------------------------------------------------------
# Kernel selftest

226
arch/arm/include/asm/sec_debug.h Normal file
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@@ -0,0 +1,226 @@
#ifndef SEC_DEBUG_ARM_H
#define SEC_DEBUG_ARM_H
#if defined(CONFIG_ARM) && defined(CONFIG_SEC_DEBUG)
struct sec_debug_mmu_reg_t {
uint32_t SCTLR;
uint32_t TTBR0;
uint32_t TTBR1;
uint32_t TTBCR;
uint32_t DACR;
uint32_t DFSR;
uint32_t DFAR;
uint32_t IFSR;
uint32_t IFAR;
uint32_t DAFSR;
uint32_t IAFSR;
uint32_t PMRRR;
uint32_t NMRRR;
uint32_t FCSEPID;
uint32_t CONTEXT;
uint32_t URWTPID;
uint32_t UROTPID;
uint32_t POTPIDR;
};
/* ARM CORE regs mapping structure */
struct sec_debug_core_t {
/* COMMON */
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r4;
uint32_t r5;
uint32_t r6;
uint32_t r7;
uint32_t r8;
uint32_t r9;
uint32_t r10;
uint32_t r11;
uint32_t r12;
/* SVC */
uint32_t r13_svc;
uint32_t r14_svc;
uint32_t spsr_svc;
/* PC & CPSR */
uint32_t pc;
uint32_t cpsr;
/* USR/SYS */
uint32_t r13_usr;
uint32_t r14_usr;
/* FIQ */
uint32_t r8_fiq;
uint32_t r9_fiq;
uint32_t r10_fiq;
uint32_t r11_fiq;
uint32_t r12_fiq;
uint32_t r13_fiq;
uint32_t r14_fiq;
uint32_t spsr_fiq;
/* IRQ */
uint32_t r13_irq;
uint32_t r14_irq;
uint32_t spsr_irq;
/* MON */
uint32_t r13_mon;
uint32_t r14_mon;
uint32_t spsr_mon;
/* ABT */
uint32_t r13_abt;
uint32_t r14_abt;
uint32_t spsr_abt;
/* UNDEF */
uint32_t r13_und;
uint32_t r14_und;
uint32_t spsr_und;
};
static inline void sec_debug_save_core_reg(struct sec_debug_core_t *core_reg)
{
/* we will be in SVC mode when we enter this function. Collect
SVC registers along with cmn registers. */
asm volatile (
"str r0, [%0,#0]\n\t" /* R0 is pushed first to core_reg */
"mov r0, %0\n\t" /* R0 will be alias for core_reg */
"str r1, [r0,#4]\n\t" /* R1 */
"str r2, [r0,#8]\n\t" /* R2 */
"str r3, [r0,#12]\n\t" /* R3 */
"str r4, [r0,#16]\n\t" /* R4 */
"str r5, [r0,#20]\n\t" /* R5 */
"str r6, [r0,#24]\n\t" /* R6 */
"str r7, [r0,#28]\n\t" /* R7 */
"str r8, [r0,#32]\n\t" /* R8 */
"str r9, [r0,#36]\n\t" /* R9 */
"str r10, [r0,#40]\n\t" /* R10 */
"str r11, [r0,#44]\n\t" /* R11 */
"str r12, [r0,#48]\n\t" /* R12 */
/* SVC */
"str r13, [r0,#52]\n\t" /* R13_SVC */
"str r14, [r0,#56]\n\t" /* R14_SVC */
"mrs r1, spsr\n\t" /* SPSR_SVC */
"str r1, [r0,#60]\n\t"
/* PC and CPSR */
"sub r1, r15, #0x4\n\t" /* PC */
"str r1, [r0,#64]\n\t"
"mrs r1, cpsr\n\t" /* CPSR */
"str r1, [r0,#68]\n\t"
/* SYS/USR */
"mrs r1, cpsr\n\t" /* switch to SYS mode */
"and r1, r1, #0xFFFFFFE0\n\t"
"orr r1, r1, #0x1f\n\t"
"msr cpsr,r1\n\t"
"str r13, [r0,#72]\n\t" /* R13_USR */
"str r14, [r0,#76]\n\t" /* R14_USR */
/* FIQ */
"mrs r1, cpsr\n\t" /* switch to FIQ mode */
"and r1,r1,#0xFFFFFFE0\n\t"
"orr r1,r1,#0x11\n\t"
"msr cpsr,r1\n\t"
"str r8, [r0,#80]\n\t" /* R8_FIQ */
"str r9, [r0,#84]\n\t" /* R9_FIQ */
"str r10, [r0,#88]\n\t" /* R10_FIQ */
"str r11, [r0,#92]\n\t" /* R11_FIQ */
"str r12, [r0,#96]\n\t" /* R12_FIQ */
"str r13, [r0,#100]\n\t" /* R13_FIQ */
"str r14, [r0,#104]\n\t" /* R14_FIQ */
"mrs r1, spsr\n\t" /* SPSR_FIQ */
"str r1, [r0,#108]\n\t"
/* IRQ */
"mrs r1, cpsr\n\t" /* switch to IRQ mode */
"and r1, r1, #0xFFFFFFE0\n\t"
"orr r1, r1, #0x12\n\t"
"msr cpsr,r1\n\t"
"str r13, [r0,#112]\n\t" /* R13_IRQ */
"str r14, [r0,#116]\n\t" /* R14_IRQ */
"mrs r1, spsr\n\t" /* SPSR_IRQ */
"str r1, [r0,#120]\n\t"
/* ABT */
"mrs r1, cpsr\n\t" /* switch to Abort mode */
"and r1, r1, #0xFFFFFFE0\n\t"
"orr r1, r1, #0x17\n\t"
"msr cpsr,r1\n\t"
"str r13, [r0,#136]\n\t" /* R13_ABT */
"str r14, [r0,#140]\n\t" /* R14_ABT */
"mrs r1, spsr\n\t" /* SPSR_ABT */
"str r1, [r0,#144]\n\t"
/* UND */
"mrs r1, cpsr\n\t" /* switch to undef mode */
"and r1, r1, #0xFFFFFFE0\n\t"
"orr r1, r1, #0x1B\n\t"
"msr cpsr,r1\n\t"
"str r13, [r0,#148]\n\t" /* R13_UND */
"str r14, [r0,#152]\n\t" /* R14_UND */
"mrs r1, spsr\n\t" /* SPSR_UND */
"str r1, [r0,#156]\n\t"
/* restore to SVC mode */
"mrs r1, cpsr\n\t" /* switch to SVC mode */
"and r1, r1, #0xFFFFFFE0\n\t"
"orr r1, r1, #0x13\n\t"
"msr cpsr,r1\n\t" : /* output */
: "r"(core_reg) /* input */
: "%r0", "%r1" /* clobbered registers */
);
}
static void sec_debug_save_mmu_reg(struct sec_debug_mmu_reg_t *mmu_reg)
{
asm volatile (
"mrc p15, 0, r1, c1, c0, 0\n\t" /* SCTLR */
"str r1, [%0]\n\t"
"mrc p15, 0, r1, c2, c0, 0\n\t" /* TTBR0 */
"str r1, [%0,#4]\n\t"
"mrc p15, 0, r1, c2, c0,1\n\t" /* TTBR1 */
"str r1, [%0,#8]\n\t"
"mrc p15, 0, r1, c2, c0,2\n\t" /* TTBCR */
"str r1, [%0,#12]\n\t"
"mrc p15, 0, r1, c3, c0,0\n\t" /* DACR */
"str r1, [%0,#16]\n\t"
"mrc p15, 0, r1, c5, c0,0\n\t" /* DFSR */
"str r1, [%0,#20]\n\t"
"mrc p15, 0, r1, c6, c0,0\n\t" /* DFAR */
"str r1, [%0,#24]\n\t"
"mrc p15, 0, r1, c5, c0,1\n\t" /* IFSR */
"str r1, [%0,#28]\n\t"
"mrc p15, 0, r1, c6, c0,2\n\t" /* IFAR */
"str r1, [%0,#32]\n\t"
/* Don't populate DAFSR and RAFSR */
"mrc p15, 0, r1, c10, c2,0\n\t" /* PMRRR */
"str r1, [%0,#44]\n\t"
"mrc p15, 0, r1, c10, c2,1\n\t" /* NMRRR */
"str r1, [%0,#48]\n\t"
"mrc p15, 0, r1, c13, c0,0\n\t" /* FCSEPID */
"str r1, [%0,#52]\n\t"
"mrc p15, 0, r1, c13, c0,1\n\t" /* CONTEXT */
"str r1, [%0,#56]\n\t"
"mrc p15, 0, r1, c13, c0,2\n\t" /* URWTPID */
"str r1, [%0,#60]\n\t"
"mrc p15, 0, r1, c13, c0,3\n\t" /* UROTPID */
"str r1, [%0,#64]\n\t"
"mrc p15, 0, r1, c13, c0,4\n\t" /* POTPIDR */
"str r1, [%0,#68]\n\t" : /* output */
: "r"(mmu_reg) /* input */
: "%r1", "memory" /* clobbered register */
);
}
#endif /* defined(CONFIG_ARM) && defined(CONFIG_SEC_DEBUG) */
#endif /* SEC_DEBUG_ARM64_H */

87
arch/arm64/Kconfig
View File

@@ -109,9 +109,7 @@ config ARM64
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_API_DEBUG
select HAVE_DMA_CONTIGUOUS
select HAVE_DYNAMIC_FTRACE
select HAVE_EFFICIENT_UNALIGNED_ACCESS
select HAVE_FTRACE_MCOUNT_RECORD
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_GRAPH_TRACER if !SHADOW_CALL_STACK
select HAVE_GCC_PLUGINS
@@ -313,6 +311,7 @@ source "init/Kconfig"
source "kernel/Kconfig.freezer"
source "arch/arm64/Kconfig.projects"
source "arch/arm64/Kconfig.platforms"
menu "Bus support"
@@ -1024,16 +1023,6 @@ config ARM64_TAGGED_ADDR_ABI
to system calls as pointer arguments. For details, see
Documentation/arm64/tagged-address-abi.rst.
config MITIGATE_SPECTRE_BRANCH_HISTORY
bool "Mitigate Spectre style attacks against branch history" if EXPERT
default y
depends on HARDEN_BRANCH_PREDICTOR || !KVM
help
Speculation attacks against some high-performance processors can
make use of branch history to influence future speculation.
When taking an exception from user-space, a sequence of branches
or a firmware call overwrites the branch history.
menuconfig ARMV8_DEPRECATED
bool "Emulate deprecated/obsolete ARMv8 instructions"
depends on COMPAT
@@ -1109,6 +1098,78 @@ config ARM64_SW_TTBR0_PAN
zeroed area and reserved ASID. The user access routines
restore the valid TTBR0_EL1 temporarily.
config UH
bool "Enable micro hypervisor feature of Samsung"
depends on !SEC_FACTORY
default n
help
It enables a micro hypervisor.
It's samsung's hypervisor and it should be combined with QC hyp.
So you must check a hypX(samsung hypervisor image)
RKP and etc can be loaded on it.
config UH_RKP
bool "Enable RKP (Realtime Kernel Protection) UH feature"
select UH
default n
help
it protects a kernel text and etc.
config RKP_MODULE_SUPPORT
bool "RKP (Realtime Kernel Protection) supports and protect modules"
depends on UH_RKP
default n
help
it protects a kernel module text and etc.
config RKP_KDP
bool "Protection for cred structure"
depends on !SEC_VTS_TEST
depends on UH_RKP
default n
help
Prevents unauthorized cred modification.
config RKP_NS_PROT
bool "Protection for namespace structure"
depends on RKP_KDP
default n
help
Prevents unauthorized namespace modification.
config RKP_DMAP_PROT
bool "Page Double Mapping protection"
depends on RKP_KDP
default n
help
Prevents unauthorized mapping for page table.
config RKP_TEST
bool "Enable RKP test"
depends on UH_RKP && !SAMSUNG_PRODUCT_SHIP
default n
help
enable RKP test.
config KDP_TEST
bool "Enable KDP test"
depends on RKP_KDP && RKP_NS_PROT && !SAMSUNG_PRODUCT_SHIP
default n
help
enable KDP test.
config UH_LKMAUTH
bool "Enable LKM authentication by micro hypervisor"
depends on MODULES
help
micro hypervisor authenticates loaded kernel modules. Disable it if you don't
want CONFIG_UH enabled.
config UH_LKM_BLOCK
bool "Block LKM by micro hypervisor"
help
LKM is not allowed by Samsung security policy.
menu "ARMv8.1 architectural features"
config ARM64_HW_AFDBM
@@ -1443,6 +1504,8 @@ config SYSVIPC_COMPAT
endmenu
source "arch/arm64/Kconfig.sec"
menu "Power management options"
source "kernel/power/Kconfig"

24
arch/arm64/Kconfig.debug
View File

@@ -99,6 +99,30 @@ config ARM64_RELOC_TEST
config ARM64_STRICT_BREAK_BEFORE_MAKE
bool "Enforce strict break-before-make on page table updates "
comment "PowerManagement Feature"
menuconfig SEC_PM
bool "Samsung TN PowerManagement Feature"
default y
help
Samsung TN PowerManagement Feature.
if SEC_PM
config SEC_PM_DEBUG
bool "Samsung TN PowerManagement Debug Feature"
default n
help
Samsung TN PowerManagement Debug Feature.
endif
config KERNEL_MODE_NEON_DEBUG
bool "enable kernel neon mode debug. ex) fp/simd context checking "
depends on KERNEL_MODE_NEON
default n
help
Say Y here if you want to check debug information for simd/fp in kernel
source "drivers/hwtracing/coresight/Kconfig"
endmenu

3
arch/arm64/Kconfig.platforms
View File

@@ -222,6 +222,9 @@ config ARCH_SDMMAGPIE
This enables support for the SDMMAGPIE chipset. If you do not
wish to build a kernel that runs on this chipset, say 'N' here.
config ARCH_SEC_SM7150
bool "Enable Support for Qualcomm Technologies, Inc. SEC_SM7150"
config ARCH_TRINKET
bool "Enable Support for Qualcomm Technologies, Inc. TRINKET"
depends on ARCH_QCOM

0
arch/arm64/Kconfig.projects Normal file
View File

0
arch/arm64/Kconfig.sec Normal file
View File

3
arch/arm64/Makefile
View File

@@ -199,7 +199,8 @@ zinstall install:
PHONY += dtbs dtbs_install
dtbs: prepare scripts
$(Q)$(MAKE) $(build)=$(boot)/dts
# $(Q)$(MAKE) $(build)=$(boot)/dts
$(Q)$(MAKE) $(build)=$(boot)/dts/samsung
dtbs_install:
$(Q)$(MAKE) $(dtbinst)=$(boot)/dts

3
arch/arm64/boot/dts/Makefile
View File

@@ -15,10 +15,11 @@ dts-dirs += hisilicon
dts-dirs += marvell
dts-dirs += mediatek
dts-dirs += nvidia
dts-dirs += qcom
#dts-dirs += qcom
dts-dirs += realtek
dts-dirs += renesas
dts-dirs += rockchip
dts-dirs += samsung
dts-dirs += socionext
dts-dirs += sprd
dts-dirs += xilinx

2
arch/arm64/boot/dts/qcom/Makefile
View File

@@ -358,7 +358,6 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
trinket-usbc-external-codec-idp-overlay.dtbo \
trinket-usbc-idp-overlay.dtbo \
trinket-dp-idp-overlay.dtbo \
trinket-facepay-overlay.dtbo \
trinket-iot-idp-overlay.dtbo \
trinketp-iot-idp-overlay.dtbo \
trinket-iot-external-codec-idp-overlay.dtbo \
@@ -377,7 +376,6 @@ trinket-external-codec-idp-overlay.dtbo-base := trinket.dtb
trinket-usbc-external-codec-idp-overlay.dtbo-base := trinket.dtb
trinket-usbc-idp-overlay.dtbo-base := trinket.dtb
trinket-dp-idp-overlay.dtbo-base := trinket.dtb
trinket-facepay-overlay.dtbo-base := trinket-iot.dtb
trinket-iot-idp-overlay.dtbo-base := trinket-iot.dtb
trinketp-iot-idp-overlay.dtbo-base := trinketp-iot.dtb
trinket-iot-external-codec-idp-overlay.dtbo-base := trinket-iot.dtb

4
arch/arm64/boot/dts/qcom/atoll-audio-overlay.dtsi
View File

@@ -226,7 +226,7 @@
qcom,cdc-vdd-buck-current = <650000>;
cdc-vdd-mic-bias-supply = <&BOB>;
qcom,cdc-vdd-mic-bias-voltage = <3300000 3600000>;
qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>;
qcom,cdc-vdd-mic-bias-current = <30000>;
qcom,cdc-micbias1-mv = <1800>;
@@ -273,7 +273,7 @@
qcom,cdc-vdd-buck-current = <650000>;
cdc-vdd-mic-bias-supply = <&BOB>;
qcom,cdc-vdd-mic-bias-voltage = <3300000 3600000>;
qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>;
qcom,cdc-vdd-mic-bias-current = <30000>;
qcom,cdc-micbias1-mv = <1800>;

92
arch/arm64/boot/dts/qcom/atoll-camera-sensor-idp.dtsi
View File

@@ -63,17 +63,6 @@
switch-source = <&pm6150l_switch2 &pm6150l_switch2>;
status = "ok";
};
vreg_tof: regulator-dbb1 {
compatible = "regulator-fixed";
regulator-name = "vdd_tof";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 118 GPIO_ACTIVE_HIGH>;
startup-delay-us = <1000>;
enable-active-high;
};
};
&cam_cci0 {
@@ -326,44 +315,6 @@
clock-rates = <19200000>;
};
eeprom_tof: qcom,eeprom@7 {
cell-index = <7>;
reg = <7>;
compatible = "qcom,eeprom";
cam_vio-supply = <&L5P>;
cam_vana-supply = <&L4P>;
cam_vdig-supply = <&vreg_tof>;
cam_clk-supply = <&titan_top_gdsc>;
regulator-names = "cam_vio", "cam_vana", "cam_vdig",
"cam_clk";
rgltr-cntrl-support;
rgltr-min-voltage = <1800000 3300000 1800000 0>;
rgltr-max-voltage = <1800000 3300000 1800000 0>;
rgltr-load-current = <0 80000 4000 0>;
gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk3_active
&cam_sensor_tof_active>;
pinctrl-1 = <&cam_sensor_mclk3_suspend
&cam_sensor_tof_suspend>;
gpios = <&tlmm 16 0>,
<&tlmm 24 0>;
gpio-reset = <1>;
gpio-req-tbl-num = <0 1>;
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
sensor-mode = <0>;
cci-device = <1>;
cci-master = <0>;
status = "ok";
clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "turbo";
clock-rates = <24000000>;
};
qcom,cam-sensor@0 {
cell-index = <0>;
compatible = "qcom,cam-sensor";
@@ -619,47 +570,4 @@
clock-cntl-level = "turbo";
clock-rates = <19200000>;
};
qcom,cam-sensor@7 {
cell-index = <7>;
compatible = "qcom,cam-sensor";
reg = <0x7>;
csiphy-sd-index = <3>;
sensor-position-roll = <270>;
sensor-position-pitch = <0>;
sensor-position-yaw = <0>;
eeprom-src = <&eeprom_tof>;
cam_vio-supply = <&L5P>;
cam_vana-supply = <&L4P>;
cam_vdig-supply = <&vreg_tof>;
cam_clk-supply = <&titan_top_gdsc>;
regulator-names = "cam_vio", "cam_vana", "cam_vdig",
"cam_clk";
rgltr-cntrl-support;
rgltr-min-voltage = <1800000 3300000 1800000 0>;
rgltr-max-voltage = <1800000 3300000 1800000 0>;
rgltr-load-current = <0 80000 4000 0>;
gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk3_active
&cam_sensor_tof_active>;
pinctrl-1 = <&cam_sensor_mclk3_suspend
&cam_sensor_tof_suspend>;
gpios = <&tlmm 16 0>,
<&tlmm 24 0>;
gpio-reset = <1>;
gpio-req-tbl-num = <0 1>;
gpio-req-tbl-flags = <1 0>;
gpio-req-tbl-label = "CAMIF_MCLK3",
"CAM_RESET3";
sensor-mode = <0>;
cci-device = <1>;
cci-master = <0>;
status = "ok";
clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
clock-names = "cam_clk";
clock-cntl-level = "turbo";
clock-rates = <24000000>;
};
};

4
arch/arm64/boot/dts/qcom/atoll-camera.dtsi
View File

@@ -140,7 +140,7 @@
src-clock-name = "csi2phytimer_clk_src";
clock-cntl-level = "svs", "svs_l1", "turbo";
clock-rates =
<0 0 0 0 270000000 0 300000000 0>,
<0 0 0 0 300000000 0 300000000 0>,
<0 0 0 0 360000000 0 300000000 0>,
<0 0 0 0 360000000 0 300000000 0>;
status = "ok";
@@ -827,7 +827,7 @@
status = "ok";
};
qcom,cpas-cdm0@ac48000 {
camera:qcom,cpas-cdm0@ac48000 {
cell-index = <0>;
compatible = "qcom,cam170-cpas-cdm0";
label = "cpas-cdm";

5
arch/arm64/boot/dts/qcom/atoll-idp.dtsi
View File

@@ -14,7 +14,6 @@
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
#include "atoll-camera-sensor-idp.dtsi"
#include "atoll-sde-display.dtsi"
#include "sdmmagpie-thermal-overlay.dtsi"
@@ -48,6 +47,7 @@
};
};
/*
&usb0 {
extcon = <&pm6150_pdphy>, <&pm6150_charger>, <&eud>;
};
@@ -55,6 +55,7 @@
&usb_qmp_dp_phy {
extcon = <&pm6150_pdphy>;
};
*/
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v3";
@@ -199,7 +200,7 @@
};
&soc {
gpio_keys {
gpio_key:gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";

2
arch/arm64/boot/dts/qcom/atoll-ion.dtsi
View File

@@ -44,7 +44,7 @@
qcom,ion-heap-type = "HYP_CMA";
};
qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */
secure_carveout_heap: qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */
reg = <14>;
qcom,ion-heap-type = "SECURE_CARVEOUT";
cdsp {

108
arch/arm64/boot/dts/qcom/atoll-lpi.dtsi
View File

@@ -419,5 +419,113 @@
bias-bus-hold;
};
};
lpi_i2s1_sck_active: lpi_i2s1_sck_active {
mux {
pins = "gpio6";
function = "func2";
};
config {
pins = "gpio6";
drive-strength = <8>;
output-high;
};
};
lpi_i2s1_sck_sleep: lpi_i2s1_sck_sleep {
mux {
pins = "gpio6";
function = "func2";
};
config {
pins = "gpio6";
drive-strength = <2>;
bias-disable;
output-low;
};
};
lpi_i2s1_ws_active: lpi_i2s1_ws_active {
mux {
pins = "gpio7";
function = "func2";
};
config {
pins = "gpio7";
drive-strength = <8>;
output-high;
};
};
lpi_i2s1_ws_sleep: lpi_i2s1_ws_sleep {
mux {
pins = "gpio7";
function = "func2";
};
config {
pins = "gpio7";
drive-strength = <2>;
bias-disable;
output-low;
};
};
lpi_i2s1_sd0_active: lpi_i2s1_sd0_active {
mux {
pins = "gpio8";
function = "func2";
};
config {
pins = "gpio8";
drive-strength = <8>;
output-high;
};
};
lpi_i2s1_sd0_sleep: lpi_i2s1_sd0_sleep {
mux {
pins = "gpio8";
function = "func2";
};
config {
pins = "gpio8";
drive-strength = <2>;
bias-disable;
output-low;
};
};
lpi_i2s1_sd1_active: lpi_i2s1_sd1_active {
mux {
pins = "gpio9";
function = "func2";
};
config {
pins = "gpio9";
drive-strength = <8>;
output-high;
};
};
lpi_i2s1_sd1_sleep: lpi_i2s1_sd1_sleep {
mux {
pins = "gpio9";
function = "func2";
};
config {
pins = "gpio9";
drive-strength = <2>;
bias-disable;
output-low;
};
};
};
};

8
arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi
View File

@@ -951,7 +951,7 @@
config {
pins = "gpio46", "gpio47";
drive-strength = <2>;
bias-disable;
bias-pull-down;
};
};
@@ -964,7 +964,7 @@
config {
pins = "gpio46", "gpio47";
drive-strength = <2>;
bias-pull-up;
bias-pull-down;
};
};
};
@@ -979,7 +979,7 @@
config {
pins = "gpio86", "gpio87";
drive-strength = <2>;
bias-disable;
bias-pull-down;
};
};
@@ -992,7 +992,7 @@
config {
pins = "gpio86", "gpio87";
drive-strength = <2>;
bias-pull-up;
bias-pull-down;
};
};
};

8
arch/arm64/boot/dts/qcom/atoll-thermal.dtsi
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -611,12 +611,6 @@
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};

15
arch/arm64/boot/dts/qcom/atoll.dtsi
View File

@@ -45,7 +45,7 @@
mboxes = <&qmp_aop 0>;
};
aliases {
aliases: aliases {
serial0 = &qupv3_se8_2uart;
sdhc1 = &sdhc_1; /* eMMC */
sdhc2 = &sdhc_2; /* SD Card */
@@ -463,11 +463,11 @@
firmware: firmware {
android {
compatible = "android,firmware";
vbmeta {
shared_meta: vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
android_q_fstab: fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
@@ -869,7 +869,7 @@
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
qcom,msm-imem@146aa000 {
msm_imem: qcom,msm-imem@146aa000 {
compatible = "qcom,msm-imem";
reg = <0x146aa000 0x1000>;
ranges = <0x0 0x146aa000 0x1000>;
@@ -1494,7 +1494,7 @@
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<129 512 0 0>,
<129 512 0 1041408>;
<129 512 0 8171520>;
/* Inputs from mss */
interrupts-extended = <&pdc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
@@ -1601,6 +1601,7 @@
qcom,msm_fastrpc {
compatible = "qcom,msm-fastrpc-compute";
qcom,rpc-latency-us = <611>;
qcom,secure-domains = <0x0F>;
qcom,adsp-remoteheap-vmid = <22 37>;
qcom,fastrpc-adsp-audio-pdr;
qcom,fastrpc-adsp-sensors-pdr;
@@ -2799,6 +2800,8 @@
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100750000 200000000 4294967295>;
qcom,restore-after-cx-collapse;
/* PM QoS */
qcom,pm-qos-irq-type = "affine_irq";
qcom,pm-qos-irq-latency = <67 67>;
@@ -4277,7 +4280,7 @@
&L4P {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3400000>;
regulator-max-microvolt = <2800000>;
qcom,min-dropout-voltage = <200000>;
};

21
arch/arm64/boot/dts/qcom/mdm9607-thermal.dtsi
View File

@@ -40,16 +40,6 @@
};
};
};
ddr_cdev: qcom,ddr-cdev {
compatible = "qcom,ddr-cooling-device";
qcom,msm-bus,name = "ddr-cdev";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <1 512 0 0>,
<1 512 0 366000>;
#cooling-cells = <2>;
};
};
&thermal_zones {
@@ -184,12 +174,6 @@
thermal-governor = "step_wise";
wake-capable-sensor;
trips {
cdev_trip: cdev-trip {
temperature = <78000>;
hysteresis = <8000>;
type = "passive";
};
modem_pa_trip0: modem_pa_trip0 {
temperature = <95000>;
hysteresis = <5000>;
@@ -218,11 +202,6 @@
};
cooling-maps {
ddr_cdev0 {
trip = <&cdev_trip>;
cooling-device = <&ddr_cdev 1 1>;
};
modem_pa0_cdev {
trip = <&modem_pa_trip0>;
cooling-device = <&modem_pa 1 1>;

8
arch/arm64/boot/dts/qcom/mdm9607.dtsi
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -1400,12 +1400,6 @@
qcom,smdpkt-dev-name = "apr_apps2";
};
qcom,smdpkt-data-mdm1 {
qcom,smdpkt-edge = "modem";
qcom,smdpkt-ch-name = "DS";
qcom,smdpkt-dev-name = "at_mdm1";
};
qcom,smdpkt-data1 {
qcom,smdpkt-edge = "modem";
qcom,smdpkt-ch-name = "DATA1";

18
arch/arm64/boot/dts/qcom/pm6150.dtsi
View File

@@ -359,7 +359,6 @@
"temp-change",
"temp-change-smb";
};
qcom,sdam@b100 {
reg = <0xb100 0x100>;
interrupts =
@@ -416,6 +415,8 @@
qcom,vbatt-empty-mv = <3000>;
qcom,vbatt-empty-cold-mv = <3000>;
qcom,s3-entry-fifo-length = <2>;
qcom,s3-entry-ibat-ua = <15000>;
qcom,s3-exit-ibat-ua = <35000>;
qcom,pmic-revid = <&pm6150_revid>;
io-channels = <&pm6150_vadc ADC_BAT_THERM_PU2>,
@@ -497,6 +498,16 @@
gpio-controller;
#gpio-cells = <2>;
qcom,gpios-disallowed = <5 6 9 10>;
afc_switch {
gpio1_afc_switch_default: gpio1_afc_switch_default {
pins = "gpio1"; /* GPIO 1 */
function = "normal"; /* normal output */
power-source = <0>; /* VIN0 */
output-low; /* digital output, no invert */
input-disable; /* prevent GPIO from being set to DIO */
};
};
};
pm6150_rtc: qcom,pm6150_rtc {
@@ -526,7 +537,7 @@
pm6150_vib: qcom,vibrator@5300 {
compatible = "qcom,qpnp-vibrator-ldo";
reg = <0x5300 0x100>;
qcom,vib-ldo-volt-uv = <3000000>;
qcom,vib-ldo-volt-uv = <3300000>;
qcom,disable-overdrive;
};
};
@@ -643,6 +654,7 @@
};
pm6150-bcl-lvl0 {
disable-thermal-zone;
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
@@ -659,6 +671,7 @@
};
pm6150-bcl-lvl1 {
disable-thermal-zone;
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
@@ -675,6 +688,7 @@
};
pm6150-bcl-lvl2 {
disable-thermal-zone;
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";

48
arch/arm64/boot/dts/qcom/pm6150l.dtsi
View File

@@ -87,6 +87,15 @@
label = "vph_pwr";
qcom,pre-scaling = <1 3>;
};
rid_adc {
reg = <ADC_GPIO4>;
label = "rid_adc";
qcom,pre-scaling = <1 1>;
qcom,hw-settle-time = <700>;
qcom,decimation = <840>;
qcom,avg-samples = <4>;
};
};
pm6150l_adc_tm: adc_tm@3500 {
@@ -134,6 +143,25 @@
"pm6150l_gpio11", "pm6150l_gpio12";
gpio-controller;
#gpio-cells = <2>;
rid_adc_irq {
rid_adc_irq_default: rid_adc_irq_default {
pins = "gpio9";
function = "normal";
bias-disable;
power-source = <1>;
input-enable;
};
};
gpio11_dig_out {
gpio11_dig_out_default: gpio11_dig_out_default {
pins = "gpio11"; /* GPIO 11 */
function = "normal"; /* normal output */
power-source = <0>; /* VIN0 */
input-disable; /* prevent GPIO from being set to DIO */
};
};
};
};
@@ -143,15 +171,6 @@
#address-cells = <1>;
#size-cells = <1>;
pm6150l_pwm_1: qcom,pwms@bc00 {
status = "disabled";
compatible = "qcom,pwm-lpg";
reg = <0xbc00 0x100>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <1>;
#pwm-cells = <2>;
};
pm6150l_lcdb: qcom,lcdb@ec00 {
compatible = "qcom,qpnp-lcdb-regulator";
#address-cells = <1>;
@@ -377,6 +396,14 @@
};
};
pm6150l_pwm: qcom,pwms@bc00 {
compatible = "qcom,pwm-lpg";
reg = <0xbc00 0x200>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <2>;
#pwm-cells = <2>;
};
pm6150l_rgb_led: qcom,leds@d000 {
compatible = "qcom,tri-led";
reg = <0xd000 0x100>;
@@ -513,6 +540,7 @@
};
pm6150l-bcl-lvl0 {
disable-thermal-zone;
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
@@ -529,6 +557,7 @@
};
pm6150l-bcl-lvl1 {
disable-thermal-zone;
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
@@ -545,6 +574,7 @@
};
pm6150l-bcl-lvl2 {
disable-thermal-zone;
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";

14
arch/arm64/boot/dts/qcom/pm8008.dtsi
View File

@@ -57,7 +57,7 @@ pm8008_9: qcom,pm8008@9 {
regulator-min-microvolt = <528000>;
regulator-max-microvolt = <1504000>;
qcom,min-dropout-voltage = <225000>;
qcom,hpm-min-load = <0>;
qcom,hpm-min-load = <10000>;
};
L2P: qcom,pm8008-l2@4100 {
@@ -66,7 +66,7 @@ pm8008_9: qcom,pm8008@9 {
regulator-min-microvolt = <528000>;
regulator-max-microvolt = <1504000>;
qcom,min-dropout-voltage = <225000>;
qcom,hpm-min-load = <0>;
qcom,hpm-min-load = <10000>;
};
L3P: qcom,pm8008-l3@4200 {
@@ -75,7 +75,7 @@ pm8008_9: qcom,pm8008@9 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3400000>;
qcom,min-dropout-voltage = <200000>;
qcom,hpm-min-load = <0>;
qcom,hpm-min-load = <10000>;
};
L4P: qcom,pm8008-l4@4300 {
@@ -84,7 +84,7 @@ pm8008_9: qcom,pm8008@9 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3400000>;
qcom,min-dropout-voltage = <200000>;
qcom,hpm-min-load = <0>;
qcom,hpm-min-load = <10000>;
};
L5P: qcom,pm8008-l5@4400 {
@@ -93,7 +93,7 @@ pm8008_9: qcom,pm8008@9 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3400000>;
qcom,min-dropout-voltage = <300000>;
qcom,hpm-min-load = <0>;
qcom,hpm-min-load = <10000>;
};
L6P: qcom,pm8008-l6@4400 {
@@ -102,7 +102,7 @@ pm8008_9: qcom,pm8008@9 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3400000>;
qcom,min-dropout-voltage = <300000>;
qcom,hpm-min-load = <0>;
qcom,hpm-min-load = <10000>;
};
L7P: qcom,pm8008-l7@4400 {
@@ -111,7 +111,7 @@ pm8008_9: qcom,pm8008@9 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <3400000>;
qcom,min-dropout-voltage = <300000>;
qcom,hpm-min-load = <0>;
qcom,hpm-min-load = <10000>;
};
};
};

0
arch/arm64/boot/dts/qcom/sdmmagpie-camera-sensor-qrd.dtsi Normal file → Executable file
View File

19
arch/arm64/boot/dts/qcom/sdmmagpie-camera.dtsi
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, 2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -10,7 +10,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&soc {
qcom,cam-req-mgr {
compatible = "qcom,cam-req-mgr";
@@ -593,9 +592,10 @@
cam_vfe0: qcom,vfe0@acaf000 {
cell-index = <0>;
compatible = "qcom,vfe175_130";
reg-names = "ife";
reg = <0xacaf000 0x5200>;
reg-cam-base = <0xaf000>;
reg-names = "ife", "cam_camnoc";
reg = <0xacaf000 0x5200>,
<0xac42000 0x6000>;
reg-cam-base = <0xaf000 0x42000>;
interrupt-names = "ife";
interrupts = <0 465 0>;
regulator-names = "camss", "ife0";
@@ -665,9 +665,10 @@
cam_vfe1: qcom,vfe1@acb6000 {
cell-index = <1>;
compatible = "qcom,vfe175_130";
reg-names = "ife";
reg = <0xacb6000 0x5200>;
reg-cam-base = <0xb6000>;
reg-names = "ife", "cam_camnoc";
reg = <0xacb6000 0x5200>,
<0xac42000 0x6000>;
reg-cam-base = <0xb6000 0x42000>;
interrupt-names = "ife";
interrupts = <0 467 0>;
regulator-names = "camss", "ife1";
@@ -994,7 +995,7 @@
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
clock-rates =
<380000000 0 0>,
<400000000 0 0>,
<384000000 0 0>,
<480000000 0 0>,
<600000000 0 0>;
status = "ok";

35
arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi
View File

@@ -16,7 +16,7 @@
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
#include "sdmmagpie-sde-display.dtsi"
#include "sdmmagpie-camera-sensor-idp.dtsi"
/*#include "sdmmagpie-camera-sensor-idp.dtsi"*/
&soc {
mtp_batterydata: qcom,battery-data {
@@ -55,7 +55,7 @@
vcc-supply = <&pm6150_l19>;
vcc-voltage-level = <2950000 2960000>;
vccq2-supply = <&pm6150_l12>;
vccq2-voltage-level = <1750000 1950000>;
vccq2-voltage-level = <1800000 1800000>;
vcc-max-microamp = <600000>;
vccq2-max-microamp = <600000>;
@@ -129,7 +129,6 @@
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
};
&dsi_sw43404_amoled_cmd {
@@ -138,7 +137,6 @@
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
};
&dsi_sw43404_amoled_fhd_plus_cmd {
@@ -156,7 +154,6 @@
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
qcom,platform-en-gpio = <&pm6150l_gpios 4 0>;
qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>;
};
@@ -202,37 +199,31 @@
&dsi_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
};
&dsi_sim_vid {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
};
&dsi_dual_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
};
&dsi_dual_sim_vid {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
};
&dsi_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
};
&dsi_dual_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
};
&dsi_nt35695b_truly_fhd_video {
@@ -367,14 +358,12 @@
<&pm6150_vadc ADC_USB_IN_I>,
<&pm6150_vadc ADC_CHG_TEMP>,
<&pm6150_vadc ADC_DIE_TEMP>,
<&pm6150l_vadc ADC_AMUX_THM1_PU2>,
<&pm6150_vadc ADC_SBUx>,
<&pm6150_vadc ADC_VPH_PWR>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage";
qcom,battery-data = <&mtp_batterydata>;
@@ -404,6 +393,24 @@
};
};
&soc {
i2c_13: 12c@13 {
status = "ok";
cell-index = <13>;
compatible = "i2c-gpio";
gpios = <&tlmm 42 0 /*sda*/
&tlmm 43 0 /*scl*/
>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&smb1390_i2c_active>;
#include "smb1390.dtsi"
};
};
#if 0 /* block for smb1355 + sm7150 */
&qupv3_se9_i2c {
status = "ok";
#include "smb1390.dtsi"
@@ -419,7 +426,7 @@
&smb1355_charger {
status = "ok";
};
#endif
&smb1390 {
/delete-property/ interrupts;
interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>;

43
arch/arm64/boot/dts/qcom/sdmmagpie-pinctrl.dtsi
View File

@@ -486,6 +486,22 @@
};
};
/* smb1390 i2c */
smb1390_i2c: smb1390_i2c {
smb1390_i2c_active: smb1390_i2c_active {
mux {
pins = "gpio43", "gpio42";
function = "gpio";
};
config {
pins = "gpio43", "gpio42";
drive-strength = <2>;
bias-disable;
};
};
};
qupv3_se4_4uart_pins: qupv3_se4_4uart_pins {
qupv3_se4_ctsrx: qupv3_se4_ctsrx {
mux {
@@ -927,6 +943,7 @@
pins = "gpio101", "gpio102";
drive-strength = <2>;
bias-pull-up;
input-enable;
};
};
};
@@ -1270,7 +1287,7 @@
config {
pins = "gpio17","gpio18";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
drive-strength = <16>; /* 16 MA */
};
};
@@ -1283,8 +1300,8 @@
config {
pins = "gpio17","gpio18";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
bias-disable; /* NO PULL */
drive-strength = <16>; /* 16 MA */
};
};
@@ -1298,7 +1315,7 @@
config {
pins = "gpio19","gpio20";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
drive-strength = <16>; /* 16 MA */
};
};
@@ -1311,8 +1328,8 @@
config {
pins = "gpio19","gpio20";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
bias-disable; /* NO PULL */
drive-strength = <16>; /* 16 MA */
};
};
@@ -1326,7 +1343,7 @@
config {
pins = "gpio27","gpio28";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
drive-strength = <16>; /* 16 MA */
};
};
@@ -1339,8 +1356,8 @@
config {
pins = "gpio27","gpio28";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
bias-disable; /* NO PULL */
drive-strength = <16>; /* 16 MA */
};
};
@@ -1570,12 +1587,12 @@
sdc2_cd_on: cd_on {
mux {
pins = "gpio69";
pins = "gpio00";
function = "gpio";
};
config {
pins = "gpio69";
pins = "gpio00";
drive-strength = <2>;
bias-pull-up;
};
@@ -1583,12 +1600,12 @@
sdc2_cd_off: cd_off {
mux {
pins = "gpio69";
pins = "gpio00";
function = "gpio";
};
config {
pins = "gpio69";
pins = "gpio00";
drive-strength = <2>;
bias-disable;
};

4
arch/arm64/boot/dts/qcom/sdmmagpie-qrd.dtsi
View File

@@ -17,7 +17,7 @@
#include "sdmmagpie-thermal-overlay.dtsi"
#include "sdmmagpie-sde-display.dtsi"
#include "sdmmagpie-camera-sensor-qrd.dtsi"
/*#include "sdmmagpie-camera-sensor-qrd.dtsi"*/
&soc {
fpc1020 {
compatible = "fpc,fpc1020";
@@ -285,14 +285,12 @@
<&pm6150_vadc ADC_USB_IN_I>,
<&pm6150_vadc ADC_CHG_TEMP>,
<&pm6150_vadc ADC_DIE_TEMP>,
<&pm6150l_vadc ADC_AMUX_THM1_PU2>,
<&pm6150_vadc ADC_SBUx>,
<&pm6150_vadc ADC_VPH_PWR>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage";
qcom,battery-data = <&mtp_batterydata>;

1
arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi
View File

@@ -371,7 +371,6 @@
pinctrl-1 = <&sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
qcom,panel-te-source = <0>;
vddio-supply = <&pm6150_l13>;

8
arch/arm64/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi
View File

@@ -14,6 +14,7 @@
&thermal_zones {
pm6150-tz {
disable-thermal-zone;
cooling-maps {
trip0_bat {
trip = <&pm6150_trip0>;
@@ -31,6 +32,7 @@
};
pm6150l-tz {
disable-thermal-zone;
cooling-maps {
trip0_cpu0 {
trip = <&pm6150l_trip0>;
@@ -126,6 +128,7 @@
};
pm6150-bcl-lvl0 {
disable-thermal-zone;
cooling-maps {
vbat_cpu6 {
trip = <&bcl_lvl0>;
@@ -143,6 +146,7 @@
};
pm6150-bcl-lvl1 {
disable-thermal-zone;
cooling-maps {
ibat_cpu6 {
trip = <&bcl_lvl1>;
@@ -160,6 +164,7 @@
};
pm6150-bcl-lvl2 {
disable-thermal-zone;
cooling-maps {
ibat_cpu6 {
trip = <&bcl_lvl2>;
@@ -177,6 +182,7 @@
};
soc {
disable-thermal-zone;
cooling-maps {
soc_cpu6 {
trip = <&soc_trip>;
@@ -196,4 +202,4 @@
&mdss_mdp {
#cooling-cells = <2>;
};
};

601
arch/arm64/boot/dts/qcom/sdmmagpie-thermal.dtsi
View File

@@ -1013,104 +1013,23 @@
};
};
aoss-0-lowf {
aoss-lowc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-governor = "low_limits_cap";
thermal-sensors = <&tsens0 0>;
wake-capable-sensor;
tracks-low;
trips {
aoss0_trip: aoss0-trip {
aoss_lowc: aoss-lowc {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&aoss0_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&aoss0_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
cpu-0-0-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 1>;
wake-capable-sensor;
tracks-low;
trips {
cpu_0_0_trip: cpu-0-0-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&cpu_0_0_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&cpu_0_0_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&cpu_0_0_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&cpu_0_0_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&cpu_0_0_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&cpu_0_0_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&cpu_0_0_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&cpu_0_0_trip>;
cooling-device = <&cdsp_vdd 0 0>;
audio_cdev {
trip = <&aoss_lowc>;
};
};
};
@@ -1166,516 +1085,6 @@
};
};
gpuss-0-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 13>;
wake-capable-sensor;
tracks-low;
trips {
gpuss_0_trip: gpuss-0-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&gpuss_0_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&gpuss_0_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&gpuss_0_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&gpuss_0_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&gpuss_0_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&gpuss_0_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&gpuss_0_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&gpuss_0_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
cwlan-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens1 1>;
wake-capable-sensor;
tracks-low;
trips {
cwlan_trip: cwlan-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&cwlan_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&cwlan_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&cwlan_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&cwlan_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&cwlan_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&cwlan_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&cwlan_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&cwlan_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
audio-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens1 2>;
wake-capable-sensor;
tracks-low;
trips {
audio_trip: audio-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&audio_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&audio_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&audio_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&audio_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&audio_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&audio_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&audio_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&audio_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
ddr-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens1 3>;
wake-capable-sensor;
tracks-low;
trips {
ddr_trip: ddr-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&ddr_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&ddr_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&ddr_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&ddr_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&ddr_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&ddr_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&ddr_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&ddr_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
q6-hvx-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens1 4>;
wake-capable-sensor;
tracks-low;
trips {
q6_hvx_trip: q6-hvx-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
camera-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens1 5>;
wake-capable-sensor;
tracks-low;
trips {
camera_trip: camera-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&camera_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&camera_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
mdm-core-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens1 6>;
wake-capable-sensor;
tracks-low;
trips {
mdm_core_trip: mdm-core-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
mdm-dsp-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens1 7>;
wake-capable-sensor;
tracks-low;
trips {
mdm_dsp_trip: mdm-dsp-lowf-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&mdm_dsp_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&mdm_dsp_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&mdm_dsp_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&mdm_dsp_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&mdm_dsp_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&mdm_dsp_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&mdm_dsp_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&mdm_dsp_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
npu-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens1 8>;
wake-capable-sensor;
tracks-low;
trips {
npu_trip: npu-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&npu_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&npu_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&npu_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&npu_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&npu_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&npu_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&npu_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&npu_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
video-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens1 9>;
wake-capable-sensor;
tracks-low;
trips {
video_trip: video-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&video_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&video_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
npu-step {
polling-delay-passive = <10>;
polling-delay = <0>;

1
arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi
View File

@@ -221,7 +221,6 @@
vdd-supply = <&pm6150_l4>;
qcom,vdd-voltage-level = <0 880000 880000>;
core-supply = <&pm6150l_l3>;
extcon = <&pm6150_pdphy>;
qcom,vbus-valid-override;
qcom,qmp-phy-init-seq =
/* <reg_offset, value, delay> */

34
arch/arm64/boot/dts/qcom/sdmmagpie.dtsi
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -35,7 +35,7 @@
qcom,msm-name = "SDMMAGPIE";
interrupt-parent = <&pdc>;
aliases {
aliases: aliases {
spi0 = &qupv3_se0_spi;
spi1 = &qupv3_se4_spi;
i2c0 = &qupv3_se2_i2c;
@@ -465,13 +465,15 @@
soc: soc { };
firmware: firmware {
android {
android: android {
compatible = "android,firmware";
vbmeta {
shared_meta: vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
/* Disabled for VTS. VTS test check if devicetree-dt fstab is or not. If it is, it check metadata.
* It does not match SS style. Because SS does not support dt fstab in Q
android_q_fstab: fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
@@ -482,10 +484,11 @@
status = "ok";
};
};
*/
};
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -496,10 +499,10 @@
reg = <0 0x85700000 0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@85e00000 {
xbl_aop_mem: xbl_aop_mem@85d00000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x85e00000 0x0 0x1ff000>;
reg = <0x0 0x85d00000 0x0 0x2ff000>;
};
sec_apps_mem: sec_apps_region@85fff000 {
@@ -643,7 +646,7 @@
};
dfps_data_memory: dfps_data_region@9d700000 {
reg = <0x0 0x9d700000 0x0 0x0100000>;
reg = <0x0 0x9e300000 0x0 0x0100000>;
label = "dfps_data_region";
};
@@ -663,6 +666,7 @@
linux,cma-default;
};
};
};
&soc {
@@ -1057,6 +1061,11 @@
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 200>;
};
upload_cause@66c {
compatible = "qcom,msm-imem-upload_cause";
reg = <0x66c 4>;
};
};
restart@c264000 {
@@ -1611,6 +1620,7 @@
qcom,msm_fastrpc {
compatible = "qcom,msm-fastrpc-compute";
qcom,rpc-latency-us = <611>;
qcom,secure-domains = <0x0F>;
qcom,adsp-remoteheap-vmid = <22 37>;
qcom,fastrpc-adsp-audio-pdr;
qcom,fastrpc-adsp-sensors-pdr;
@@ -2346,7 +2356,6 @@
lanes-per-direction = <1>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
spm-level = <5>;
clock-names =
"core_clk",
@@ -2637,8 +2646,8 @@
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<129 512 0 0>,
<129 512 0 7000000>;
<129 512 0 0>,
<129 512 0 7000000>;
/* Inputs from mss */
interrupts-extended = <&pdc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
@@ -2726,7 +2735,6 @@
vdd-1.8-xo-supply = <&pm6150l_l1>;
vdd-1.3-rfa-supply = <&pm6150l_l2>;
vdd-3.3-ch0-supply = <&pm6150l_l10>;
vdd-3.3-ch1-supply = <&pm6150l_l11>;
qcom,vdd-cx-mx-config = <640000 640000>;
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,

3
arch/arm64/boot/dts/qcom/sm6150-camera-sensor-idp.dtsi
View File

@@ -79,9 +79,6 @@
regulator-max-microvolt = <2850000>;
regulator-enable-ramp-delay = <233>;
enable-active-high;
gpio = <&pm6150l_gpios 9 0>;
pinctrl-names = "default";
pinctrl-0 = <&cam_sensor_0_vana>;
vin-supply = <&pm6150l_bob>;
};

3
arch/arm64/boot/dts/qcom/sm6150-camera-sensor-qrd.dtsi
View File

@@ -71,9 +71,6 @@
regulator-max-microvolt = <2850000>;
regulator-enable-ramp-delay = <233>;
enable-active-high;
gpio = <&pm6150l_gpios 9 0>;
pinctrl-names = "default";
pinctrl-0 = <&cam_sensor_0_vana>;
vin-supply = <&pm6150l_bob>;
};

60
arch/arm64/boot/dts/qcom/sm6150-camera.dtsi
View File

@@ -19,43 +19,34 @@
cam_csiphy0: qcom,csiphy@ac65000 {
cell-index = <0>;
compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v1.1", "qcom,csiphy";
reg = <0x0ac65000 0x1000>;
reg-names = "csiphy";
reg-cam-base = <0x65000>;
interrupts = <0 477 0>;
interrupt-names = "csiphy";
regulator-names = "gdscr";
gdscr-supply = <&titan_top_gdsc>;
regulator-names = "gdscr";
csi-vdd-voltage = <1200000>;
mipi-csi-vdd-supply = <&pm6150l_l3>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY0_CLK>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;
clock-names = "camnoc_axi_clk",
"soc_ahb_clk",
"slow_ahb_src_clk",
"cpas_ahb_clk",
"cphy_rx_clk_src",
clock-names = "cphy_rx_clk_src",
"csiphy0_clk",
"csi0phytimer_clk_src",
"csi0phytimer_clk";
src-clock-name = "csi0phytimer_clk_src";
clock-cntl-level = "svs_l1", "turbo";
clock-cntl-level = "nominal";
clock-rates =
<0 0 0 0 269333333 0 269333333 0>,
<0 0 0 0 384000000 0 269333333 0>;
<320000000 0 269333333 0>;
status = "ok";
};
cam_csiphy1: qcom,csiphy@ac66000{
cell-index = <1>;
compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v1.1", "qcom,csiphy";
reg = <0xac66000 0x1000>;
reg-names = "csiphy";
reg-cam-base = <0x66000>;
@@ -65,34 +56,24 @@
gdscr-supply = <&titan_top_gdsc>;
csi-vdd-voltage = <1200000>;
mipi-csi-vdd-supply = <&pm6150l_l3>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY1_CLK>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;
clock-names = "camnoc_axi_clk",
"soc_ahb_clk",
"slow_ahb_src_clk",
"cpas_ahb_clk",
"cphy_rx_clk_src",
clock-names = "cphy_rx_clk_src",
"csiphy1_clk",
"csi1phytimer_clk_src",
"csi1phytimer_clk";
src-clock-name = "csi1phytimer_clk_src";
clock-cntl-level = "svs_l1", "turbo";
clock-cntl-level = "nominal";
clock-rates =
<0 0 0 0 269333333 0 269333333 0>,
<0 0 0 0 384000000 0 269333333 0>;
<320000000 0 269333333 0>;
status = "ok";
};
cam_csiphy2: qcom,csiphy@ac67000 {
cell-index = <2>;
compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
compatible = "qcom,csiphy-v1.1", "qcom,csiphy";
reg = <0xac67000 0x1000>;
reg-names = "csiphy";
reg-cam-base = <0x67000>;
@@ -102,27 +83,18 @@
gdscr-supply = <&titan_top_gdsc>;
csi-vdd-voltage = <1200000>;
mipi-csi-vdd-supply = <&pm6150l_l3>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY2_CLK>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;
clock-names = "camnoc_axi_clk",
"soc_ahb_clk",
"slow_ahb_src_clk",
"cpas_ahb_clk",
"cphy_rx_clk_src",
clock-names = "cphy_rx_clk_src",
"csiphy2_clk",
"csi2phytimer_clk_src",
"csi2phytimer_clk";
src-clock-name = "csi2phytimer_clk_src";
clock-cntl-level = "svs_l1", "turbo";
clock-cntl-level = "nominal";
clock-rates =
<0 0 0 0 269333333 0 269333333 0>,
<0 0 0 0 384000000 0 269333333 0>;
<320000000 0 269333333 0>;
status = "ok";
};

2
arch/arm64/boot/dts/qcom/sm6150-ext-codec-audio-overlay.dtsi
View File

@@ -57,7 +57,7 @@
};
&qupv3_se4_spi {
status = "okay";
status = "disabled";
};
&tavil_wdsp {

3
arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi
View File

@@ -34,9 +34,10 @@
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
status = "ok";
reg = <0x5000000 0x90000>,
<0x509e000 0x1000>,
<0x780000 0x6fff>;
reg-names = "kgsl_3d0_reg_memory",
"qfprom_memory";
"cx_misc", "qfprom_memory";
interrupts = <0 300 0>;
interrupt-names = "kgsl_3d0_irq";
qcom,id = <0>;

29
arch/arm64/boot/dts/qcom/sm6150-idp.dtsi
View File

@@ -11,13 +11,30 @@
*/
#include "sm6150-thermal-overlay.dtsi"
#include "sm6150-camera-sensor-idp.dtsi"
/*#include "sm6150-camera-sensor-idp.dtsi"*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
#include "sm6150-sde-display.dtsi"
#include <dt-bindings/clock/qcom,gcc-sm6150.h>
&soc {
i2c_13: 12c@13 {
status = "ok";
cell-index = <13>;
compatible = "i2c-gpio";
gpios = <&tlmm 114 0 /*sda*/
&tlmm 113 0 /*scl*/
>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&smb1390_i2c_active>;
#include "smb1390.dtsi"
};
};
#if 0
&qupv3_se3_i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -26,6 +43,7 @@
#include "smb1390.dtsi"
#include "smb1355.dtsi"
};
#endif
&pm6150l_gpios {
key_vol_up {
@@ -179,6 +197,7 @@
vcc-supply = <&pm6150l_l11>;
vcc-voltage-level = <2950000 2960000>;
vccq2-supply = <&pm6150_l12>;
vccq2-voltage-level = <1800000 1800000>;
vcc-max-microamp = <600000>;
vccq2-max-microamp = <600000>;
@@ -239,6 +258,8 @@
&sdhc_1 {
vdd-supply = <&pm6150l_l11>;
qcom,vdd-always-on;
qcom,vdd-lpm-sup;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 570000>;
@@ -252,7 +273,7 @@
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
status = "ok";
status = "disabled";
};
&sdhc_2 {
@@ -286,14 +307,12 @@
<&pm6150_vadc ADC_USB_IN_I>,
<&pm6150_vadc ADC_CHG_TEMP>,
<&pm6150_vadc ADC_DIE_TEMP>,
<&pm6150_vadc ADC_AMUX_THM4_PU2>,
<&pm6150_vadc ADC_SBUx>,
<&pm6150_vadc ADC_VPH_PWR>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage";
qcom,battery-data = <&mtp_batterydata>;
@@ -326,6 +345,7 @@
status = "ok";
};
#if 0 /* block for smb1390 + sm6150 */
&smb1355 {
/delete-property/ interrupts;
interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>;
@@ -335,6 +355,7 @@
&smb1355_charger {
status = "ok";
};
#endif
&dsi_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;

79
arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi
View File

@@ -256,6 +256,7 @@
pins = "gpio18", "gpio19";
drive-strength = <2>;
bias-pull-up;
input-enable;
};
};
};
@@ -266,7 +267,7 @@
pins = "gpio87", "gpio18";
function = "gpio";
};
config {
pins = "gpio87", "gpio18";
drive-strength = <16>; /* 16 mA */
@@ -274,7 +275,7 @@
output-high;
};
};
ss5_pwr_ctrl_rst_off: ss5_pwr_ctrl_off {
mux {
pins = "gpio87", "gpio18";
@@ -290,36 +291,52 @@
};
};
/* QUPv3_1 North instances */
/* SE 4 pin mappings */
qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
qupv3_se4_i2c_active: qupv3_se4_i2c_active {
mux {
pins = "gpio20", "gpio21";
function = "qup10";
};
/* SE 4 pin mappings for AFC*/
qupv3_se4_afc_pins: qupv3_se4_afc_pins {
qupv3_se4_afc_active: qupv3_se4_afc_active {
mux {
pins = "gpio20";
function = "qup10";
};
config {
pins = "gpio20", "gpio21";
drive-strength = <2>;
bias-disable;
};
};
config {
pins = "gpio20";
drive-strength = <2>;
bias-disable;
};
};
qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
qupv3_se4_afc_sleep: qupv3_se4_afc_sleep {
mux {
pins = "gpio20";
function = "gpio";
};
config {
pins = "gpio20";
drive-strength = <2>;
bias-pull-up;
};
};
};
/* smb1390 i2c */
smb1390_i2c: smb1390_i2c {
smb1390_i2c_active: smb1390_i2c_active {
mux {
pins = "gpio20", "gpio21";
pins = "gpio113", "gpio114";
function = "gpio";
};
config {
pins = "gpio20", "gpio21";
pins = "gpio113", "gpio114";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
};
};
qupv3_se4_spi_pins: qupv3_se4_spi_pins {
qupv3_se4_spi_active: qupv3_se4_spi_active {
mux {
@@ -866,7 +883,7 @@
sdc1_cmd_on: sdc1_cmd_on {
config {
pins = "sdc1_cmd";
bias-pull-up; /* pull up */
bias-disable; /* NO pull */
drive-strength = <10>; /* 10 MA */
};
};
@@ -875,7 +892,7 @@
config {
pins = "sdc1_cmd";
num-grp-pins = <1>;
bias-pull-up; /* pull up */
bias-disable; /* NO pull */
drive-strength = <2>; /* 2 MA */
};
};
@@ -967,7 +984,7 @@
config {
pins = "gpio99";
drive-strength = <2>;
bias-pull-up;
bias-disable;
};
};
@@ -1495,7 +1512,7 @@
config {
pins = "gpio32", "gpio33";
bias-pull-up; /* PULL UP*/
bias-disable; /*No PULL*/
drive-strength = <2>; /* 2 MA */
};
};
@@ -1509,7 +1526,7 @@
config {
pins = "gpio32", "gpio33";
bias-pull-down; /* PULL DOWN */
bias-disable; /*No PULL */
drive-strength = <2>; /* 2 MA */
};
};
@@ -1523,7 +1540,7 @@
config {
pins = "gpio34", "gpio35";
bias-pull-up; /* PULL UP*/
bias-disable; /*No PULL*/
drive-strength = <2>; /* 2 MA */
};
};
@@ -1537,7 +1554,7 @@
config {
pins = "gpio34", "gpio35";
bias-pull-down; /* PULL DOWN */
bias-disable; /*No PULL */
drive-strength = <2>; /* 2 MA */
};
};
@@ -2332,12 +2349,6 @@
power-source = <0>;
output-low;
};
cam_sensor_0_vana: cam_sensor_0_vana {
pins = "gpio9";
function = "normal";
power-source = <0>;
output-low;
};
cam_sensor_1_2_vana: cam_sensor_1_2_vana {
pins = "gpio4";
function = "normal";

4
arch/arm64/boot/dts/qcom/sm6150-qrd.dtsi
View File

@@ -15,7 +15,7 @@
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
#include "sm6150-sde-display.dtsi"
#include "sm6150-camera-sensor-qrd.dtsi"
/*#include "sm6150-camera-sensor-qrd.dtsi"*/
&qupv3_se3_i2c {
#address-cells = <1>;
@@ -124,14 +124,12 @@
<&pm6150_vadc ADC_USB_IN_I>,
<&pm6150_vadc ADC_CHG_TEMP>,
<&pm6150_vadc ADC_DIE_TEMP>,
<&pm6150_vadc ADC_AMUX_THM4_PU2>,
<&pm6150_vadc ADC_SBUx>,
<&pm6150_vadc ADC_VPH_PWR>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage";
qcom,battery-data = <&mtp_batterydata>;

20
arch/arm64/boot/dts/qcom/sm6150-qupv3.dtsi
View File

@@ -174,26 +174,6 @@
};
/* I2C */
qupv3_se4_i2c: i2c@a80000 {
compatible = "qcom,i2c-geni";
reg = <0xa80000 0x4000>;
interrupts = <GIC_SPI 353 0>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
dmas = <&gpi_dma1 0 0 3 64 0>,
<&gpi_dma1 1 0 3 64 0>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_active>;
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
qupv3_se5_i2c: i2c@a84000 {
compatible = "qcom,i2c-geni";
reg = <0xa84000 0x4000>;

8
arch/arm64/boot/dts/qcom/sm6150-thermal-overlay.dtsi
View File

@@ -14,6 +14,7 @@
&thermal_zones {
pm6150-tz {
disable-thermal-zone;
cooling-maps {
trip0_bat {
trip = <&pm6150_trip0>;
@@ -31,6 +32,7 @@
};
pm6150l-tz {
disable-thermal-zone;
cooling-maps {
trip0_cpu0 {
trip = <&pm6150l_trip0>;
@@ -126,6 +128,7 @@
};
pm6150-bcl-lvl0 {
disable-thermal-zone;
cooling-maps {
vbat_cpu6 {
trip = <&bcl_lvl0>;
@@ -143,6 +146,7 @@
};
pm6150-bcl-lvl1 {
disable-thermal-zone;
cooling-maps {
ibat_cpu6 {
trip = <&bcl_lvl1>;
@@ -160,6 +164,7 @@
};
pm6150-bcl-lvl2 {
disable-thermal-zone;
cooling-maps {
ibat_cpu6 {
trip = <&bcl_lvl2>;
@@ -177,6 +182,7 @@
};
soc {
disable-thermal-zone;
cooling-maps {
soc_cpu6 {
trip = <&soc_trip>;
@@ -196,4 +202,4 @@
&mdss_mdp {
#cooling-cells = <2>;
};
};

754
arch/arm64/boot/dts/qcom/sm6150-thermal.dtsi
View File

@@ -779,257 +779,23 @@
};
};
aoss-lowf {
aoss-lowc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-governor = "low_limits_cap";
thermal-sensors = <&tsens0 0>;
wake-capable-sensor;
tracks-low;
trips {
aoss0_trip: aoss0-trip {
aoss_lowc: aoss-lowc {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&aoss0_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&aoss0_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&aoss0_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
cpuss-0-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 1>;
wake-capable-sensor;
tracks-low;
trips {
cpuss_0_trip: cpuss-0-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&cpuss_0_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&cpuss_0_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&cpuss_0_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&cpuss_0_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&cpuss_0_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&cpuss_0_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&cpuss_0_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&cpuss_0_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
cpuss-1-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 2>;
wake-capable-sensor;
tracks-low;
trips {
cpuss_1_trip: cpuss-1-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&cpuss_1_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&cpuss_1_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&cpuss_1_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&cpuss_1_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&cpuss_1_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&cpuss_1_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&cpuss_1_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&cpuss_1_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
cpuss-2-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 3>;
wake-capable-sensor;
tracks-low;
trips {
cpuss_2_trip: cpuss-2-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&cpuss_2_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&cpuss_2_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&cpuss_2_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&cpuss_2_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&cpuss_2_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&cpuss_2_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&cpuss_2_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&cpuss_2_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
cpuss-3-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 4>;
wake-capable-sensor;
tracks-low;
trips {
cpuss_3_trip: cpuss-3-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&cpuss_3_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&cpuss_3_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&cpuss_3_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&cpuss_3_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&cpuss_3_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&cpuss_3_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&cpuss_3_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&cpuss_3_trip>;
cooling-device = <&cdsp_vdd 0 0>;
audio_cdev {
trip = <&aoss_lowc>;
};
};
};
@@ -1085,516 +851,6 @@
};
};
cpu-1-1-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 6>;
wake-capable-sensor;
tracks-low;
trips {
cpu_1_1_trip: cpu-1-1-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&cpu_1_1_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&cpu_1_1_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&cpu_1_1_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&cpu_1_1_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&cpu_1_1_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&cpu_1_1_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&cpu_1_1_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&cpu_1_1_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
cpu-1-2-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 7>;
wake-capable-sensor;
tracks-low;
trips {
cpu_1_2_trip: cpu-1-2-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&cpu_1_2_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&cpu_1_2_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&cpu_1_2_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&cpu_1_2_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&cpu_1_2_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&cpu_1_2_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&cpu_1_2_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&cpu_1_2_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
cpu-1-3-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 8>;
wake-capable-sensor;
tracks-low;
trips {
cpu_1_3_trip: cpu-1-3-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&cpu_1_3_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&cpu_1_3_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&cpu_1_3_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&cpu_1_3_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&cpu_1_3_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&cpu_1_3_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&cpu_1_3_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&cpu_1_3_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
gpu-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 9>;
wake-capable-sensor;
tracks-low;
trips {
gpu_lowf_trip: gpu-lowf-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&gpu_lowf_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&gpu_lowf_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&gpu_lowf_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&gpu_lowf_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&gpu_lowf_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&gpu_lowf_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&gpu_lowf_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&gpu_lowf_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
q6-hvx-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 10>;
wake-capable-sensor;
tracks-low;
trips {
q6_hvx_trip: q6-hvx-lowf-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&q6_hvx_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
mdm-core-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 11>;
wake-capable-sensor;
tracks-low;
trips {
mdm_core_trip: mdm-core-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&mdm_core_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
camera-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 12>;
wake-capable-sensor;
tracks-low;
trips {
camera_trip: camera-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&camera_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&camera_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&camera_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
wlan-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 13>;
wake-capable-sensor;
tracks-low;
trips {
wlan_trip: wlan-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&wlan_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&wlan_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&wlan_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&wlan_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&wlan_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&wlan_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&wlan_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&wlan_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
display-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 14>;
wake-capable-sensor;
tracks-low;
trips {
display_trip: display-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&display_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&display_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&display_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&display_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&display_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&display_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&display_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&display_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
video-lowf {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-governor = "low_limits_floor";
thermal-sensors = <&tsens0 15>;
wake-capable-sensor;
tracks-low;
trips {
video_trip: video-trip {
temperature = <5000>;
hysteresis = <5000>;
type = "passive";
};
};
cooling-maps {
cpu0_cdev {
trip = <&video_trip>;
cooling-device = <&CPU0 2 2>;
};
cpu1_cdev {
trip = <&video_trip>;
cooling-device = <&CPU6 4 4>;
};
gpu_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3)
(THERMAL_MAX_LIMIT-3)>;
};
cx_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&cx_cdev 0 0>;
};
mx_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&mx_cdev 0 0>;
};
modem_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&modem_vdd 0 0>;
};
adsp_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&adsp_vdd 0 0>;
};
cdsp_vdd_cdev {
trip = <&video_trip>;
cooling-device = <&cdsp_vdd 0 0>;
};
};
};
q6-hvx-step {
polling-delay-passive = <0>;
polling-delay = <0>;

32
arch/arm64/boot/dts/qcom/sm6150.dtsi
View File

@@ -493,10 +493,10 @@
reg = <0 0x85700000 0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@85e00000 {
xbl_aop_mem: xbl_aop_mem@85d00000 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x85e00000 0x0 0x140000>;
reg = <0x0 0x85d00000 0x0 0x240000>;
};
sec_apps_mem: sec_apps_region@85fff000 {
@@ -984,6 +984,12 @@
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 200>;
};
upload_cause@66c {
compatible = "qcom,msm-imem-upload_cause";
reg = <0x66c 4>;
};
};
restart@c264000 {
@@ -1489,7 +1495,7 @@
qcom,bus-width = <4>;
qcom,large-address-bus;
qcom,clk-rates = <400000 20000000 25000000
qcom,clk-rates = <300000 400000 20000000 25000000
50000000 100000000 202000000>;
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
"SDR104";
@@ -1526,6 +1532,8 @@
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100750000 200000000 4294967295>;
qcom,restore-after-cx-collapse;
/* PM QoS */
qcom,pm-qos-irq-type = "affine_irq";
qcom,pm-qos-irq-latency = <67 67>;
@@ -1630,7 +1638,6 @@
lanes-per-direction = <1>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
spm-level = <5>;
clock-names =
"core_clk",
@@ -3082,21 +3089,12 @@
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
quiet_therm {
reg = <ADC_GPIO4_PU2>;
label = "quiet_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
&pm6150l_adc_tm {
io-channels = <&pm6150l_vadc ADC_AMUX_THM1_PU2>,
<&pm6150l_vadc ADC_AMUX_THM2_PU2>,
<&pm6150l_vadc ADC_GPIO1_PU2>,
<&pm6150l_vadc ADC_GPIO4_PU2>;
<&pm6150l_vadc ADC_GPIO1_PU2>;
/* Channel nodes */
emmc_ufs_therm {
@@ -3116,12 +3114,6 @@
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
quiet_therm {
reg = <ADC_GPIO4_PU2>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&emac_gdsc {

40
arch/arm64/boot/dts/qcom/sm8150-sdxprairie-audio-overlay.dtsi Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&soc {
quat_mi2s_gpios: quat_mi2s_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&quat_mi2s_active
&quat_mi2s_sd0_active &quat_mi2s_sd1_active>;
pinctrl-1 = <&quat_mi2s_sleep
&quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>;
};
audio_slimslave {
compatible = "qcom,audio-slimslave";
elemental-addr = [00 01 50 02 17 02];
};
};
&snd_934x {
compatible = "qcom,sm8150-asoc-snd-hana55";
qcom,model = "sm8150-hana55-snd-card";
qcom,quat-mi2s-gpios = <&quat_mi2s_gpios>;
};
&dai_mi2s3 {
qcom,msm-mi2s-rx-lines = <2>;
qcom,msm-mi2s-tx-lines = <1>;
};

1
arch/arm64/boot/dts/qcom/sm8150-sdxprairie-v3-mtp-overlay.dts
View File

@@ -23,6 +23,7 @@
#include "sdx5xm-external-soc.dtsi"
#include "sm8150-sdxprairie-v2.dtsi"
#include "sm8150-mtp-audio-overlay.dtsi"
#include "sm8150-sdxprairie-audio-overlay.dtsi"
/ {
model = "SDXPRAIRIE V3 MTP";

4
arch/arm64/boot/dts/qcom/sm8150-usb.dtsi
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -120,7 +120,7 @@
qcom,pipe0 {
label = "ssusb-qdss-in-0";
qcom,usb-bam-mem-type = <1>;
qcom,usb-bam-mem-type = <2>;
qcom,dir = <1>;
qcom,pipe-num = <0>;
qcom,peer-bam = <0>;

174
arch/arm64/boot/dts/qcom/trinket-camera-sensor-idp.dtsi
View File

@@ -21,40 +21,6 @@
};
};
&tlmm {
cam_sensor_tof_active: cam_sensor_tof_active {
mux {
pins = "gpio48", "gpio94";
function = "gpio";
};
config {
pins = "gpio48", "gpio94";
bias-disable;
drive-strength = <8>;
};
};
cam_sensor_tof_suspend: cam_sensor_tof_suspend {
mux {
pins = "gpio48", "gpio94";
function = "gpio";
};
config {
pins = "gpio48", "gpio94";
bias-pull-down;
drive-strength = <8>;
output-low;
};
};
};
&L3P {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3300000>;
};
&cci {
actuator0: qcom,actuator@0 {
cell-index = <0>;
@@ -188,53 +154,6 @@
qcom,clock-rates = <24000000 0>;
};
/*ToF imx528 sensor */
eeprom3: qcom,eeprom@3 {
cell-index = <3>;
reg = <0x3>;
compatible = "qcom,eeprom";
cam_vio-supply = <&L12A>;
cam_vana-supply = <&L3P>;
cam_vdig-supply = <&L1P>;
cam_clk-supply = <&camss_top_gdsc>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
"cam_clk";
qcom,cam-vreg-min-voltage = <1800000 3300000 1200000 0>;
qcom,cam-vreg-max-voltage = <1800000 3300000 1200000 0>;
qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_active
&cam_sensor_rear_active
&cam_sensor_custom1_active
&cam_sensor_custom2_active>;
pinctrl-1 = <&cam_sensor_mclk0_suspend
&cam_sensor_rear_suspend
&cam_sensor_custom1_suspend
&cam_sensor_custom2_suspend>;
gpios = <&tlmm 34 0>,
<&tlmm 48 0>,
<&tlmm 44 0>,//VILLU_3P65
<&tlmm 47 0>;//LDD_XCLR
qcom,gpio-reset = <1>;
qcom,gpio-custom1 = <2>;
qcom,gpio-custom2 = <3>;
qcom,gpio-req-tbl-num = <0 1 2 3>;
qcom,gpio-req-tbl-flags = <1 0 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0",
"CUSTOM_GPIO1",//VILLU_3P65
"CUSTOM_GPIO2";//LDD_XCLR
qcom,sensor-position = <0>;
qcom,sensor-mode = <0>;
qcom,cci-master = <0>;
status = "ok";
clocks = <&clock_gcc GCC_CAMSS_MCLK0_CLK_SRC>,
<&clock_gcc GCC_CAMSS_MCLK0_CLK>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
qcom,camera@0 {
cell-index = <0>;
compatible = "qcom,camera";
@@ -359,97 +278,4 @@
qcom,clock-rates = <24000000 0>;
};
/*ToF imx528 sensor */
qcom,camera@3 {
cell-index = <3>;
compatible = "qcom,camera";
reg = <0x3>;
qcom,csiphy-sd-index = <0>;
qcom,csid-sd-index = <0>;
qcom,mount-angle = <90>;
qcom,eeprom-src = <&eeprom3>;
cam_vio-supply = <&L12A>;
cam_vana-supply = <&L3P>;
cam_vdig-supply = <&L1P>;
cam_clk-supply = <&camss_top_gdsc>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
"cam_clk";
qcom,cam-vreg-min-voltage = <1800000 3300000 1200000 0>;
qcom,cam-vreg-max-voltage = <1800000 3300000 1200000 0>;
qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_active
&cam_sensor_rear_active
&cam_sensor_custom1_active
&cam_sensor_custom2_active>;
pinctrl-1 = <&cam_sensor_mclk0_suspend
&cam_sensor_rear_suspend
&cam_sensor_custom1_suspend
&cam_sensor_custom2_suspend>;
gpios = <&tlmm 34 0>,
<&tlmm 48 0>,
<&tlmm 44 0>,//VILLU_3P65
<&tlmm 47 0>;//LDD_XCLR
qcom,gpio-reset = <1>;
qcom,gpio-custom1 = <2>;
qcom,gpio-custom2 = <3>;
qcom,gpio-req-tbl-num = <0 1 2 3>;
qcom,gpio-req-tbl-flags = <1 0 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0",
"CUSTOM_GPIO1",//VILLU_3P65
"CUSTOM_GPIO2";//LDD_XCLR
qcom,sensor-position = <0>;
qcom,sensor-mode = <0>;
qcom,cci-master = <0>;
status = "ok";
clocks = <&clock_gcc GCC_CAMSS_MCLK0_CLK_SRC>,
<&clock_gcc GCC_CAMSS_MCLK0_CLK>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
/*RGB sensor*/
qcom,camera@4 {
cell-index = <4>;
compatible = "qcom,camera";
reg = <0x4>;
qcom,csiphy-sd-index = <1>;
qcom,csid-sd-index = <1>;
qcom,mount-angle = <90>;
cam_vio-supply = <&L12A>;
cam_vana-supply = <&L4P>;
cam_vdig-supply = <&L2P>;
cam_clk-supply = <&camss_top_gdsc>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
"cam_clk";
qcom,cam-vreg-min-voltage = <1800000 2800000 1104000 0>;
qcom,cam-vreg-max-voltage = <1800000 2800000 1104000 0>;
qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk1_active
&cam_sensor_rear2_active>;
pinctrl-1 = <&cam_sensor_mclk1_suspend
&cam_sensor_rear2_suspend>;
gpios = <&tlmm 35 0>,
<&tlmm 46 0>,
<&tlmm 41 0>;
qcom,gpio-reset = <1>;
qcom,gpio-custom1 = <2>;
qcom,gpio-req-tbl-num = <0 1 2>;
qcom,gpio-req-tbl-flags = <1 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1",
"CUSTOM_GPIO1";//PWDN
qcom,sensor-position = <1>;
qcom,sensor-mode = <0>;
qcom,cci-master = <1>;
status = "ok";
clocks = <&clock_gcc GCC_CAMSS_MCLK1_CLK_SRC>,
<&clock_gcc GCC_CAMSS_MCLK1_CLK>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
};

6
arch/arm64/boot/dts/qcom/trinket-ion.dtsi
View File

@@ -21,12 +21,6 @@
qcom,ion-heap-type = "SYSTEM";
};
qcom,ion-heap@26 { /* USER CONTIG HEAP */
reg = <26>;
memory-region = <&user_contig_mem>;
qcom,ion-heap-type = "DMA";
};
qcom,ion-heap@27 { /* QSEECOM HEAP */
reg = <27>;
memory-region = <&qseecom_mem>;

3
arch/arm64/boot/dts/qcom/trinket-iot-idp-overlay.dts
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -15,7 +15,6 @@
/plugin/;
#include "trinket-iot-idp.dtsi"
#include "trinket-audio-overlay.dtsi"
/ {
model = "Qualcomm Technologies, Inc. TRINKET IOT IDP Overlay";

103
arch/arm64/boot/dts/qcom/trinket-pinctrl.dtsi
View File

@@ -461,47 +461,6 @@
};
};
qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
qupv3_se6_ctsrx: qupv3_se6_ctsrx {
mux {
pins = "gpio30", "gpio33";
function = "qup11";
};
config {
pins = "gpio30", "gpio33";
drive-strength = <2>;
bias-no-pull;
};
};
qupv3_se6_rts: qupv3_se6_rts {
mux {
pins = "gpio31";
function = "qup11";
};
config {
pins = "gpio31";
drive-strength = <2>;
bias-pull-down;
};
};
qupv3_se6_tx: qupv3_se6_tx {
mux {
pins = "gpio32";
function = "qup11";
};
config {
pins = "gpio32";
drive-strength = <2>;
bias-pull-up;
};
};
};
qupv3_se9_4uart_pins: qupv3_se9_4uart_pins {
qupv3_se9_ctsrx: qupv3_se9_ctsrx {
mux {
@@ -1674,7 +1633,7 @@
config {
pins = "gpio34";
bias-disable; /* No PULL */
drive-strength = <8>; /* 2 MA */
drive-strength = <2>; /* 2 MA */
};
};
@@ -1688,7 +1647,7 @@
config {
pins = "gpio34";
bias-pull-down; /* PULL DOWN */
drive-strength = <8>; /* 2 MA */
drive-strength = <2>; /* 2 MA */
};
};
@@ -1721,64 +1680,6 @@
};
};
cam_sensor_custom1_active: cam_sensor_custom1_active {
/* CUSTOM1 */
mux {
pins = "gpio44";
function = "gpio";
};
config {
pins = "gpio44";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_custom1_suspend: cam_sensor_custom1_suspend {
/* CUSTOM1 */
mux {
pins = "gpio44";
function = "gpio";
};
config {
pins = "gpio44";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_custom2_active: cam_sensor_custom2_active {
/* CUSTOM2 */
mux {
pins = "gpio47";
function = "gpio";
};
config {
pins = "gpio47";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_custom2_suspend: cam_sensor_custom2_suspend {
/* CUSTOM2 */
mux {
pins = "gpio47";
function = "gpio";
};
config {
pins = "gpio47";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_front_active: cam_sensor_front_active {
/* RESET */
mux {

18
arch/arm64/boot/dts/qcom/trinket-qupv3.dtsi
View File

@@ -269,24 +269,6 @@
status = "disabled";
};
qupv3_se6_4uart: qcom,qup_uart@0x4c84000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0x4c84000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
<&qupv3_se6_tx>;
pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
<&qupv3_se6_tx>;
interrupts = <GIC_SPI 309 0>;
qcom,wrapper-core = <&qupv3_1>;
status = "disabled";
};
/* I2C */
qupv3_se5_i2c: i2c@4c80000 {
compatible = "qcom,i2c-geni";

8
arch/arm64/boot/dts/qcom/trinket.dtsi
View File

@@ -507,13 +507,7 @@
no-map;
reg = <0 0x5e400000 0 0x1400000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;

3
arch/arm64/boot/dts/qcom/trinketp-iot-idp-overlay.dts
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -15,7 +15,6 @@
/plugin/;
#include "trinketp-iot-idp.dtsi"
#include "trinket-audio-overlay.dtsi"
/ {
model = "Qualcomm Technologies, Inc. TRINKETP IOT IDP Overlay";

503
arch/arm64/boot/dts/samsung/Makefile Normal file
View File

@@ -0,0 +1,503 @@
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
# A60Q(SM6150)
SEC_A60Q_CHN_DTBO := \
sm6150-sec-a60q-chn-overlay-r00.dtbo \
sm6150-sec-a60q-chn-overlay-r01.dtbo \
sm6150-sec-a60q-chn-overlay-r02.dtbo \
sm6150-sec-a60q-chn-overlay-r03.dtbo \
sm6150-sec-a60q-chn-overlay-r04.dtbo \
sm6150-sec-a60q-chn-overlay-r05.dtbo \
sm6150-sec-a60q-chn-overlay-r06.dtbo \
sm6150-sec-a60q-chn-overlay-r08.dtbo
# A60Q_SWA_OPEN(SM6150)
SEC_A60Q_SWA_DTBO := \
sm6150-sec-a60q-swa-overlay-r00.dtbo \
sm6150-sec-a60q-swa-overlay-r01.dtbo \
sm6150-sec-a60q-swa-overlay-r02.dtbo \
sm6150-sec-a60q-swa-overlay-r03.dtbo \
sm6150-sec-a60q-swa-overlay-r04.dtbo \
sm6150-sec-a60q-swa-overlay-r05.dtbo
# M40_SWA_OPEN(SM6150)
SEC_M40_SWA_DTBO := \
sm6150-sec-m40-swa-overlay-r00.dtbo \
sm6150-sec-m40-swa-overlay-r01.dtbo \
sm6150-sec-m40-swa-overlay-r02.dtbo \
sm6150-sec-m40-swa-overlay-r03.dtbo \
sm6150-sec-m40-swa-overlay-r04.dtbo \
sm6150-sec-m40-swa-overlay-r05.dtbo \
sm6150-sec-m40-swa-overlay-r06.dtbo \
sm6150-sec-m40-swa-overlay-r08.dtbo
# A70Q(SM6150)
SEC_A70Q_EUR_DTBO := \
sm6150-sec-a70q-eur-overlay-r00.dtbo \
sm6150-sec-a70q-eur-overlay-r01.dtbo \
sm6150-sec-a70q-eur-overlay-r02.dtbo \
sm6150-sec-a70q-eur-overlay-r03.dtbo \
sm6150-sec-a70q-eur-overlay-r05.dtbo \
sm6150-sec-a70q-eur-overlay-r06.dtbo \
sm6150-sec-a70q-eur-overlay-r09.dtbo \
sm6150-sec-a70q-eur-overlay-r10.dtbo \
sm6150-sec-a70q-eur-overlay-r11.dtbo \
sm6150-sec-a70q-eur-overlay-r12.dtbo \
sm6150-sec-a70q-eur-overlay-r13.dtbo \
sm6150-sec-a70q-eur-overlay-r14.dtbo
SEC_A70Q_CHN_DTBO := \
sm6150-sec-a70q-chn-overlay-r00.dtbo \
sm6150-sec-a70q-chn-overlay-r01.dtbo \
sm6150-sec-a70q-chn-overlay-r02.dtbo \
sm6150-sec-a70q-chn-overlay-r03.dtbo \
sm6150-sec-a70q-chn-overlay-r05.dtbo \
sm6150-sec-a70q-chn-overlay-r06.dtbo \
sm6150-sec-a70q-chn-overlay-r09.dtbo \
sm6150-sec-a70q-chn-overlay-r10.dtbo \
sm6150-sec-a70q-chn-overlay-r11.dtbo \
sm6150-sec-a70q-chn-overlay-r12.dtbo
SEC_A70Q_EUR_LDU_DTBO := \
sm6150-sec-a70q-eur-ldu-overlay-r00.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r01.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r02.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r03.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r05.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r06.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r09.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r10.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r11.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r12.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r13.dtbo \
sm6150-sec-a70q-eur-ldu-overlay-r14.dtbo
SEC_A70Q_USA_DTBO := \
sm6150-sec-a70q-usa-overlay-r00.dtbo \
sm6150-sec-a70q-usa-overlay-r02.dtbo \
sm6150-sec-a70q-usa-overlay-r03.dtbo
SEC_A70Q_KOR_DTBO := \
sm6150-sec-a70q-kor-overlay-r00.dtbo \
sm6150-sec-a70q-kor-overlay-r01.dtbo \
sm6150-sec-a70q-kor-overlay-r02.dtbo \
sm6150-sec-a70q-kor-overlay-r03.dtbo
SEC_A70Q_SEA_OPEN_DTBO := \
sm6150-sec-a70q-sea-overlay-r00.dtbo \
sm6150-sec-a70q-sea-overlay-r01.dtbo \
sm6150-sec-a70q-sea-overlay-r02.dtbo \
sm6150-sec-a70q-sea-overlay-r03.dtbo \
sm6150-sec-a70q-sea-overlay-r05.dtbo \
sm6150-sec-a70q-sea-overlay-r06.dtbo \
sm6150-sec-a70q-sea-overlay-r09.dtbo \
sm6150-sec-a70q-sea-overlay-r10.dtbo \
sm6150-sec-a70q-sea-overlay-r11.dtbo \
sm6150-sec-a70q-sea-overlay-r12.dtbo \
sm6150-sec-a70q-sea-overlay-r13.dtbo \
sm6150-sec-a70q-sea-overlay-r14.dtbo
SEC_A70Q_SEA_XTC_DTBO := \
sm6150-sec-a70q-sea-xtc-overlay-r00.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r01.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r02.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r03.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r05.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r06.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r09.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r10.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r11.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r12.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r13.dtbo \
sm6150-sec-a70q-sea-xtc-overlay-r14.dtbo
SEC_A70Q_SEA_XSA_DTBO := \
sm6150-sec-a70q-sea-xsa-overlay-r00.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r01.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r02.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r03.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r05.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r06.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r09.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r10.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r11.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r12.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r13.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r14.dtbo \
sm6150-sec-a70q-sea-xsa-overlay-r15.dtbo
SEC_A70Q_SWA_DTBO := \
sm6150-sec-a70q-swa-overlay-r00.dtbo \
sm6150-sec-a70q-swa-overlay-r01.dtbo \
sm6150-sec-a70q-swa-overlay-r02.dtbo \
sm6150-sec-a70q-swa-overlay-r03.dtbo \
sm6150-sec-a70q-swa-overlay-r05.dtbo \
sm6150-sec-a70q-swa-overlay-r06.dtbo \
sm6150-sec-a70q-swa-overlay-r09.dtbo \
sm6150-sec-a70q-swa-overlay-r10.dtbo \
sm6150-sec-a70q-swa-overlay-r11.dtbo \
sm6150-sec-a70q-swa-overlay-r12.dtbo \
sm6150-sec-a70q-swa-overlay-r13.dtbo \
sm6150-sec-a70q-swa-overlay-r14.dtbo
SEC_A70Q_CAN_DTBO := \
sm6150-sec-a70q-can-overlay-r00.dtbo \
sm6150-sec-a70q-can-overlay-r01.dtbo \
sm6150-sec-a70q-can-overlay-r02.dtbo \
sm6150-sec-a70q-can-overlay-r03.dtbo \
sm6150-sec-a70q-can-overlay-r05.dtbo \
sm6150-sec-a70q-can-overlay-r06.dtbo \
sm6150-sec-a70q-can-overlay-r09.dtbo \
sm6150-sec-a70q-can-overlay-r10.dtbo \
sm6150-sec-a70q-can-overlay-r11.dtbo \
sm6150-sec-a70q-can-overlay-r12.dtbo \
sm6150-sec-a70q-can-overlay-r13.dtbo \
sm6150-sec-a70q-can-overlay-r14.dtbo
# A70S(SM6150)
SEC_A70S_SWA_DTBO := \
sm6150-sec-a70s-swa-overlay-r00.dtbo \
sm6150-sec-a70s-swa-overlay-r01.dtbo
SEC_A70S_CHN_DTBO := \
sm6150-sec-a70s-chn-overlay-r00.dtbo
# R1Q(SM7150)
SEC_R1Q_EUR_DTBO := \
sm7150-sec-r1q-eur-overlay-r00.dtbo \
sm7150-sec-r1q-eur-overlay-r01.dtbo \
sm7150-sec-r1q-eur-overlay-r02.dtbo \
sm7150-sec-r1q-eur-overlay-r03.dtbo \
sm7150-sec-r1q-eur-overlay-r04.dtbo \
sm7150-sec-r1q-eur-overlay-r05.dtbo \
sm7150-sec-r1q-eur-overlay-r06.dtbo \
sm7150-sec-r1q-eur-overlay-r07.dtbo \
sm7150-sec-r1q-eur-overlay-r08.dtbo
SEC_R1Q_CHN_DTBO := \
sm7150-sec-r1q-chn-overlay-r00.dtbo \
sm7150-sec-r1q-chn-overlay-r01.dtbo \
sm7150-sec-r1q-chn-overlay-r02.dtbo \
sm7150-sec-r1q-chn-overlay-r03.dtbo \
sm7150-sec-r1q-chn-overlay-r04.dtbo \
sm7150-sec-r1q-chn-overlay-r05.dtbo \
sm7150-sec-r1q-chn-overlay-r06.dtbo \
sm7150-sec-r1q-chn-overlay-r07.dtbo \
sm7150-sec-r1q-chn-overlay-r08.dtbo
SEC_R1Q_KOR_DTBO := \
sm7150-sec-r1q-kor-overlay-r00.dtbo \
sm7150-sec-r1q-kor-overlay-r01.dtbo \
sm7150-sec-r1q-kor-overlay-r02.dtbo \
sm7150-sec-r1q-kor-overlay-r03.dtbo \
sm7150-sec-r1q-kor-overlay-r04.dtbo \
sm7150-sec-r1q-kor-overlay-r05.dtbo \
sm7150-sec-r1q-kor-overlay-r06.dtbo \
sm7150-sec-r1q-kor-overlay-r07.dtbo \
sm7150-sec-r1q-kor-overlay-r08.dtbo \
sm7150-sec-r1q-kor-overlay-r09.dtbo
# A70S(SM7150)
SEC_A70SQ_EUR_DTBO := \
sm7150-sec-a70sq-eur-overlay-r00.dtbo \
sm7150-sec-a70sq-eur-overlay-r01.dtbo
# A71(SM7150)
SEC_A71_CAN_DTBO := \
sm7150-sec-a71-can-overlay-r00.dtbo \
sm7150-sec-a71-can-overlay-r01.dtbo \
sm7150-sec-a71-can-overlay-r02.dtbo \
sm7150-sec-a71-can-overlay-r03.dtbo \
sm7150-sec-a71-can-overlay-r04.dtbo \
sm7150-sec-a71-can-overlay-r05.dtbo \
sm7150-sec-a71-can-overlay-r06.dtbo
SEC_A71_EUR_LDU_DTBO := \
sm7150-sec-a71-eur-ldu-overlay-r00.dtbo \
sm7150-sec-a71-eur-ldu-overlay-r01.dtbo \
sm7150-sec-a71-eur-ldu-overlay-r02.dtbo \
sm7150-sec-a71-eur-ldu-overlay-r03.dtbo \
sm7150-sec-a71-eur-ldu-overlay-r04.dtbo \
sm7150-sec-a71-eur-ldu-overlay-r05.dtbo \
sm7150-sec-a71-eur-ldu-overlay-r06.dtbo
SEC_A71_SWA_DTBO := \
sm7150-sec-a71-swa-overlay-r00.dtbo \
sm7150-sec-a71-swa-overlay-r01.dtbo \
sm7150-sec-a71-swa-overlay-r02.dtbo \
sm7150-sec-a71-swa-overlay-r03.dtbo
SEC_A71_EUR_DTBO := \
sm7150-sec-a71-eur-overlay-r00.dtbo \
sm7150-sec-a71-eur-overlay-r01.dtbo \
sm7150-sec-a71-eur-overlay-r02.dtbo \
sm7150-sec-a71-eur-overlay-r03.dtbo \
sm7150-sec-a71-eur-overlay-r04.dtbo \
sm7150-sec-a71-eur-overlay-r05.dtbo \
sm7150-sec-a71-eur-overlay-r06.dtbo \
sm7150-sec-a71-eur-overlay-r07.dtbo
# A70S(SM7150)
SEC_A70SQ_SWA_DTBO := \
sm7150-sec-a70sq-swa-overlay-r00.dtbo \
sm7150-sec-a70sq-swa-overlay-r01.dtbo
# M41(SM7150)
SEC_M41_SWA_DTBO := \
sm7150-sec-m41-swa-overlay-r00.dtbo
# M51(SM7150)
SEC_M51_EUR_DTBO := \
sm7150-sec-m51-eur-overlay-r00.dtbo \
sm7150-sec-m51-eur-overlay-r01.dtbo \
sm7150-sec-m51-eur-overlay-r02.dtbo \
sm7150-sec-m51-eur-overlay-r04.dtbo \
sm7150-sec-m51-eur-overlay-r05.dtbo
SEC_M51_SWA_DTBO := \
sm7150-sec-m51-swa-overlay-r00.dtbo \
sm7150-sec-m51-swa-overlay-r01.dtbo \
sm7150-sec-m51-swa-overlay-r02.dtbo
# A52Q EUR
SEC_A52Q_EUR_DTBO := \
atoll-sec-a52q-eur-overlay-r00.dtbo \
atoll-sec-a52q-eur-overlay-r01.dtbo \
atoll-sec-a52q-eur-overlay-r02.dtbo \
atoll-sec-a52q-eur-overlay-r04.dtbo \
atoll-sec-a52q-eur-overlay-r05.dtbo \
atoll-sec-a52q-eur-overlay-r06.dtbo
# A52Q LTN
SEC_A52Q_LTN_DTBO := \
atoll-sec-a52q-ltn-overlay-r04.dtbo \
atoll-sec-a52q-ltn-overlay-r05.dtbo \
atoll-sec-a52q-ltn-overlay-r06.dtbo
# A72Q EUR
SEC_A72Q_EUR_DTBO := \
atoll-sec-a72q-eur-overlay-r00.dtbo \
atoll-sec-a72q-eur-overlay-r01.dtbo \
atoll-sec-a72q-eur-overlay-r02.dtbo \
atoll-sec-a72q-eur-overlay-r04.dtbo \
atoll-sec-a72q-eur-overlay-r05.dtbo
# A72Q LTN
SEC_A72Q_LTN_DTBO := \
atoll-sec-a72q-ltn-overlay-r00.dtbo \
atoll-sec-a72q-ltn-overlay-r01.dtbo \
atoll-sec-a72q-ltn-overlay-r02.dtbo \
atoll-sec-a72q-ltn-overlay-r04.dtbo \
atoll-sec-a72q-ltn-overlay-r05.dtbo
# M42Q EUR
SEC_M42Q_EUR_DTBO := \
atoll-sec-m42q-eur-overlay-r00.dtbo \
atoll-sec-m42q-eur-overlay-r01.dtbo \
atoll-sec-m42q-eur-overlay-r02.dtbo \
atoll-sec-m42q-eur-overlay-r04.dtbo \
atoll-sec-m42q-eur-overlay-r05.dtbo \
atoll-sec-m42q-eur-overlay-r06.dtbo
# M42Q JPN
SEC_M42Q_JPN_DTBO := \
atoll-sec-m42q-jpn-overlay-r00.dtbo \
atoll-sec-m42q-jpn-overlay-r01.dtbo \
atoll-sec-m42q-jpn-overlay-r02.dtbo \
atoll-sec-m42q-jpn-overlay-r04.dtbo
# M42Q USA
SEC_M42Q_USA_DTBO := \
atoll-sec-m42q-usa-overlay-r01.dtbo \
atoll-sec-m42q-usa-overlay-r02.dtbo \
atoll-sec-m42q-usa-overlay-r04.dtbo \
atoll-sec-m42q-usa-overlay-r06.dtbo
# GTA4XLVE EUR
SEC_GTA4XLVE_EUR_DTBO := \
atoll-sec-gta4xlve-eur-overlay-r00.dtbo
# GTA4XLVEWIFI EUR
SEC_GTA4XLVEWIFI_EUR_DTBO := \
atoll-sec-gta4xlvewifi-eur-overlay-r00.dtbo
# GTA4XLVE KOR
SEC_GTA4XLVE_KOR_DTBO := \
atoll-sec-gta4xlve-kor-overlay-r00.dtbo
# GTA4XLVE CHN
SEC_GTA4XLVE_CHN_DTBO := \
atoll-sec-gta4xlve-chn-overlay-r00.dtbo
# GTA4XLVEWIFI CHN
SEC_GTA4XLVEWIFI_CHN_DTBO := \
atoll-sec-gta4xlvewifi-chn-overlay-r00.dtbo
# GTA4XLVEWIFI KOR
SEC_GTA4XLVEWIFI_KOR_DTBO := \
atoll-sec-gta4xlvewifi-kor-overlay-r00.dtbo
define __sec_dtbo_build
dtbo-$(2) += $(1)
$(1)-base := $(3)
endef
define sec_dtbo_build
$(foreach dtbo, $(1), $(eval $(call __sec_dtbo_build, $(dtbo),$(2),$(3))))
endef
# SM6150 BASE DTB
SEC_SM6150_BASE_DTB := ../qcom/sm6150.dtb
# SM7150 BASE DTB
SEC_SM7150_BASE_DTB := ../qcom/sdmmagpie.dtb
# SM7125 BASE DTB
SEC_ATOLL_BASE_DTB := ../qcom/atoll-ab-idp.dtb
$(eval $(call sec_dtbo_build, \
$(SEC_A60Q_CHN_DTBO),$(CONFIG_SEC_A60Q_CHN_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_M40_SWA_DTBO),$(CONFIG_SEC_M40_SWA_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A60Q_SWA_DTBO),$(CONFIG_SEC_A60Q_SWA_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70Q_EUR_DTBO),$(CONFIG_SEC_A70Q_EUR_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70Q_EUR_LDU_DTBO),$(CONFIG_SEC_A70Q_EUR_LDU_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70Q_CHN_DTBO),$(CONFIG_SEC_A70Q_CHN_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70Q_USA_DTBO),$(CONFIG_SEC_A70Q_USA_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70Q_KOR_DTBO),$(CONFIG_SEC_A70Q_KOR_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70Q_SEA_OPEN_DTBO),$(CONFIG_SEC_A70Q_SEA_OPEN_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70Q_SEA_XTC_DTBO),$(CONFIG_SEC_A70Q_SEA_XTC_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70Q_SEA_XSA_DTBO),$(CONFIG_SEC_A70Q_SEA_XSA_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70Q_CAN_DTBO),$(CONFIG_SEC_A70Q_CAN_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70Q_SWA_DTBO),$(CONFIG_SEC_A70Q_SWA_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70S_SWA_DTBO),$(CONFIG_SEC_A70S_SWA_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70S_CHN_DTBO),$(CONFIG_SEC_A70S_CHN_PROJECT),$(SEC_SM6150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_R1Q_EUR_DTBO),$(CONFIG_SEC_R1Q_EUR_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_R1Q_EUR_DTBO),$(CONFIG_SEC_R1Q_EUR_LDU_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_R1Q_CHN_DTBO),$(CONFIG_SEC_R1Q_CHN_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_R1Q_CHN_DTBO),$(CONFIG_SEC_R1Q_CHN_LDU_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_R1Q_KOR_DTBO),$(CONFIG_SEC_R1Q_KOR_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70SQ_EUR_DTBO),$(CONFIG_SEC_A70SQ_EUR_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A71_EUR_LDU_DTBO),$(CONFIG_SEC_A71_EUR_LDU_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A71_CAN_DTBO),$(CONFIG_SEC_A71_CAN_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A71_SWA_DTBO),$(CONFIG_SEC_A71_SWA_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A71_EUR_DTBO),$(CONFIG_SEC_A71_EUR_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A70SQ_SWA_DTBO),$(CONFIG_SEC_A70SQ_SWA_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_M41_SWA_DTBO),$(CONFIG_SEC_M41_SWA_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_M51_EUR_DTBO),$(CONFIG_SEC_M51_EUR_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_M51_SWA_DTBO),$(CONFIG_SEC_M51_SWA_PROJECT),$(SEC_SM7150_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A52Q_EUR_DTBO),$(CONFIG_SEC_A52Q_EUR_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A52Q_LTN_DTBO),$(CONFIG_SEC_A52Q_LTN_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A72Q_EUR_DTBO),$(CONFIG_SEC_A72Q_EUR_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_A72Q_LTN_DTBO),$(CONFIG_SEC_A72Q_LTN_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_M42Q_EUR_DTBO),$(CONFIG_SEC_M42Q_EUR_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_M42Q_JPN_DTBO),$(CONFIG_SEC_M42Q_JPN_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_M42Q_USA_DTBO),$(CONFIG_SEC_M42Q_USA_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_GTA4XLVE_EUR_DTBO),$(CONFIG_SEC_GTA4XLVE_EUR_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_GTA4XLVEWIFI_EUR_DTBO),$(CONFIG_SEC_GTA4XLVEWIFI_EUR_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_GTA4XLVE_KOR_DTBO),$(CONFIG_SEC_GTA4XLVE_KOR_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_GTA4XLVE_CHN_DTBO),$(CONFIG_SEC_GTA4XLVE_CHN_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_GTA4XLVEWIFI_CHN_DTBO),$(CONFIG_SEC_GTA4XLVEWIFI_CHN_OPEN),$(SEC_ATOLL_BASE_DTB)))
$(eval $(call sec_dtbo_build, \
$(SEC_GTA4XLVEWIFI_KOR_DTBO),$(CONFIG_SEC_GTA4XLVEWIFI_KOR_OPEN),$(SEC_ATOLL_BASE_DTB)))
endif
ifeq ($(CONFIG_ARM64),y)
always := $(dtb-y)
subdir-y := $(dts-dirs)
else
targets += dtbs
targets += $(addprefix ../, $(dtb-y))
$(obj)/../%.dtb: $(src)/%.dts FORCE
$(call if_changed_dep,dtc)
dtbs: $(addprefix $(obj)/../,$(dtb-y))
endif
clean-files := *.dtb *.reverse.dts *.dtbo

16
arch/arm64/include/asm/alternative.h
View File

@@ -68,11 +68,11 @@ void apply_alternatives(void *start, size_t length);
".pushsection .altinstructions,\"a\"\n" \
ALTINSTR_ENTRY(feature) \
".popsection\n" \
".pushsection .altinstr_replacement, \"a\"\n" \
".subsection 1\n" \
"663:\n\t" \
newinstr "\n" \
"664:\n\t" \
".popsection\n\t" \
".previous\n\t" \
".org . - (664b-663b) + (662b-661b)\n\t" \
".org . - (662b-661b) + (664b-663b)\n" \
".endif\n"
@@ -112,9 +112,9 @@ void apply_alternatives(void *start, size_t length);
662: .pushsection .altinstructions, "a"
altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f
.popsection
.pushsection .altinstr_replacement, "ax"
.subsection 1
663: \insn2
664: .popsection
664: .previous
.org . - (664b-663b) + (662b-661b)
.org . - (662b-661b) + (664b-663b)
.endif
@@ -155,7 +155,7 @@ void apply_alternatives(void *start, size_t length);
.pushsection .altinstructions, "a"
altinstruction_entry 663f, 661f, \cap, 664f-663f, 662f-661f
.popsection
.pushsection .altinstr_replacement, "ax"
.subsection 1
.align 2 /* So GAS knows label 661 is suitably aligned */
661:
.endm
@@ -174,9 +174,9 @@ void apply_alternatives(void *start, size_t length);
.macro alternative_else
662:
.if .Lasm_alt_mode==0
.pushsection .altinstr_replacement, "ax"
.subsection 1
.else
.popsection
.previous
.endif
663:
.endm
@@ -187,7 +187,7 @@ void apply_alternatives(void *start, size_t length);
.macro alternative_endif
664:
.if .Lasm_alt_mode==0
.popsection
.previous
.endif
.org . - (664b-663b) + (662b-661b)
.org . - (662b-661b) + (664b-663b)

34
arch/arm64/include/asm/assembler.h
View File

@@ -117,13 +117,6 @@
hint #20
.endm
/*
* Clear Branch History instruction
*/
.macro clearbhb
hint #22
.endm
/*
* Sanitise a 64-bit bounded index wrt speculation, returning zero if out
* of bounds.
@@ -577,31 +570,4 @@ alternative_endif
.Ldone\@:
.endm
.macro __mitigate_spectre_bhb_loop tmp
#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
alternative_cb spectre_bhb_patch_loop_iter
mov \tmp, #32 // Patched to correct the immediate
alternative_cb_end
.Lspectre_bhb_loop\@:
b . + 4
subs \tmp, \tmp, #1
b.ne .Lspectre_bhb_loop\@
dsb nsh
isb
#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
.endm
/* Save/restores x0-x3 to the stack */
.macro __mitigate_spectre_bhb_fw
#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
stp x0, x1, [sp, #-16]!
stp x2, x3, [sp, #-16]!
mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3
alternative_cb arm64_update_smccc_conduit
nop // Patched to SMC/HVC #0
alternative_cb_end
ldp x2, x3, [sp], #16
ldp x0, x1, [sp], #16
#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
.endm
#endif /* __ASM_ASSEMBLER_H */

1
arch/arm64/include/asm/cpu.h
View File

@@ -36,7 +36,6 @@ struct cpuinfo_arm64 {
u64 reg_id_aa64dfr1;
u64 reg_id_aa64isar0;
u64 reg_id_aa64isar1;
u64 reg_id_aa64isar2;
u64 reg_id_aa64mmfr0;
u64 reg_id_aa64mmfr1;
u64 reg_id_aa64mmfr2;

3
arch/arm64/include/asm/cpucaps.h
View File

@@ -47,8 +47,7 @@
#define ARM64_SSBS 27
#define ARM64_HW_DBM 28
#define ARM64_WORKAROUND_1188873 29
#define ARM64_SPECTRE_BHB 30
#define ARM64_NCAPS 31
#define ARM64_NCAPS 30
#endif /* __ASM_CPUCAPS_H */

39
arch/arm64/include/asm/cpufeature.h
View File

@@ -462,34 +462,6 @@ static inline bool cpu_supports_mixed_endian_el0(void)
return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
}
static inline bool supports_csv2p3(int scope)
{
u64 pfr0;
u8 csv2_val;
if (scope == SCOPE_LOCAL_CPU)
pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
else
pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
csv2_val = cpuid_feature_extract_unsigned_field(pfr0,
ID_AA64PFR0_CSV2_SHIFT);
return csv2_val == 3;
}
static inline bool supports_clearbhb(int scope)
{
u64 isar2;
if (scope == SCOPE_LOCAL_CPU)
isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1);
else
isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
return cpuid_feature_extract_unsigned_field(isar2,
ID_AA64ISAR2_CLEARBHB_SHIFT);
}
static inline bool system_supports_32bit_el0(void)
{
return cpus_have_const_cap(ARM64_HAS_32BIT_EL0);
@@ -523,17 +495,6 @@ static inline int arm64_get_ssbd_state(void)
void arm64_set_ssbd_mitigation(bool state);
/* Watch out, ordering is important here. */
enum mitigation_state {
SPECTRE_UNAFFECTED,
SPECTRE_MITIGATED,
SPECTRE_VULNERABLE,
};
enum mitigation_state arm64_get_spectre_bhb_state(void);
bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry, int scope);
u8 spectre_bhb_loop_affected(int scope);
void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *__unused);
#endif /* __ASSEMBLY__ */
#endif

20
arch/arm64/include/asm/cputype.h
View File

@@ -90,17 +90,9 @@
#define ARM_CPU_PART_KRYO3S 0x803
#define ARM_CPU_PART_KRYO4S 0x803
#define ARM_CPU_PART_KRYO4G 0x804
#define ARM_CPU_PART_KRYO5S 0x805
#define ARM_CPU_PART_KRYO2XX_GOLD 0x800
#define ARM_CPU_PART_KRYO2XX_SILVER 0x801
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
#define ARM_CPU_PART_CORTEX_A77 0xD0D
#define ARM_CPU_PART_NEOVERSE_V1 0xD40
#define ARM_CPU_PART_CORTEX_A78 0xD41
#define ARM_CPU_PART_CORTEX_X1 0xD44
#define ARM_CPU_PART_CORTEX_A710 0xD47
#define ARM_CPU_PART_CORTEX_X2 0xD48
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
#define APM_CPU_PART_POTENZA 0x000
@@ -129,15 +121,7 @@
#define MIDR_KRYO3S MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO3S)
#define MIDR_KRYO4S MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO4S)
#define MIDR_KRYO4G MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO4G)
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
#define MIDR_KRYO5S MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO5S)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

6
arch/arm64/include/asm/fixmap.h
View File

@@ -59,11 +59,9 @@ enum fixed_addresses {
#endif /* CONFIG_ACPI_APEI_GHES */
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
FIX_ENTRY_TRAMP_TEXT3,
FIX_ENTRY_TRAMP_TEXT2,
FIX_ENTRY_TRAMP_TEXT1,
FIX_ENTRY_TRAMP_DATA,
#define TRAMP_VALIAS (__fix_to_virt(FIX_ENTRY_TRAMP_TEXT1))
FIX_ENTRY_TRAMP_TEXT,
#define TRAMP_VALIAS (__fix_to_virt(FIX_ENTRY_TRAMP_TEXT))
#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
__end_of_permanent_fixed_addresses,

6
arch/arm64/include/asm/io.h
View File

@@ -110,7 +110,8 @@ static inline u64 __raw_readq_no_log(const volatile void __iomem *addr)
volatile void __iomem *_a = (a); \
void *_addr = (void __force *)(_a); \
_ret = uncached_logk(LOGK_WRITEL, _addr); \
ETB_WAYPOINT; \
if (_ret) /* COFNIG_SEC_DEBUG */\
ETB_WAYPOINT; \
__raw_write##_t##_no_log((v), _a); \
if (_ret) \
LOG_BARRIER; \
@@ -127,7 +128,8 @@ static inline u64 __raw_readq_no_log(const volatile void __iomem *addr)
void *_addr = (void __force *)(_a); \
int _ret; \
_ret = uncached_logk(LOGK_READL, _addr); \
ETB_WAYPOINT; \
if (_ret) /* CONFIG_SEC_DEBUG */ \
ETB_WAYPOINT; \
__a = __raw_read##_l##_no_log(_a); \
if (_ret) \
LOG_BARRIER; \

5
arch/arm64/include/asm/kvm_host.h
View File

@@ -448,9 +448,4 @@ static inline int kvm_arm_have_ssbd(void)
}
}
static inline enum mitigation_state kvm_arm_get_spectre_bhb_state(void)
{
return arm64_get_spectre_bhb_state();
}
#endif /* __ARM64_KVM_HOST_H__ */

2
arch/arm64/include/asm/kvm_mmu.h
View File

@@ -358,7 +358,7 @@ static inline void *kvm_get_hyp_vector(void)
struct bp_hardening_data *data = arm64_get_bp_hardening_data();
void *vect = kvm_ksym_ref(__kvm_hyp_vector);
if (data->template_start) {
if (data->fn) {
vect = __bp_harden_hyp_vecs_start +
data->hyp_vectors_slot * SZ_2K;

8
arch/arm64/include/asm/mmu.h
View File

@@ -35,7 +35,7 @@ typedef struct {
*/
#define ASID(mm) ((mm)->context.id.counter & 0xffff)
static __always_inline bool arm64_kernel_unmapped_at_el0(void)
static inline bool arm64_kernel_unmapped_at_el0(void)
{
return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) &&
cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0);
@@ -46,12 +46,6 @@ typedef void (*bp_hardening_cb_t)(void);
struct bp_hardening_data {
int hyp_vectors_slot;
bp_hardening_cb_t fn;
/*
* template_start is only used by the BHB mitigation to identify the
* hyp_vectors_slot sequence.
*/
const char *template_start;
};
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

29
arch/arm64/include/asm/pgalloc.h
View File

@@ -23,6 +23,9 @@
#include <asm/processor.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#ifdef CONFIG_UH_RKP
#include <linux/rkp.h>
#endif
#define check_pgt_cache() do { } while (0)
@@ -33,12 +36,25 @@
static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
{
#ifdef CONFIG_UH_RKP
/* FIXME not zeroing the page */
pmd_t *rkp_ropage = NULL;
if (mm == &init_mm && (rkp_ropage = (pmd_t *)rkp_ro_alloc()))
return rkp_ropage;
else
#endif
return (pmd_t *)__get_free_page(PGALLOC_GFP);
}
static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
{
BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
#ifdef CONFIG_UH_RKP
if (is_rkp_ro_page((unsigned long)pmd))
rkp_ro_free((void *)pmd);
else
#endif
free_page((unsigned long)pmd);
}
@@ -62,12 +78,25 @@ static inline void __pud_populate(pud_t *pud, phys_addr_t pmd, pudval_t prot)
static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
{
#ifdef CONFIG_UH_RKP
pmd_t *rkp_ropage = NULL;
rkp_ropage = (pud_t *)rkp_ro_alloc();
if (rkp_ropage)
return rkp_ropage;
else
#endif
return (pud_t *)__get_free_page(PGALLOC_GFP);
}
static inline void pud_free(struct mm_struct *mm, pud_t *pud)
{
BUG_ON((unsigned long)pud & (PAGE_SIZE-1));
#ifdef CONFIG_UH_RKP
if (is_rkp_ro_page((u64)pud))
rkp_ro_free((void *)pud);
else
#endif
free_page((unsigned long)pud);
}

57
arch/arm64/include/asm/pgtable.h
View File

@@ -24,6 +24,13 @@
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable-prot.h>
#ifdef CONFIG_UH
#include <linux/uh.h>
#ifdef CONFIG_UH_RKP
#include <linux/rkp.h>
#endif
#endif
/*
* VMALLOC range.
*
@@ -93,8 +100,6 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
#define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
#define pte_valid_not_user(pte) \
((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
#define pte_valid_young(pte) \
((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF))
#define pte_valid_user(pte) \
((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
@@ -102,9 +107,12 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
* Could the pte be present in the TLB? We must check mm_tlb_flush_pending
* so that we don't erroneously return false for pages that have been
* remapped as PROT_NONE but are yet to be flushed from the TLB.
* Note that we can't make any assumptions based on the state of the access
* flag, since ptep_clear_flush_young() elides a DSB when invalidating the
* TLB.
*/
#define pte_accessible(mm, pte) \
(mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte))
(mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
/*
* p??_access_permitted() is true for valid user mappings (subject to the
@@ -228,8 +236,23 @@ pte_bad:
pte_ok:
#endif
*ptep = pte;
#ifdef CONFIG_UH_RKP
/* bug on double mapping */
BUG_ON(pte_val(pte) && rkp_is_pg_dbl_mapped(pte_val(pte)));
if (rkp_is_pg_protected((u64)ptep)) {
uh_call(UH_APP_RKP, RKP_WRITE_PGT3, (u64)ptep, pte_val(pte), 0, 0);
} else {
asm volatile("mov x1, %0\n"
"mov x2, %1\n"
"str x2, [x1]\n"
:
: "r" (ptep), "r" (pte)
: "x1", "x2", "memory");
}
#else
*ptep = pte;
#endif
/*
* Only if the new pte is valid and kernel, otherwise TLB maintenance
* or update_mmu_cache() have the necessary barriers.
@@ -414,7 +437,20 @@ static inline bool pud_table(pud_t pud) { return true; }
static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
{
#ifdef CONFIG_UH_RKP
if (rkp_is_pg_protected((u64)pmdp)) {
uh_call(UH_APP_RKP, RKP_WRITE_PGT2, (u64)pmdp, pmd_val(pmd), 0, 0);
} else {
asm volatile("mov x1, %0\n"
"mov x2, %1\n"
"str x2, [x1]\n"
:
: "r" (pmdp), "r" (pmd)
: "x1", "x2", "memory");
}
#else
*pmdp = pmd;
#endif
dsb(ishst);
isb();
}
@@ -471,7 +507,20 @@ static inline void pte_unmap(pte_t *pte) { }
static inline void set_pud(pud_t *pudp, pud_t pud)
{
#ifdef CONFIG_UH_RKP
if (rkp_is_pg_protected((u64)pudp)) {
uh_call(UH_APP_RKP, RKP_WRITE_PGT1, (u64)pudp, pud_val(pud), 0, 0);
} else {
asm volatile("mov x1, %0\n"
"mov x2, %1\n"
"str x2, [x1]\n"
:
: "r" (pudp), "r" (pud)
: "x1", "x2", "memory");
}
#else
*pudp = pud;
#endif
dsb(ishst);
isb();
}

199
arch/arm64/include/asm/sec_debug.h Normal file
View File

@@ -0,0 +1,199 @@
/*
* arch/arm64/include/asm/sec_debug.h
*
* COPYRIGHT(C) 2006-2016 Samsung Electronics Co., Ltd. All Right Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef SEC_DEBUG_ARM64_H
#define SEC_DEBUG_ARM64_H
#if defined(CONFIG_ARM64) && defined(CONFIG_SEC_DEBUG)
struct sec_debug_mmu_reg_t {
uint64_t TTBR0_EL1;
uint64_t TTBR1_EL1;
uint64_t TCR_EL1;
uint64_t MAIR_EL1;
uint64_t ATCR_EL1;
uint64_t AMAIR_EL1;
uint64_t HSTR_EL2;
uint64_t HACR_EL2;
uint64_t TTBR0_EL2;
uint64_t VTTBR_EL2;
uint64_t TCR_EL2;
uint64_t VTCR_EL2;
uint64_t MAIR_EL2;
uint64_t ATCR_EL2;
uint64_t TTBR0_EL3;
uint64_t MAIR_EL3;
uint64_t ATCR_EL3;
};
/* ARM CORE regs mapping structure */
struct sec_debug_core_t {
/* COMMON */
uint64_t x0;
uint64_t x1;
uint64_t x2;
uint64_t x3;
uint64_t x4;
uint64_t x5;
uint64_t x6;
uint64_t x7;
uint64_t x8;
uint64_t x9;
uint64_t x10;
uint64_t x11;
uint64_t x12;
uint64_t x13;
uint64_t x14;
uint64_t x15;
uint64_t x16;
uint64_t x17;
uint64_t x18;
uint64_t x19;
uint64_t x20;
uint64_t x21;
uint64_t x22;
uint64_t x23;
uint64_t x24;
uint64_t x25;
uint64_t x26;
uint64_t x27;
uint64_t x28;
uint64_t x29; /* sp */
uint64_t x30; /* lr */
uint64_t pc; /* pc */
uint64_t cpsr; /* cpsr */
/* EL0 */
uint64_t sp_el0;
/* EL1 */
uint64_t sp_el1;
uint64_t elr_el1;
uint64_t spsr_el1;
/* EL2 */
uint64_t sp_el2;
uint64_t elr_el2;
uint64_t spsr_el2;
/* EL3 */
/* uint64_t sp_el3; */
/* uint64_t elr_el3; */
/* uint64_t spsr_el3; */
};
#define READ_SPECIAL_REG(x) ({ \
uint64_t val; \
asm volatile ("mrs %0, " # x : "=r"(val)); \
val; \
})
static inline void sec_debug_save_mmu_reg(struct sec_debug_mmu_reg_t *mmu_reg)
{
uint64_t pstate, which_el;
pstate = READ_SPECIAL_REG(CurrentEl);
which_el = pstate & PSR_MODE_MASK;
/* pr_emerg("%s: sec_debug EL mode=%d\n", __func__,which_el); */
mmu_reg->TTBR0_EL1 = READ_SPECIAL_REG(TTBR0_EL1);
mmu_reg->TTBR1_EL1 = READ_SPECIAL_REG(TTBR1_EL1);
mmu_reg->TCR_EL1 = READ_SPECIAL_REG(TCR_EL1);
mmu_reg->MAIR_EL1 = READ_SPECIAL_REG(MAIR_EL1);
mmu_reg->AMAIR_EL1 = READ_SPECIAL_REG(AMAIR_EL1);
}
static inline void sec_debug_save_core_reg(struct sec_debug_core_t *core_reg)
{
uint64_t pstate,which_el;
pstate = READ_SPECIAL_REG(CurrentEl);
which_el = pstate & PSR_MODE_MASK;
/* pr_emerg("%s: sec_debug EL mode=%d\n", __func__,which_el); */
asm volatile (
"str x0, [%0,#0]\n\t" /* x0 is pushed first to core_reg */
"mov x0, %0\n\t"
"add x0, x0, 0x8\n\t"
"stp x1, x2, [x0], #0x10\n\t"
"stp x3, x4, [x0], #0x10\n\t"
"stp x5, x6, [x0], #0x10\n\t"
"stp x7, x8, [x0], #0x10\n\t"
"stp x9, x10, [x0], #0x10\n\t"
"stp x11, x12, [x0], #0x10\n\t"
"stp x13, x14, [x0], #0x10\n\t"
#if (!defined CONFIG_RKP_CFP_ROPP) || (defined CONFIG_RKP_CFP_TEST)
"stp x15, x16, [x0], #0x10\n\t"
"stp x17, x18, [x0], #0x10\n\t"
#else
"stp x15, xZR, [x0], #0x10\n\t"
"stp xZR, x18, [x0], #0x10\n\t"
#endif
"stp x19, x20, [x0], #0x10\n\t"
"stp x21, x22, [x0], #0x10\n\t"
"stp x23, x24, [x0], #0x10\n\t"
"stp x25, x26, [x0], #0x10\n\t"
"stp x27, x28, [x0], #0x10\n\t"
"stp x29, x30, [x0], #0x10\n\t"
/* pc */
"adr x1, .\n\t"
/* pstate */
"mrs x15, NZCV\n\t"
"bic x15, x15, #0xFFFFFFFF0FFFFFFF\n\t"
"mrs x9, DAIF\n\t"
"bic x9, x9, #0xFFFFFFFFFFFFFC3F\n\t"
"orr x15, x15, x9\n\t"
"mrs x10, CurrentEL\n\t"
"bic x10, x10, #0xFFFFFFFFFFFFFFF3\n\t"
"orr x15, x15, x10\n\t"
"mrs x11, SPSel\n\t"
"bic x11, x11, #0xFFFFFFFFFFFFFFFE\n\t"
"orr x15, x15, x11\n\t"
/* store pc & pstate */
"stp x1, x15, [x0], #0x10\n\t"
: /* output */
: "r"(core_reg) /* input */
: "%x0", "%x1" /* clobbered registers */
);
core_reg->sp_el0 = READ_SPECIAL_REG(sp_el0);
if(which_el >= PSR_MODE_EL2t){
core_reg->sp_el0 = READ_SPECIAL_REG(sp_el1);
core_reg->elr_el1 = READ_SPECIAL_REG(elr_el1);
core_reg->spsr_el1 = READ_SPECIAL_REG(spsr_el1);
core_reg->sp_el2 = READ_SPECIAL_REG(sp_el2);
core_reg->elr_el2 = READ_SPECIAL_REG(elr_el2);
core_reg->spsr_el2 = READ_SPECIAL_REG(spsr_el2);
}
}
#endif /* defined(CONFIG_ARM64) && defined(CONFIG_SEC_DEBUG) */
#endif /* SEC_DEBUG_ARM64_H */

6
arch/arm64/include/asm/sections.h
View File

@@ -28,11 +28,5 @@ extern char __initdata_begin[], __initdata_end[];
extern char __inittext_begin[], __inittext_end[];
extern char __irqentry_text_start[], __irqentry_text_end[];
extern char __mmuoff_data_start[], __mmuoff_data_end[];
extern char __entry_tramp_text_start[], __entry_tramp_text_end[];
static inline size_t entry_tramp_text_size(void)
{
return __entry_tramp_text_end - __entry_tramp_text_start;
}
#endif /* __ASM_SECTIONS_H */

5
arch/arm64/include/asm/sysreg.h
View File

@@ -168,7 +168,6 @@
#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
@@ -419,9 +418,6 @@
#define ID_AA64ISAR1_JSCVT_SHIFT 12
#define ID_AA64ISAR1_DPB_SHIFT 0
/* id_aa64isar2 */
#define ID_AA64ISAR2_CLEARBHB_SHIFT 28
/* id_aa64pfr0 */
#define ID_AA64PFR0_CSV3_SHIFT 60
#define ID_AA64PFR0_CSV2_SHIFT 56
@@ -469,7 +465,6 @@
#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
/* id_aa64mmfr1 */
#define ID_AA64MMFR1_ECBHB_SHIFT 60
#define ID_AA64MMFR1_PAN_SHIFT 20
#define ID_AA64MMFR1_LOR_SHIFT 16
#define ID_AA64MMFR1_HPD_SHIFT 12

15
arch/arm64/include/asm/tlb.h
View File

@@ -21,6 +21,9 @@
#include <linux/pagemap.h>
#include <linux/swap.h>
#ifdef CONFIG_UH_RKP
#include <linux/rkp.h>
#endif
#ifdef CONFIG_HAVE_RCU_TABLE_FREE
@@ -66,7 +69,11 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
unsigned long addr)
{
__flush_tlb_pgtable(tlb->mm, addr);
#ifdef CONFIG_UH_RKP
if (is_rkp_ro_page((unsigned long)pmdp)) {
rkp_ro_free((void *)pmdp);
} else
#endif
tlb_remove_entry(tlb, virt_to_page(pmdp));
}
#endif
@@ -75,7 +82,11 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pudp,
unsigned long addr)
{
__flush_tlb_pgtable(tlb->mm, addr);
#ifdef CONFIG_UH_RKP
if (is_rkp_ro_page((unsigned long)pudp)) {
rkp_ro_free((void *)pudp);
else
#endif
tlb_remove_entry(tlb, virt_to_page(pudp));
}
#endif

1
arch/arm64/include/asm/uaccess.h
View File

@@ -28,6 +28,7 @@
#include <linux/bitops.h>
#include <linux/kasan-checks.h>
#include <linux/string.h>
#include <linux/sched.h>
#include <asm/cpufeature.h>
#include <asm/ptrace.h>

2
arch/arm64/include/uapi/asm/setup.h
View File

@@ -22,6 +22,6 @@
#include <linux/types.h>
#define COMMAND_LINE_SIZE 2048
#define COMMAND_LINE_SIZE 4096
#endif

2
arch/arm64/kernel/Makefile
View File

@@ -63,6 +63,8 @@ arm64-obj-$(CONFIG_HARDEN_BRANCH_PREDICTOR) += bpi.o
endif
arm64-obj-$(CONFIG_ARM64_SSBD) += ssbd.o
arm64-obj-$(CONFIG_UH) += uh_entry.o
obj-y += $(arm64-obj-y) vdso/ probes/
obj-m += $(arm64-obj-m)
head-y := head.o

9
arch/arm64/kernel/armv8_deprecated.c
View File

@@ -63,6 +63,7 @@ struct insn_emulation {
static LIST_HEAD(insn_emulation);
static int nr_insn_emulated __initdata;
static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
static DEFINE_MUTEX(insn_emulation_mutex);
static void register_emulation_hooks(struct insn_emulation_ops *ops)
{
@@ -208,10 +209,10 @@ static int emulation_proc_handler(struct ctl_table *table, int write,
loff_t *ppos)
{
int ret = 0;
struct insn_emulation *insn = (struct insn_emulation *) table->data;
struct insn_emulation *insn = container_of(table->data, struct insn_emulation, current_mode);
enum insn_emulation_mode prev_mode = insn->current_mode;
table->data = &insn->current_mode;
mutex_lock(&insn_emulation_mutex);
ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
if (ret || !write || prev_mode == insn->current_mode)
@@ -224,7 +225,7 @@ static int emulation_proc_handler(struct ctl_table *table, int write,
update_insn_emulation_mode(insn, INSN_UNDEF);
}
ret:
table->data = insn;
mutex_unlock(&insn_emulation_mutex);
return ret;
}
@@ -254,7 +255,7 @@ static void __init register_insn_emulation_sysctl(struct ctl_table *table)
sysctl->maxlen = sizeof(int);
sysctl->procname = insn->ops->name;
sysctl->data = insn;
sysctl->data = &insn->current_mode;
sysctl->extra1 = &insn->min;
sysctl->extra2 = &insn->max;
sysctl->proc_handler = emulation_proc_handler;

55
arch/arm64/kernel/bpi.S
View File

@@ -66,58 +66,3 @@ ENTRY(__smccc_workaround_1_smc_start)
ldp x0, x1, [sp, #(8 * 2)]
add sp, sp, #(8 * 4)
ENTRY(__smccc_workaround_1_smc_end)
ENTRY(__smccc_workaround_3_smc_start)
sub sp, sp, #(8 * 4)
stp x2, x3, [sp, #(8 * 0)]
stp x0, x1, [sp, #(8 * 2)]
mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3
smc #0
ldp x2, x3, [sp, #(8 * 0)]
ldp x0, x1, [sp, #(8 * 2)]
add sp, sp, #(8 * 4)
ENTRY(__smccc_workaround_3_smc_end)
ENTRY(__spectre_bhb_loop_k8_start)
sub sp, sp, #(8 * 2)
stp x0, x1, [sp, #(8 * 0)]
mov x0, #8
2: b . + 4
subs x0, x0, #1
b.ne 2b
dsb nsh
isb
ldp x0, x1, [sp, #(8 * 0)]
add sp, sp, #(8 * 2)
ENTRY(__spectre_bhb_loop_k8_end)
ENTRY(__spectre_bhb_loop_k24_start)
sub sp, sp, #(8 * 2)
stp x0, x1, [sp, #(8 * 0)]
mov x0, #24
2: b . + 4
subs x0, x0, #1
b.ne 2b
dsb nsh
isb
ldp x0, x1, [sp, #(8 * 0)]
add sp, sp, #(8 * 2)
ENTRY(__spectre_bhb_loop_k24_end)
ENTRY(__spectre_bhb_loop_k32_start)
sub sp, sp, #(8 * 2)
stp x0, x1, [sp, #(8 * 0)]
mov x0, #32
2: b . + 4
subs x0, x0, #1
b.ne 2b
dsb nsh
isb
ldp x0, x1, [sp, #(8 * 0)]
add sp, sp, #(8 * 2)
ENTRY(__spectre_bhb_loop_k32_end)
ENTRY(__spectre_bhb_clearbhb_start)
hint #22 /* aka clearbhb */
isb
ENTRY(__spectre_bhb_clearbhb_end)

412
arch/arm64/kernel/cpu_errata.c
View File

@@ -23,7 +23,6 @@
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/cpufeature.h>
#include <asm/vectors.h>
static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
@@ -86,16 +85,6 @@ DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
#ifdef CONFIG_KVM
extern char __smccc_workaround_1_smc_start[];
extern char __smccc_workaround_1_smc_end[];
extern char __smccc_workaround_3_smc_start[];
extern char __smccc_workaround_3_smc_end[];
extern char __spectre_bhb_loop_k8_start[];
extern char __spectre_bhb_loop_k8_end[];
extern char __spectre_bhb_loop_k24_start[];
extern char __spectre_bhb_loop_k24_end[];
extern char __spectre_bhb_loop_k32_start[];
extern char __spectre_bhb_loop_k32_end[];
extern char __spectre_bhb_clearbhb_start[];
extern char __spectre_bhb_clearbhb_end[];
static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
const char *hyp_vecs_end)
@@ -109,14 +98,12 @@ static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
}
static DEFINE_SPINLOCK(bp_lock);
static int last_slot = -1;
static void install_bp_hardening_cb(bp_hardening_cb_t fn,
const char *hyp_vecs_start,
const char *hyp_vecs_end)
{
static int last_slot = -1;
static DEFINE_SPINLOCK(bp_lock);
int cpu, slot = -1;
spin_lock(&bp_lock);
@@ -137,7 +124,6 @@ static void install_bp_hardening_cb(bp_hardening_cb_t fn,
__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
__this_cpu_write(bp_hardening_data.fn, fn);
__this_cpu_write(bp_hardening_data.template_start, hyp_vecs_start);
spin_unlock(&bp_lock);
}
#else
@@ -314,31 +300,6 @@ void arm64_set_ssbd_mitigation(bool state)
}
}
#if defined(CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY) || \
defined(CONFIG_ARM64_SSBD)
void __init arm64_update_smccc_conduit(struct alt_instr *alt,
__le32 *origptr, __le32 *updptr,
int nr_inst)
{
u32 insn;
BUG_ON(nr_inst != 1);
switch (psci_ops.conduit) {
case PSCI_CONDUIT_HVC:
insn = aarch64_insn_get_hvc_value();
break;
case PSCI_CONDUIT_SMC:
insn = aarch64_insn_get_smc_value();
break;
default:
return;
}
*updptr = cpu_to_le32(insn);
}
#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY || CONFIG_ARM64_SSBD */
static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
int scope)
{
@@ -767,13 +728,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
15, 15),
},
#endif
{
.desc = "Spectre-BHB",
.capability = ARM64_SPECTRE_BHB,
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
.matches = is_spectre_bhb_affected,
.cpu_enable = spectre_bhb_enable_mitigation,
},
{
}
};
@@ -784,39 +738,14 @@ ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
return sprintf(buf, "Mitigation: __user pointer sanitization\n");
}
static const char *get_bhb_affected_string(enum mitigation_state bhb_state)
{
switch (bhb_state) {
case SPECTRE_UNAFFECTED:
return "";
default:
case SPECTRE_VULNERABLE:
return ", but not BHB";
case SPECTRE_MITIGATED:
return ", BHB";
}
}
ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
char *buf)
{
enum mitigation_state bhb_state = arm64_get_spectre_bhb_state();
const char *bhb_str = get_bhb_affected_string(bhb_state);
const char *v2_str = "Branch predictor hardening";
if (__spectrev2_safe) {
if (bhb_state == SPECTRE_UNAFFECTED)
return sprintf(buf, "Not affected\n");
/*
* Platforms affected by Spectre-BHB can't report
* "Not affected" for Spectre-v2.
*/
v2_str = "CSV2";
}
if (__spectrev2_safe)
return sprintf(buf, "Not affected\n");
if (__hardenbp_enab)
return sprintf(buf, "Mitigation: %s%s\n", v2_str, bhb_str);
return sprintf(buf, "Mitigation: Branch predictor hardening\n");
return sprintf(buf, "Vulnerable\n");
}
@@ -837,334 +766,3 @@ ssize_t cpu_show_spec_store_bypass(struct device *dev,
return sprintf(buf, "Vulnerable\n");
}
/*
* We try to ensure that the mitigation state can never change as the result of
* onlining a late CPU.
*/
static void update_mitigation_state(enum mitigation_state *oldp,
enum mitigation_state new)
{
enum mitigation_state state;
do {
state = READ_ONCE(*oldp);
if (new <= state)
break;
} while (cmpxchg_relaxed(oldp, state, new) != state);
}
/*
* Spectre BHB.
*
* A CPU is either:
* - Mitigated by a branchy loop a CPU specific number of times, and listed
* in our "loop mitigated list".
* - Mitigated in software by the firmware Spectre v2 call.
* - Has the ClearBHB instruction to perform the mitigation.
* - Has the 'Exception Clears Branch History Buffer' (ECBHB) feature, so no
* software mitigation in the vectors is needed.
* - Has CSV2.3, so is unaffected.
*/
static enum mitigation_state spectre_bhb_state;
enum mitigation_state arm64_get_spectre_bhb_state(void)
{
return spectre_bhb_state;
}
/*
* This must be called with SCOPE_LOCAL_CPU for each type of CPU, before any
* SCOPE_SYSTEM call will give the right answer.
*/
u8 spectre_bhb_loop_affected(int scope)
{
u8 k = 0;
static u8 max_bhb_k;
if (scope == SCOPE_LOCAL_CPU) {
static const struct midr_range spectre_bhb_k32_list[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
{},
};
static const struct midr_range spectre_bhb_k24_list[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
{},
};
static const struct midr_range spectre_bhb_k8_list[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
{},
};
if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list))
k = 32;
else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list))
k = 24;
else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list))
k = 8;
max_bhb_k = max(max_bhb_k, k);
} else {
k = max_bhb_k;
}
return k;
}
static enum mitigation_state spectre_bhb_get_cpu_fw_mitigation_state(void)
{
int ret;
struct arm_smccc_res res;
if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
return SPECTRE_VULNERABLE;
switch (psci_ops.conduit) {
case PSCI_CONDUIT_HVC:
arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
ARM_SMCCC_ARCH_WORKAROUND_3, &res);
break;
case PSCI_CONDUIT_SMC:
arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
ARM_SMCCC_ARCH_WORKAROUND_3, &res);
break;
default:
return SPECTRE_VULNERABLE;
}
ret = res.a0;
switch (ret) {
case SMCCC_RET_SUCCESS:
return SPECTRE_MITIGATED;
case SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED:
return SPECTRE_UNAFFECTED;
default:
case SMCCC_RET_NOT_SUPPORTED:
return SPECTRE_VULNERABLE;
}
}
static bool is_spectre_bhb_fw_affected(int scope)
{
static bool system_affected;
enum mitigation_state fw_state;
bool has_smccc = (psci_ops.smccc_version >= SMCCC_VERSION_1_1);
static const struct midr_range spectre_bhb_firmware_mitigated_list[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
{},
};
bool cpu_in_list = is_midr_in_range_list(read_cpuid_id(),
spectre_bhb_firmware_mitigated_list);
if (scope != SCOPE_LOCAL_CPU)
return system_affected;
fw_state = spectre_bhb_get_cpu_fw_mitigation_state();
if (cpu_in_list || (has_smccc && fw_state == SPECTRE_MITIGATED)) {
system_affected = true;
return true;
}
return false;
}
static bool supports_ecbhb(int scope)
{
u64 mmfr1;
if (scope == SCOPE_LOCAL_CPU)
mmfr1 = read_sysreg_s(SYS_ID_AA64MMFR1_EL1);
else
mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
return cpuid_feature_extract_unsigned_field(mmfr1,
ID_AA64MMFR1_ECBHB_SHIFT);
}
bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry,
int scope)
{
WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
if (supports_csv2p3(scope))
return false;
if (supports_clearbhb(scope))
return true;
if (spectre_bhb_loop_affected(scope))
return true;
if (is_spectre_bhb_fw_affected(scope))
return true;
return false;
}
static void this_cpu_set_vectors(enum arm64_bp_harden_el1_vectors slot)
{
const char *v = arm64_get_bp_hardening_vector(slot);
if (slot < 0)
return;
__this_cpu_write(this_cpu_vector, v);
/*
* When KPTI is in use, the vectors are switched when exiting to
* user-space.
*/
if (arm64_kernel_unmapped_at_el0())
return;
write_sysreg(v, vbar_el1);
isb();
}
#ifdef CONFIG_KVM
static const char *kvm_bhb_get_vecs_end(const char *start)
{
if (start == __smccc_workaround_3_smc_start)
return __smccc_workaround_3_smc_end;
else if (start == __spectre_bhb_loop_k8_start)
return __spectre_bhb_loop_k8_end;
else if (start == __spectre_bhb_loop_k24_start)
return __spectre_bhb_loop_k24_end;
else if (start == __spectre_bhb_loop_k32_start)
return __spectre_bhb_loop_k32_end;
else if (start == __spectre_bhb_clearbhb_start)
return __spectre_bhb_clearbhb_end;
return NULL;
}
static void kvm_setup_bhb_slot(const char *hyp_vecs_start)
{
int cpu, slot = -1;
const char *hyp_vecs_end;
if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available())
return;
hyp_vecs_end = kvm_bhb_get_vecs_end(hyp_vecs_start);
if (WARN_ON_ONCE(!hyp_vecs_start || !hyp_vecs_end))
return;
spin_lock(&bp_lock);
for_each_possible_cpu(cpu) {
if (per_cpu(bp_hardening_data.template_start, cpu) == hyp_vecs_start) {
slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
break;
}
}
if (slot == -1) {
last_slot++;
BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start)
/ SZ_2K) <= last_slot);
slot = last_slot;
__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
}
__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
__this_cpu_write(bp_hardening_data.template_start, hyp_vecs_start);
spin_unlock(&bp_lock);
}
#else
#define __smccc_workaround_3_smc_start NULL
#define __spectre_bhb_loop_k8_start NULL
#define __spectre_bhb_loop_k24_start NULL
#define __spectre_bhb_loop_k32_start NULL
#define __spectre_bhb_clearbhb_start NULL
static void kvm_setup_bhb_slot(const char *hyp_vecs_start) { };
#endif
void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *entry)
{
enum mitigation_state fw_state, state = SPECTRE_VULNERABLE;
if (!is_spectre_bhb_affected(entry, SCOPE_LOCAL_CPU))
return;
if (!__spectrev2_safe && !__hardenbp_enab) {
/* No point mitigating Spectre-BHB alone. */
} else if (!IS_ENABLED(CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY)) {
pr_info_once("spectre-bhb mitigation disabled by compile time option\n");
} else if (cpu_mitigations_off()) {
pr_info_once("spectre-bhb mitigation disabled by command line option\n");
} else if (supports_ecbhb(SCOPE_LOCAL_CPU)) {
state = SPECTRE_MITIGATED;
} else if (supports_clearbhb(SCOPE_LOCAL_CPU)) {
kvm_setup_bhb_slot(__spectre_bhb_clearbhb_start);
this_cpu_set_vectors(EL1_VECTOR_BHB_CLEAR_INSN);
state = SPECTRE_MITIGATED;
} else if (spectre_bhb_loop_affected(SCOPE_LOCAL_CPU)) {
switch (spectre_bhb_loop_affected(SCOPE_SYSTEM)) {
case 8:
kvm_setup_bhb_slot(__spectre_bhb_loop_k8_start);
break;
case 24:
kvm_setup_bhb_slot(__spectre_bhb_loop_k24_start);
break;
case 32:
kvm_setup_bhb_slot(__spectre_bhb_loop_k32_start);
break;
default:
WARN_ON_ONCE(1);
}
this_cpu_set_vectors(EL1_VECTOR_BHB_LOOP);
state = SPECTRE_MITIGATED;
} else if (is_spectre_bhb_fw_affected(SCOPE_LOCAL_CPU)) {
fw_state = spectre_bhb_get_cpu_fw_mitigation_state();
if (fw_state == SPECTRE_MITIGATED) {
kvm_setup_bhb_slot(__smccc_workaround_3_smc_start);
this_cpu_set_vectors(EL1_VECTOR_BHB_FW);
/*
* With WA3 in the vectors, the WA1 calls can be
* removed.
*/
__this_cpu_write(bp_hardening_data.fn, NULL);
state = SPECTRE_MITIGATED;
}
}
update_mitigation_state(&spectre_bhb_state, state);
}
/* Patched to correct the immediate */
void __init spectre_bhb_patch_loop_iter(struct alt_instr *alt,
__le32 *origptr, __le32 *updptr, int nr_inst)
{
u8 rd;
u32 insn;
u16 loop_count = spectre_bhb_loop_affected(SCOPE_SYSTEM);
BUG_ON(nr_inst != 1); /* MOV -> MOV */
if (!IS_ENABLED(CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY))
return;
insn = le32_to_cpu(*origptr);
rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, insn);
insn = aarch64_insn_gen_movewide(rd, loop_count, 0,
AARCH64_INSN_VARIANT_64BIT,
AARCH64_INSN_MOVEWIDE_ZERO);
*updptr++ = cpu_to_le32(insn);
}

22
arch/arm64/kernel/cpufeature.c
View File

@@ -20,13 +20,11 @@
#include <linux/bsearch.h>
#include <linux/cpumask.h>
#include <linux/percpu.h>
#include <linux/sort.h>
#include <linux/stop_machine.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/cpu.h>
#include <asm/cpu.h>
#include <asm/cpufeature.h>
#include <asm/cpu_ops.h>
@@ -34,7 +32,6 @@
#include <asm/processor.h>
#include <asm/sysreg.h>
#include <asm/traps.h>
#include <asm/vectors.h>
#include <asm/virt.h>
unsigned long elf_hwcap __read_mostly;
@@ -53,8 +50,6 @@ unsigned int compat_elf_hwcap2 __read_mostly;
DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
EXPORT_SYMBOL(cpu_hwcaps);
DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
{
/* file-wide pr_fmt adds "CPU features: " prefix */
@@ -139,11 +134,6 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
ARM64_FTR_END,
};
static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
ARM64_FTR_END,
};
static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
@@ -374,7 +364,6 @@ static const struct __ftr_reg_entry {
/* Op1 = 0, CRn = 0, CRm = 6 */
ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
/* Op1 = 0, CRn = 0, CRm = 7 */
ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
@@ -520,7 +509,6 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
@@ -632,8 +620,6 @@ void update_cpu_features(int cpu,
info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
/*
* Differing PARange support is fine as long as all peripherals and
@@ -757,7 +743,6 @@ static u64 __read_sysreg_by_encoding(u32 sys_id)
read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
read_sysreg_case(SYS_CNTFRQ_EL0);
read_sysreg_case(SYS_CTR_EL0);
@@ -855,6 +840,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
MIDR_ALL_VERSIONS(MIDR_KRYO5S),
{ /* sentinel */ }
};
char const *str = "kpti command line option";
@@ -918,12 +904,6 @@ kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
static bool kpti_applied = false;
int cpu = smp_processor_id();
if (__this_cpu_read(this_cpu_vector) == vectors) {
const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
__this_cpu_write(this_cpu_vector, v);
}
if (kpti_applied)
return;

1
arch/arm64/kernel/cpuinfo.c
View File

@@ -348,7 +348,6 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);

243
arch/arm64/kernel/entry.S
View File

@@ -74,21 +74,18 @@
.macro kernel_ventry, el, label, regsize = 64
.align 7
.Lventry_start\@:
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
alternative_if ARM64_UNMAP_KERNEL_AT_EL0
.if \el == 0
/*
* This must be the first instruction of the EL0 vector entries. It is
* skipped by the trampoline vectors, to trigger the cleanup.
*/
b .Lskip_tramp_vectors_cleanup\@
.if \regsize == 64
mrs x30, tpidrro_el0
msr tpidrro_el0, xzr
.else
mov x30, xzr
.endif
.Lskip_tramp_vectors_cleanup\@:
.endif
alternative_else_nop_endif
#endif
sub sp, sp, #S_FRAME_SIZE
#ifdef CONFIG_VMAP_STACK
@@ -134,15 +131,11 @@
mrs x0, tpidrro_el0
#endif
b el\()\el\()_\label
.org .Lventry_start\@ + 128 // Did we overflow the ventry slot?
.endm
.macro tramp_alias, dst, sym, tmp
.macro tramp_alias, dst, sym
mov_q \dst, TRAMP_VALIAS
adr_l \tmp, \sym
add \dst, \dst, \tmp
adr_l \tmp, .entry.tramp.text
sub \dst, \dst, \tmp
add \dst, \dst, #(\sym - .entry.tramp.text)
.endm
// This macro corrupts x0-x3. It is the caller's duty
@@ -159,9 +152,6 @@
tbnz \tmp2, #TIF_SSBD, \targ
mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
mov w1, #\state
alternative_cb arm64_update_smccc_conduit
nop // Patched to SMC/HVC #0
alternative_cb_end
smc #0
#endif
.endm
@@ -370,25 +360,21 @@ alternative_else_nop_endif
ldp x24, x25, [sp, #16 * 12]
ldp x26, x27, [sp, #16 * 13]
ldp x28, x29, [sp, #16 * 14]
.if \el == 0
alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
ldr lr, [sp, #S_LR]
add sp, sp, #S_FRAME_SIZE // restore sp
eret
alternative_else_nop_endif
.if \el == 0
alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
bne 4f
msr far_el1, x29
tramp_alias x30, tramp_exit_native, x29
msr far_el1, x30
tramp_alias x30, tramp_exit_native
br x30
4:
tramp_alias x30, tramp_exit_compat, x29
tramp_alias x30, tramp_exit_compat
br x30
#endif
.else
ldr lr, [sp, #S_LR]
add sp, sp, #S_FRAME_SIZE // restore sp
eret
.endif
.endm
@@ -982,6 +968,29 @@ el0_svc_naked: // compat entry point
b.ne __sys_trace
cmp wscno, wsc_nr // check upper syscall limit
b.hs ni_sys
#ifdef CONFIG_SECURITY_DEFEX
/*
* Defex enter hook
*/
ldr x16, =defex_syscall_catch_enter
ldr x16, [x16]
cmp x16, xzr
b.eq 2f
uxtw x0, wscno // it will copy wscno to low bits of x0 and fill high bits with 0
mov x1, sp
blr x16
cbnz w0, ret_fast_syscall // block this syscall?
# adr lr, ret_fast_syscall // return address (not needed here)
ldp x0, x1, [sp] // restore the syscall args
ldp x2, x3, [sp, #S_X2]
ldp x4, x5, [sp, #S_X4]
ldp x6, x7, [sp, #S_X6]
2:
#endif
mask_nospec64 xscno, xsc_nr, x19 // enforce bounds for syscall number
ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
blr x16 // call sys_* routine
@@ -1009,6 +1018,23 @@ __sys_trace:
mov x1, sp // pointer to regs
cmp wscno, wsc_nr // check upper syscall limit
b.hs __ni_sys_trace
#ifdef CONFIG_SECURITY_DEFEX
/*
* Defex enter hook
*/
ldr x16, =defex_syscall_catch_enter
ldr x16, [x16]
cmp x16, xzr
b.eq 3f
uxtw x0, wscno // it will copy wscno to low bits of x0 and fill high bits with 0
mov x1, sp
blr x16
cbnz w0, __sys_trace_return // block this syscall?
# adr lr, __sys_trace_return // return address (not neede here)
3:
#endif
ldp x0, x1, [sp] // restore the syscall args
ldp x2, x3, [sp, #S_X2]
ldp x4, x5, [sp, #S_X4]
@@ -1030,7 +1056,12 @@ __ni_sys_trace:
.popsection // .entry.text
// Move from tramp_pg_dir to swapper_pg_dir
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
/*
* Exception vectors trampoline.
*/
.pushsection ".entry.tramp.text", "ax"
.macro tramp_map_kernel, tmp
mrs \tmp, ttbr1_el1
sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
@@ -1062,47 +1093,12 @@ alternative_else_nop_endif
*/
.endm
.macro tramp_data_page dst
adr_l \dst, .entry.tramp.text
sub \dst, \dst, PAGE_SIZE
.endm
.macro tramp_data_read_var dst, var
#ifdef CONFIG_RANDOMIZE_BASE
tramp_data_page \dst
add \dst, \dst, #:lo12:__entry_tramp_data_\var
ldr \dst, [\dst]
#else
ldr \dst, =\var
#endif
.endm
#define BHB_MITIGATION_NONE 0
#define BHB_MITIGATION_LOOP 1
#define BHB_MITIGATION_FW 2
#define BHB_MITIGATION_INSN 3
.macro tramp_ventry, vector_start, regsize, kpti, bhb
.macro tramp_ventry, regsize = 64
.align 7
1:
.if \regsize == 64
msr tpidrro_el0, x30 // Restored in kernel_ventry
.endif
.if \bhb == BHB_MITIGATION_LOOP
/*
* This sequence must appear before the first indirect branch. i.e. the
* ret out of tramp_ventry. It appears here because x30 is free.
*/
__mitigate_spectre_bhb_loop x30
.endif // \bhb == BHB_MITIGATION_LOOP
.if \bhb == BHB_MITIGATION_INSN
clearbhb
isb
.endif // \bhb == BHB_MITIGATION_INSN
.if \kpti == 1
/*
* Defend against branch aliasing attacks by pushing a dummy
* entry onto the return stack and using a RET instruction to
@@ -1112,75 +1108,43 @@ alternative_else_nop_endif
b .
2:
tramp_map_kernel x30
#ifdef CONFIG_RANDOMIZE_BASE
adr x30, tramp_vectors + PAGE_SIZE
alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
tramp_data_read_var x30, vectors
prfm plil1strm, [x30, #(1b - \vector_start)]
msr vbar_el1, x30
isb
.else
ldr x30, [x30]
#else
ldr x30, =vectors
.endif // \kpti == 1
.if \bhb == BHB_MITIGATION_FW
/*
* The firmware sequence must appear before the first indirect branch.
* i.e. the ret out of tramp_ventry. But it also needs the stack to be
* mapped to save/restore the registers the SMC clobbers.
*/
__mitigate_spectre_bhb_fw
.endif // \bhb == BHB_MITIGATION_FW
add x30, x30, #(1b - \vector_start + 4)
#endif
prfm plil1strm, [x30, #(1b - tramp_vectors)]
msr vbar_el1, x30
add x30, x30, #(1b - tramp_vectors)
isb
ret
.org 1b + 128 // Did we overflow the ventry slot?
.endm
.macro tramp_exit, regsize = 64
tramp_data_read_var x30, this_cpu_vector
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
mrs x29, tpidr_el1
alternative_else
mrs x29, tpidr_el2
alternative_endif
ldr x30, [x30, x29]
adr x30, tramp_vectors
msr vbar_el1, x30
ldr lr, [sp, #S_LR]
tramp_unmap_kernel x29
tramp_unmap_kernel x30
.if \regsize == 64
mrs x29, far_el1
mrs x30, far_el1
.endif
add sp, sp, #S_FRAME_SIZE // restore sp
eret
.endm
.macro generate_tramp_vector, kpti, bhb
.Lvector_start\@:
.space 0x400
.rept 4
tramp_ventry .Lvector_start\@, 64, \kpti, \bhb
.endr
.rept 4
tramp_ventry .Lvector_start\@, 32, \kpti, \bhb
.endr
.endm
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
/*
* Exception vectors trampoline.
* The order must match __bp_harden_el1_vectors and the
* arm64_bp_harden_el1_vectors enum.
*/
.pushsection ".entry.tramp.text", "ax"
.align 11
ENTRY(tramp_vectors)
#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP
generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW
generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN
#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE
.space 0x400
tramp_ventry
tramp_ventry
tramp_ventry
tramp_ventry
tramp_ventry 32
tramp_ventry 32
tramp_ventry 32
tramp_ventry 32
END(tramp_vectors)
ENTRY(tramp_exit_native)
@@ -1198,54 +1162,11 @@ END(tramp_exit_compat)
.align PAGE_SHIFT
.globl __entry_tramp_data_start
__entry_tramp_data_start:
__entry_tramp_data_vectors:
.quad vectors
#ifdef CONFIG_ARM_SDE_INTERFACE
__entry_tramp_data___sdei_asm_trampoline_next_handler:
.quad __sdei_asm_handler
#endif /* CONFIG_ARM_SDE_INTERFACE */
__entry_tramp_data_this_cpu_vector:
.quad this_cpu_vector
.popsection // .rodata
#endif /* CONFIG_RANDOMIZE_BASE */
#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
/*
* Exception vectors for spectre mitigations on entry from EL1 when
* kpti is not in use.
*/
.macro generate_el1_vector, bhb
.Lvector_start\@:
kernel_ventry 1, sync_invalid // Synchronous EL1t
kernel_ventry 1, irq_invalid // IRQ EL1t
kernel_ventry 1, fiq_invalid // FIQ EL1t
kernel_ventry 1, error_invalid // Error EL1t
kernel_ventry 1, sync // Synchronous EL1h
kernel_ventry 1, irq // IRQ EL1h
kernel_ventry 1, fiq_invalid // FIQ EL1h
kernel_ventry 1, error_invalid // Error EL1h
.rept 4
tramp_ventry .Lvector_start\@, 64, 0, \bhb
.endr
.rept 4
tramp_ventry .Lvector_start\@, 32, 0, \bhb
.endr
.endm
/* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */
.pushsection ".entry.text", "ax"
.align 11
ENTRY(__bp_harden_el1_vectors)
#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
generate_el1_vector bhb=BHB_MITIGATION_LOOP
generate_el1_vector bhb=BHB_MITIGATION_FW
generate_el1_vector bhb=BHB_MITIGATION_INSN
#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
END(__bp_harden_el1_vectors)
.popsection
/*
* Special system call wrappers.
*/

10
arch/arm64/kernel/fpsimd.c
View File

@@ -32,6 +32,8 @@
#include <asm/cputype.h>
#include <asm/simd.h>
#include <linux/sec_debug.h>
#define FPEXC_IOF (1 << 0)
#define FPEXC_DZF (1 << 1)
#define FPEXC_OFF (1 << 2)
@@ -159,9 +161,15 @@ void fpsimd_thread_switch(struct task_struct *next)
struct fpsimd_state *st = &next->thread.fpsimd_state;
if (__this_cpu_read(fpsimd_last_state) == st
&& st->cpu == smp_processor_id())
&& st->cpu == smp_processor_id()) {
#ifdef CONFIG_KERNEL_MODE_NEON_DEBUG
fpsimd_context_check(next);
#endif
clear_ti_thread_flag(task_thread_info(next),
TIF_FOREIGN_FPSTATE);
}
else
set_ti_thread_flag(task_thread_info(next),
TIF_FOREIGN_FPSTATE);

11
arch/arm64/kernel/head.S
View File

@@ -90,7 +90,11 @@ _head:
le64sym _kernel_size_le // Effective size of kernel image, little-endian
le64sym _kernel_flags_le // Informative flags, little-endian
.quad 0 // reserved
.quad 0 // reserved
#ifdef CONFIG_PROCA
le64sym _proca_conf_offset // memory info for proca ta
#else
.quad 0xecefecef // Magic number for proca ta
#endif
.quad 0 // reserved
.ascii "ARM\x64" // Magic number
#ifdef CONFIG_EFI
@@ -140,8 +144,13 @@ preserve_boot_args:
mov x21, x0 // x21=FDT
adr_l x0, boot_args // record the contents of
#ifndef CONFIG_RANDOMIZE_BASE
stp x21, x1, [x0] // x0 .. x3 at kernel entry
stp x2, x3, [x0, #16]
#else
stp x21, xzr, [x0] // x0 .. x3 at kernel entry
stp xzr, xzr, [x0, #16]
#endif
dmb sy // needed before dc ivac with
// MMU off

10
arch/arm64/kernel/image.h
View File

@@ -60,6 +60,13 @@
#define __HEAD_FLAGS ((__HEAD_FLAG_BE << 0) | \
(__HEAD_FLAG_PAGE_SIZE << 1) | \
(__HEAD_FLAG_PHYS_BASE << 3))
#ifdef CONFIG_PROCA
#define PROCA_CONF_OFFSET_IMAGE_LE64 \
DEFINE_IMAGE_LE64(_proca_conf_offset, g_proca_config - _text);
#else
#define PROCA_CONF_OFFSET_IMAGE_LE64
#endif
/*
* These will output as part of the Image header, which should be little-endian
@@ -69,7 +76,8 @@
#define HEAD_SYMBOLS \
DEFINE_IMAGE_LE64(_kernel_size_le, _end - _text); \
DEFINE_IMAGE_LE64(_kernel_offset_le, TEXT_OFFSET); \
DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS);
DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS); \
PROCA_CONF_OFFSET_IMAGE_LE64
#ifdef CONFIG_EFI

60
arch/arm64/kernel/process.c
View File

@@ -183,64 +183,6 @@ void machine_restart(char *cmd)
while (1);
}
/*
* dump a block of kernel memory from around the given address
*/
static void show_data(unsigned long addr, int nbytes, const char *name)
{
int i, j;
int nlines;
u32 *p;
/*
* don't attempt to dump non-kernel addresses or
* values that are probably just small negative numbers
*/
if (addr < KIMAGE_VADDR || addr > -256UL)
return;
printk("\n%s: %#lx:\n", name, addr);
/*
* round address down to a 32 bit boundary
* and always dump a multiple of 32 bytes
*/
p = (u32 *)(addr & ~(sizeof(u32) - 1));
nbytes += (addr & (sizeof(u32) - 1));
nlines = (nbytes + 31) / 32;
for (i = 0; i < nlines; i++) {
/*
* just display low 16 bits of address to keep
* each line of the dump < 80 characters
*/
printk("%04lx ", (unsigned long)p & 0xffff);
for (j = 0; j < 8; j++) {
u32 data;
if (probe_kernel_address(p, data)) {
pr_cont(" ********");
} else {
pr_cont(" %08x", data);
}
++p;
}
pr_cont("\n");
}
}
static void show_extra_register_data(struct pt_regs *regs, int nbytes)
{
mm_segment_t fs;
fs = get_fs();
set_fs(KERNEL_DS);
show_data(regs->pc - nbytes, nbytes * 2, "PC");
show_data(regs->regs[30] - nbytes, nbytes * 2, "LR");
show_data(regs->sp - nbytes, nbytes * 2, "SP");
set_fs(fs);
}
void __show_regs(struct pt_regs *regs)
{
int i, top_reg;
@@ -274,8 +216,6 @@ void __show_regs(struct pt_regs *regs)
pr_cont("\n");
}
if (!user_mode(regs))
show_extra_register_data(regs, 64);
printk("\n");
}

5
arch/arm64/kernel/smp.c
View File

@@ -67,6 +67,8 @@
#define CREATE_TRACE_POINTS
#include <trace/events/ipi.h>
#include <linux/sec_debug.h>
DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number);
EXPORT_PER_CPU_SYMBOL(cpu_number);
@@ -831,6 +833,9 @@ static void ipi_cpu_stop(unsigned int cpu, struct pt_regs *regs)
__show_regs(regs);
dump_stack();
dump_stack_minidump(regs->sp);
#ifdef CONFIG_SEC_DEBUG
sec_debug_save_context();
#endif
raw_spin_unlock(&stop_lock);
}

98
arch/arm64/kernel/traps.c
View File

@@ -53,6 +53,10 @@
#include <asm/sysreg.h>
#include <trace/events/exception.h>
#ifdef CONFIG_SEC_DEBUG
#include <linux/sec_debug.h>
#endif
static const char *handler[]= {
"Synchronous Abort",
"IRQ",
@@ -62,6 +66,57 @@ static const char *handler[]= {
int show_unhandled_signals = 0;
#ifdef CONFIG_SEC_DEBUG
/*
* Dump out the contents of some kernel memory nicely...
*/
static void dump_mem(const char *lvl, const char *str, unsigned long bottom,
unsigned long top)
{
unsigned long first;
mm_segment_t fs;
int i;
/*
* We need to switch to kernel mode so that we can use __get_user
* to safely read from kernel space.
*/
fs = get_fs();
set_fs(KERNEL_DS);
printk("%s%s(0x%016lx to 0x%016lx)\n", lvl, str, bottom, top);
if (!IS_ENABLED(CONFIG_SEC_DEBUG_DUMP_TASK_STACK)) {
pr_warn("CONFIG_SEC_DEBUG_DUMP_TASK_STACK is not enabled!\n");
goto done;
}
for (first = bottom & ~31; first < top; first += 32) {
unsigned long p;
char str[sizeof(" 12345678") * 8 + 1];
memset(str, ' ', sizeof(str));
str[sizeof(str) - 1] = '\0';
for (p = first, i = 0; i < (32 / 8)
&& p < top; i++, p += 8) {
if (p >= bottom && p < top) {
unsigned long val;
if (__get_user(val, (unsigned long *)p) == 0)
sprintf(str + i * 17, " %016lx", val);
else
sprintf(str + i * 17, " ????????????????");
}
}
printk("%s%04lx:%s\n", lvl, first & 0xffff, str);
}
done:
set_fs(fs);
}
#endif
static void dump_backtrace_entry(unsigned long where)
{
printk(" %pS\n", (void *)where);
@@ -108,6 +163,10 @@ void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
unsigned long cur_sp = 0;
unsigned long cur_fp = 0;
#ifdef CONFIG_SEC_DEBUG
unsigned long prev_fp = 0;
#endif
pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
if (regs) {
@@ -172,6 +231,20 @@ void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
*/
dump_backtrace_entry(regs->pc);
}
#ifdef CONFIG_SEC_DEBUG
if (prev_fp >= frame.fp) {
if (on_accessible_stack(tsk, frame.fp)) {
printk("FP looks invalid : "
"0x%016lx state(0x%016lx) "
"on_cpu(%d)@cpu%u\n",
frame.fp, tsk->state,
tsk->on_cpu, tsk->cpu);
}
break;
}
prev_fp = frame.fp;
#endif
} while (!unwind_frame(tsk, &frame));
put_task_stack(tsk);
@@ -210,8 +283,23 @@ static int __die(const char *str, int err, struct pt_regs *regs)
end_of_stack(tsk));
show_regs(regs);
if (!user_mode(regs))
if (!user_mode(regs)) {
#ifdef CONFIG_SEC_DEBUG
unsigned long bottom = regs->sp;
if (!object_is_on_stack((void *)bottom)) {
unsigned long irq_stack =
(unsigned long)this_cpu_read(irq_stack_ptr);
if ((irq_stack <= bottom) &&
(bottom < irq_stack + IRQ_STACK_SIZE))
dump_mem(KERN_EMERG, "Stack: ", bottom,
irq_stack + IRQ_STACK_SIZE);
bottom = (unsigned long)task_stack_page(tsk);
}
dump_mem(KERN_EMERG, "Stack: ", bottom,
THREAD_SIZE + (unsigned long)task_stack_page(tsk));
#endif
dump_instr(KERN_EMERG, regs);
}
return ret;
}
@@ -230,6 +318,9 @@ void die(const char *str, struct pt_regs *regs, int err)
oops_enter();
sec_debug_sched_msg("!!die!!");
sec_debug_summary_save_die_info(str, regs);
console_verbose();
bust_spinlocks(1);
ret = __die(str, err, regs);
@@ -738,6 +829,11 @@ asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
{
console_verbose();
#ifdef CONFIG_SEC_USER_RESET_DEBUG
sec_debug_save_badmode_info(reason, handler[reason],
esr, esr_get_class_string(esr));
#endif
pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
handler[reason], smp_processor_id(), esr,
esr_get_class_string(esr));

54
arch/arm64/kernel/uh_entry.S Normal file
View File

@@ -0,0 +1,54 @@
#include <linux/linkage.h>
#include <linux/uh.h>
ENTRY(uh_call)
stp x1, x0, [sp, #-16]!
stp x3, x2, [sp, #-16]!
stp x5, x4, [sp, #-16]!
stp x7, x6, [sp, #-16]!
stp x9, x8, [sp, #-16]!
stp x11, x10, [sp, #-16]!
stp x13, x12, [sp, #-16]!
stp x15, x14, [sp, #-16]!
#ifdef CONFIG_RKP_CFP_ROPP
stp xzr, x16, [sp, #-16]!
#else
stp x17, x16, [sp, #-16]!
#endif
stp x19, x18, [sp, #-16]!
stp x21, x20, [sp, #-16]!
stp x23, x22, [sp, #-16]!
stp x25, x24, [sp, #-16]!
stp x27, x26, [sp, #-16]!
stp x29, x28, [sp, #-16]!
stp xzr, x30, [sp, #-16]!
back:
smc #0x0
cmp x0, #0x1
b.eq back
ldp xzr, x30, [sp], #16
ldp x29, x28, [sp], #16
ldp x27, x26, [sp], #16
ldp x25, x24, [sp], #16
ldp x23, x22, [sp], #16
ldp x21, x20, [sp], #16
ldp x19, x18, [sp], #16
#ifdef CONFIG_RKP_CFP_ROPP
ldp xzr, x16, [sp], #16
#else
ldp x17, x16, [sp], #16
#endif
ldp x15, x14, [sp], #16
ldp x13, x12, [sp], #16
ldp x11, x10, [sp], #16
ldp x9, x8, [sp], #16
ldp x7, x6, [sp], #16
ldp x5, x4, [sp], #16
ldp x3, x2, [sp], #16
ldp x1, x0, [sp], #16
ret
ENDPROC(uh_call)

4
arch/arm64/kernel/vmlinux.lds.S
View File

@@ -232,6 +232,7 @@ SECTIONS
BSS_SECTION(0, 0, 0)
. = ALIGN(PAGE_SIZE);
#ifndef CONFIG_UH_RKP
idmap_pg_dir = .;
. += IDMAP_DIR_SIZE;
swapper_pg_dir = .;
@@ -245,6 +246,7 @@ SECTIONS
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
tramp_pg_dir = .;
. += PAGE_SIZE;
#endif
#endif
__pecoff_data_size = ABSOLUTE(. - __initdata_begin);
@@ -272,7 +274,7 @@ ASSERT(__hibernate_exit_text_end - (__hibernate_exit_text_start & ~(SZ_4K - 1))
<= SZ_4K, "Hibernate exit text too big or misaligned")
#endif
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
ASSERT((__entry_tramp_text_end - __entry_tramp_text_start) <= 3*PAGE_SIZE,
ASSERT((__entry_tramp_text_end - __entry_tramp_text_start) == PAGE_SIZE,
"Entry trampoline text too big")
#endif
/*

4
arch/arm64/kvm/hyp/hyp-entry.S
View File

@@ -111,10 +111,6 @@ el1_hvc_guest:
/* ARM_SMCCC_ARCH_WORKAROUND_2 handling */
eor w1, w1, #(ARM_SMCCC_ARCH_WORKAROUND_1 ^ \
ARM_SMCCC_ARCH_WORKAROUND_2)
cbz w1, wa_epilogue
eor w1, w1, #(ARM_SMCCC_ARCH_WORKAROUND_2 ^ \
ARM_SMCCC_ARCH_WORKAROUND_3)
cbnz w1, el1_trap
#ifdef CONFIG_ARM64_SSBD

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