Evolution-X-Devices/kernel_xiaomi_mt6781
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

thermal: Import Xiaomi changes

Browse Source 
Signed-off-by: claxten10 <claxten10@gmail.com>
This commit is contained in:
claxten10
2024-11-09 21:10:02 +00:00
committed by nisel
parent ed2cb9ab33
commit 94ad0ad661
187 changed files with 2839 additions and 59014 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/misc/mediatek/thermal/Makefile
View File

@@ -47,13 +47,16 @@ ccflags-y += -I$(srctree)/drivers/gpu/mediatek/gpufreq/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/$(PDIR)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/include/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/include/gpufreq_v1/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/flashlight/
obj-y += mtk_thermal_monitor.o
obj-y += mtk_cooler_shutdown.o
ifeq ($(CONFIG_MTK_LEDS), y)
# setMaxbrightness() defined in mediatek/kernel/drivers/leds/leds_drv.c only built when CONFIG_MTK_LEDS is set
obj-y += mtk_cooler_backlight.o
# obj-y += mtk_cooler_backlight.o
obj-y += mtk_cooler_backlight_cus.o
endif
obj-y += mtk_cooler_flashlight_cus.o
obj-y += mtk_cooler_kshutdown.o
obj-y += mtk_cooler_cam.o

12
drivers/misc/mediatek/thermal/common/coolers/Makefile
View File

@@ -38,6 +38,7 @@ ccflags-y += -I$(srctree)/drivers/misc/mediatek/include/mt-plat/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/thermal/fakeHeader/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/include/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/ppm_v3/src/mach/$(PDIR)
ccflags-y += -I$(srctree)/drivers/power/supply/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/video/include
ccflags-y += -I$(srctree)/drivers/misc/mediatek/gpu/ged/include
ccflags-y += -I$(srctree)/drivers/misc/mediatek/thermal/common/inc/
@@ -92,6 +93,7 @@ obj-$(CONFIG_THERMAL) += mtk_cooler_bcct_v1.o
ifeq ($(CONFIG_MTK_DUAL_CHARGER_SUPPORT),y)
obj-$(CONFIG_THERMAL) += mtk_cooler_bcct_2nd.o
endif
obj-$(CONFIG_THERMAL) += mtk_cooler_atm.o
obj-$(CONFIG_THERMAL) += mtk_cooler_dtm.o
obj-$(CONFIG_THERMAL) += mtk_cooler_sysrst.o
@@ -108,13 +110,14 @@ endif
ccflags-y += -I$(srctree)/drivers/gpu/mediatek/mt-plat/
obj-$(CONFIG_THERMAL) += mtk_cooler_bcct_v1.o
obj-$(CONFIG_THERMAL) += mtk_cooler_bcct_2nd.o
obj-$(CONFIG_THERMAL) += mtk_cooler_atm.o
obj-$(CONFIG_THERMAL) += mtk_cooler_dtm.o
obj-$(CONFIG_THERMAL) += mtk_cooler_sysrst.o
obj-$(CONFIG_THERMAL) += mtk_cooler_VR_FPS.o
endif
ifneq (,$(filter $(CONFIG_MTK_PLATFORM), "mt6785"))
ifneq (,$(filter $(CONFIG_MTK_PLATFORM), "mt6785" "mt6781"))
ifeq ($(CONFIG_MTK_THERMAL_PA_VIA_ATCMD),y)
obj-$(CONFIG_THERMAL) += mtk_cooler_mutt.o
endif
@@ -123,6 +126,12 @@ ccflags-y += -I$(srctree)/drivers/gpu/mediatek/mt-plat/
obj-$(CONFIG_THERMAL) += mtk_cooler_bcct_v2.o
obj-$(CONFIG_THERMAL) += mtk_cooler_bcct_2nd.o
obj-$(CONFIG_THERMAL) += mtk_cooler_gpu_cus.o
ifeq ($(CONFIG_MTK_VPU_SUPPORT),y)
obj-$(CONFIG_THERMAL) += mtk_cooler_vpu_cus.o
endif
obj-$(CONFIG_THERMAL) += mtk_cooler_char_curr_cus.o
obj-$(CONFIG_THERMAL) += mtk_cooler_atm.o
obj-$(CONFIG_THERMAL) += mtk_cooler_dtm.o
obj-$(CONFIG_THERMAL) += mtk_cooler_sysrst.o
@@ -137,7 +146,6 @@ endif
obj-$(CONFIG_THERMAL) += mtk_cooler_bcct_v1.o
obj-$(CONFIG_THERMAL) += mtk_cooler_bcct_2nd.o
obj-$(CONFIG_THERMAL) += mtk_cooler_atm.o
obj-$(CONFIG_THERMAL) += mtk_cooler_dtm.o
obj-$(CONFIG_THERMAL) += mtk_cooler_sysrst.o

66
drivers/misc/mediatek/thermal/common/coolers/mtk_cooler_atm.c
View File

@@ -3851,6 +3851,71 @@ static int krtatm_thread(void *arg)
}
#endif /* FAST_RESPONSE_ATM */
static void init_ctm_param(void)
{
int t_K_SUM_TT_HIGH = CLCTM_TT_HIGH;
int t_K_SUM_TT_LOW = CLCTM_TT_LOW;
int t_CATMP_STEADY_TTJ_DELTA = CLCTM_STEADY_TTJ_DELTA;
ctm_on = CLATM_INIT_CFG_CATM; /* 2: cATM+, 1: cATMv1, 0: off */
MAX_TARGET_TJ = CLCTM_TARGET_TJ;
STEADY_TARGET_TJ = CLCTM_TARGET_TJ;
TRIP_TPCB = CLCTM_TPCB_1;
STEADY_TARGET_TPCB = CLCTM_TPCB_2;
MAX_EXIT_TJ = CLCTM_EXIT_TJ;
STEADY_EXIT_TJ = CLCTM_EXIT_TJ;
COEF_AE = CLCTM_AE;
COEF_BE = CLCTM_BE;
COEF_AX = CLCTM_AX;
COEF_BX = CLCTM_BX;
#if defined(CATM_TPCB_EXTEND)
if (g_turbo_bin && (STEADY_TARGET_TPCB >= 52000)) {
if (t_TPCB_EXTEND > 0 && t_TPCB_EXTEND < 10000) {
TRIP_TPCB += t_TPCB_EXTEND;
STEADY_TARGET_TPCB += t_TPCB_EXTEND;
COEF_AE = STEADY_TARGET_TJ +
(STEADY_TARGET_TPCB * COEF_BE) / 1000;
COEF_AX = STEADY_EXIT_TJ +
(STEADY_TARGET_TPCB * COEF_BX) / 1000;
TPCB_EXTEND = t_TPCB_EXTEND;
}
}
#endif
/* +++ cATM+ parameters +++ */
if (ctm_on == 2) {
if (t_K_SUM_TT_HIGH >= 0
&& t_K_SUM_TT_HIGH < MAX_K_SUM_TT)
K_SUM_TT_HIGH = t_K_SUM_TT_HIGH;
if (t_K_SUM_TT_LOW >= 0
&& t_K_SUM_TT_LOW < MAX_K_SUM_TT)
K_SUM_TT_LOW = t_K_SUM_TT_LOW;
if (t_CATMP_STEADY_TTJ_DELTA >= 0)
CATMP_STEADY_TTJ_DELTA =
t_CATMP_STEADY_TTJ_DELTA;
catmplus_update_params();
}
/* --- cATM+ parameters --- */
/* --- SPA parameters --- */
thermal_spa_t.t_spa_Tpolicy_info.steady_target_tj =
STEADY_TARGET_TJ;
thermal_spa_t.t_spa_Tpolicy_info.steady_exit_tj =
STEADY_EXIT_TJ;
#ifdef CONFIG_MTK_TINYSYS_SSPM_SUPPORT
#if THERMAL_ENABLE_TINYSYS_SSPM && CPT_ADAPTIVE_AP_COOLER && \
PRECISE_HYBRID_POWER_BUDGET && CONTINUOUS_TM
atm_update_catm_param_to_sspm();
#endif
#endif
}
static int __init mtk_cooler_atm_init(void)
{
int err = 0;
@@ -3923,6 +3988,7 @@ static int __init mtk_cooler_atm_init(void)
#if 0
reset_gpu_power_history();
#endif
init_ctm_param();
tscpu_dprintk("%s: end\n", __func__);
return 0;
}

333
drivers/misc/mediatek/thermal/common/coolers/mtk_cooler_char_curr_cus.c Normal file
View File

@@ -0,0 +1,333 @@
/*
* Copyright (C) 2019 MediaTek Inc.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifdef pr_fmt
#undef pr_fmt
#endif
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/printk.h>
#include <linux/proc_fs.h>
#include <linux/types.h>
#include <linux/kobject.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#if (CONFIG_MTK_GAUGE_VERSION == 30)
#include <mt-plat/v1/charger_type.h>
#include <mt-plat/v1/mtk_charger.h>
#include <mt-plat/v1/mtk_battery.h>
#else
#include <tmp_battery.h>
#include <charging.h>
#endif
#if (CONFIG_MTK_GAUGE_VERSION == 30)
static struct charger_consumer *thm_chr_consumer;
#endif
/*#define CHAR_CURR_INTERVAL 200 interval 200mA */
#define CHAR_CURR_TABLE_INDEX 16
#define mtk_cooler_char_curr_dprintk(fmt, args...) \
pr_notice("thermal/cooler/char_curr " fmt, ##args)
static struct thermal_cooling_device
*cl_char_curr_dev = { 0 };
static unsigned int g_cl_id;
static unsigned int g_char_curr_level;
static unsigned int g_thm_en_charging;
static unsigned int max_char_curr_index;
/* char_curr_t = charging current table
* -1 : unlimit charging current
* 0 : stop charging
* positive integer: charging current limit (unit: mA)
*/
static int char_curr_t[CHAR_CURR_TABLE_INDEX] = {
-1, 2800, 2600, 2400, 2200,
2000, 1800, 1600, 1400, 1200,
1000, 800, 600, 400, 200,
0
};
static int _cl_char_curr_read(struct seq_file *m, void *v)
{
int i = 0;
mtk_cooler_char_curr_dprintk("%s\n", __func__);
seq_printf(m, "charger_current state=%d max=%d\n",
g_char_curr_level, max_char_curr_index);
seq_puts(m, "[index, current]\n");
for (i = 0; i < max_char_curr_index; i++)
seq_printf(m, "(%4d, %4d)\n", i, char_curr_t[i]);
return 0;
}
static int _cl_char_curr_open(struct inode *inode, struct file *file)
{
return single_open(file, _cl_char_curr_read, PDE_DATA(inode));
}
static const struct file_operations _cl_char_curr_fops = {
.owner = THIS_MODULE,
.open = _cl_char_curr_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int mtk_cl_char_curr_get_max_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = max_char_curr_index - 1;
return 0;
}
static int mtk_cl_char_curr_get_cur_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = g_char_curr_level;
return 0;
}
static int mtk_cl_char_curr_set_cur_state
(struct thermal_cooling_device *cdev, unsigned long state)
{
int chr_input_curr_limit = 0;
#if (CONFIG_MTK_GAUGE_VERSION == 30)
if (state >= max_char_curr_index || state < 0) {
mtk_cooler_char_curr_dprintk("%s: wrong state=%d %d\n",
__func__, (int)state, max_char_curr_index);
} else {
g_char_curr_level = state;
if (g_char_curr_level == 0) {
chr_input_curr_limit = -1;/* unlimit input current*/
} else {
chr_input_curr_limit =
char_curr_t[g_char_curr_level] * 1000;
}
if (chr_input_curr_limit != 0) {
charger_manager_set_input_current_limit(
thm_chr_consumer, 0, chr_input_curr_limit);
mtk_cooler_char_curr_dprintk("%s: l=%d curr=%d\n",
__func__, g_char_curr_level,
chr_input_curr_limit);
if (g_thm_en_charging == 0) {
g_thm_en_charging = 1;
charger_manager_enable_power_path(
thm_chr_consumer, 0,
g_thm_en_charging);
mtk_cooler_char_curr_dprintk(
"%s: en_charging = %d\n",
__func__, g_thm_en_charging);
}
} else if (chr_input_curr_limit == 0 && g_thm_en_charging) {
g_thm_en_charging = 0;
charger_manager_enable_power_path(thm_chr_consumer, 0,
g_thm_en_charging);
}
}
#endif
return 0;
}
#if 0
static int update_char_curr_table(void)
{
int input_curr = 0, ret = 0, curr_opp, i;
#if 0
mutex_lock(thm_chr_mutex);
ret = charger_manager_get_input_current_limit(
thm_chr_consumer, 0, &input_curr);
mtk_cooler_char_curr_dprintk("%d\n", input_curr);
input_curr /= 1000;/*uA to mA*/
if (!ret) {
max_char_curr_index = 0;
memset(char_curr_t, 0, sizeof(char_curr_t));
curr_opp = input_curr;
for (i = 0; curr_opp > 0; i++) {
max_char_curr_index = i;
char_curr_t[i] = curr_opp;
curr_opp -= CHAR_CURR_INTERVAL;
if (i == CHAR_CURR_TABLE_INDEX - 2) {
i++;
break;
}
}
max_char_curr_index = i;
char_curr_t[i] = 0;
} else {
max_char_curr_index = 0;
memset(char_curr_t, 0, sizeof(char_curr_t));
mtk_cooler_char_curr_dprintk(
"%s: can't get intput current ret = %d\n",
__func__, ret);
}
mutex_unlock(thm_chr_mutex);
#else
char_curr_t[0] = -1;/* max current */
for (i = 0; i < CHAR_CURR_TABLE_INDEX - 1; i++)
char_curr_t[CHAR_CURR_TABLE_INDEX - i - 1] =
i * CHAR_CURR_INTERVAL;
#endif
return ret;
}
#endif
#if 0
static int mtk_cl_char_curr_get_available
(struct thermal_cooling_device *cdev, char *available)
{
int len = 0, i;
for (i = 0; i < max_char_curr_index; i++)
len += snprintf(available + len, 20, "%d %d\n",
i, char_curr_t[i]);
mtk_cooler_char_curr_dprintk("%s\n", available);
return 0;
}
#endif
#if (CONFIG_MTK_GAUGE_VERSION == 30)
static int mtkcooler_char_curr_pdrv_probe(struct platform_device *pdev)
{
mtk_cooler_char_curr_dprintk("%s\n", __func__);
thm_chr_consumer = charger_manager_get_by_name(&pdev->dev, "charger");
return 0;
}
static int mtkcooler_char_curr_pdrv_remove(struct platform_device *pdev)
{
return 0;
}
struct platform_device mtk_cooler_char_curr_device = {
.name = "mtk-cooler-char_curr",
.id = -1,
};
static struct platform_driver mtk_cooler_char_curr_driver = {
.probe = mtkcooler_char_curr_pdrv_probe,
.remove = mtkcooler_char_curr_pdrv_remove,
.driver = {
.name = "mtk-cooler-char_curr",
.owner = THIS_MODULE,
},
};
static int __init mtkcooler_char_curr_late_init(void)
{
int ret = 0;
/* register platform device/driver */
ret = platform_device_register(&mtk_cooler_char_curr_device);
if (ret) {
mtk_cooler_char_curr_dprintk(
"fail to register device @ %s()\n",
__func__);
goto fail;
}
ret = platform_driver_register(&mtk_cooler_char_curr_driver);
if (ret) {
mtk_cooler_char_curr_dprintk(
"fail to register driver @ %s()\n",
__func__);
goto reg_platform_driver_fail;
}
return ret;
reg_platform_driver_fail:
platform_device_unregister(&mtk_cooler_char_curr_device);
fail:
return ret;
}
#endif
static struct thermal_cooling_device_ops mtk_cl_char_curr_ops = {
.get_max_state = mtk_cl_char_curr_get_max_state,
.get_cur_state = mtk_cl_char_curr_get_cur_state,
.set_cur_state = mtk_cl_char_curr_set_cur_state,
//.get_available = mtk_cl_char_curr_get_available,
};
static int mtk_cooler_char_curr_register_ltf(void)
{
mtk_cooler_char_curr_dprintk("%s\n", __func__);
g_cl_id = 0;
cl_char_curr_dev = mtk_thermal_cooling_device_register
("mtk-cl-char_curr", (void *)&g_cl_id,
&mtk_cl_char_curr_ops);
return 0;
}
static void mtk_cooler_char_curr_unregister_ltf(void)
{
mtk_cooler_char_curr_dprintk("%s\n", __func__);
if (cl_char_curr_dev) {
mtk_thermal_cooling_device_unregister(cl_char_curr_dev);
cl_char_curr_dev = NULL;
}
}
static int __init mtk_cooler_char_curr_init(void)
{
int err = 0;
err = mtk_cooler_char_curr_register_ltf();
if (err)
goto err_unreg;
proc_create("thm_char_curr", 0444, NULL, &_cl_char_curr_fops);
max_char_curr_index = CHAR_CURR_TABLE_INDEX;
g_thm_en_charging = 1;
return 0;
err_unreg:
mtk_cooler_char_curr_unregister_ltf();
return err;
}
static void __exit mtk_cooler_char_curr_exit(void)
{
mtk_cooler_char_curr_unregister_ltf();
}
module_init(mtk_cooler_char_curr_init);
module_exit(mtk_cooler_char_curr_exit);
#if (CONFIG_MTK_GAUGE_VERSION == 30)
late_initcall(mtkcooler_char_curr_late_init);
#endif

145
drivers/misc/mediatek/thermal/common/coolers/mtk_cooler_gpu_cus.c Normal file
View File

@@ -0,0 +1,145 @@
/*
* Copyright (C) 2019 MediaTek Inc.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifdef pr_fmt
#undef pr_fmt
#endif
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/printk.h>
#include <linux/types.h>
#include <linux/kobject.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include <tscpu_settings.h>
#include "mtk_gpufreq.h"
#define mtk_cooler_gpu_dprintk(fmt, args...) \
pr_notice("thermal/cooler/gpu " fmt, ##args)
static struct thermal_cooling_device
*cl_gpu_dev = { 0 };
static unsigned int g_cl_id;
static unsigned int g_gpu_level;
static int mtk_cl_gpu_get_max_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = Num_of_GPU_OPP - gpu_max_opp - 1;
return 0;
}
static int mtk_cl_gpu_get_cur_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = g_gpu_level;
return 0;
}
static int mtk_cl_gpu_set_cur_state
(struct thermal_cooling_device *cdev, unsigned long state)
{
if (mtk_gpu_power != NULL && state >= 0 && state < Num_of_GPU_OPP - gpu_max_opp) {
g_gpu_level = state;
if (g_gpu_level == 0)
mtk_cooler_gpu_dprintk("%d\n", g_gpu_level);
else {
mtk_cooler_gpu_dprintk("%d %d %d\n", g_gpu_level,
mtk_gpu_power[g_gpu_level + gpu_max_opp].gpufreq_khz,
mtk_gpu_power[g_gpu_level + gpu_max_opp].gpufreq_power);
}
mt_gpufreq_thermal_protect((g_gpu_level == 0) ? 0 :
mtk_gpu_power[g_gpu_level + gpu_max_opp].gpufreq_power);
} else {
mtk_cooler_gpu_dprintk("%s: mtk_gpu_power_table=%p, state=%lu, GPU_OPP=%d\n",
__func__, mtk_gpu_power, state, Num_of_GPU_OPP - gpu_max_opp);
}
return 0;
}
#if 0
static int mtk_cl_gpu_get_available
(struct thermal_cooling_device *cdev, char *available)
{
int i = 0, len = 0;
if (mtk_gpu_power != NULL) {
for (i = 0; i < Num_of_GPU_OPP - gpu_max_opp; i++) {
len += snprintf(available+len, 256, "%d %u %u\n", i, mtk_gpu_power[i + gpu_max_opp].gpufreq_khz, mtk_gpu_power[i+gpu_max_opp].gpufreq_power);
mtk_cooler_gpu_dprintk("len=%d\n", len);
mtk_cooler_gpu_dprintk("%u %u\n", mtk_gpu_power[i + gpu_max_opp].gpufreq_khz, mtk_gpu_power[i + gpu_max_opp].gpufreq_power);
}
} else
mtk_cooler_gpu_dprintk("%s: not gpu_power table\n", __func__);
return 0;
}
#endif
/* bind fan callbacks to fan device */
static struct thermal_cooling_device_ops mtk_cl_gpu_ops = {
.get_max_state = mtk_cl_gpu_get_max_state,
.get_cur_state = mtk_cl_gpu_get_cur_state,
.set_cur_state = mtk_cl_gpu_set_cur_state,
//.get_available = mtk_cl_gpu_get_available,
};
static int mtk_cooler_gpu_register_ltf(void)
{
mtk_cooler_gpu_dprintk("%s\n", __func__);
g_cl_id = 0;
cl_gpu_dev = mtk_thermal_cooling_device_register
("mtk-cl-gpu", (void *)&g_cl_id,
&mtk_cl_gpu_ops);
return 0;
}
static void mtk_cooler_gpu_unregister_ltf(void)
{
mtk_cooler_gpu_dprintk("%s\n", __func__);
if (cl_gpu_dev) {
mtk_thermal_cooling_device_unregister(cl_gpu_dev);
cl_gpu_dev = NULL;
}
}
static int __init mtk_cooler_gpu_init(void)
{
int err = 0;
err = mtk_cooler_gpu_register_ltf();
if (err)
goto err_unreg;
return 0;
err_unreg:
mtk_cooler_gpu_unregister_ltf();
return err;
}
static void __exit mtk_cooler_gpu_exit(void)
{
mtk_cooler_gpu_unregister_ltf();
}
module_init(mtk_cooler_gpu_init);
module_exit(mtk_cooler_gpu_exit);

138
drivers/misc/mediatek/thermal/common/coolers/mtk_cooler_vpu_cus.c Normal file
View File

@@ -0,0 +1,138 @@
/*
* Copyright (C) 2019 MediaTek Inc.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifdef pr_fmt
#undef pr_fmt
#endif
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/printk.h>
#include <linux/types.h>
#include <linux/kobject.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include <tscpu_settings.h>
#include "vpu_dvfs.h"
#define mtk_cooler_vpu_dprintk(fmt, args...) \
pr_notice("thermal/cooler/vpu " fmt, ##args)
static struct thermal_cooling_device
*cl_vpu_dev = { 0 };
static unsigned int g_cl_id;
static unsigned int g_vpu_level;
static int mtk_cl_vpu_get_max_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
mtk_cooler_vpu_dprintk("%s\n", __func__);
*state = VPU_OPP_NUM - 1;
return 0;
}
static int mtk_cl_vpu_get_cur_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
mtk_cooler_vpu_dprintk("%s\n", __func__);
*state = g_vpu_level;
return 0;
}
static int mtk_cl_vpu_set_cur_state
(struct thermal_cooling_device *cdev, unsigned long state)
{
if (g_vpu_opp_table != NULL) {
if (state >= 0 && state < VPU_OPP_NUM)
g_vpu_level = state;
if (g_vpu_level != 0)
vpu_thermal_en_throttle_cb(0xff, g_vpu_level);
else
vpu_thermal_dis_throttle_cb();
} else
mtk_cooler_vpu_dprintk(
"%s: vpu_power table = NULL\n", __func__);
return 0;
}
#if 0
static int mtk_cl_vpu_get_available
(struct thermal_cooling_device *cdev, char *available)
{
int i = 0, len = 0;
if (g_vpu_opp_table != NULL) {
for (i = 0; i < VPU_OPP_NUM; i++)
len += snprintf(available+len, 256, "%d %d\n",
i, g_vpu_opp_table[i]);
} else
mtk_cooler_vpu_dprintk(
"%s: vpu_power table = NULL\n", __func__);
return 0;
}
#endif
/* bind fan callbacks to fan device */
static struct thermal_cooling_device_ops mtk_cl_vpu_ops = {
.get_max_state = mtk_cl_vpu_get_max_state,
.get_cur_state = mtk_cl_vpu_get_cur_state,
.set_cur_state = mtk_cl_vpu_set_cur_state,
//.get_available = mtk_cl_vpu_get_available,
};
static int mtk_cooler_vpu_register_ltf(void)
{
mtk_cooler_vpu_dprintk("%s\n", __func__);
g_cl_id = 0;
cl_vpu_dev = mtk_thermal_cooling_device_register
("mtk-cl-vpu", (void *)&g_cl_id,
&mtk_cl_vpu_ops);
return 0;
}
static void mtk_cooler_vpu_unregister_ltf(void)
{
if (cl_vpu_dev) {
mtk_thermal_cooling_device_unregister(cl_vpu_dev);
cl_vpu_dev = NULL;
}
}
static int __init mtk_cooler_vpu_init(void)
{
int err = 0;
err = mtk_cooler_vpu_register_ltf();
if (err)
goto err_unreg;
return 0;
err_unreg:
mtk_cooler_vpu_unregister_ltf();
return err;
}
static void __exit mtk_cooler_vpu_exit(void)
{
mtk_cooler_vpu_unregister_ltf();
}
module_init(mtk_cooler_vpu_init);
module_exit(mtk_cooler_vpu_exit);

2
drivers/misc/mediatek/thermal/common/coolers/mtk_ta.c
View File

@@ -522,7 +522,7 @@ static int __init ta_init(void)
g_tad_pid = 0;
init_flag = false;
g_tad_ttj = 0;
g_tad_ttj = CLCTM_TARGET_TJ;
g_ta_status = 0;
/*add by willcai for the userspace to kernelspace*/

2
drivers/misc/mediatek/thermal/common/thermal_zones/mtk_ts_battery.c
View File

@@ -423,7 +423,7 @@ struct thermal_cooling_device *cdev, unsigned long state)
/* To trigger data abort to reset the system
* for thermal protection.
*/
BUG();
//BUG();
}
return 0;
}

1425
drivers/misc/mediatek/thermal/common/thermal_zones/mtk_ts_blk_ntc.c Normal file
View File

File diff suppressed because it is too large Load Diff

6
drivers/misc/mediatek/thermal/common/thermal_zones/mtk_ts_bts.c
View File

@@ -60,7 +60,7 @@ static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static int trip_temp[10] = { 120000, 110000, 100000, 90000, 80000,
static int trip_temp[10] = { 100000, 96000, 95000, 90000, 80000,
70000, 65000, 60000, 55000, 50000 };
static struct thermal_zone_device *thz_dev;
@@ -68,8 +68,8 @@ static int mtkts_bts_debug_log;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip;
static char g_bind0[20] = {"mtktsAP-sysrst"};
static int num_trip = 1;
static char g_bind0[20] = "mtktsAP-sysrst";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };

4
drivers/misc/mediatek/thermal/common/thermal_zones/mtk_ts_btsmdpa.c
View File

@@ -62,8 +62,8 @@ static int mtkts_btsmdpa_debug_log;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip;
static char g_bind0[20] = {"mtk-cl-shutdown02"};
static int num_trip = 1;
static char g_bind0[20] = "mtk-cl-shutdown02";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };

4
drivers/misc/mediatek/thermal/common/thermal_zones/mtk_ts_charger.c
View File

@@ -43,9 +43,9 @@ static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int kernelmode;
static unsigned int interval; /* seconds, 0 : no auto polling */
static unsigned int interval = 2; /* seconds, 0 : no auto polling */
static int num_trip = 1;
static int trip_temp[10] = { 125000, 110000, 100000, 90000, 80000,
static int trip_temp[10] = { 120000, 110000, 100000, 90000, 80000,
70000, 65000, 60000, 55000, 50000 };
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };

2
drivers/misc/mediatek/thermal/common/thermal_zones/mtk_ts_cpu_noBank.c
View File

@@ -415,7 +415,7 @@ int mtk_gpufreq_register(struct mt_gpufreq_power_table_info *freqs, int num)
mtk_gpu_power[i].gpufreq_khz = freqs[i].gpufreq_khz;
mtk_gpu_power[i].gpufreq_power = freqs[i].gpufreq_power;
tscpu_dprintk("[%d].gpufreq_khz=%u, .gpufreq_power=%u\n",
tscpu_printk("[%d].gpufreq_khz=%u, .gpufreq_power=%u\n",
i, freqs[i].gpufreq_khz, freqs[i].gpufreq_power);
}

14
drivers/misc/mediatek/thermal/common/thermal_zones/mtk_ts_pa.c
View File

@@ -40,8 +40,8 @@ static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int isTimerCancelled;
static unsigned int interval; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 85000, 80000, 70000, 60000, 50000,
static unsigned int interval = 2; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 120000, 80000, 70000, 60000, 50000,
40000, 30000, 20000, 10000, 5000 };
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
@@ -52,7 +52,7 @@ static struct thermal_cooling_device *cl_dev_sysrst;
static int mtktspa_debug_log;
static int kernelmode;
static int num_trip;
static int num_trip = 1;
static char g_bind0[20] = "mtktspa-sysrst";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
@@ -193,10 +193,10 @@ static void pa_cal_stats(struct timer_list *t)
*struct md_info g_pinfo_list[] =
*{{"TXPWR_MD1", -127, "db", -127, 0},
* {"TXPWR_MD2", -127, "db", -127, 1},
* {"RFTEMP_2G_MD1", -32767, "¢XC", -32767, 2},
* {"RFTEMP_2G_MD2", -32767, "¢XC", -32767, 3},
* {"RFTEMP_3G_MD1", -32767, "¢XC", -32767, 4},
* {"RFTEMP_3G_MD2", -32767, "¢XC", -32767, 5}};
* {"RFTEMP_2G_MD1", -32767, "<EFBFBD>XC", -32767, 2},
* {"RFTEMP_2G_MD2", -32767, "<EFBFBD>XC", -32767, 3},
* {"RFTEMP_3G_MD1", -32767, "<EFBFBD>XC", -32767, 4},
* {"RFTEMP_3G_MD2", -32767, "<EFBFBD>XC", -32767, 5}};
*/
static DEFINE_MUTEX(TSPA_lock);
static int mtktspa_get_hw_temp(void)

6
drivers/misc/mediatek/thermal/common/thermal_zones/mtk_ts_pmic.c
View File

@@ -46,7 +46,7 @@ static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 120000, 110000, 100000, 90000, 80000,
static unsigned int trip_temp[10] = { 136000, 110000, 100000, 90000, 80000,
70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
@@ -57,8 +57,8 @@ static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip;
static char g_bind0[20] = { 0 };
static int num_trip = 1;
static char g_bind0[20] = "mtktspmic-sysrst";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };

6
drivers/misc/mediatek/thermal/common/thermal_zones/mtk_ts_wmt.c
View File

@@ -116,8 +116,8 @@ static unsigned int tm_wfd_stat;
static struct task_struct *pg_task;
/* + Cooler info + */
static int g_num_trip;
static char g_bind0[20] = { 0 };
static int g_num_trip = 1;
static char g_bind0[20] = "mtktswmt-sysrst";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
@@ -142,7 +142,7 @@ static int polling_factor2 = 10;
static unsigned int cl_dev_state;
static unsigned int cl_pa1_dev_state;
static unsigned int cl_pa2_dev_state;
static unsigned int g_trip_temp[COOLER_NUM] = { 125000, 115000, 105000, 85000,
static unsigned int g_trip_temp[COOLER_NUM] = { 120000, 115000, 105000, 85000,
0, 0, 0, 0, 0, 0 };
/* static int g_thro[COOLER_THRO_NUM] =

14
drivers/misc/mediatek/thermal/mt6739/Makefile
View File

@@ -1,14 +0,0 @@
#
# Copyright (C) 2015 MediaTek Inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
obj-y += src/

56
drivers/misc/mediatek/thermal/mt6739/inc/clatm_initcfg.h
View File

@@ -1,56 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __CLATM_INITCFG_H__
#define __CLATM_INITCFG_H__
#define CLATM_SET_INIT_CFG (1)
#define CLATM_INIT_CFG_0_TARGET_TJ (75000)
#define CLATM_INIT_CFG_0_EXIT_POINT (10000)
#define CLATM_INIT_CFG_0_FIRST_STEP (2000)
#define CLATM_INIT_CFG_0_THETA_RISE (2)
#define CLATM_INIT_CFG_0_THETA_FALL (8)
#define CLATM_INIT_CFG_0_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_0_MIN_CPU_PWR (400)
#define CLATM_INIT_CFG_0_MAX_CPU_PWR (2000)
#define CLATM_INIT_CFG_0_MIN_GPU_PWR (200)
#define CLATM_INIT_CFG_0_MAX_GPU_PWR (700)
#define CLATM_INIT_CFG_1_TARGET_TJ (65000)
#define CLATM_INIT_CFG_1_EXIT_POINT (10000)
#define CLATM_INIT_CFG_1_FIRST_STEP (3000)
#define CLATM_INIT_CFG_1_THETA_RISE (2)
#define CLATM_INIT_CFG_1_THETA_FALL (8)
#define CLATM_INIT_CFG_1_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_1_MIN_CPU_PWR (300)
#define CLATM_INIT_CFG_1_MAX_CPU_PWR (3000)
#define CLATM_INIT_CFG_1_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_1_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_2_TARGET_TJ (75000)
#define CLATM_INIT_CFG_2_EXIT_POINT (10000)
#define CLATM_INIT_CFG_2_FIRST_STEP (3960)
#define CLATM_INIT_CFG_2_THETA_RISE (2)
#define CLATM_INIT_CFG_2_THETA_FALL (8)
#define CLATM_INIT_CFG_2_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_2_MIN_CPU_PWR (600)
#define CLATM_INIT_CFG_2_MAX_CPU_PWR (3960)
#define CLATM_INIT_CFG_2_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_2_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_ACTIVE_ATM_COOLER (0)
#define CLATM_INIT_CFG_CATM (0)
#define CLATM_INIT_CFG_PHPB_CPU_TT (10)
#define CLATM_INIT_CFG_PHPB_CPU_TP (10)
#define CLATM_INIT_CFG_PHPB_GPU_TT (80)
#define CLATM_INIT_CFG_PHPB_GPU_TP (80)
#define CLATM_INIT_HRTIMER_POLLING_DELAY (100)
#define CLATM_USE_MIN_CPU_OPP (1)
#endif /* __CLATM_INITCFG_H__ */

29
drivers/misc/mediatek/thermal/mt6739/inc/mtk_cooler_setting.h
View File

@@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MTK_COOLER_SETTING_H
#define _MTK_COOLER_SETTING_H
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/* mtk_cooler_mutt.c */
/* 1: turn on MD throttle V2 cooler; 0: turn off */
#define FEATURE_MUTT_V2 (1)
/* mtk_cooler_mutt.c */
/* 1: turn on MD Thermal Warning Notification; 0: turn off */
#define FEATURE_THERMAL_DIAG (1)
/* mtk_cooler_mutt.c */
/* 1: turn on adaptive MD throttle cooler; 0: turn off */
#define FEATURE_ADAPTIVE_MUTT (1)
/* mtk_ta.c */
/* 1: turn on SPA; 0: turn off */
#define FEATURE_SPA (0)
#endif /* _MTK_COOLER_SETTING_H */

59
drivers/misc/mediatek/thermal/mt6739/inc/mtk_thermal_ipi.h
View File

@@ -1,59 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MTK_THERMAL_IPI_H__
#define __MTK_THERMAL_IPI_H__
#ifdef CONFIG_MTK_TINYSYS_SSPM_SUPPORT
#define THERMAL_ENABLE_TINYSYS_SSPM (0)
#else
#define THERMAL_ENABLE_TINYSYS_SSPM (0)
#endif
#if THERMAL_ENABLE_TINYSYS_SSPM
#include "sspm_ipi.h"
#include <sspm_reservedmem_define.h>
#define THERMAL_SLOT_NUM (4)
/* IPI Msg type */
enum {
THERMAL_IPI_INIT_GRP1,
THERMAL_IPI_INIT_GRP2,
THERMAL_IPI_INIT_GRP3,
THERMAL_IPI_INIT_GRP4,
THERMAL_IPI_INIT_GRP5,
THERMAL_IPI_INIT_GRP6,
THERMAL_IPI_GET_TEMP,
THERMAL_IPI_SET_ATM_CFG_GRP1,
THERMAL_IPI_SET_ATM_CFG_GRP2,
THERMAL_IPI_SET_ATM_CFG_GRP3,
THERMAL_IPI_SET_ATM_CFG_GRP4,
THERMAL_IPI_SET_ATM_CFG_GRP5,
THERMAL_IPI_SET_ATM_CFG_GRP6,
THERMAL_IPI_SET_ATM_CFG_GRP7,
THERMAL_IPI_SET_ATM_CFG_GRP8,
THERMAL_IPI_SET_ATM_TTJ,
THERMAL_IPI_SET_ATM_EN,
THERMAL_IPI_GET_ATM_CPU_LIMIT,
THERMAL_IPI_GET_ATM_GPU_LIMIT,
NR_THERMAL_IPI
};
/* IPI Msg data structure */
struct thermal_ipi_data {
unsigned int cmd;
union {
struct {
int arg[THERMAL_SLOT_NUM - 1];
} data;
} u;
};
extern unsigned int thermal_to_sspm(unsigned int cmd,
struct thermal_ipi_data *thermal_data);
extern int atm_to_sspm(unsigned int cmd, int data_len,
struct thermal_ipi_data *thermal_data, int *ackData);
#endif /* THERMAL_ENABLE_TINYSYS_SSPM */
#endif

32
drivers/misc/mediatek/thermal/mt6739/inc/mtk_ts_setting.h
View File

@@ -1,32 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MTK_TS_SETTING_H
#define _MTK_TS_SETTING_H
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/* mtk_ts_pa.c */
/* 1: turn on MD UL throughput update; 0: turn off */
#define Feature_Thro_update (1)
/*
* Request HPM in Low temperature condition
*/
#define THERMAL_LT_SET_HPM (1)
#if THERMAL_LT_SET_HPM
extern int enter_hpm_temp;
extern int leave_hpm_temp;
extern int enable_hpm_temp;
#endif
/*In src/mtk_tc.c*/
extern int get_immediate_ts4_wrap(void);
#endif /* _MTK_TS_SETTING_H */

26
drivers/misc/mediatek/thermal/mt6739/inc/tmp_bts.h
View File

@@ -1,26 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TMP_BTS_H__
#define __TMP_BTS_H__
#define AUX_IN0_NTC (0)
#define AUX_IN1_NTC (1)
#define BTS_RAP_PULL_UP_R 390000 /* 390K,pull up resister */
#define BTS_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp default value -40 deg */
#define BTS_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTS_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTS_RAP_ADC_CHANNEL AUX_IN0_NTC /* default is 0 */
#define BTSMDPA_RAP_PULL_UP_R 390000 /* 390K,pull up resister */
#define BTSMDPA_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp default value -40 deg */
#define BTSMDPA_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTSMDPA_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTSMDPA_RAP_ADC_CHANNEL AUX_IN1_NTC /* default is 1 */
extern int IMM_GetOneChannelValue(int dwChannel, int data[4], int *rawdata);
extern int IMM_IsAdcInitReady(void);
#endif /* __TMP_BTS_H__ */

689
drivers/misc/mediatek/thermal/mt6739/inc/tscpu_settings.h
View File

@@ -1,689 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TSCPU_SETTINGS_H__
#define __TSCPU_SETTINGS_H__
#include <linux/of.h>
#include <linux/of_address.h>
#include "tzcpu_initcfg.h"
#include "clatm_initcfg.h"
/*=============================================================
* Genernal
*=============================================================
*/
#define MIN(_a_, _b_) ((_a_) > (_b_) ? (_b_) : (_a_))
#define MAX(_a_, _b_) ((_a_) > (_b_) ? (_a_) : (_b_))
#define _BIT_(_bit_) (unsigned)(1 << (_bit_))
#define _BITMASK_(_bits_) (((unsigned) -1 >> (31 - ((1) ? _bits_))) & ~((1U << ((0) ? _bits_)) - 1))
#define THERMAL_TPROFILE_INIT() long long thermal_pTime_us, thermal_cTime_us, thermal_diff_us
#define THERMAL_GET_PTIME() {thermal_pTime_us = thermal_get_current_time_us()}
#define THERMAL_GET_CTIME() {thermal_cTime_us = thermal_get_current_time_us()}
#define THERMAL_TIME_TH 3000
#define THERMAL_IS_TOO_LONG() \
do { \
thermal_diff_us = thermal_cTime_us - thermal_pTime_us; \
if (thermal_diff_us > THERMAL_TIME_TH) { \
pr_info(TSCPU_LOG_TAG "%s: %llu us\n", __func__, thermal_diff_us); \
} else if (thermal_diff_us < 0) { \
pr_info(TSCPU_LOG_TAG "Warning: tProfiling uses incorrect %s %d\n", __func__, __LINE__); \
} \
} while (0)
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
#define ENALBE_UART_LIMIT (0)
#define TEMP_EN_UART (80000)
#define TEMP_DIS_UART (85000)
#define TEMP_TOLERANCE (0)
#define ENALBE_SW_FILTER (0)
#define ATM_USES_PPM (1)
#define THERMAL_GET_AHB_BUS_CLOCK (0)
#define THERMAL_PERFORMANCE_PROFILE (0)
/* 1: turn on GPIO toggle monitor; 0: turn off */
#define THERMAL_GPIO_OUT_TOGGLE (0)
/* 1: turn on adaptive AP cooler; 0: turn off */
#define CPT_ADAPTIVE_AP_COOLER (1)
/* 1: turn on supports to MET logging; 0: turn off */
#define CONFIG_SUPPORT_MET_MTKTSCPU (0)
/* Thermal controller HW filtering function. Only 1, 2, 4, 8, 16 are valid values,
* they means one reading is a avg of X samples
*/
#define THERMAL_CONTROLLER_HW_FILTER (2) /* 1, 2, 4, 8, 16 */
/* 1: turn on thermal controller HW thermal protection; 0: turn off */
#define THERMAL_CONTROLLER_HW_TP (1)
/* 1: turn on fast polling in this sw module; 0: turn off */
#define MTKTSCPU_FAST_POLLING (1)
#if CPT_ADAPTIVE_AP_COOLER
#define MAX_CPT_ADAPTIVE_COOLERS (3)
#define THERMAL_HEADROOM (0)
#define CONTINUOUS_TM (1)
#define DYNAMIC_GET_GPU_POWER (1)
/* 1: turn on precise power budgeting; 0: turn off */
#define PRECISE_HYBRID_POWER_BUDGET (1)
#define PHPB_DEFAULT_ON (1)
#endif
/* 1: thermal driver fast polling, use hrtimer; 0: turn off */
/*#define THERMAL_DRV_FAST_POLL_HRTIMER (1)*/
/* 1: thermal driver update temp to MET directly, use hrtimer; 0: turn off */
#define THERMAL_DRV_UPDATE_TEMP_DIRECT_TO_MET (1)
/* Define this in tscpu_settings.h enables this feature. It polls CPU TS in hrtimer and
* run ATM in RT 98 kthread. This is for MT6797 only.
*/
#define FAST_RESPONSE_ATM (1)
#define THERMAL_INIT_VALUE (0xDA1)
/* 1: mtk_tc.c supports LVTS; 0: o.w. */
#define CFG_THERM_LVTS (0)
/*=============================================================
* Chip related
*=============================================================
*/
/* double check */
#define TS_CONFIGURE TS_CON1_TM /* depend on CPU design*/
#define TS_CONFIGURE_P TS_CON1_P /* depend on CPU design*/
#define TS_TURN_ON 0xFFFFFFCF /* turn on TS_CON1[5:4] 2'b 00 11001111 -> 0xCF ~(0x30)*/
#define TS_TURN_OFF 0x00000030 /* turn off thermal*/
/* chip dependent */
/* TODO: change to new reg addr. */
#define ADDRESS_INDEX_0 103
#define ADDRESS_INDEX_1 102
#define ADDRESS_INDEX_2 104
#define CLEAR_TEMP 26111
/* TSCON1 bit table */
#define TSCON0_bit_6_7_00 0x00 /* TSCON0[7:6]=2'b00*/
#define TSCON0_bit_6_7_01 0x40 /* TSCON0[7:6]=2'b01*/
#define TSCON0_bit_6_7_10 0x80 /* TSCON0[7:6]=2'b10*/
#define TSCON0_bit_6_7_11 0xc0 /* TSCON0[7:6]=2'b11*/
#define TSCON0_bit_6_7_MASK 0xc0
#define TSCON1_bit_4_5_00 0x00 /* TSCON1[5:4]=2'b00*/
#define TSCON1_bit_4_5_01 0x10 /* TSCON1[5:4]=2'b01*/
#define TSCON1_bit_4_5_10 0x20 /* TSCON1[5:4]=2'b10*/
#define TSCON1_bit_4_5_11 0x30 /* TSCON1[5:4]=2'b11*/
#define TSCON1_bit_4_5_MASK 0x30
#define TSCON1_bit_0_2_000 0x00 /*TSCON1[2:0]=3'b000*/
#define TSCON1_bit_0_2_001 0x01 /*TSCON1[2:0]=3'b001*/
#define TSCON1_bit_0_2_010 0x02 /*TSCON1[2:0]=3'b010*/
#define TSCON1_bit_0_2_011 0x03 /*TSCON1[2:0]=3'b011*/
#define TSCON1_bit_0_2_100 0x04 /*TSCON1[2:0]=3'b100*/
#define TSCON1_bit_0_2_101 0x05 /*TSCON1[2:0]=3'b101*/
#define TSCON1_bit_0_2_110 0x06 /*TSCON1[2:0]=3'b110*/
#define TSCON1_bit_0_2_111 0x07 /*TSCON1[2:0]=3'b111*/
#define TSCON1_bit_0_2_MASK 0x07
/* ADC value to mcu */
/*chip dependent*/
#define TEMPADC_MCU1 ((0x30&TSCON1_bit_4_5_00)|(0x07&TSCON1_bit_0_2_000))
#define TEMPADC_MCU2 ((0x30&TSCON1_bit_4_5_00)|(0x07&TSCON1_bit_0_2_001))
#define TEMPADC_MCU3 ((0x30&TSCON1_bit_4_5_00)|(0x07&TSCON1_bit_0_2_010))
#define TEMPADC_ABB ((0x30&TSCON1_bit_4_5_01)|(0x07&TSCON1_bit_0_2_000))
#define TS_FILL(n) {#n, n}
/*#define TS_LEN_ARRAY(name) (sizeof(name)/sizeof(name[0]))*/
#define MAX_TS_NAME 20
#define CPU_COOLER_NUM 34
#define MTK_TS_CPU_RT (0)
#ifdef CONFIG_MTK_RAM_CONSOLE
#define CONFIG_THERMAL_AEE_RR_REC (1)
#else
#define CONFIG_THERMAL_AEE_RR_REC (0)
#endif
#define CFG_THERMAL_KERNEL_IGNORE_HOT_SENSOR (0)
/*=============================================================
*REG ACCESS
*=============================================================
*/
#define thermal_setl(addr, val) mt_reg_sync_writel(readl(addr) | (val), ((void *)addr))
#define thermal_clrl(addr, val) mt_reg_sync_writel(readl(addr) & ~(val), ((void *)addr))
#define MTKTSCPU_TEMP_CRIT 120000 /* 120.000 degree Celsius */
#define y_curr_repeat_times 1
#define THERMAL_NAME "mtk-thermal"
#define TS_MS_TO_NS(x) (x * 1000 * 1000)
#if THERMAL_GET_AHB_BUS_CLOCK
#define THERMAL_MODULE_SW_CG_SET (therm_clk_infracfg_ao_base + 0x88)
#define THERMAL_MODULE_SW_CG_CLR (therm_clk_infracfg_ao_base + 0x8C)
#define THERMAL_MODULE_SW_CG_STA (therm_clk_infracfg_ao_base + 0x94)
#define THERMAL_CG (therm_clk_infracfg_ao_base + 0x80)
#define THERMAL_DCM (therm_clk_infracfg_ao_base + 0x70)
#endif
/*=============================================================
*LOG
*=============================================================
*/
#define TSCPU_LOG_TAG "[Thermal/TZ/CPU]"
#define tscpu_dprintk(fmt, args...) \
do { \
if (tscpu_debug_log == 1) { \
pr_info(TSCPU_LOG_TAG fmt, ##args); \
} \
} while (0)
#define tscpu_printk(fmt, args...) pr_info(TSCPU_LOG_TAG fmt, ##args)
#define tscpu_warn(fmt, args...) pr_notice(TSCPU_LOG_TAG fmt, ##args)
/*=============================================================
* Structures
*=============================================================
*/
enum thermal_controller_name {
THERMAL_CONTROLLER0 = 0,
THERMAL_CONTROLLER1,
THERMAL_CONTROLLER_NUM
};
struct thermal_controller_speed {
unsigned int tempMonCtl1;
unsigned int tempMonCtl2;
unsigned int tempAhbPoll;
};
struct thermal_controller {
enum thermal_sensor ts[TS_ENUM_MAX];
int ts_number;
int tc_offset;
struct thermal_controller_speed tc_speed;
};
#if (CONFIG_THERMAL_AEE_RR_REC == 1)
enum thermal_state {
TSCPU_SUSPEND = 0,
TSCPU_RESUME = 1,
TSCPU_NORMAL = 2,
TSCPU_INIT = 3,
TSCPU_PAUSE = 4,
TSCPU_RELEASE = 5
};
enum atm_state {
ATM_WAKEUP = 0,
ATM_CPULIMIT = 1,
ATM_GPULIMIT = 2,
ATM_DONE = 3,
};
#endif
struct mtk_cpu_power_info {
unsigned int cpufreq_khz;
unsigned int cpufreq_ncpu;
unsigned int cpufreq_power;
};
/*=============================================================
* Shared variables
*=============================================================
*/
/*In src/mtk_tc.c*/
extern int temp_eUART;
extern int temp_dUART;
extern int tscpu_debug_log;
extern const struct of_device_id mt_thermal_of_match[2];
extern int tscpu_ts_temp[TS_ENUM_MAX];
extern int tscpu_ts_temp_r[TS_ENUM_MAX]; /* raw data */
extern struct thermal_controller tscpu_g_tc[THERMAL_CONTROLLER_NUM];
extern int tscpu_polling_trip_temp1;
extern int tscpu_polling_trip_temp2;
extern int tscpu_polling_factor1;
extern int tscpu_polling_factor2;
#if MTKTSCPU_FAST_POLLING
/* Combined fast_polling_trip_temp and fast_polling_factor,
*it means polling_delay will be 1/5 of original interval
*after mtktscpu reports > 65C w/o exit point
*/
extern int fast_polling_trip_temp;
extern int fast_polling_trip_temp_high;
extern int fast_polling_factor;
extern int tscpu_cur_fp_factor;
extern int tscpu_next_fp_factor;
#endif
//#if !IS_ENABLED(CONFIG_MTK_GPU_SUPPORT)
struct mt_gpufreq_power_table_info {
unsigned int gpufreq_khz;
unsigned int gpufreq_volt;
unsigned int gpufreq_power;
};
//#endif
/*In common/thermal_zones/mtk_ts_cpu.c*/
extern long long thermal_get_current_time_us(void);
extern void tscpu_workqueue_cancel_timer(void);
extern void tscpu_workqueue_start_timer(void);
extern void __iomem *therm_clk_infracfg_ao_base;
extern int Num_of_GPU_OPP;
extern int gpu_max_opp;
extern struct mt_gpufreq_power_table_info *mtk_gpu_power;
extern int mtk_gpufreq_register(struct mt_gpufreq_power_table_info *freqs, int num);
extern int tscpu_read_curr_temp;
#if MTKTSCPU_FAST_POLLING
extern int tscpu_cur_fp_factor;
#endif
#if !defined(CONFIG_MTK_CLKMGR)
extern struct clk *therm_main; /* main clock for Thermal*/
#endif
#if CPT_ADAPTIVE_AP_COOLER
extern int tscpu_g_curr_temp;
extern int tscpu_g_prev_temp;
#if (THERMAL_HEADROOM == 1) || (CONTINUOUS_TM == 1)
extern int bts_cur_temp; /* in mtk_ts_bts.c */
#endif
#if PRECISE_HYBRID_POWER_BUDGET
/* tscpu_prev_cpu_temp: previous CPUSYS temperature
* tscpu_curr_cpu_temp: current CPUSYS temperature
* tscpu_prev_gpu_temp: previous GPUSYS temperature
* tscpu_curr_gpu_temp: current GPUSYS temperature
*/
extern int tscpu_prev_cpu_temp, tscpu_prev_gpu_temp;
extern int tscpu_curr_cpu_temp, tscpu_curr_gpu_temp;
#endif
#endif
#ifdef CONFIG_OF
extern u32 thermal_irq_number;
extern void __iomem *thermal_base;
extern void __iomem *auxadc_ts_base;
extern void __iomem *infracfg_ao_base;
extern void __iomem *th_apmixed_base;
extern void __iomem *INFRACFG_AO_base;
extern int thermal_phy_base;
extern int auxadc_ts_phy_base;
extern int apmixed_phy_base;
extern int pericfg_phy_base;
#endif
extern char *adaptive_cooler_name;
/*common/coolers/mtk_cooler_atm.c*/
extern unsigned int adaptive_cpu_power_limit;
extern unsigned int adaptive_gpu_power_limit;
extern int TARGET_TJS[MAX_CPT_ADAPTIVE_COOLERS];
#ifdef FAST_RESPONSE_ATM
extern void atm_cancel_hrtimer(void);
extern void atm_restart_hrtimer(void);
#endif
/*common/coolers/mtk_cooler_dtm.c*/
extern unsigned int static_cpu_power_limit;
extern unsigned int static_gpu_power_limit;
extern int tscpu_cpu_dmips[CPU_COOLER_NUM];
/*=============================================================
* Shared functions
*=============================================================
*/
/*In common/thermal_zones/mtk_ts_cpu.c*/
extern void thermal_init_interrupt_for_UART(int temp_e, int temp_d);
extern void tscpu_update_tempinfo(void);
#if THERMAL_GPIO_OUT_TOGGLE
void tscpu_set_GPIO_toggle_for_monitor(void);
#endif
extern void tscpu_update_tempinfo(void);
extern int tscpu_max_temperature(void);
/*In src/mtk_tc.c*/
extern int get_io_reg_base(void);
extern void tscpu_config_all_tc_hw_protect(int temperature, int temperature2);
extern void tscpu_reset_thermal(void);
extern void tscpu_thermal_initial_all_tc(void);
extern void tscpu_thermal_read_tc_temp(int tc_num, enum thermal_sensor type, int order);
extern void tscpu_thermal_cal_prepare(void);
extern void tscpu_thermal_cal_prepare_2(unsigned int ret);
extern irqreturn_t tscpu_thermal_all_tc_interrupt_handler(int irq, void *dev_id);
extern int tscpu_thermal_clock_on(void);
extern int tscpu_thermal_clock_off(void);
extern int tscpu_read_temperature_info(struct seq_file *m, void *v);
extern int tscpu_thermal_fast_init(int tc_num);
extern int tscpu_get_curr_temp(void);
extern int tscpu_get_curr_max_ts_temp(void);
extern void thermal_get_AHB_clk_info(void);
extern void print_risky_temps(char *prefix, int offset, int printLevel);
extern void thermal_pause_all_periodoc_temp_sensing(void);
extern void thermal_release_all_periodoc_temp_sensing(void);
extern int (*max_temperature_in_bank[THERMAL_BANK_NUM])(void);
extern void thermal_disable_all_periodoc_temp_sensing(void);
/*
*In drivers/misc/mediatek/gpu/hal/mtk_gpu_utility.c
*It's not our api, ask them to provide header file
*/
extern bool mtk_get_gpu_loading(unsigned int *pLoading);
/*
*In drivers/misc/mediatek/auxadc/mt_auxadc.c
*It's not our api, ask them to provide header file
*/
extern int IMM_IsAdcInitReady(void);
/*=============================================================
* Register macro for internal use
*=============================================================
*/
#if 1
extern void __iomem *thermal_base;
extern void __iomem *auxadc_base;
extern void __iomem *infracfg_ao_base;
extern void __iomem *th_apmixed_base;
extern void __iomem *INFRACFG_AO_base;
#define THERM_CTRL_BASE_2 thermal_base
#define AUXADC_BASE_2 auxadc_ts_base
#define INFRACFG_AO_BASE_2 infracfg_ao_base
#define APMIXED_BASE_2 th_apmixed_base
#else
#include <mach/mt_reg_base.h>
#define AUXADC_BASE_2 AUXADC_BASE
#define THERM_CTRL_BASE_2 THERM_CTRL_BASE
#define PERICFG_BASE_2 PERICFG_BASE
#define APMIXED_BASE_2 APMIXED_BASE
#endif
/*******************************************************************************
* AUXADC Register Definition
*****************************************************************************
*/
#define AUXADC_CON0_V (AUXADC_BASE_2 + 0x000)
#define AUXADC_CON1_V (AUXADC_BASE_2 + 0x004)
#define AUXADC_CON1_SET_V (AUXADC_BASE_2 + 0x008)
#define AUXADC_CON1_CLR_V (AUXADC_BASE_2 + 0x00C)
#define AUXADC_CON2_V (AUXADC_BASE_2 + 0x010)
/*#define AUXADC_CON3_V (AUXADC_BASE_2 + 0x014)*/
#define AUXADC_DAT0_V (AUXADC_BASE_2 + 0x014)
#define AUXADC_DAT1_V (AUXADC_BASE_2 + 0x018)
#define AUXADC_DAT2_V (AUXADC_BASE_2 + 0x01C)
#define AUXADC_DAT3_V (AUXADC_BASE_2 + 0x020)
#define AUXADC_DAT4_V (AUXADC_BASE_2 + 0x024)
#define AUXADC_DAT5_V (AUXADC_BASE_2 + 0x028)
#define AUXADC_DAT6_V (AUXADC_BASE_2 + 0x02C)
#define AUXADC_DAT7_V (AUXADC_BASE_2 + 0x030)
#define AUXADC_DAT8_V (AUXADC_BASE_2 + 0x034)
#define AUXADC_DAT9_V (AUXADC_BASE_2 + 0x038)
#define AUXADC_DAT10_V (AUXADC_BASE_2 + 0x03C)
#define AUXADC_DAT11_V (AUXADC_BASE_2 + 0x040)
#define AUXADC_MISC_V (AUXADC_BASE_2 + 0x094)
#define AUXADC_CON0_P (auxadc_ts_phy_base + 0x000)
#define AUXADC_CON1_P (auxadc_ts_phy_base + 0x004)
#define AUXADC_CON1_SET_P (auxadc_ts_phy_base + 0x008)
#define AUXADC_CON1_CLR_P (auxadc_ts_phy_base + 0x00C)
#define AUXADC_CON2_P (auxadc_ts_phy_base + 0x010)
/*#define AUXADC_CON3_P (auxadc_ts_phy_base + 0x014)*/
#define AUXADC_DAT0_P (auxadc_ts_phy_base + 0x014)
#define AUXADC_DAT1_P (auxadc_ts_phy_base + 0x018)
#define AUXADC_DAT2_P (auxadc_ts_phy_base + 0x01C)
#define AUXADC_DAT3_P (auxadc_ts_phy_base + 0x020)
#define AUXADC_DAT4_P (auxadc_ts_phy_base + 0x024)
#define AUXADC_DAT5_P (auxadc_ts_phy_base + 0x028)
#define AUXADC_DAT6_P (auxadc_ts_phy_base + 0x02C)
#define AUXADC_DAT7_P (auxadc_ts_phy_base + 0x030)
#define AUXADC_DAT8_P (auxadc_ts_phy_base + 0x034)
#define AUXADC_DAT9_P (auxadc_ts_phy_base + 0x038)
#define AUXADC_DAT10_P (auxadc_ts_phy_base + 0x03C)
#define AUXADC_DAT11_P (auxadc_ts_phy_base + 0x040)
#define AUXADC_MISC_P (auxadc_ts_phy_base + 0x094)
/*******************************************************************************
* Peripheral Configuration Register Definition
*****************************************************************************
*/
/*APB Module infracfg_ao*/
#define INFRA_GLOBALCON_RST_0_SET (INFRACFG_AO_BASE_2 + 0x120) /*yes, 0x10000000*/
#define INFRA_GLOBALCON_RST_0_CLR (INFRACFG_AO_BASE_2 + 0x124) /*yes, 0x10000000*/
#define INFRA_GLOBALCON_RST_0_STA (INFRACFG_AO_BASE_2 + 0x128) /*yes, 0x10000000*/
/*******************************************************************************
* APMixedSys Configuration Register Definition
*****************************************************************************
*/
/* TODO: check base addr. */
#define TS_CON0_TM (APMIXED_BASE_2 + 0x600) /*yes 0x10212000*/
#define TS_CON1_TM (APMIXED_BASE_2 + 0x604)
#define TS_CON0_P (apmixed_phy_base + 0x600)
#define TS_CON1_P (apmixed_phy_base + 0x604)
/*******************************************************************************
* Thermal Controller Register Definition
*****************************************************************************
*/
#define TEMPMONCTL0 (THERM_CTRL_BASE_2 + 0x000)
#define TEMPMONCTL1 (THERM_CTRL_BASE_2 + 0x004)
#define TEMPMONCTL2 (THERM_CTRL_BASE_2 + 0x008)
#define TEMPMONINT (THERM_CTRL_BASE_2 + 0x00C)
#define TEMPMONINTSTS (THERM_CTRL_BASE_2 + 0x010)
#define TEMPMONIDET0 (THERM_CTRL_BASE_2 + 0x014)
#define TEMPMONIDET1 (THERM_CTRL_BASE_2 + 0x018)
#define TEMPMONIDET2 (THERM_CTRL_BASE_2 + 0x01C)
#define TEMPH2NTHRE (THERM_CTRL_BASE_2 + 0x024)
#define TEMPHTHRE (THERM_CTRL_BASE_2 + 0x028)
#define TEMPCTHRE (THERM_CTRL_BASE_2 + 0x02C)
#define TEMPOFFSETH (THERM_CTRL_BASE_2 + 0x030)
#define TEMPOFFSETL (THERM_CTRL_BASE_2 + 0x034)
#define TEMPMSRCTL0 (THERM_CTRL_BASE_2 + 0x038)
#define TEMPMSRCTL1 (THERM_CTRL_BASE_2 + 0x03C)
#define TEMPAHBPOLL (THERM_CTRL_BASE_2 + 0x040)
#define TEMPAHBTO (THERM_CTRL_BASE_2 + 0x044)
#define TEMPADCPNP0 (THERM_CTRL_BASE_2 + 0x048)
#define TEMPADCPNP1 (THERM_CTRL_BASE_2 + 0x04C)
#define TEMPADCPNP2 (THERM_CTRL_BASE_2 + 0x050)
#define TEMPADCMUX (THERM_CTRL_BASE_2 + 0x054)
#define TEMPADCEXT (THERM_CTRL_BASE_2 + 0x058)
#define TEMPADCEXT1 (THERM_CTRL_BASE_2 + 0x05C)
#define TEMPADCEN (THERM_CTRL_BASE_2 + 0x060)
#define TEMPPNPMUXADDR (THERM_CTRL_BASE_2 + 0x064)
#define TEMPADCMUXADDR (THERM_CTRL_BASE_2 + 0x068)
#define TEMPADCEXTADDR (THERM_CTRL_BASE_2 + 0x06C)
#define TEMPADCEXT1ADDR (THERM_CTRL_BASE_2 + 0x070)
#define TEMPADCENADDR (THERM_CTRL_BASE_2 + 0x074)
#define TEMPADCVALIDADDR (THERM_CTRL_BASE_2 + 0x078)
#define TEMPADCVOLTADDR (THERM_CTRL_BASE_2 + 0x07C)
#define TEMPRDCTRL (THERM_CTRL_BASE_2 + 0x080)
#define TEMPADCVALIDMASK (THERM_CTRL_BASE_2 + 0x084)
#define TEMPADCVOLTAGESHIFT (THERM_CTRL_BASE_2 + 0x088)
#define TEMPADCWRITECTRL (THERM_CTRL_BASE_2 + 0x08C)
#define TEMPMSR0 (THERM_CTRL_BASE_2 + 0x090)
#define TEMPMSR1 (THERM_CTRL_BASE_2 + 0x094)
#define TEMPMSR2 (THERM_CTRL_BASE_2 + 0x098)
#define TEMPADCHADDR (THERM_CTRL_BASE_2 + 0x09C)
#define TEMPIMMD0 (THERM_CTRL_BASE_2 + 0x0A0)
#define TEMPIMMD1 (THERM_CTRL_BASE_2 + 0x0A4)
#define TEMPIMMD2 (THERM_CTRL_BASE_2 + 0x0A8)
#define TEMPMONIDET3 (THERM_CTRL_BASE_2 + 0x0B0)
#define TEMPADCPNP3 (THERM_CTRL_BASE_2 + 0x0B4)
#define TEMPMSR3 (THERM_CTRL_BASE_2 + 0x0B8)
#define TEMPIMMD3 (THERM_CTRL_BASE_2 + 0x0BC)
#define TEMPPROTCTL (THERM_CTRL_BASE_2 + 0x0C0)
#define TEMPPROTTA (THERM_CTRL_BASE_2 + 0x0C4)
#define TEMPPROTTB (THERM_CTRL_BASE_2 + 0x0C8)
#define TEMPPROTTC (THERM_CTRL_BASE_2 + 0x0CC)
#define TEMPSPARE0 (THERM_CTRL_BASE_2 + 0x0F0)
#define TEMPSPARE1 (THERM_CTRL_BASE_2 + 0x0F4)
#define TEMPSPARE2 (THERM_CTRL_BASE_2 + 0x0F8)
#define TEMPSPARE3 (THERM_CTRL_BASE_2 + 0x0FC)
#define TEMPMONCTL0_1 (THERM_CTRL_BASE_2 + 0x100)
#define TEMPMONCTL1_1 (THERM_CTRL_BASE_2 + 0x104)
#define TEMPMONCTL2_1 (THERM_CTRL_BASE_2 + 0x108)
#define TEMPMONINT_1 (THERM_CTRL_BASE_2 + 0x10C)
#define TEMPMONINTSTS_1 (THERM_CTRL_BASE_2 + 0x110)
#define TEMPMONIDET0_1 (THERM_CTRL_BASE_2 + 0x114)
#define TEMPMONIDET1_1 (THERM_CTRL_BASE_2 + 0x118)
#define TEMPMONIDET2_1 (THERM_CTRL_BASE_2 + 0x11C)
#define TEMPH2NTHRE_1 (THERM_CTRL_BASE_2 + 0x124)
#define TEMPHTHRE_1 (THERM_CTRL_BASE_2 + 0x128)
#define TEMPCTHRE_1 (THERM_CTRL_BASE_2 + 0x12C)
#define TEMPOFFSETH_1 (THERM_CTRL_BASE_2 + 0x130)
#define TEMPOFFSETL_1 (THERM_CTRL_BASE_2 + 0x134)
#define TEMPMSRCTL0_1 (THERM_CTRL_BASE_2 + 0x138)
#define TEMPMSRCTL1_1 (THERM_CTRL_BASE_2 + 0x13C)
#define TEMPAHBPOLL_1 (THERM_CTRL_BASE_2 + 0x140)
#define TEMPAHBTO_1 (THERM_CTRL_BASE_2 + 0x144)
#define TEMPADCPNP0_1 (THERM_CTRL_BASE_2 + 0x148)
#define TEMPADCPNP1_1 (THERM_CTRL_BASE_2 + 0x14C)
#define TEMPADCPNP2_1 (THERM_CTRL_BASE_2 + 0x150)
#define TEMPADCMUX_1 (THERM_CTRL_BASE_2 + 0x154)
#define TEMPADCEXT_1 (THERM_CTRL_BASE_2 + 0x158)
#define TEMPADCEXT1_1 (THERM_CTRL_BASE_2 + 0x15C)
#define TEMPADCEN_1 (THERM_CTRL_BASE_2 + 0x160)
#define TEMPPNPMUXADDR_1 (THERM_CTRL_BASE_2 + 0x164)
#define TEMPADCMUXADDR_1 (THERM_CTRL_BASE_2 + 0x168)
#define TEMPADCEXTADDR_1 (THERM_CTRL_BASE_2 + 0x16C)
#define TEMPADCEXT1ADDR_1 (THERM_CTRL_BASE_2 + 0x170)
#define TEMPADCENADDR_1 (THERM_CTRL_BASE_2 + 0x174)
#define TEMPADCVALIDADDR_1 (THERM_CTRL_BASE_2 + 0x178)
#define TEMPADCVOLTADDR_1 (THERM_CTRL_BASE_2 + 0x17C)
#define TEMPRDCTRL_1 (THERM_CTRL_BASE_2 + 0x180)
#define TEMPADCVALIDMASK_1 (THERM_CTRL_BASE_2 + 0x184)
#define TEMPADCVOLTAGESHIFT_1 (THERM_CTRL_BASE_2 + 0x188)
#define TEMPADCWRITECTRL_1 (THERM_CTRL_BASE_2 + 0x18C)
#define TEMPMSR0_1 (THERM_CTRL_BASE_2 + 0x190)
#define TEMPMSR1_1 (THERM_CTRL_BASE_2 + 0x194)
#define TEMPMSR2_1 (THERM_CTRL_BASE_2 + 0x198)
#define TEMPADCHADDR_1 (THERM_CTRL_BASE_2 + 0x19C)
#define TEMPIMMD0_1 (THERM_CTRL_BASE_2 + 0x1A0)
#define TEMPIMMD1_1 (THERM_CTRL_BASE_2 + 0x1A4)
#define TEMPIMMD2_1 (THERM_CTRL_BASE_2 + 0x1A8)
#define TEMPMONIDET3_1 (THERM_CTRL_BASE_2 + 0x1B0)
#define TEMPADCPNP3_1 (THERM_CTRL_BASE_2 + 0x1B4)
#define TEMPMSR3_1 (THERM_CTRL_BASE_2 + 0x1B8)
#define TEMPIMMD3_1 (THERM_CTRL_BASE_2 + 0x1BC)
#define TEMPPROTCTL_1 (THERM_CTRL_BASE_2 + 0x1C0)
#define TEMPPROTTA_1 (THERM_CTRL_BASE_2 + 0x1C4)
#define TEMPPROTTB_1 (THERM_CTRL_BASE_2 + 0x1C8)
#define TEMPPROTTC_1 (THERM_CTRL_BASE_2 + 0x1CC)
#define TEMPSPARE0_1 (THERM_CTRL_BASE_2 + 0x1F0)
#define TEMPSPARE1_1 (THERM_CTRL_BASE_2 + 0x1F4)
#define TEMPSPARE2_1 (THERM_CTRL_BASE_2 + 0x1F8)
#define TEMPSPARE3_1 (THERM_CTRL_BASE_2 + 0x1FC)
#define PTPCORESEL (THERM_CTRL_BASE_2 + 0xF00)
#define THERMINTST (THERM_CTRL_BASE_2 + 0xF04)
#define PTPODINTST (THERM_CTRL_BASE_2 + 0xF08)
#define THSTAGE0ST (THERM_CTRL_BASE_2 + 0xF0C)
#define THSTAGE1ST (THERM_CTRL_BASE_2 + 0xF10)
#define THSTAGE2ST (THERM_CTRL_BASE_2 + 0xF14)
#define THAHBST0 (THERM_CTRL_BASE_2 + 0xF18)
#define THAHBST1 (THERM_CTRL_BASE_2 + 0xF1C)
#define PTPSPARE0 (THERM_CTRL_BASE_2 + 0xF20)
#define PTPSPARE1 (THERM_CTRL_BASE_2 + 0xF24)
#define PTPSPARE2 (THERM_CTRL_BASE_2 + 0xF28)
#define PTPSPARE3 (THERM_CTRL_BASE_2 + 0xF2C)
#define THSLPEVEB (THERM_CTRL_BASE_2 + 0xF30)
#define PTPSPARE0_P (thermal_phy_base + 0xF20)
#define PTPSPARE1_P (thermal_phy_base + 0xF24)
#define PTPSPARE2_P (thermal_phy_base + 0xF28)
#define PTPSPARE3_P (thermal_phy_base + 0xF2C)
/*******************************************************************************
* Thermal Controller Register Mask Definition
*****************************************************************************
*/
#define THERMAL_ENABLE_SEN0 0x1
#define THERMAL_ENABLE_SEN1 0x2
#define THERMAL_ENABLE_SEN2 0x4
#define THERMAL_MONCTL0_MASK 0x00000007
#define THERMAL_PUNT_MASK 0x00000FFF
#define THERMAL_FSINTVL_MASK 0x03FF0000
#define THERMAL_SPINTVL_MASK 0x000003FF
#define THERMAL_MON_INT_MASK 0x0007FFFF
#define THERMAL_MON_CINTSTS0 0x000001
#define THERMAL_MON_HINTSTS0 0x000002
#define THERMAL_MON_LOINTSTS0 0x000004
#define THERMAL_MON_HOINTSTS0 0x000008
#define THERMAL_MON_NHINTSTS0 0x000010
#define THERMAL_MON_CINTSTS1 0x000020
#define THERMAL_MON_HINTSTS1 0x000040
#define THERMAL_MON_LOINTSTS1 0x000080
#define THERMAL_MON_HOINTSTS1 0x000100
#define THERMAL_MON_NHINTSTS1 0x000200
#define THERMAL_MON_CINTSTS2 0x000400
#define THERMAL_MON_HINTSTS2 0x000800
#define THERMAL_MON_LOINTSTS2 0x001000
#define THERMAL_MON_HOINTSTS2 0x002000
#define THERMAL_MON_NHINTSTS2 0x004000
#define THERMAL_MON_TOINTSTS 0x008000
#define THERMAL_MON_IMMDINTSTS0 0x010000
#define THERMAL_MON_IMMDINTSTS1 0x020000
#define THERMAL_MON_IMMDINTSTS2 0x040000
#define THERMAL_MON_FILTINTSTS0 0x080000
#define THERMAL_MON_FILTINTSTS1 0x100000
#define THERMAL_MON_FILTINTSTS2 0x200000
#define THERMAL_tri_SPM_State0 0x20000000
#define THERMAL_tri_SPM_State1 0x40000000
#define THERMAL_tri_SPM_State2 0x80000000
#define THERMAL_MSRCTL0_MASK 0x00000007
#define THERMAL_MSRCTL1_MASK 0x00000038
#define THERMAL_MSRCTL2_MASK 0x000001C0
/*cpu core nums*/
#define TZCPU_NO_CPU_CORES CONFIG_NR_CPUS
#endif /* __TSCPU_SETTINGS_H__ */

44
drivers/misc/mediatek/thermal/mt6739/inc/tzbatt_initcfg.h
View File

@@ -1,44 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TZBATT_INITCFG_H__
#define __TZBATT_INITCFG_H__
#define TZBATT_SET_INIT_CFG (1)
#define TZBATT_INITCFG_INTERVAL (1)
#define TZBATT_INITCFG_NUM_TRIPS (3)
#define TZBATT_INITCFG_TRIP_0_TEMP (49000)
#define TZBATT_INITCFG_TRIP_0_COOLER "mtk-cl-bcct02"
#define TZBATT_INITCFG_TRIP_1_TEMP (48000)
#define TZBATT_INITCFG_TRIP_1_COOLER "mtk-cl-bcct01"
#define TZBATT_INITCFG_TRIP_2_TEMP (46000)
#define TZBATT_INITCFG_TRIP_2_COOLER "mtk-cl-bcct00"
#define TZBATT_INITCFG_TRIP_3_TEMP (45000)
#define TZBATT_INITCFG_TRIP_3_COOLER ""
#define TZBATT_INITCFG_TRIP_4_TEMP (44000)
#define TZBATT_INITCFG_TRIP_4_COOLER ""
#define TZBATT_INITCFG_TRIP_5_TEMP (43000)
#define TZBATT_INITCFG_TRIP_5_COOLER ""
#define TZBATT_INITCFG_TRIP_6_TEMP (42000)
#define TZBATT_INITCFG_TRIP_6_COOLER ""
#define TZBATT_INITCFG_TRIP_7_TEMP (41000)
#define TZBATT_INITCFG_TRIP_7_COOLER ""
#define TZBATT_INITCFG_TRIP_8_TEMP (40000)
#define TZBATT_INITCFG_TRIP_8_COOLER ""
#define TZBATT_INITCFG_TRIP_9_TEMP (39000)
#define TZBATT_INITCFG_TRIP_9_COOLER ""
#endif /* __TZBATT_INITCFG_H__ */

47
drivers/misc/mediatek/thermal/mt6739/inc/tzcpu_initcfg.h
View File

@@ -1,47 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TZCPU_INITCFG_H__
#define __TZCPU_INITCFG_H__
#define TZCPU_SET_INIT_CFG (1)
#define TZCPU_INITCFG_INTERVAL (40)
#define TZCPU_INITCFG_NUM_TRIPS (4)
#define TZCPU_INITCFG_TRIP_0_TEMP (117000)
#define TZCPU_INITCFG_TRIP_0_COOLER "mtktscpu-sysrst"
#define TZCPU_INITCFG_TRIP_1_TEMP (95000)
#define TZCPU_INITCFG_TRIP_1_COOLER "cpu00"
#define TZCPU_INITCFG_TRIP_2_TEMP (85000)
#define TZCPU_INITCFG_TRIP_2_COOLER "cpu03"
#define TZCPU_INITCFG_TRIP_3_TEMP (65000)
#define TZCPU_INITCFG_TRIP_3_COOLER "cpu_adaptive_0"
#define TZCPU_INITCFG_TRIP_4_TEMP (63000)
#define TZCPU_INITCFG_TRIP_4_COOLER ""
#define TZCPU_INITCFG_TRIP_5_TEMP (60000)
#define TZCPU_INITCFG_TRIP_5_COOLER ""
#define TZCPU_INITCFG_TRIP_6_TEMP (55000)
#define TZCPU_INITCFG_TRIP_6_COOLER ""
#define TZCPU_INITCFG_TRIP_7_TEMP (50000)
#define TZCPU_INITCFG_TRIP_7_COOLER ""
#define TZCPU_INITCFG_TRIP_8_TEMP (45000)
#define TZCPU_INITCFG_TRIP_8_COOLER ""
#define TZCPU_INITCFG_TRIP_9_TEMP (40000)
#define TZCPU_INITCFG_TRIP_9_COOLER ""
#endif /* __TZCPU_INITCFG_H__ */

27
drivers/misc/mediatek/thermal/mt6739/src/Makefile
View File

@@ -1,27 +0,0 @@
#
# Copyright (C) 2015 MediaTek Inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
THERMAL_CHIP_DRIVER_DIR := $(srctree)/drivers/misc/mediatek/thermal/$(MTK_PLATFORM)
ccflags-y += -I$(THERMAL_CHIP_DRIVER_DIR)/inc
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/$(MTK_PLATFORM)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/gpu/hal/
ccflags-y += -I$(srctree)/drivers/gpu/mediatek/mt-plat/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/thermal/fakeHeader/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/eem_v2/$(MTK_PLATFORM)/inc/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/pmic/include/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/thermal/common/inc/
obj-$(CONFIG_MTK_LEGACY_THERMAL) += mtk_tc.o
obj-$(CONFIG_MTK_LEGACY_THERMAL) += mtk_pmic_efuse.o
obj-$(CONFIG_MTK_LEGACY_THERMAL) += mtk_ts_6357buck1.o
obj-$(CONFIG_MTK_LEGACY_THERMAL) += mtk_ts_6357buck2.o

327
drivers/misc/mediatek/thermal/mt6739/src/mtk_pmic_efuse.c
View File

@@ -1,327 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mtk_thermal_typedefs.h"
#include "mach/mtk_thermal.h"
#include <mt-plat/upmu_common.h>
#include <mt-plat/mtk_auxadc_intf.h>
#include <tspmic_settings.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
int mtktspmic_debug_log;
/* Cali */
static __s32 g_o_vts;
static __s32 g_o_vts_2;
static __s32 g_o_vts_3;
static __s32 g_degc_cali;
static __s32 g_adc_cali_en;
static __s32 g_o_slope;
static __s32 g_o_slope_sign;
static __s32 g_id;
static __s32 g_slope1 = 1;
static __s32 g_slope2 = 1;
static __s32 g_intercept;
static __s32 g_tsbuck1_slope1 = 1;
static __s32 g_tsbuck1_slope2 = 1;
static __s32 g_tsbuck1_intercept;
static __s32 g_tsbuck2_slope1 = 1;
static __s32 g_tsbuck2_slope2 = 1;
static __s32 g_tsbuck2_intercept;
static DEFINE_MUTEX(TSPMIC_lock);
static int pre_temp1 = 0, PMIC_counter;
static int pre_tsbuck1_temp1 = 0, tsbuck1_cnt;
static int pre_tsbuck2_temp1 = 0, tsbuck2_cnt;
/*=============================================================*/
static __s32 pmic_raw_to_temp(__u32 ret)
{
__s32 t_current;
__s32 y_curr = ret;
t_current = g_intercept + ((g_slope1 * y_curr) / (g_slope2));
mtktspmic_dprintk("[pmic_raw_to_temp] t_current=%d\n", t_current);
return t_current;
}
static __s32 tsbuck1_raw_to_temp(__u32 ret)
{
__s32 t_current;
__s32 y_curr = ret;
t_current = g_tsbuck1_intercept + ((g_tsbuck1_slope1 * y_curr) / (g_tsbuck1_slope2));
mtktspmic_dprintk("[tsbuck1_raw_to_temp] t_current=%d\n", t_current);
return t_current;
}
static __s32 tsbuck2_raw_to_temp(__u32 ret)
{
__s32 t_current;
__s32 y_curr = ret;
t_current = g_tsbuck2_intercept + ((g_tsbuck2_slope1 * y_curr) / (g_tsbuck2_slope2));
mtktspmic_dprintk("[tsbuck2_raw_to_temp] t_current=%d\n", t_current);
return t_current;
}
static void mtktspmic_read_efuse(void)
{
mtktspmic_info("[pmic_debug] start\n");
g_o_vts = pmic_get_register_value(PMIC_AUXADC_EFUSE_O_VTS);
g_o_vts_2 = pmic_get_register_value(PMIC_AUXADC_EFUSE_O_VTS_2);
g_o_vts_3 = pmic_get_register_value(PMIC_AUXADC_EFUSE_O_VTS_3);
g_adc_cali_en = pmic_get_register_value(PMIC_AUXADC_EFUSE_ADC_CALI_EN);
g_degc_cali = pmic_get_register_value(PMIC_AUXADC_EFUSE_DEGC_CALI);
g_o_slope_sign = pmic_get_register_value(PMIC_AUXADC_EFUSE_O_SLOPE_SIGN);
g_o_slope = pmic_get_register_value(PMIC_AUXADC_EFUSE_O_SLOPE);
g_id = pmic_get_register_value(PMIC_AUXADC_EFUSE_ID);
mtktspmic_info("[pmic_debug] 6357_efuse: g_o_vts = %d\n", g_o_vts);
mtktspmic_info("[pmic_debug] 6357_efuse: g_o_vts_2 = %d\n", g_o_vts_2);
mtktspmic_info("[pmic_debug] 6357_efuse: g_o_vts_3 = %d\n", g_o_vts_3);
mtktspmic_info("[pmic_debug] 6357_efuse: g_degc_cali = %d\n", g_degc_cali);
mtktspmic_info("[pmic_debug] 6357_efuse: g_adc_cali_en = %d\n", g_adc_cali_en);
mtktspmic_info("[pmic_debug] 6357_efuse: g_o_slope = %d\n", g_o_slope);
mtktspmic_info("[pmic_debug] 6357_efuse: g_o_slope_sign = %d\n", g_o_slope_sign);
mtktspmic_info("[pmic_debug] 6357_efuse: g_id = %d\n", g_id);
mtktspmic_info("[pmic_debug] end\n");
}
void mtktspmic_cali_prepare(void)
{
mtktspmic_read_efuse();
if (g_id == 0)
g_o_slope = 0;
/* g_adc_cali_en=0;//FIX ME */
if (g_adc_cali_en == 0) { /* no calibration */
mtktspmic_info("[pmic_debug] It isn't calibration values\n");
g_o_vts = 1600;
g_o_vts_2 = 1600;
g_o_vts_3 = 1600;
g_degc_cali = 50;
g_o_slope = 0;
g_o_slope_sign = 0;
}
/*SW workaround patch for mt6755 E2*/
if (g_degc_cali < 38 || g_degc_cali > 60)
g_degc_cali = 53;
mtktspmic_info("[pmic_debug] g_o_vts = 0x%x\n", g_o_vts);
mtktspmic_info("[pmic_debug] g_o_vts_2 = 0x%x\n", g_o_vts_2);
mtktspmic_info("[pmic_debug] g_o_vts_3 = 0x%x\n", g_o_vts_3);
mtktspmic_info("[pmic_debug] g_degc_cali = 0x%x\n", g_degc_cali);
mtktspmic_info("[pmic_debug] g_adc_cali_en = 0x%x\n", g_adc_cali_en);
mtktspmic_info("[pmic_debug] g_o_slope = 0x%x\n", g_o_slope);
mtktspmic_info("[pmic_debug] g_o_slope_sign = 0x%x\n", g_o_slope_sign);
mtktspmic_info("[pmic_debug] g_id = 0x%x\n", g_id);
}
void mtktspmic_cali_prepare2(void)
{
__s32 vbe_t;
int factor;
factor = 1681;
g_slope1 = (100 * 1000 * 10); /* 1000 is for 0.001 degree */
if (g_o_slope_sign == 0)
g_slope2 = -(factor + g_o_slope);
else
g_slope2 = -(factor - g_o_slope);
vbe_t = (-1) * ((((g_o_vts) * 1800)) / 4096) * 1000;
if (g_o_slope_sign == 0)
g_intercept = (vbe_t * 1000) / (-(factor + g_o_slope * 10)); /*0.001 degree */
else
g_intercept = (vbe_t * 1000) / (-(factor - g_o_slope * 10)); /*0.001 degree */
g_intercept = g_intercept + (g_degc_cali * (1000 / 2)); /* 1000 is for 0.1 degree */
mtktspmic_info("[Thermal calibration] SLOPE1=%d SLOPE2=%d INTERCEPT=%d, Vbe = %d\n",
g_slope1, g_slope2, g_intercept, vbe_t);
factor = 1863;
g_tsbuck1_slope1 = (100 * 1000 * 10); /* 1000 is for 0.001 degree */
if (g_o_slope_sign == 0)
g_tsbuck1_slope2 = -(factor + g_o_slope);
else
g_tsbuck1_slope2 = -(factor - g_o_slope);
vbe_t = (-1) * ((((g_o_vts_2) * 1800)) / 4096) * 1000;
if (g_o_slope_sign == 0)
g_tsbuck1_intercept = (vbe_t * 1000) / (-(factor + g_o_slope * 10)); /*0.001 degree */
else
g_tsbuck1_intercept = (vbe_t * 1000) / (-(factor - g_o_slope * 10)); /*0.001 degree */
g_tsbuck1_intercept = g_tsbuck1_intercept + (g_degc_cali * (1000 / 2)); /* 1000 is for 0.1 degree */
mtktspmic_info("[Thermal calibration] SLOPE1=%d SLOPE2=%d INTERCEPT=%d, Vbe = %d\n",
g_tsbuck1_slope1, g_tsbuck1_slope2, g_tsbuck1_intercept, vbe_t);
factor = 1863;
g_tsbuck2_slope1 = (100 * 1000 * 10); /* 1000 is for 0.001 degree */
if (g_o_slope_sign == 0)
g_tsbuck2_slope2 = -(factor + g_o_slope);
else
g_tsbuck2_slope2 = -(factor - g_o_slope);
vbe_t = (-1) * ((((g_o_vts_3) * 1800)) / 4096) * 1000;
if (g_o_slope_sign == 0)
g_tsbuck2_intercept = (vbe_t * 1000) / (-(factor + g_o_slope * 10)); /*0.001 degree */
else
g_tsbuck2_intercept = (vbe_t * 1000) / (-(factor - g_o_slope * 10)); /*0.001 degree */
g_tsbuck2_intercept = g_tsbuck2_intercept + (g_degc_cali * (1000 / 2)); /* 1000 is for 0.1 degree */
mtktspmic_info("[Thermal calibration] SLOPE1=%d SLOPE2=%d INTERCEPT=%d, Vbe = %d\n",
g_tsbuck2_slope1, g_tsbuck2_slope2, g_tsbuck2_intercept, vbe_t);
}
int mtktspmic_get_hw_temp(void)
{
int temp = 0, temp1 = 0;
mutex_lock(&TSPMIC_lock);
temp = pmic_get_auxadc_value(AUXADC_LIST_MT6357_CHIP_TEMP);
temp1 = pmic_raw_to_temp(temp);
mtktspmic_dprintk("[pmic_debug] Raw=%d, T=%d\n", temp, temp1);
if ((temp1 > 100000) || (temp1 < -30000))
mtktspmic_info("[mtktspmic_get_hw_temp] raw=%d, PMIC T=%d", temp, temp1);
if ((temp1 > 150000) || (temp1 < -50000)) {
mtktspmic_info("[mtktspmic_get_hw_temp] temp(%d) too high, drop this data!\n",
temp1);
temp1 = pre_temp1;
} else if ((PMIC_counter != 0)
&& (((pre_temp1 - temp1) > 30000) || ((temp1 - pre_temp1) > 30000))) {
mtktspmic_info("[mtktspmic_get_hw_temp] temp diff too large, drop this data\n");
temp1 = pre_temp1;
} else {
/* update previous temp */
pre_temp1 = temp1;
mtktspmic_dprintk("[mtktspmic_get_hw_temp] pre_temp1=%d\n", pre_temp1);
if (PMIC_counter == 0)
PMIC_counter++;
}
mutex_unlock(&TSPMIC_lock);
return temp1;
}
int mt6357tsbuck1_get_hw_temp(void)
{
int temp = 0, temp1 = 0;
mutex_lock(&TSPMIC_lock);
temp = pmic_get_auxadc_value(AUXADC_LIST_MT6357_BUCK1_TEMP);
temp1 = tsbuck1_raw_to_temp(temp);
mtktspmic_dprintk("%s raw=%d T=%d\n", __func__, temp, temp1);
if ((temp1 > 100000) || (temp1 < -30000))
mtktspmic_info("%s raw=%d T=%d\n", __func__, temp, temp1);
if ((temp1 > 150000) || (temp1 < -50000)) {
mtktspmic_info("%s T=%d too high, drop it!\n", __func__,
temp1);
temp1 = pre_tsbuck1_temp1;
} else if ((tsbuck1_cnt != 0)
&& (((pre_tsbuck1_temp1 - temp1) > 30000) || ((temp1 - pre_tsbuck1_temp1) > 30000))) {
mtktspmic_info("%s delta temp too large, drop it!\n", __func__);
temp1 = pre_tsbuck1_temp1;
} else {
/* update previous temp */
pre_tsbuck1_temp1 = temp1;
mtktspmic_dprintk("%s pre_tsbuck1_temp1=%d\n", __func__, pre_tsbuck1_temp1);
if (tsbuck1_cnt == 0)
tsbuck1_cnt++;
}
mutex_unlock(&TSPMIC_lock);
return temp1;
}
int mt6357tsbuck2_get_hw_temp(void)
{
int temp = 0, temp1 = 0;
mutex_lock(&TSPMIC_lock);
temp = pmic_get_auxadc_value(AUXADC_LIST_MT6357_BUCK2_TEMP);
temp1 = tsbuck2_raw_to_temp(temp);
mtktspmic_dprintk("%s raw=%d T=%d\n", __func__, temp, temp1);
if ((temp1 > 100000) || (temp1 < -30000))
mtktspmic_info("%s raw=%d T=%d\n", __func__, temp, temp1);
if ((temp1 > 150000) || (temp1 < -50000)) {
mtktspmic_info("%s T=%d too high, drop it!\n", __func__,
temp1);
temp1 = pre_tsbuck2_temp1;
} else if ((tsbuck2_cnt != 0)
&& (((pre_tsbuck2_temp1 - temp1) > 30000) || ((temp1 - pre_tsbuck2_temp1) > 30000))) {
mtktspmic_info("%s delta temp too large, drop it!\n", __func__);
temp1 = pre_tsbuck2_temp1;
} else {
/* update previous temp */
pre_tsbuck2_temp1 = temp1;
mtktspmic_dprintk("%s pre_tsbuck2_temp1=%d\n", __func__, pre_tsbuck2_temp1);
if (tsbuck2_cnt == 0)
tsbuck2_cnt++;
}
mutex_unlock(&TSPMIC_lock);
return temp1;
}

1402
drivers/misc/mediatek/thermal/mt6739/src/mtk_tc.c
View File

File diff suppressed because it is too large Load Diff

517
drivers/misc/mediatek/thermal/mt6739/src/mtk_ts_6357buck1.c
View File

@@ -1,517 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static int doing_tz_unregister;
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2 && curr_temp < polling_trip_temp1, use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 150000, 110000, 100000, 90000, 80000, 70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = "sysrst.6357buck1";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long int mt6357tsbuck1_cur_temp;
/*
*static long int mt6357tsbuck1_start_temp;
*static long int mt6357tsbuck1_end_temp;
*/
/*=============================================================*/
static int mt6357tsbuck1_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6357tsbuck1_get_hw_temp();
mt6357tsbuck1_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6357tsbuck1_bind(struct thermal_zone_device *thermal, struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[mt6357tsbuck1_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[mt6357tsbuck1_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[mt6357tsbuck1_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[mt6357tsbuck1_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[mt6357tsbuck1_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[mt6357tsbuck1_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[mt6357tsbuck1_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[mt6357tsbuck1_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[mt6357tsbuck1_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[mt6357tsbuck1_bind] %s\n", cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[mt6357tsbuck1_bind] error binding cooling dev\n");
return -EINVAL;
}
mtktspmic_dprintk("[mt6357tsbuck1_bind] binding OK, %d\n", table_val);
return 0;
}
static int mt6357tsbuck1_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[mt6357tsbuck1_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[mt6357tsbuck1_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[mt6357tsbuck1_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[mt6357tsbuck1_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[mt6357tsbuck1_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[mt6357tsbuck1_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[mt6357tsbuck1_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[mt6357tsbuck1_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[mt6357tsbuck1_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[mt6357tsbuck1_unbind] %s\n", cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[mt6357tsbuck1_unbind] error unbinding cooling dev\n");
return -EINVAL;
}
mtktspmic_dprintk("[mt6357tsbuck1_unbind] unbinding OK\n");
return 0;
}
static int mt6357tsbuck1_get_mode(struct thermal_zone_device *thermal, enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6357tsbuck1_set_mode(struct thermal_zone_device *thermal, enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6357tsbuck1_get_trip_type(struct thermal_zone_device *thermal, int trip,
enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6357tsbuck1_get_trip_temp(struct thermal_zone_device *thermal, int trip,
int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6357tsbuck1_get_crit_temp(struct thermal_zone_device *thermal, int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6357tsbuck1_dev_ops = {
.bind = mt6357tsbuck1_bind,
.unbind = mt6357tsbuck1_unbind,
.get_temp = mt6357tsbuck1_get_temp,
.get_mode = mt6357tsbuck1_get_mode,
.set_mode = mt6357tsbuck1_set_mode,
.get_trip_type = mt6357tsbuck1_get_trip_type,
.get_trip_temp = mt6357tsbuck1_get_trip_temp,
.get_crit_temp = mt6357tsbuck1_get_crit_temp,
};
static int mt6357tsbuck1_sysrst_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6357tsbuck1_sysrst_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6357tsbuck1_sysrst_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("MT6357TSBUCK1 OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
#if 0 /* temp marked off to check temperature correctness. */
BUG();
#endif
}
return 0;
}
static struct thermal_cooling_device_ops mt6357tsbuck1_cooling_sysrst_ops = {
.get_max_state = mt6357tsbuck1_sysrst_get_max_state,
.get_cur_state = mt6357tsbuck1_sysrst_get_cur_state,
.set_cur_state = mt6357tsbuck1_sysrst_set_cur_state,
};
static int mt6357tsbuck1_read(struct seq_file *m, void *v)
{
seq_printf(m, "[mt6357tsbuck1_read] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
seq_printf(m, "trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7], trip_temp[8], trip_temp[9]);
seq_printf(m, "g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2], g_THERMAL_TRIP[3]);
seq_printf(m, "g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6], g_THERMAL_TRIP[7]);
seq_printf(m, "g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n", g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
seq_printf(m, "cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m, "cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s,time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6357tsbuck1_register_thermal(void);
static void mt6357tsbuck1_unregister_thermal(void);
static ssize_t mt6357tsbuck1_write(struct file *file, const char __user *buffer, size_t count,
loff_t *data)
{
int len = 0;
int i;
struct mt6357tsbuck1_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6357tsbuck1_data *ptr_mt6357tsbuck1_data;
ptr_mt6357tsbuck1_data = kmalloc(sizeof(*ptr_mt6357tsbuck1_data), GFP_KERNEL);
if (ptr_mt6357tsbuck1_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6357tsbuck1_data->desc) - 1)) ? count : (sizeof(ptr_mt6357tsbuck1_data->desc) - 1);
if (copy_from_user(ptr_mt6357tsbuck1_data->desc, buffer, len)) {
kfree(ptr_mt6357tsbuck1_data);
return 0;
}
ptr_mt6357tsbuck1_data->desc[len] = '\0';
if (sscanf
(ptr_mt6357tsbuck1_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6357tsbuck1_data->trip[0], &ptr_mt6357tsbuck1_data->t_type[0], ptr_mt6357tsbuck1_data->bind0,
&ptr_mt6357tsbuck1_data->trip[1], &ptr_mt6357tsbuck1_data->t_type[1], ptr_mt6357tsbuck1_data->bind1,
&ptr_mt6357tsbuck1_data->trip[2], &ptr_mt6357tsbuck1_data->t_type[2], ptr_mt6357tsbuck1_data->bind2,
&ptr_mt6357tsbuck1_data->trip[3], &ptr_mt6357tsbuck1_data->t_type[3], ptr_mt6357tsbuck1_data->bind3,
&ptr_mt6357tsbuck1_data->trip[4], &ptr_mt6357tsbuck1_data->t_type[4], ptr_mt6357tsbuck1_data->bind4,
&ptr_mt6357tsbuck1_data->trip[5], &ptr_mt6357tsbuck1_data->t_type[5], ptr_mt6357tsbuck1_data->bind5,
&ptr_mt6357tsbuck1_data->trip[6], &ptr_mt6357tsbuck1_data->t_type[6], ptr_mt6357tsbuck1_data->bind6,
&ptr_mt6357tsbuck1_data->trip[7], &ptr_mt6357tsbuck1_data->t_type[7], ptr_mt6357tsbuck1_data->bind7,
&ptr_mt6357tsbuck1_data->trip[8], &ptr_mt6357tsbuck1_data->t_type[8], ptr_mt6357tsbuck1_data->bind8,
&ptr_mt6357tsbuck1_data->trip[9], &ptr_mt6357tsbuck1_data->t_type[9], ptr_mt6357tsbuck1_data->bind9,
&ptr_mt6357tsbuck1_data->time_msec) == 32) {
mtktspmic_dprintk("[mt6357tsbuck1_write] mt6357tsbuck1_unregister_thermal\n");
mt6357tsbuck1_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT, "mt6357tsbuck1_write",
"Bad argument");
#endif
mtktspmic_dprintk("[mt6357tsbuck1_write] bad argument\n");
kfree(ptr_mt6357tsbuck1_data);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6357tsbuck1_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] = g_bind4[0] = g_bind5[0] =
g_bind6[0] = g_bind7[0] = g_bind8[0] = g_bind9[0] = '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6357tsbuck1_data->bind0[i];
g_bind1[i] = ptr_mt6357tsbuck1_data->bind1[i];
g_bind2[i] = ptr_mt6357tsbuck1_data->bind2[i];
g_bind3[i] = ptr_mt6357tsbuck1_data->bind3[i];
g_bind4[i] = ptr_mt6357tsbuck1_data->bind4[i];
g_bind5[i] = ptr_mt6357tsbuck1_data->bind5[i];
g_bind6[i] = ptr_mt6357tsbuck1_data->bind6[i];
g_bind7[i] = ptr_mt6357tsbuck1_data->bind7[i];
g_bind8[i] = ptr_mt6357tsbuck1_data->bind8[i];
g_bind9[i] = ptr_mt6357tsbuck1_data->bind9[i];
}
mtktspmic_dprintk("[mt6357tsbuck1_write] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2]);
mtktspmic_dprintk("g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6]);
mtktspmic_dprintk("g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
mtktspmic_dprintk("[mt6357tsbuck1_write] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk("cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6357tsbuck1_data->trip[i];
interval = ptr_mt6357tsbuck1_data->time_msec / 1000;
mtktspmic_dprintk("[mt6357tsbuck1_write] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
mtktspmic_dprintk("trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7], trip_temp[8]);
mtktspmic_dprintk("trip_9_temp=%d,time_ms=%d\n", trip_temp[9], interval * 1000);
mtktspmic_dprintk("[mt6357tsbuck1_write] mt6357tsbuck1_register_thermal\n");
mt6357tsbuck1_register_thermal();
kfree(ptr_mt6357tsbuck1_data);
return count;
}
mtktspmic_dprintk("[mt6357tsbuck1_write] bad argument\n");
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT, "mt6357tsbuck1_write",
"Bad argument");
#endif
kfree(ptr_mt6357tsbuck1_data);
return -EINVAL;
}
static void mt6357tsbuck1_cancel_thermal_timer(void)
{
/* cancel timer */
/* pr_debug("mtkts_pmic_cancel_thermal_timer\n"); */
/* stop thermal framework polling when entering deep idle */
if (thz_dev && !doing_tz_unregister)
cancel_delayed_work(&(thz_dev->poll_queue));
}
static void mt6357tsbuck1_start_thermal_timer(void)
{
/* pr_debug("mtkts_pmic_start_thermal_timer\n"); */
/* resume thermal framework polling when leaving deep idle */
if (thz_dev != NULL && interval != 0 && !doing_tz_unregister)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue),
round_jiffies(msecs_to_jiffies(1000)));
}
static int mt6357tsbuck1_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register("sysrst.6357buck1", NULL,
&mt6357tsbuck1_cooling_sysrst_ops);
return 0;
}
static int mt6357tsbuck1_register_thermal(void)
{
mtktspmic_dprintk("[mt6357tsbuck1_register_thermal]\n");
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register("mt6357tsbuck1", num_trip, NULL,
&mt6357tsbuck1_dev_ops, 0, 0, 0, interval * 1000);
return 0;
}
static void mt6357tsbuck1_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6357tsbuck1_unregister_thermal(void)
{
mtktspmic_dprintk("[mt6357tsbuck1_unregister_thermal]\n");
if (thz_dev) {
doing_tz_unregister = 1;
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
doing_tz_unregister = 0;
}
}
static int mt6357tsbuck1_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6357tsbuck1_read, NULL);
}
static const struct file_operations mt6357tsbuck1_fops = {
.owner = THIS_MODULE,
.open = mt6357tsbuck1_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6357tsbuck1_write,
.release = single_release,
};
static int __init mt6357tsbuck1_init(void)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6357tsbuck1_dir = NULL;
mtktspmic_info("[mt6357tsbuck1_init]\n");
mtktspmic_cali_prepare();
mtktspmic_cali_prepare2();
err = mt6357tsbuck1_register_cooler();
if (err)
return err;
err = mt6357tsbuck1_register_thermal();
if (err)
goto err_unreg;
mt6357tsbuck1_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6357tsbuck1_dir) {
mtktspmic_info("[%s]: mkdir /proc/driver/thermal failed\n", __func__);
} else {
entry =
proc_create("tz6357buck1", S_IRUGO | S_IWUSR | S_IWGRP, mt6357tsbuck1_dir,
&mt6357tsbuck1_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6357tsbuck1", mt6357tsbuck1_start_thermal_timer, mt6357tsbuck1_cancel_thermal_timer);
return 0;
err_unreg:
mt6357tsbuck1_unregister_cooler();
return err;
}
static void __exit mt6357tsbuck1_exit(void)
{
mtktspmic_info("[mt6357tsbuck1_exit]\n");
mt6357tsbuck1_unregister_thermal();
mt6357tsbuck1_unregister_cooler();
mtkTTimer_unregister("mt6357tsbuck1");
}
module_init(mt6357tsbuck1_init);
module_exit(mt6357tsbuck1_exit);

517
drivers/misc/mediatek/thermal/mt6739/src/mtk_ts_6357buck2.c
View File

@@ -1,517 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static int doing_tz_unregister;
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2 && curr_temp < polling_trip_temp1, use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 150000, 110000, 100000, 90000, 80000, 70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = "sysrst.6357buck2";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long int mt6357tsbuck2_cur_temp;
/*
*static long int mt6357tsbuck2_start_temp;
*static long int mt6357tsbuck2_end_temp;
*/
/*=============================================================*/
static int mt6357tsbuck2_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6357tsbuck2_get_hw_temp();
mt6357tsbuck2_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6357tsbuck2_bind(struct thermal_zone_device *thermal, struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[mt6357tsbuck2_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[mt6357tsbuck2_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[mt6357tsbuck2_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[mt6357tsbuck2_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[mt6357tsbuck2_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[mt6357tsbuck2_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[mt6357tsbuck2_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[mt6357tsbuck2_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[mt6357tsbuck2_bind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[mt6357tsbuck2_bind] %s\n", cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[mt6357tsbuck2_bind] error binding cooling dev\n");
return -EINVAL;
}
mtktspmic_dprintk("[mt6357tsbuck2_bind] binding OK, %d\n", table_val);
return 0;
}
static int mt6357tsbuck2_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[mt6357tsbuck2_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[mt6357tsbuck2_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[mt6357tsbuck2_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[mt6357tsbuck2_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[mt6357tsbuck2_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[mt6357tsbuck2_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[mt6357tsbuck2_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[mt6357tsbuck2_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[mt6357tsbuck2_unbind] %s\n", cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[mt6357tsbuck2_unbind] %s\n", cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[mt6357tsbuck2_unbind] error unbinding cooling dev\n");
return -EINVAL;
}
mtktspmic_dprintk("[mt6357tsbuck2_unbind] unbinding OK\n");
return 0;
}
static int mt6357tsbuck2_get_mode(struct thermal_zone_device *thermal, enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6357tsbuck2_set_mode(struct thermal_zone_device *thermal, enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6357tsbuck2_get_trip_type(struct thermal_zone_device *thermal, int trip,
enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6357tsbuck2_get_trip_temp(struct thermal_zone_device *thermal, int trip,
int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6357tsbuck2_get_crit_temp(struct thermal_zone_device *thermal, int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6357tsbuck2_dev_ops = {
.bind = mt6357tsbuck2_bind,
.unbind = mt6357tsbuck2_unbind,
.get_temp = mt6357tsbuck2_get_temp,
.get_mode = mt6357tsbuck2_get_mode,
.set_mode = mt6357tsbuck2_set_mode,
.get_trip_type = mt6357tsbuck2_get_trip_type,
.get_trip_temp = mt6357tsbuck2_get_trip_temp,
.get_crit_temp = mt6357tsbuck2_get_crit_temp,
};
static int mt6357tsbuck2_sysrst_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6357tsbuck2_sysrst_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6357tsbuck2_sysrst_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("MT6357TSBUCK2 OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
#if 0 /* temp marked off to check temperature correctness. */
BUG();
#endif
}
return 0;
}
static struct thermal_cooling_device_ops mt6357tsbuck2_cooling_sysrst_ops = {
.get_max_state = mt6357tsbuck2_sysrst_get_max_state,
.get_cur_state = mt6357tsbuck2_sysrst_get_cur_state,
.set_cur_state = mt6357tsbuck2_sysrst_set_cur_state,
};
static int mt6357tsbuck2_read(struct seq_file *m, void *v)
{
seq_printf(m, "[mt6357tsbuck2_read] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
seq_printf(m, "trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7], trip_temp[8], trip_temp[9]);
seq_printf(m, "g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2], g_THERMAL_TRIP[3]);
seq_printf(m, "g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6], g_THERMAL_TRIP[7]);
seq_printf(m, "g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n", g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
seq_printf(m, "cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m, "cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s,time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6357tsbuck2_register_thermal(void);
static void mt6357tsbuck2_unregister_thermal(void);
static ssize_t mt6357tsbuck2_write(struct file *file, const char __user *buffer, size_t count,
loff_t *data)
{
int len = 0;
int i;
struct mt6357tsbuck2_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6357tsbuck2_data *ptr_mt6357tsbuck2_data;
ptr_mt6357tsbuck2_data = kmalloc(sizeof(*ptr_mt6357tsbuck2_data), GFP_KERNEL);
if (ptr_mt6357tsbuck2_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6357tsbuck2_data->desc) - 1)) ? count : (sizeof(ptr_mt6357tsbuck2_data->desc) - 1);
if (copy_from_user(ptr_mt6357tsbuck2_data->desc, buffer, len)) {
kfree(ptr_mt6357tsbuck2_data);
return 0;
}
ptr_mt6357tsbuck2_data->desc[len] = '\0';
if (sscanf
(ptr_mt6357tsbuck2_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6357tsbuck2_data->trip[0], &ptr_mt6357tsbuck2_data->t_type[0], ptr_mt6357tsbuck2_data->bind0,
&ptr_mt6357tsbuck2_data->trip[1], &ptr_mt6357tsbuck2_data->t_type[1], ptr_mt6357tsbuck2_data->bind1,
&ptr_mt6357tsbuck2_data->trip[2], &ptr_mt6357tsbuck2_data->t_type[2], ptr_mt6357tsbuck2_data->bind2,
&ptr_mt6357tsbuck2_data->trip[3], &ptr_mt6357tsbuck2_data->t_type[3], ptr_mt6357tsbuck2_data->bind3,
&ptr_mt6357tsbuck2_data->trip[4], &ptr_mt6357tsbuck2_data->t_type[4], ptr_mt6357tsbuck2_data->bind4,
&ptr_mt6357tsbuck2_data->trip[5], &ptr_mt6357tsbuck2_data->t_type[5], ptr_mt6357tsbuck2_data->bind5,
&ptr_mt6357tsbuck2_data->trip[6], &ptr_mt6357tsbuck2_data->t_type[6], ptr_mt6357tsbuck2_data->bind6,
&ptr_mt6357tsbuck2_data->trip[7], &ptr_mt6357tsbuck2_data->t_type[7], ptr_mt6357tsbuck2_data->bind7,
&ptr_mt6357tsbuck2_data->trip[8], &ptr_mt6357tsbuck2_data->t_type[8], ptr_mt6357tsbuck2_data->bind8,
&ptr_mt6357tsbuck2_data->trip[9], &ptr_mt6357tsbuck2_data->t_type[9], ptr_mt6357tsbuck2_data->bind9,
&ptr_mt6357tsbuck2_data->time_msec) == 32) {
mtktspmic_dprintk("[mt6357tsbuck2_write] mt6357tsbuck2_unregister_thermal\n");
mt6357tsbuck2_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT, "mt6357tsbuck2_write",
"Bad argument");
#endif
mtktspmic_dprintk("[mt6357tsbuck2_write] bad argument\n");
kfree(ptr_mt6357tsbuck2_data);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6357tsbuck2_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] = g_bind4[0] = g_bind5[0] =
g_bind6[0] = g_bind7[0] = g_bind8[0] = g_bind9[0] = '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6357tsbuck2_data->bind0[i];
g_bind1[i] = ptr_mt6357tsbuck2_data->bind1[i];
g_bind2[i] = ptr_mt6357tsbuck2_data->bind2[i];
g_bind3[i] = ptr_mt6357tsbuck2_data->bind3[i];
g_bind4[i] = ptr_mt6357tsbuck2_data->bind4[i];
g_bind5[i] = ptr_mt6357tsbuck2_data->bind5[i];
g_bind6[i] = ptr_mt6357tsbuck2_data->bind6[i];
g_bind7[i] = ptr_mt6357tsbuck2_data->bind7[i];
g_bind8[i] = ptr_mt6357tsbuck2_data->bind8[i];
g_bind9[i] = ptr_mt6357tsbuck2_data->bind9[i];
}
mtktspmic_dprintk("[mt6357tsbuck2_write] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2]);
mtktspmic_dprintk("g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6]);
mtktspmic_dprintk("g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
mtktspmic_dprintk("[mt6357tsbuck2_write] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk("cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6357tsbuck2_data->trip[i];
interval = ptr_mt6357tsbuck2_data->time_msec / 1000;
mtktspmic_dprintk("[mt6357tsbuck2_write] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
mtktspmic_dprintk("trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7], trip_temp[8]);
mtktspmic_dprintk("trip_9_temp=%d,time_ms=%d\n", trip_temp[9], interval * 1000);
mtktspmic_dprintk("[mt6357tsbuck2_write] mt6357tsbuck2_register_thermal\n");
mt6357tsbuck2_register_thermal();
kfree(ptr_mt6357tsbuck2_data);
return count;
}
mtktspmic_dprintk("[mt6357tsbuck2_write] bad argument\n");
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT, "mt6357tsbuck2_write",
"Bad argument");
#endif
kfree(ptr_mt6357tsbuck2_data);
return -EINVAL;
}
static void mt6357tsbuck2_cancel_thermal_timer(void)
{
/* cancel timer */
/* pr_debug("mtkts_pmic_cancel_thermal_timer\n"); */
/* stop thermal framework polling when entering deep idle */
if (thz_dev && !doing_tz_unregister)
cancel_delayed_work(&(thz_dev->poll_queue));
}
static void mt6357tsbuck2_start_thermal_timer(void)
{
/* pr_debug("mtkts_pmic_start_thermal_timer\n"); */
/* resume thermal framework polling when leaving deep idle */
if (thz_dev != NULL && interval != 0 && !doing_tz_unregister)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue),
round_jiffies(msecs_to_jiffies(1000)));
}
static int mt6357tsbuck2_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register("sysrst.6357buck2", NULL,
&mt6357tsbuck2_cooling_sysrst_ops);
return 0;
}
static int mt6357tsbuck2_register_thermal(void)
{
mtktspmic_dprintk("[mt6357tsbuck2_register_thermal]\n");
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register("mt6357tsbuck2", num_trip, NULL,
&mt6357tsbuck2_dev_ops, 0, 0, 0, interval * 1000);
return 0;
}
static void mt6357tsbuck2_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6357tsbuck2_unregister_thermal(void)
{
mtktspmic_dprintk("[mt6357tsbuck2_unregister_thermal]\n");
if (thz_dev) {
doing_tz_unregister = 1;
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
doing_tz_unregister = 0;
}
}
static int mt6357tsbuck2_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6357tsbuck2_read, NULL);
}
static const struct file_operations mt6357tsbuck2_fops = {
.owner = THIS_MODULE,
.open = mt6357tsbuck2_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6357tsbuck2_write,
.release = single_release,
};
static int __init mt6357tsbuck2_init(void)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6357tsbuck2_dir = NULL;
mtktspmic_info("[mt6357tsbuck2_init]\n");
mtktspmic_cali_prepare();
mtktspmic_cali_prepare2();
err = mt6357tsbuck2_register_cooler();
if (err)
return err;
err = mt6357tsbuck2_register_thermal();
if (err)
goto err_unreg;
mt6357tsbuck2_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6357tsbuck2_dir) {
mtktspmic_info("[%s]: mkdir /proc/driver/thermal failed\n", __func__);
} else {
entry =
proc_create("tz6357buck2", S_IRUGO | S_IWUSR | S_IWGRP, mt6357tsbuck2_dir,
&mt6357tsbuck2_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6357tsbuck2", mt6357tsbuck2_start_thermal_timer, mt6357tsbuck2_cancel_thermal_timer);
return 0;
err_unreg:
mt6357tsbuck2_unregister_cooler();
return err;
}
static void __exit mt6357tsbuck2_exit(void)
{
mtktspmic_info("[mt6357tsbuck2_exit]\n");
mt6357tsbuck2_unregister_thermal();
mt6357tsbuck2_unregister_cooler();
mtkTTimer_unregister("mt6357tsbuck2");
}
module_init(mt6357tsbuck2_init);
module_exit(mt6357tsbuck2_exit);

14
drivers/misc/mediatek/thermal/mt6761/Makefile
View File

@@ -1,14 +0,0 @@
#
# Copyright (C) 2017 MediaTek Inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
obj-y += src/

56
drivers/misc/mediatek/thermal/mt6761/inc/clatm_initcfg.h
View File

@@ -1,56 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __CLATM_INITCFG_H__
#define __CLATM_INITCFG_H__
#define CLATM_SET_INIT_CFG (1)
#define CLATM_INIT_CFG_0_TARGET_TJ (75000)
#define CLATM_INIT_CFG_0_EXIT_POINT (10000)
#define CLATM_INIT_CFG_0_FIRST_STEP (2000)
#define CLATM_INIT_CFG_0_THETA_RISE (2)
#define CLATM_INIT_CFG_0_THETA_FALL (8)
#define CLATM_INIT_CFG_0_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_0_MIN_CPU_PWR (400)
#define CLATM_INIT_CFG_0_MAX_CPU_PWR (2000)
#define CLATM_INIT_CFG_0_MIN_GPU_PWR (200)
#define CLATM_INIT_CFG_0_MAX_GPU_PWR (700)
#define CLATM_INIT_CFG_1_TARGET_TJ (65000)
#define CLATM_INIT_CFG_1_EXIT_POINT (10000)
#define CLATM_INIT_CFG_1_FIRST_STEP (3000)
#define CLATM_INIT_CFG_1_THETA_RISE (2)
#define CLATM_INIT_CFG_1_THETA_FALL (8)
#define CLATM_INIT_CFG_1_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_1_MIN_CPU_PWR (300)
#define CLATM_INIT_CFG_1_MAX_CPU_PWR (3000)
#define CLATM_INIT_CFG_1_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_1_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_2_TARGET_TJ (75000)
#define CLATM_INIT_CFG_2_EXIT_POINT (10000)
#define CLATM_INIT_CFG_2_FIRST_STEP (3960)
#define CLATM_INIT_CFG_2_THETA_RISE (2)
#define CLATM_INIT_CFG_2_THETA_FALL (8)
#define CLATM_INIT_CFG_2_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_2_MIN_CPU_PWR (600)
#define CLATM_INIT_CFG_2_MAX_CPU_PWR (3960)
#define CLATM_INIT_CFG_2_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_2_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_ACTIVE_ATM_COOLER (0)
#define CLATM_INIT_CFG_CATM (0)
#define CLATM_INIT_CFG_PHPB_CPU_TT (10)
#define CLATM_INIT_CFG_PHPB_CPU_TP (10)
#define CLATM_INIT_CFG_PHPB_GPU_TT (80)
#define CLATM_INIT_CFG_PHPB_GPU_TP (80)
#define CLATM_INIT_HRTIMER_POLLING_DELAY (100)
#endif /* __CLATM_INITCFG_H__ */

142
drivers/misc/mediatek/thermal/mt6761/inc/mach/mtk_thermal.h
View File

@@ -1,142 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MT6761_THERMAL_H__
#define __MT6761_THERMAL_H__
#include <linux/module.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include "mt-plat/sync_write.h"
#if IS_ENABLED(CONFIG_MTK_GPU_SUPPORT)
#include "mtk_gpufreq.h"
#endif
/*
*Bank0: CA7L (TSMCU1)
*Bank3: GPU (TSMCU2)
*Bank4: SoC (TSMCU3)
*/
/*
* TC0: (TS_MCU1, TS_MCU2, TS_MCU3)
*/
enum thermal_sensor {
TS_MCU1 = 0,
TS_MCU2,
TS_MCU3,
TS_ENUM_MAX,
};
enum thermal_bank_name {
THERMAL_BANK0 = 0,
THERMAL_BANK3 = 1,
THERMAL_BANK4 = 2,
THERMAL_BANK_NUM
};
struct TS_PTPOD {
unsigned int ts_MTS;
unsigned int ts_BTS;
};
extern int mtktscpu_limited_dmips;
extern int tscpu_get_temperature_range(void);
/* Valid if it returns 1, invalid if it returns 0. */
extern int tscpu_is_temp_valid(void);
extern void get_thermal_slope_intercept
(struct TS_PTPOD *ts_info, enum thermal_bank_name ts_bank);
extern void set_taklking_flag(bool flag);
extern int tscpu_get_cpu_temp(void);
extern int tscpu_get_temp_by_bank(enum thermal_bank_name ts_bank);
#define THERMAL_WRAP_WR32(val, addr) \
mt_reg_sync_writel((val), ((void *)addr))
extern int get_immediate_gpu_wrap(void);
extern int get_immediate_cpuL_wrap(void);
extern int get_immediate_cpuLL_wrap(void);
extern int get_immediate_mcucci_wrap(void);
/* Added for DLPT. */
extern int tscpu_get_min_cpu_pwr(void);
extern int tscpu_get_min_gpu_pwr(void);
/* Five thermal sensors. */
enum mtk_thermal_sensor_cpu_id_met {
MTK_THERMAL_SENSOR_TS1 = 0,
MTK_THERMAL_SENSOR_TS2,
MTK_THERMAL_SENSOR_TS3,
ATM_CPU_LIMIT,
ATM_GPU_LIMIT,
MTK_THERMAL_SENSOR_CPU_COUNT
};
extern int tscpu_get_cpu_temp_met(enum mtk_thermal_sensor_cpu_id_met id);
typedef void (*met_thermalsampler_funcMET)(void);
extern void mt_thermalsampler_registerCB(met_thermalsampler_funcMET pCB);
extern void mtkTTimer_cancel_timer(void);
extern void mtkTTimer_start_timer(void);
extern int mtkts_bts_get_hw_temp(void);
extern int get_immediate_ts1_wrap(void);
extern int get_immediate_ts2_wrap(void);
extern int get_immediate_ts3_wrap(void);
extern int get_immediate_ts4_wrap(void);
extern int get_immediate_ts5_wrap(void);
extern int (*get_immediate_tsX[TS_ENUM_MAX])(void);
extern int is_cpu_power_unlimit(void); /* in mtk_ts_cpu.c */
extern int is_cpu_power_min(void); /* in mtk_ts_cpu.c */
extern int get_cpu_target_tj(void);
extern int get_cpu_target_offset(void);
extern int mtk_gpufreq_register
(struct mt_gpufreq_power_table_info *freqs, int num);
extern int get_target_tj(void);
extern int mtk_thermal_get_tpcb_target(void);
extern void thermal_set_big_core_speed
(unsigned int tempMonCtl1, unsigned int tempMonCtl2, unsigned int tempAhbPoll);
/* return value(1): cooler of abcct/abcct_lcmoff is deactive,
* and no thermal current limit.
*/
extern int mtk_cooler_is_abcct_unlimit(void);
#endif /* __MT6761_THERMAL_H__ */

11
drivers/misc/mediatek/thermal/mt6761/inc/mtk_cl_amddulthro.h
View File

@@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MT_CL_AMDDULTHRO_H__
#define __MT_CL_AMDDULTHRO_H__
extern int amddulthro_backoff(int level);
#endif /* __MT_CL_AMDDULTHRO_H__ */

29
drivers/misc/mediatek/thermal/mt6761/inc/mtk_cooler_setting.h
View File

@@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef _MTK_COOLER_SETTING_H
#define _MTK_COOLER_SETTING_H
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/* mtk_cooler_mutt.c */
/* 1: turn on MD throttle V2 cooler; 0: turn off */
#define FEATURE_MUTT_V2 (1)
/* mtk_cooler_mutt.c */
/* 1: turn on MD Thermal Warning Notification; 0: turn off */
#define FEATURE_THERMAL_DIAG (1)
/* mtk_cooler_mutt.c */
/* 1: turn on adaptive MD throttle cooler; 0: turn off */
#define FEATURE_ADAPTIVE_MUTT (1)
/* mtk_ta.c */
/* 1: turn on SPA; 0: turn off */
#define FEATURE_SPA (0)
#endif /* _MTK_COOLER_SETTING_H */

59
drivers/misc/mediatek/thermal/mt6761/inc/mtk_thermal_ipi.h
View File

@@ -1,59 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_THERMAL_IPI_H__
#define __MTK_THERMAL_IPI_H__
#ifdef CONFIG_MTK_TINYSYS_SSPM_SUPPORT
#define THERMAL_ENABLE_TINYSYS_SSPM (0)
#else
#define THERMAL_ENABLE_TINYSYS_SSPM (0)
#endif
#if THERMAL_ENABLE_TINYSYS_SSPM
#include "sspm_ipi.h"
#include <sspm_reservedmem_define.h>
#define THERMAL_SLOT_NUM (4)
/* IPI Msg type */
enum {
THERMAL_IPI_INIT_GRP1,
THERMAL_IPI_INIT_GRP2,
THERMAL_IPI_INIT_GRP3,
THERMAL_IPI_INIT_GRP4,
THERMAL_IPI_INIT_GRP5,
THERMAL_IPI_INIT_GRP6,
THERMAL_IPI_GET_TEMP,
THERMAL_IPI_SET_ATM_CFG_GRP1,
THERMAL_IPI_SET_ATM_CFG_GRP2,
THERMAL_IPI_SET_ATM_CFG_GRP3,
THERMAL_IPI_SET_ATM_CFG_GRP4,
THERMAL_IPI_SET_ATM_CFG_GRP5,
THERMAL_IPI_SET_ATM_CFG_GRP6,
THERMAL_IPI_SET_ATM_CFG_GRP7,
THERMAL_IPI_SET_ATM_CFG_GRP8,
THERMAL_IPI_SET_ATM_TTJ,
THERMAL_IPI_SET_ATM_EN,
THERMAL_IPI_GET_ATM_CPU_LIMIT,
THERMAL_IPI_GET_ATM_GPU_LIMIT,
NR_THERMAL_IPI
};
/* IPI Msg data structure */
struct thermal_ipi_data {
unsigned int cmd;
union {
struct {
int arg[THERMAL_SLOT_NUM - 1];
} data;
} u;
};
extern unsigned int thermal_to_sspm(unsigned int cmd,
struct thermal_ipi_data *thermal_data);
extern int atm_to_sspm(unsigned int cmd, int data_len,
struct thermal_ipi_data *thermal_data, int *ackData);
#endif /* THERMAL_ENABLE_TINYSYS_SSPM */
#endif

32
drivers/misc/mediatek/thermal/mt6761/inc/mtk_ts_setting.h
View File

@@ -1,32 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef _MTK_TS_SETTING_H
#define _MTK_TS_SETTING_H
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/* mtk_ts_pa.c */
/* 1: turn on MD UL throughput update; 0: turn off */
#define Feature_Thro_update (1)
/*
* Request HPM in Low temperature condition
*/
#define THERMAL_LT_SET_HPM (1)
#if THERMAL_LT_SET_HPM
extern int enter_hpm_temp;
extern int leave_hpm_temp;
extern int enable_hpm_temp;
#endif
/*In src/mtk_tc.c*/
extern int get_immediate_ts4_wrap(void);
#endif /* _MTK_TS_SETTING_H */

11
drivers/misc/mediatek/thermal/mt6761/inc/tmp_6311buck.h
View File

@@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TMP_6311BUCK_H__
#define __TMP_6311BUCK_H__
extern int is_ext_buck_exist(void);
#endif /* __TMP_6311BUCK_H__ */

31
drivers/misc/mediatek/thermal/mt6761/inc/tmp_battery.h
View File

@@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TMP_BATTERY_H__
#define __TMP_BATTERY_H__
#include <charging.h>
/* Extern two API functions from battery driver
* to limit max charging current.
*/
/**
* return value means charging current in mA
* -1 means error
* Implementation in mt_battery.c and mt_battery_fan5405.c
*/
extern int get_bat_charging_current_level(void);
/**
* current_limit means limit of charging current in mA
* -1 means no limit
* Implementation in mt_battery.c and mt_battery_fan5405.c
*/
extern int set_bat_charging_current_limit(int current_limit);
extern enum charger_type mt_get_charger_type(void);
extern int read_tbat_value(void);
#endif /* __TMP_BATTERY_H__ */

43
drivers/misc/mediatek/thermal/mt6761/inc/tmp_bts.h
View File

@@ -1,43 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TMP_BTS_H__
#define __TMP_BTS_H__
/* chip dependent */
#define APPLY_PRECISE_NTC_TABLE
#define APPLY_AUXADC_CALI_DATA
#define AUX_IN0_NTC (0)
#define AUX_IN1_NTC (1)
#define BTS_RAP_PULL_UP_R 390000 /* 390K, pull up resister */
#define BTS_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp
* default value -40 deg
*/
#define BTS_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTS_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTS_RAP_ADC_CHANNEL AUX_IN0_NTC /* default is 0 */
#define BTSMDPA_RAP_PULL_UP_R 390000 /* 390K, pull up resister */
#define BTSMDPA_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp
* default value -40 deg
*/
#define BTSMDPA_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTSMDPA_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTSMDPA_RAP_ADC_CHANNEL AUX_IN1_NTC /* default is 1 */
extern int IMM_GetOneChannelValue(int dwChannel, int data[4], int *rawdata);
extern int IMM_IsAdcInitReady(void);
#endif /* __TMP_BTS_H__ */

29
drivers/misc/mediatek/thermal/mt6761/inc/tmp_btscharger.h
View File

@@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TMP_BTS_CHARGER_H__
#define __TMP_BTS_CHARGER_H__
/* chip dependent */
#define APPLY_PRECISE_NTC_TABLE
#define APPLY_AUXADC_CALI_DATA
#define AUX_IN2_NTC (2)
/* 390K, pull up resister */
#define BTSCHARGER_RAP_PULL_UP_R 390000
/* base on 100K NTC temp
* default value -40 deg
*/
#define BTSCHARGER_TAP_OVER_CRITICAL_LOW 4397119
/* 1.8V ,pull up voltage */
#define BTSCHARGER_RAP_PULL_UP_VOLTAGE 1800
/* default is NCP15WF104F03RC(100K) */
#define BTSCHARGER_RAP_NTC_TABLE 7
#define BTSCHARGER_RAP_ADC_CHANNEL AUX_IN2_NTC /* default is 2 */
extern int IMM_GetOneChannelValue(int dwChannel, int data[4], int *rawdata);
extern int IMM_IsAdcInitReady(void);
#endif /* __TMP_BTS_CHARGER_H__ */

750
drivers/misc/mediatek/thermal/mt6761/inc/tscpu_settings.h
View File

@@ -1,750 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*
*/
#ifndef __TSCPU_SETTINGS_H__
#define __TSCPU_SETTINGS_H__
#include <linux/of.h>
#include <linux/of_address.h>
#include "mach/mtk_thermal.h"
#include "tzcpu_initcfg.h"
#include "clatm_initcfg.h"
#include <linux/platform_device.h>
/*=============================================================
* Genernal
*=============================================================
*/
#define MIN(_a_, _b_) ((_a_) > (_b_) ? (_b_) : (_a_))
#define MAX(_a_, _b_) ((_a_) > (_b_) ? (_a_) : (_b_))
#define _BIT_(_bit_) (unsigned int)(1 << (_bit_))
#define _BITMASK_(_bits_) (((unsigned int) -1 >> (31 - ((1) ? \
_bits_))) & ~((1U << ((0) ? _bits_)) - 1))
#define THERMAL_TPROFILE_INIT() long long thermal_pTime_us, \
thermal_cTime_us, thermal_diff_us
#define THERMAL_GET_PTIME() {thermal_pTime_us = thermal_get_current_time_us()}
#define THERMAL_GET_CTIME() {thermal_cTime_us = thermal_get_current_time_us()}
#define THERMAL_TIME_TH 3000
#define THERMAL_IS_TOO_LONG() \
do { \
thermal_diff_us = thermal_cTime_us - thermal_pTime_us; \
if (thermal_diff_us > THERMAL_TIME_TH) { \
pr_notice(TSCPU_LOG_TAG "%s: %llu us\n", \
__func__, thermal_diff_us); \
} else if (thermal_diff_us < 0) { \
pr_notice(TSCPU_LOG_TAG "Warning: tProfiling " \
"uses incorrect %s %d\n", __func__, __LINE__); \
} \
} while (0)
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/*Enable thermal controller CG*/
#define THERMAL_EBABLE_TC_CG
#define ENALBE_UART_LIMIT (0)
#define TEMP_EN_UART (80000)
#define TEMP_DIS_UART (85000)
#define TEMP_TOLERANCE (0)
#define ENALBE_SW_FILTER (0)
#define ATM_USES_PPM (1)
#define THERMAL_GET_AHB_BUS_CLOCK (0)
#define THERMAL_PERFORMANCE_PROFILE (0)
/* 1: turn on GPIO toggle monitor; 0: turn off */
#define THERMAL_GPIO_OUT_TOGGLE (0)
/* 1: turn on adaptive AP cooler; 0: turn off */
#define CPT_ADAPTIVE_AP_COOLER (1)
/* 1: turn on supports to MET logging; 0: turn off */
#define CONFIG_SUPPORT_MET_MTKTSCPU (0)
/* Thermal controller HW filtering function.
* Only 1, 2, 4, 8, 16 are valid values,
* they means one reading is a avg of X samples
*/
#define THERMAL_CONTROLLER_HW_FILTER (2) /* 1, 2, 4, 8, 16 */
/* 1: turn on thermal controller HW thermal protection; 0: turn off */
#define THERMAL_CONTROLLER_HW_TP (1)
/* 1: turn on fast polling in this sw module; 0: turn off */
#define MTKTSCPU_FAST_POLLING (1)
#if CPT_ADAPTIVE_AP_COOLER
#define MAX_CPT_ADAPTIVE_COOLERS (3)
#define THERMAL_HEADROOM (0)
#define CONTINUOUS_TM (1)
#define DYNAMIC_GET_GPU_POWER (1)
/* 1: turn on precise power budgeting; 0: turn off */
#define PRECISE_HYBRID_POWER_BUDGET (1)
#define PHPB_DEFAULT_ON (1)
#endif
/* 1: thermal driver fast polling, use hrtimer; 0: turn off */
/*#define THERMAL_DRV_FAST_POLL_HRTIMER (1)*/
/* 1: thermal driver update temp to MET directly, use hrtimer; 0: turn off */
#define THERMAL_DRV_UPDATE_TEMP_DIRECT_TO_MET (1)
/* Define this in tscpu_settings.h enables this feature.
* It polls CPU TS in hrtimer and run ATM in RT 98 kthread.
*/
#define FAST_RESPONSE_ATM (1)
#define THERMAL_INIT_VALUE (0xDA1)
/* 1: mtk_tc.c supports LVTS; 0: o.w. */
#define CFG_THERM_LVTS (0)
/*=============================================================
* Chip related
*=============================================================
*/
/* double check */
//#define TS_CONFIGURE TS_CON1_TM /* depend on CPU design*/
#define TS_CONFIGURE TS_CON0_TM /* depend on CPU design*/
#define TS_CONFIGURE_P TS_CON1_P /* depend on CPU design*/
#define TS_TURN_ON 0xFFFFFFCF /* turn on TS_CON1[5:4] 2'b 00
* 11001111 -> 0xCF ~(0x30
*/
//#define TS_TURN_OFF 0x00000030 /* turn off thermal*/
#define TS_TURN_OFF 0x30000000 /* turn off thermal*/
/*chip dependent*/
#define ADDRESS_INDEX_0 101
#define ADDRESS_INDEX_1 100
#define ADDRESS_INDEX_2 102
#define CLEAR_TEMP 26111
/* TSCON1 bit table */
#define TSCON0_bit_6_7_00 0x00 /* TSCON0[7:6]=2'b00*/
#define TSCON0_bit_6_7_01 0x40 /* TSCON0[7:6]=2'b01*/
#define TSCON0_bit_6_7_10 0x80 /* TSCON0[7:6]=2'b10*/
#define TSCON0_bit_6_7_11 0xc0 /* TSCON0[7:6]=2'b11*/
#define TSCON0_bit_6_7_MASK 0xc0
#define TSCON1_bit_4_5_00 0x00 /* TSCON1[5:4]=2'b00*/
#define TSCON1_bit_4_5_01 0x10 /* TSCON1[5:4]=2'b01*/
#define TSCON1_bit_4_5_10 0x20 /* TSCON1[5:4]=2'b10*/
#define TSCON1_bit_4_5_11 0x30 /* TSCON1[5:4]=2'b11*/
#define TSCON1_bit_4_5_MASK 0x30
#define TSCON1_bit_0_2_000 0x00 /*TSCON1[2:0]=3'b000*/
#define TSCON1_bit_0_2_001 0x01 /*TSCON1[2:0]=3'b001*/
#define TSCON1_bit_0_2_010 0x02 /*TSCON1[2:0]=3'b010*/
#define TSCON1_bit_0_2_011 0x03 /*TSCON1[2:0]=3'b011*/
#define TSCON1_bit_0_2_100 0x04 /*TSCON1[2:0]=3'b100*/
#define TSCON1_bit_0_2_101 0x05 /*TSCON1[2:0]=3'b101*/
#define TSCON1_bit_0_2_110 0x06 /*TSCON1[2:0]=3'b110*/
#define TSCON1_bit_0_2_111 0x07 /*TSCON1[2:0]=3'b111*/
#define TSCON1_bit_0_2_MASK 0x07
#define TSCON0_bit_29_28_00 0x00000000 /* TSCON0[29:28]=2'b00*/
#define TSCON0_bit_29_28_01 0x10000000 /* TSCON0[29:28]=2'b01*/
#define TSCON0_bit_29_28_10 0x20000000 /* TSCON0[29:28]=2'b10*/
#define TSCON0_bit_29_28_11 0x30000000 /* TSCON0[29:28]=2'b11*/
#define TSCON0_bit_29_28_MASK 0x30000000
/* ADC value to mcu */
/*chip dependent*/
#define TSCPU_NEW_FLOW 1
#if TSCPU_NEW_FLOW
#define TEMPADC_MCU1 \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_00)|(0x07&TSCON1_bit_0_2_000))
#define TEMPADC_MCU2 \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_00)|(0x07&TSCON1_bit_0_2_001))
#define TEMPADC_MCU3 \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_00)|(0x07&TSCON1_bit_0_2_010))
#define TEMPADC_MCU4 \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_00)|(0x07&TSCON1_bit_0_2_011))
#define TEMPADC_MCU5 \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_00)|(0x07&TSCON1_bit_0_2_100))
#define TEMPADC_ABB \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_01)|(0x07&TSCON1_bit_0_2_000))
#else
#define TEMPADC_MCU1 ((0x30&TSCON1_bit_4_5_00)|(0x07&TSCON1_bit_0_2_000))
#define TEMPADC_MCU2 ((0x30&TSCON1_bit_4_5_00)|(0x07&TSCON1_bit_0_2_001))
#define TEMPADC_MCU3 ((0x30&TSCON1_bit_4_5_00)|(0x07&TSCON1_bit_0_2_010))
#define TEMPADC_MCU4 ((0x30&TSCON1_bit_4_5_00)|(0x07&TSCON1_bit_0_2_011))
#define TEMPADC_MCU5 ((0x30&TSCON1_bit_4_5_00)|(0x07&TSCON1_bit_0_2_100))
#define TEMPADC_ABB ((0x30&TSCON1_bit_4_5_01)|(0x07&TSCON1_bit_0_2_000))
#endif
#define TS_FILL(n) {#n, n}
/*#define TS_LEN_ARRAY(name) (sizeof(name)/sizeof(name[0]))*/
#define MAX_TS_NAME 20
#define CPU_COOLER_NUM 34
#define MTK_TS_CPU_RT (0)
#ifdef CONFIG_MTK_AEE_IPANIC
#define CONFIG_THERMAL_AEE_RR_REC (1)
#else
#define CONFIG_THERMAL_AEE_RR_REC (0)
#endif
#define CFG_THERMAL_KERNEL_IGNORE_HOT_SENSOR (0)
/*=============================================================
*REG ACCESS
*=============================================================
*/
#define thermal_setl(addr, val) mt_reg_sync_writel(readl(addr) | \
(val), ((void *)addr))
#define thermal_clrl(addr, val) mt_reg_sync_writel(readl(addr) & \
~(val), ((void *)addr))
#define MTKTSCPU_TEMP_CRIT 120000 /* 120.000 degree Celsius */
#define y_curr_repeat_times 1
#define THERMAL_NAME "mtk-thermal-legacy"
#define TS_MS_TO_NS(x) (x * 1000 * 1000)
#if THERMAL_GET_AHB_BUS_CLOCK
#define THERMAL_MODULE_SW_CG_SET (therm_clk_infracfg_ao_base + 0x88)
#define THERMAL_MODULE_SW_CG_CLR (therm_clk_infracfg_ao_base + 0x8C)
#define THERMAL_MODULE_SW_CG_STA (therm_clk_infracfg_ao_base + 0x94)
#define THERMAL_CG (therm_clk_infracfg_ao_base + 0x80)
#define THERMAL_DCM (therm_clk_infracfg_ao_base + 0x70)
#endif
/*=============================================================
*LOG
*=============================================================
*/
#define TSCPU_LOG_TAG "[Thermal/TZ/CPU]"
#define tscpu_dprintk(fmt, args...) \
do { \
if (tscpu_debug_log == 1) { \
pr_notice(TSCPU_LOG_TAG fmt, ##args); \
} \
} while (0)
#define tscpu_printk(fmt, args...) pr_notice(TSCPU_LOG_TAG fmt, ##args)
#define tscpu_warn(fmt, args...) pr_notice(TSCPU_LOG_TAG fmt, ##args)
/*=============================================================
* Structures
*=============================================================
*/
enum thermal_controller_name {
THERMAL_CONTROLLER0 = 0,
THERMAL_CONTROLLER1,
THERMAL_CONTROLLER_NUM
};
struct thermal_controller_speed {
unsigned int tempMonCtl1;
unsigned int tempMonCtl2;
unsigned int tempAhbPoll;
};
struct thermal_controller {
enum thermal_sensor ts[TS_ENUM_MAX];
int ts_number;
int tc_offset;
struct thermal_controller_speed tc_speed;
};
#if (CONFIG_THERMAL_AEE_RR_REC == 1)
enum thermal_state {
TSCPU_SUSPEND = 0,
TSCPU_RESUME = 1,
TSCPU_NORMAL = 2,
TSCPU_INIT = 3,
TSCPU_PAUSE = 4,
TSCPU_RELEASE = 5
};
enum atm_state {
ATM_WAKEUP = 0,
ATM_CPULIMIT = 1,
ATM_GPULIMIT = 2,
ATM_DONE = 3,
};
#endif
struct mtk_cpu_power_info {
unsigned int cpufreq_khz;
unsigned int cpufreq_ncpu;
unsigned int cpufreq_power;
};
/*=============================================================
* Shared variables
*=============================================================
*/
/*In src/mtk_tc.c*/
extern int temp_eUART;
extern int temp_dUART;
extern int tscpu_debug_log;
extern const struct of_device_id mt_thermal_of_match[2];
extern int tscpu_ts_temp[TS_ENUM_MAX];
extern int tscpu_ts_temp_r[TS_ENUM_MAX]; /* raw data */
extern struct thermal_controller tscpu_g_tc[THERMAL_CONTROLLER_NUM];
extern int tscpu_polling_trip_temp1;
extern int tscpu_polling_trip_temp2;
extern int tscpu_polling_factor1;
extern int tscpu_polling_factor2;
#if MTKTSCPU_FAST_POLLING
/* Combined fast_polling_trip_temp and fast_polling_factor,
*it means polling_delay will be 1/5 of original interval
*after mtktscpu reports > 65C w/o exit point
*/
extern int fast_polling_trip_temp;
extern int fast_polling_trip_temp_high;
extern int fast_polling_factor;
extern int tscpu_cur_fp_factor;
extern int tscpu_next_fp_factor;
#endif
extern struct platform_device *tscpu_pdev;
/*In common/thermal_zones/mtk_ts_cpu.c*/
extern long long thermal_get_current_time_us(void);
extern void tscpu_workqueue_cancel_timer(void);
extern void tscpu_workqueue_start_timer(void);
extern void __iomem *therm_clk_infracfg_ao_base;
extern int Num_of_GPU_OPP;
extern int gpu_max_opp;
extern struct mt_gpufreq_power_table_info *mtk_gpu_power;
extern int tscpu_read_curr_temp;
#if MTKTSCPU_FAST_POLLING
extern int tscpu_cur_fp_factor;
#endif
#if !defined(CONFIG_MTK_CLKMGR)
extern struct clk *therm_main; /* main clock for Thermal*/
#endif
#if CPT_ADAPTIVE_AP_COOLER
extern int tscpu_g_curr_temp;
extern int tscpu_g_prev_temp;
#if (THERMAL_HEADROOM == 1) || (CONTINUOUS_TM == 1)
extern int bts_cur_temp; /* in mtk_ts_bts.c */
#endif
#if PRECISE_HYBRID_POWER_BUDGET
/* tscpu_prev_cpu_temp: previous CPUSYS temperature
* tscpu_curr_cpu_temp: current CPUSYS temperature
* tscpu_prev_gpu_temp: previous GPUSYS temperature
* tscpu_curr_gpu_temp: current GPUSYS temperature
*/
extern int tscpu_prev_cpu_temp, tscpu_prev_gpu_temp;
extern int tscpu_curr_cpu_temp, tscpu_curr_gpu_temp;
#endif
#endif
#ifdef CONFIG_OF
extern u32 thermal_irq_number;
extern void __iomem *thermal_base;
extern void __iomem *auxadc_ts_base;
extern void __iomem *infracfg_ao_base;
extern void __iomem *th_apmixed_base;
extern void __iomem *INFRACFG_AO_base;
extern int thermal_phy_base;
extern int auxadc_ts_phy_base;
extern int apmixed_phy_base;
extern int pericfg_phy_base;
#endif
extern char *adaptive_cooler_name;
/*common/coolers/mtk_cooler_atm.c*/
extern unsigned int adaptive_cpu_power_limit;
extern unsigned int adaptive_gpu_power_limit;
extern int TARGET_TJS[MAX_CPT_ADAPTIVE_COOLERS];
#ifdef FAST_RESPONSE_ATM
extern void atm_cancel_hrtimer(void);
extern void atm_restart_hrtimer(void);
#endif
/*common/coolers/mtk_cooler_dtm.c*/
extern unsigned int static_cpu_power_limit;
extern unsigned int static_gpu_power_limit;
extern int tscpu_cpu_dmips[CPU_COOLER_NUM];
/*=============================================================
* Shared functions
*=============================================================
*/
/*In common/thermal_zones/mtk_ts_cpu.c*/
extern void thermal_init_interrupt_for_UART(int temp_e, int temp_d);
extern void tscpu_update_tempinfo(void);
#if THERMAL_GPIO_OUT_TOGGLE
void tscpu_set_GPIO_toggle_for_monitor(void);
#endif
extern void tscpu_update_tempinfo(void);
extern int tscpu_max_temperature(void);
/*In src/mtk_tc.c*/
extern int get_io_reg_base(void);
extern void tscpu_config_all_tc_hw_protect(int temperature, int temperature2);
extern void tscpu_reset_thermal(void);
extern void tscpu_thermal_initial_all_tc(void);
extern void tscpu_thermal_read_tc_temp
(int tc_num, enum thermal_sensor type, int order);
extern void tscpu_thermal_cal_prepare(void);
extern void tscpu_thermal_cal_prepare_2(unsigned int ret);
extern irqreturn_t tscpu_thermal_all_tc_interrupt_handler
(int irq, void *dev_id);
extern int tscpu_thermal_clock_on(void);
extern int tscpu_thermal_clock_off(void);
extern int tscpu_read_temperature_info(struct seq_file *m, void *v);
extern int tscpu_thermal_fast_init(int tc_num);
extern int tscpu_get_curr_temp(void);
extern int tscpu_get_curr_max_ts_temp(void);
extern void thermal_get_AHB_clk_info(void);
extern void print_risky_temps(char *prefix, int offset, int printLevel);
extern void thermal_pause_all_periodoc_temp_sensing(void);
extern void thermal_release_all_periodoc_temp_sensing(void);
extern int (*max_temperature_in_bank[THERMAL_BANK_NUM])(void);
extern void thermal_disable_all_periodoc_temp_sensing(void);
/*
*In drivers/misc/mediatek/gpu/hal/mtk_gpu_utility.c
*It's not our api, ask them to provide header file
*/
extern bool mtk_get_gpu_loading(unsigned int *pLoading);
/*
*In drivers/misc/mediatek/auxadc/mt_auxadc.c
*It's not our api, ask them to provide header file
*/
extern int IMM_IsAdcInitReady(void);
#if defined(CATM_TPCB_EXTEND)
extern void mtk_thermal_get_turbo(void);
extern int g_turbo_bin;
#endif
/*aee related*/
#if (CONFIG_THERMAL_AEE_RR_REC == 1)
extern int aee_rr_init_thermal_temp(int num);
extern int aee_rr_rec_thermal_temp(int index, s8 val);
extern void aee_rr_rec_thermal_status(u8 val);
extern void aee_rr_rec_thermal_ATM_status(u8 val);
extern void aee_rr_rec_thermal_ktime(u64 val);
extern s8 aee_rr_curr_thermal_temp(int index);
extern u8 aee_rr_curr_thermal_status(void);
extern u8 aee_rr_curr_thermal_ATM_status(void);
extern u64 aee_rr_curr_thermal_ktime(void);
#endif
/*=============================================================
* Register macro for internal use
*=============================================================
*/
#if TSCPU_NEW_FLOW
extern void __iomem *thermal_base;
extern void __iomem *auxadc_base;
extern void __iomem *infracfg_ao_base;
extern void __iomem *th_apmixed_base;
extern void __iomem *INFRACFG_AO_base;
#define THERM_CTRL_BASE_2 thermal_base
#define AUXADC_BASE_2 auxadc_ts_base
#define INFRACFG_AO_BASE_2 infracfg_ao_base
#define APMIXED_BASE_2 th_apmixed_base
#else
#include <mach/mt_reg_base.h>
#define AUXADC_BASE_2 AUXADC_BASE
#define THERM_CTRL_BASE_2 THERM_CTRL_BASE
#define PERICFG_BASE_2 PERICFG_BASE
#define APMIXED_BASE_2 APMIXED_BASE
#endif
/*******************************************************************************
* AUXADC Register Definition
*****************************************************************************
*/
#define AUXADC_CON0_V (AUXADC_BASE_2 + 0x000)
#define AUXADC_CON1_V (AUXADC_BASE_2 + 0x004)
#define AUXADC_CON1_SET_V (AUXADC_BASE_2 + 0x008)
#define AUXADC_CON1_CLR_V (AUXADC_BASE_2 + 0x00C)
#define AUXADC_CON2_V (AUXADC_BASE_2 + 0x010)
/*#define AUXADC_CON3_V (AUXADC_BASE_2 + 0x014)*/
#define AUXADC_DAT0_V (AUXADC_BASE_2 + 0x014)
#define AUXADC_DAT1_V (AUXADC_BASE_2 + 0x018)
#define AUXADC_DAT2_V (AUXADC_BASE_2 + 0x01C)
#define AUXADC_DAT3_V (AUXADC_BASE_2 + 0x020)
#define AUXADC_DAT4_V (AUXADC_BASE_2 + 0x024)
#define AUXADC_DAT5_V (AUXADC_BASE_2 + 0x028)
#define AUXADC_DAT6_V (AUXADC_BASE_2 + 0x02C)
#define AUXADC_DAT7_V (AUXADC_BASE_2 + 0x030)
#define AUXADC_DAT8_V (AUXADC_BASE_2 + 0x034)
#define AUXADC_DAT9_V (AUXADC_BASE_2 + 0x038)
#define AUXADC_DAT10_V (AUXADC_BASE_2 + 0x03C)
#define AUXADC_DAT11_V (AUXADC_BASE_2 + 0x040)
#define AUXADC_MISC_V (AUXADC_BASE_2 + 0x094)
#define AUXADC_CON0_P (auxadc_ts_phy_base + 0x000)
#define AUXADC_CON1_P (auxadc_ts_phy_base + 0x004)
#define AUXADC_CON1_SET_P (auxadc_ts_phy_base + 0x008)
#define AUXADC_CON1_CLR_P (auxadc_ts_phy_base + 0x00C)
#define AUXADC_CON2_P (auxadc_ts_phy_base + 0x010)
/*#define AUXADC_CON3_P (auxadc_ts_phy_base + 0x014)*/
#define AUXADC_DAT0_P (auxadc_ts_phy_base + 0x014)
#define AUXADC_DAT1_P (auxadc_ts_phy_base + 0x018)
#define AUXADC_DAT2_P (auxadc_ts_phy_base + 0x01C)
#define AUXADC_DAT3_P (auxadc_ts_phy_base + 0x020)
#define AUXADC_DAT4_P (auxadc_ts_phy_base + 0x024)
#define AUXADC_DAT5_P (auxadc_ts_phy_base + 0x028)
#define AUXADC_DAT6_P (auxadc_ts_phy_base + 0x02C)
#define AUXADC_DAT7_P (auxadc_ts_phy_base + 0x030)
#define AUXADC_DAT8_P (auxadc_ts_phy_base + 0x034)
#define AUXADC_DAT9_P (auxadc_ts_phy_base + 0x038)
#define AUXADC_DAT10_P (auxadc_ts_phy_base + 0x03C)
#define AUXADC_DAT11_P (auxadc_ts_phy_base + 0x040)
#define AUXADC_MISC_P (auxadc_ts_phy_base + 0x094)
/*******************************************************************************
* Peripheral Configuration Register Definition
*****************************************************************************
*/
/*APB Module infracfg_ao*/
/*yes, 0x10000000*/
#define INFRA_GLOBALCON_RST_0_SET (INFRACFG_AO_BASE_2 + 0x120)
/*yes, 0x10000000*/
#define INFRA_GLOBALCON_RST_0_CLR (INFRACFG_AO_BASE_2 + 0x124)
/*yes, 0x10000000*/
#define INFRA_GLOBALCON_RST_0_STA (INFRACFG_AO_BASE_2 + 0x128)
/*******************************************************************************
* APMixedSys Configuration Register Definition
*****************************************************************************
*/
/* TODO: check base addr. */
#define TS_CON0_TM (APMIXED_BASE_2 + 0x600) /*yes 0x10212000*/
#define TS_CON1_TM (APMIXED_BASE_2 + 0x604)
#define TS_CON0_P (apmixed_phy_base + 0x600)
#define TS_CON1_P (apmixed_phy_base + 0x604)
/*******************************************************************************
* Thermal Controller Register Definition
*****************************************************************************
*/
#define TEMPMONCTL0 (THERM_CTRL_BASE_2 + 0x000)
#define TEMPMONCTL1 (THERM_CTRL_BASE_2 + 0x004)
#define TEMPMONCTL2 (THERM_CTRL_BASE_2 + 0x008)
#define TEMPMONINT (THERM_CTRL_BASE_2 + 0x00C)
#define TEMPMONINTSTS (THERM_CTRL_BASE_2 + 0x010)
#define TEMPMONIDET0 (THERM_CTRL_BASE_2 + 0x014)
#define TEMPMONIDET1 (THERM_CTRL_BASE_2 + 0x018)
#define TEMPMONIDET2 (THERM_CTRL_BASE_2 + 0x01C)
#define TEMPH2NTHRE (THERM_CTRL_BASE_2 + 0x024)
#define TEMPHTHRE (THERM_CTRL_BASE_2 + 0x028)
#define TEMPCTHRE (THERM_CTRL_BASE_2 + 0x02C)
#define TEMPOFFSETH (THERM_CTRL_BASE_2 + 0x030)
#define TEMPOFFSETL (THERM_CTRL_BASE_2 + 0x034)
#define TEMPMSRCTL0 (THERM_CTRL_BASE_2 + 0x038)
#define TEMPMSRCTL1 (THERM_CTRL_BASE_2 + 0x03C)
#define TEMPAHBPOLL (THERM_CTRL_BASE_2 + 0x040)
#define TEMPAHBTO (THERM_CTRL_BASE_2 + 0x044)
#define TEMPADCPNP0 (THERM_CTRL_BASE_2 + 0x048)
#define TEMPADCPNP1 (THERM_CTRL_BASE_2 + 0x04C)
#define TEMPADCPNP2 (THERM_CTRL_BASE_2 + 0x050)
#define TEMPADCMUX (THERM_CTRL_BASE_2 + 0x054)
#define TEMPADCEXT (THERM_CTRL_BASE_2 + 0x058)
#define TEMPADCEXT1 (THERM_CTRL_BASE_2 + 0x05C)
#define TEMPADCEN (THERM_CTRL_BASE_2 + 0x060)
#define TEMPPNPMUXADDR (THERM_CTRL_BASE_2 + 0x064)
#define TEMPADCMUXADDR (THERM_CTRL_BASE_2 + 0x068)
#define TEMPADCEXTADDR (THERM_CTRL_BASE_2 + 0x06C)
#define TEMPADCEXT1ADDR (THERM_CTRL_BASE_2 + 0x070)
#define TEMPADCENADDR (THERM_CTRL_BASE_2 + 0x074)
#define TEMPADCVALIDADDR (THERM_CTRL_BASE_2 + 0x078)
#define TEMPADCVOLTADDR (THERM_CTRL_BASE_2 + 0x07C)
#define TEMPRDCTRL (THERM_CTRL_BASE_2 + 0x080)
#define TEMPADCVALIDMASK (THERM_CTRL_BASE_2 + 0x084)
#define TEMPADCVOLTAGESHIFT (THERM_CTRL_BASE_2 + 0x088)
#define TEMPADCWRITECTRL (THERM_CTRL_BASE_2 + 0x08C)
#define TEMPMSR0 (THERM_CTRL_BASE_2 + 0x090)
#define TEMPMSR1 (THERM_CTRL_BASE_2 + 0x094)
#define TEMPMSR2 (THERM_CTRL_BASE_2 + 0x098)
#define TEMPADCHADDR (THERM_CTRL_BASE_2 + 0x09C)
#define TEMPIMMD0 (THERM_CTRL_BASE_2 + 0x0A0)
#define TEMPIMMD1 (THERM_CTRL_BASE_2 + 0x0A4)
#define TEMPIMMD2 (THERM_CTRL_BASE_2 + 0x0A8)
#define TEMPMONIDET3 (THERM_CTRL_BASE_2 + 0x0B0)
#define TEMPADCPNP3 (THERM_CTRL_BASE_2 + 0x0B4)
#define TEMPMSR3 (THERM_CTRL_BASE_2 + 0x0B8)
#define TEMPIMMD3 (THERM_CTRL_BASE_2 + 0x0BC)
#define TEMPPROTCTL (THERM_CTRL_BASE_2 + 0x0C0)
#define TEMPPROTTA (THERM_CTRL_BASE_2 + 0x0C4)
#define TEMPPROTTB (THERM_CTRL_BASE_2 + 0x0C8)
#define TEMPPROTTC (THERM_CTRL_BASE_2 + 0x0CC)
#define TEMPSPARE0 (THERM_CTRL_BASE_2 + 0x0F0)
#define TEMPSPARE1 (THERM_CTRL_BASE_2 + 0x0F4)
#define TEMPSPARE2 (THERM_CTRL_BASE_2 + 0x0F8)
#define TEMPSPARE3 (THERM_CTRL_BASE_2 + 0x0FC)
#define TEMPMONCTL0_1 (THERM_CTRL_BASE_2 + 0x100)
#define TEMPMONCTL1_1 (THERM_CTRL_BASE_2 + 0x104)
#define TEMPMONCTL2_1 (THERM_CTRL_BASE_2 + 0x108)
#define TEMPMONINT_1 (THERM_CTRL_BASE_2 + 0x10C)
#define TEMPMONINTSTS_1 (THERM_CTRL_BASE_2 + 0x110)
#define TEMPMONIDET0_1 (THERM_CTRL_BASE_2 + 0x114)
#define TEMPMONIDET1_1 (THERM_CTRL_BASE_2 + 0x118)
#define TEMPMONIDET2_1 (THERM_CTRL_BASE_2 + 0x11C)
#define TEMPH2NTHRE_1 (THERM_CTRL_BASE_2 + 0x124)
#define TEMPHTHRE_1 (THERM_CTRL_BASE_2 + 0x128)
#define TEMPCTHRE_1 (THERM_CTRL_BASE_2 + 0x12C)
#define TEMPOFFSETH_1 (THERM_CTRL_BASE_2 + 0x130)
#define TEMPOFFSETL_1 (THERM_CTRL_BASE_2 + 0x134)
#define TEMPMSRCTL0_1 (THERM_CTRL_BASE_2 + 0x138)
#define TEMPMSRCTL1_1 (THERM_CTRL_BASE_2 + 0x13C)
#define TEMPAHBPOLL_1 (THERM_CTRL_BASE_2 + 0x140)
#define TEMPAHBTO_1 (THERM_CTRL_BASE_2 + 0x144)
#define TEMPADCPNP0_1 (THERM_CTRL_BASE_2 + 0x148)
#define TEMPADCPNP1_1 (THERM_CTRL_BASE_2 + 0x14C)
#define TEMPADCPNP2_1 (THERM_CTRL_BASE_2 + 0x150)
#define TEMPADCMUX_1 (THERM_CTRL_BASE_2 + 0x154)
#define TEMPADCEXT_1 (THERM_CTRL_BASE_2 + 0x158)
#define TEMPADCEXT1_1 (THERM_CTRL_BASE_2 + 0x15C)
#define TEMPADCEN_1 (THERM_CTRL_BASE_2 + 0x160)
#define TEMPPNPMUXADDR_1 (THERM_CTRL_BASE_2 + 0x164)
#define TEMPADCMUXADDR_1 (THERM_CTRL_BASE_2 + 0x168)
#define TEMPADCEXTADDR_1 (THERM_CTRL_BASE_2 + 0x16C)
#define TEMPADCEXT1ADDR_1 (THERM_CTRL_BASE_2 + 0x170)
#define TEMPADCENADDR_1 (THERM_CTRL_BASE_2 + 0x174)
#define TEMPADCVALIDADDR_1 (THERM_CTRL_BASE_2 + 0x178)
#define TEMPADCVOLTADDR_1 (THERM_CTRL_BASE_2 + 0x17C)
#define TEMPRDCTRL_1 (THERM_CTRL_BASE_2 + 0x180)
#define TEMPADCVALIDMASK_1 (THERM_CTRL_BASE_2 + 0x184)
#define TEMPADCVOLTAGESHIFT_1 (THERM_CTRL_BASE_2 + 0x188)
#define TEMPADCWRITECTRL_1 (THERM_CTRL_BASE_2 + 0x18C)
#define TEMPMSR0_1 (THERM_CTRL_BASE_2 + 0x190)
#define TEMPMSR1_1 (THERM_CTRL_BASE_2 + 0x194)
#define TEMPMSR2_1 (THERM_CTRL_BASE_2 + 0x198)
#define TEMPADCHADDR_1 (THERM_CTRL_BASE_2 + 0x19C)
#define TEMPIMMD0_1 (THERM_CTRL_BASE_2 + 0x1A0)
#define TEMPIMMD1_1 (THERM_CTRL_BASE_2 + 0x1A4)
#define TEMPIMMD2_1 (THERM_CTRL_BASE_2 + 0x1A8)
#define TEMPMONIDET3_1 (THERM_CTRL_BASE_2 + 0x1B0)
#define TEMPADCPNP3_1 (THERM_CTRL_BASE_2 + 0x1B4)
#define TEMPMSR3_1 (THERM_CTRL_BASE_2 + 0x1B8)
#define TEMPIMMD3_1 (THERM_CTRL_BASE_2 + 0x1BC)
#define TEMPPROTCTL_1 (THERM_CTRL_BASE_2 + 0x1C0)
#define TEMPPROTTA_1 (THERM_CTRL_BASE_2 + 0x1C4)
#define TEMPPROTTB_1 (THERM_CTRL_BASE_2 + 0x1C8)
#define TEMPPROTTC_1 (THERM_CTRL_BASE_2 + 0x1CC)
#define TEMPSPARE0_1 (THERM_CTRL_BASE_2 + 0x1F0)
#define TEMPSPARE1_1 (THERM_CTRL_BASE_2 + 0x1F4)
#define TEMPSPARE2_1 (THERM_CTRL_BASE_2 + 0x1F8)
#define TEMPSPARE3_1 (THERM_CTRL_BASE_2 + 0x1FC)
#define PTPCORESEL (THERM_CTRL_BASE_2 + 0xF00)
#define THERMINTST (THERM_CTRL_BASE_2 + 0xF04)
#define PTPODINTST (THERM_CTRL_BASE_2 + 0xF08)
#define THSTAGE0ST (THERM_CTRL_BASE_2 + 0xF0C)
#define THSTAGE1ST (THERM_CTRL_BASE_2 + 0xF10)
#define THSTAGE2ST (THERM_CTRL_BASE_2 + 0xF14)
#define THAHBST0 (THERM_CTRL_BASE_2 + 0xF18)
#define THAHBST1 (THERM_CTRL_BASE_2 + 0xF1C)
#define PTPSPARE0 (THERM_CTRL_BASE_2 + 0xF20)
#define PTPSPARE1 (THERM_CTRL_BASE_2 + 0xF24)
#define PTPSPARE2 (THERM_CTRL_BASE_2 + 0xF28)
#define PTPSPARE3 (THERM_CTRL_BASE_2 + 0xF2C)
#define THSLPEVEB (THERM_CTRL_BASE_2 + 0xF30)
#define PTPSPARE0_P (thermal_phy_base + 0xF20)
#define PTPSPARE1_P (thermal_phy_base + 0xF24)
#define PTPSPARE2_P (thermal_phy_base + 0xF28)
#define PTPSPARE3_P (thermal_phy_base + 0xF2C)
/*******************************************************************************
* Thermal Controller Register Mask Definition
*****************************************************************************
*/
#define THERMAL_ENABLE_SEN0 0x1
#define THERMAL_ENABLE_SEN1 0x2
#define THERMAL_ENABLE_SEN2 0x4
#define THERMAL_MONCTL0_MASK 0x00000007
#define THERMAL_PUNT_MASK 0x00000FFF
#define THERMAL_FSINTVL_MASK 0x03FF0000
#define THERMAL_SPINTVL_MASK 0x000003FF
#define THERMAL_MON_INT_MASK 0x0007FFFF
#define THERMAL_MON_CINTSTS0 0x000001
#define THERMAL_MON_HINTSTS0 0x000002
#define THERMAL_MON_LOINTSTS0 0x000004
#define THERMAL_MON_HOINTSTS0 0x000008
#define THERMAL_MON_NHINTSTS0 0x000010
#define THERMAL_MON_CINTSTS1 0x000020
#define THERMAL_MON_HINTSTS1 0x000040
#define THERMAL_MON_LOINTSTS1 0x000080
#define THERMAL_MON_HOINTSTS1 0x000100
#define THERMAL_MON_NHINTSTS1 0x000200
#define THERMAL_MON_CINTSTS2 0x000400
#define THERMAL_MON_HINTSTS2 0x000800
#define THERMAL_MON_LOINTSTS2 0x001000
#define THERMAL_MON_HOINTSTS2 0x002000
#define THERMAL_MON_NHINTSTS2 0x004000
#define THERMAL_MON_TOINTSTS 0x008000
#define THERMAL_MON_IMMDINTSTS0 0x010000
#define THERMAL_MON_IMMDINTSTS1 0x020000
#define THERMAL_MON_IMMDINTSTS2 0x040000
#define THERMAL_MON_FILTINTSTS0 0x080000
#define THERMAL_MON_FILTINTSTS1 0x100000
#define THERMAL_MON_FILTINTSTS2 0x200000
#define THERMAL_tri_SPM_State0 0x20000000
#define THERMAL_tri_SPM_State1 0x40000000
#define THERMAL_tri_SPM_State2 0x80000000
#define THERMAL_MSRCTL0_MASK 0x00000007
#define THERMAL_MSRCTL1_MASK 0x00000038
#define THERMAL_MSRCTL2_MASK 0x000001C0
/*cpu core nums*/
#define TZCPU_NO_CPU_CORES CONFIG_NR_CPUS
#endif /* __TSCPU_SETTINGS_H__ */

44
drivers/misc/mediatek/thermal/mt6761/inc/tzbatt_initcfg.h
View File

@@ -1,44 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TZBATT_INITCFG_H__
#define __TZBATT_INITCFG_H__
#define TZBATT_SET_INIT_CFG (1)
#define TZBATT_INITCFG_INTERVAL (1)
#define TZBATT_INITCFG_NUM_TRIPS (3)
#define TZBATT_INITCFG_TRIP_0_TEMP (49000)
#define TZBATT_INITCFG_TRIP_0_COOLER "mtk-cl-bcct02"
#define TZBATT_INITCFG_TRIP_1_TEMP (48000)
#define TZBATT_INITCFG_TRIP_1_COOLER "mtk-cl-bcct01"
#define TZBATT_INITCFG_TRIP_2_TEMP (46000)
#define TZBATT_INITCFG_TRIP_2_COOLER "mtk-cl-bcct00"
#define TZBATT_INITCFG_TRIP_3_TEMP (45000)
#define TZBATT_INITCFG_TRIP_3_COOLER ""
#define TZBATT_INITCFG_TRIP_4_TEMP (44000)
#define TZBATT_INITCFG_TRIP_4_COOLER ""
#define TZBATT_INITCFG_TRIP_5_TEMP (43000)
#define TZBATT_INITCFG_TRIP_5_COOLER ""
#define TZBATT_INITCFG_TRIP_6_TEMP (42000)
#define TZBATT_INITCFG_TRIP_6_COOLER ""
#define TZBATT_INITCFG_TRIP_7_TEMP (41000)
#define TZBATT_INITCFG_TRIP_7_COOLER ""
#define TZBATT_INITCFG_TRIP_8_TEMP (40000)
#define TZBATT_INITCFG_TRIP_8_COOLER ""
#define TZBATT_INITCFG_TRIP_9_TEMP (39000)
#define TZBATT_INITCFG_TRIP_9_COOLER ""
#endif /* __TZBATT_INITCFG_H__ */

47
drivers/misc/mediatek/thermal/mt6761/inc/tzcpu_initcfg.h
View File

@@ -1,47 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TZCPU_INITCFG_H__
#define __TZCPU_INITCFG_H__
#define TZCPU_SET_INIT_CFG (1)
#define TZCPU_INITCFG_INTERVAL (40)
#define TZCPU_INITCFG_NUM_TRIPS (4)
#define TZCPU_INITCFG_TRIP_0_TEMP (117000)
#define TZCPU_INITCFG_TRIP_0_COOLER "mtktscpu-sysrst"
#define TZCPU_INITCFG_TRIP_1_TEMP (95000)
#define TZCPU_INITCFG_TRIP_1_COOLER "cpu00"
#define TZCPU_INITCFG_TRIP_2_TEMP (85000)
#define TZCPU_INITCFG_TRIP_2_COOLER "cpu03"
#define TZCPU_INITCFG_TRIP_3_TEMP (65000)
#define TZCPU_INITCFG_TRIP_3_COOLER "cpu_adaptive_0"
#define TZCPU_INITCFG_TRIP_4_TEMP (63000)
#define TZCPU_INITCFG_TRIP_4_COOLER ""
#define TZCPU_INITCFG_TRIP_5_TEMP (60000)
#define TZCPU_INITCFG_TRIP_5_COOLER ""
#define TZCPU_INITCFG_TRIP_6_TEMP (55000)
#define TZCPU_INITCFG_TRIP_6_COOLER ""
#define TZCPU_INITCFG_TRIP_7_TEMP (50000)
#define TZCPU_INITCFG_TRIP_7_COOLER ""
#define TZCPU_INITCFG_TRIP_8_TEMP (45000)
#define TZCPU_INITCFG_TRIP_8_COOLER ""
#define TZCPU_INITCFG_TRIP_9_TEMP (40000)
#define TZCPU_INITCFG_TRIP_9_COOLER ""
#endif /* __TZCPU_INITCFG_H__ */

33
drivers/misc/mediatek/thermal/mt6761/src/Makefile
View File

@@ -1,33 +0,0 @@
#
# Copyright (C) 2017 MediaTek Inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#THERMAL_CHIP_DRIVER_DIR := $(srctree)/drivers/misc/mediatek/thermal/$(MTK_PLATFORM)
THERMAL_CHIP_DRIVER_DIR := $(srctree)/drivers/misc/mediatek/thermal/mt6761
ccflags-y += -I$(THERMAL_CHIP_DRIVER_DIR)/inc
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/mt6761
ccflags-y += -I$(srctree)/drivers/misc/mediatek/gpu/hal/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/thermal/fakeHeader/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/mt6761
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/eem_v2/mt6761/inc/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/pmic/include/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/thermal/common/inc/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/include/
ccflags-y += -I$(srctree)/include/dt-bindings/
ccflags-y += -I$(srctree)/drivers/gpu/mediatek/gpufreq/include/
obj-$(CONFIG_THERMAL) += mtk_tc.o
#obj-$(CONFIG_THERMAL) += mtk_thermal_ipi.o
obj-$(CONFIG_THERMAL) += mtk_pmic_efuse.o
obj-$(CONFIG_THERMAL) += mtk_ts_6357buck1.o
obj-$(CONFIG_THERMAL) += mtk_ts_6357buck2.o

1689
drivers/misc/mediatek/thermal/mt6761/src/mtk_tc.c
View File

File diff suppressed because it is too large Load Diff

621
drivers/misc/mediatek/thermal/mt6761/src/mtk_ts_6357buck1.c
View File

@@ -1,621 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
//#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
#include <linux/mfd/mt6397/core.h>/* PMIC MFD core header */
#include <linux/regmap.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int isTimerCancelled;
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2
*&& curr_temp < polling_trip_temp1, use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = {150000, 110000, 100000, 90000, 80000,
70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = "sysrst.6357buck1";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long mt6357tsbuck1_cur_temp;
/*
*static long int mt6357tsbuck1_start_temp;
*static long int mt6357tsbuck1_end_temp;
*/
/*=============================================================*/
static int mt6357tsbuck1_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6357tsbuck1_get_hw_temp();
mt6357tsbuck1_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6357tsbuck1_bind
(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[%s] error binding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] binding OK, %d\n", __func__, table_val);
return 0;
}
static int mt6357tsbuck1_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[%s] error unbinding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] unbinding OK\n", __func__);
return 0;
}
static int mt6357tsbuck1_get_mode
(struct thermal_zone_device *thermal,
enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6357tsbuck1_set_mode
(struct thermal_zone_device *thermal,
enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6357tsbuck1_get_trip_type
(struct thermal_zone_device *thermal, int trip,
enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6357tsbuck1_get_trip_temp
(struct thermal_zone_device *thermal, int trip,
int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6357tsbuck1_get_crit_temp(
struct thermal_zone_device *thermal, int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6357tsbuck1_dev_ops = {
.bind = mt6357tsbuck1_bind,
.unbind = mt6357tsbuck1_unbind,
.get_temp = mt6357tsbuck1_get_temp,
.get_mode = mt6357tsbuck1_get_mode,
.set_mode = mt6357tsbuck1_set_mode,
.get_trip_type = mt6357tsbuck1_get_trip_type,
.get_trip_temp = mt6357tsbuck1_get_trip_temp,
.get_crit_temp = mt6357tsbuck1_get_crit_temp,
};
static int mt6357tsbuck1_sysrst_get_max_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6357tsbuck1_sysrst_get_cur_state(
struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6357tsbuck1_sysrst_set_cur_state(
struct thermal_cooling_device *cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("MT6357TSBUCK1 OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
}
return 0;
}
static struct thermal_cooling_device_ops mt6357tsbuck1_cooling_sysrst_ops = {
.get_max_state = mt6357tsbuck1_sysrst_get_max_state,
.get_cur_state = mt6357tsbuck1_sysrst_get_cur_state,
.set_cur_state = mt6357tsbuck1_sysrst_set_cur_state,
};
static int mt6357tsbuck1_read(struct seq_file *m, void *v)
{
seq_printf(m,
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
__func__,
trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
seq_printf(m,
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d, trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8], trip_temp[9]);
seq_printf(m,
"g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d, g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2],
g_THERMAL_TRIP[3]);
seq_printf(m,
"g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d, g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6],
g_THERMAL_TRIP[7]);
seq_printf(m,
"g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n", g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
seq_printf(m,
"cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m,
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s, time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6357tsbuck1_register_thermal(void);
static void mt6357tsbuck1_unregister_thermal(void);
static ssize_t mt6357tsbuck1_write(struct file *file,
const char __user *buffer, size_t count, loff_t *data)
{
int len = 0;
int i;
struct mt6357tsbuck1_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6357tsbuck1_data *ptr_mt6357tsbuck1_data;
ptr_mt6357tsbuck1_data = kmalloc(sizeof(*ptr_mt6357tsbuck1_data),
GFP_KERNEL);
if (ptr_mt6357tsbuck1_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6357tsbuck1_data->desc) - 1)) ? count :
(sizeof(ptr_mt6357tsbuck1_data->desc) - 1);
if (copy_from_user(ptr_mt6357tsbuck1_data->desc, buffer, len)) {
kfree(ptr_mt6357tsbuck1_data);
return 0;
}
ptr_mt6357tsbuck1_data->desc[len] = '\0';
if (sscanf
(ptr_mt6357tsbuck1_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6357tsbuck1_data->trip[0], &ptr_mt6357tsbuck1_data->t_type[0],
ptr_mt6357tsbuck1_data->bind0,
&ptr_mt6357tsbuck1_data->trip[1], &ptr_mt6357tsbuck1_data->t_type[1],
ptr_mt6357tsbuck1_data->bind1,
&ptr_mt6357tsbuck1_data->trip[2], &ptr_mt6357tsbuck1_data->t_type[2],
ptr_mt6357tsbuck1_data->bind2,
&ptr_mt6357tsbuck1_data->trip[3], &ptr_mt6357tsbuck1_data->t_type[3],
ptr_mt6357tsbuck1_data->bind3,
&ptr_mt6357tsbuck1_data->trip[4], &ptr_mt6357tsbuck1_data->t_type[4],
ptr_mt6357tsbuck1_data->bind4,
&ptr_mt6357tsbuck1_data->trip[5], &ptr_mt6357tsbuck1_data->t_type[5],
ptr_mt6357tsbuck1_data->bind5,
&ptr_mt6357tsbuck1_data->trip[6], &ptr_mt6357tsbuck1_data->t_type[6],
ptr_mt6357tsbuck1_data->bind6,
&ptr_mt6357tsbuck1_data->trip[7], &ptr_mt6357tsbuck1_data->t_type[7],
ptr_mt6357tsbuck1_data->bind7,
&ptr_mt6357tsbuck1_data->trip[8], &ptr_mt6357tsbuck1_data->t_type[8],
ptr_mt6357tsbuck1_data->bind8,
&ptr_mt6357tsbuck1_data->trip[9], &ptr_mt6357tsbuck1_data->t_type[9],
ptr_mt6357tsbuck1_data->bind9,
&ptr_mt6357tsbuck1_data->time_msec) == 32) {
down(&sem_mutex);
mtktspmic_dprintk(
"[%s] mt6357tsbuck1_unregister_thermal\n", __func__);
mt6357tsbuck1_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(
__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6357tsbuck1_write", "Bad argument");
#endif
mtktspmic_dprintk(
"[%s] bad argument\n", __func__);
kfree(ptr_mt6357tsbuck1_data);
up(&sem_mutex);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6357tsbuck1_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] =
g_bind4[0] = g_bind5[0] = g_bind6[0] = g_bind7[0] =
g_bind8[0] = g_bind9[0] = '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6357tsbuck1_data->bind0[i];
g_bind1[i] = ptr_mt6357tsbuck1_data->bind1[i];
g_bind2[i] = ptr_mt6357tsbuck1_data->bind2[i];
g_bind3[i] = ptr_mt6357tsbuck1_data->bind3[i];
g_bind4[i] = ptr_mt6357tsbuck1_data->bind4[i];
g_bind5[i] = ptr_mt6357tsbuck1_data->bind5[i];
g_bind6[i] = ptr_mt6357tsbuck1_data->bind6[i];
g_bind7[i] = ptr_mt6357tsbuck1_data->bind7[i];
g_bind8[i] = ptr_mt6357tsbuck1_data->bind8[i];
g_bind9[i] = ptr_mt6357tsbuck1_data->bind9[i];
}
mtktspmic_dprintk(
"[%s] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
__func__, g_THERMAL_TRIP[0], g_THERMAL_TRIP[1],
g_THERMAL_TRIP[2]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4],
g_THERMAL_TRIP[5],
g_THERMAL_TRIP[6]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
mtktspmic_dprintk(
"[%s] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
__func__, g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk(
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6357tsbuck1_data->trip[i];
interval = ptr_mt6357tsbuck1_data->time_msec / 1000;
mtktspmic_dprintk(
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
__func__,
trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
mtktspmic_dprintk(
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8]);
mtktspmic_dprintk(
"trip_9_temp=%d,time_ms=%d\n", trip_temp[9],
interval * 1000);
mtktspmic_dprintk(
"[%s]mt6357tsbuck1_register_thermal\n", __func__);
mt6357tsbuck1_register_thermal();
up(&sem_mutex);
kfree(ptr_mt6357tsbuck1_data);
return count;
}
mtktspmic_dprintk("[%s] bad argument\n", __func__);
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6357tsbuck1_write", "Bad argument");
#endif
kfree(ptr_mt6357tsbuck1_data);
return -EINVAL;
}
static void mt6357tsbuck1_cancel_thermal_timer(void)
{
/* cancel timer */
/* pr_debug("mtkts_pmic_cancel_thermal_timer\n"); */
/* stop thermal framework polling when entering deep idle */
if (down_trylock(&sem_mutex))
return;
if (thz_dev) {
cancel_delayed_work(&(thz_dev->poll_queue));
isTimerCancelled = 1;
}
up(&sem_mutex);
}
static void mt6357tsbuck1_start_thermal_timer(void)
{
/* pr_debug("mtkts_pmic_start_thermal_timer\n"); */
/* resume thermal framework polling when leaving deep idle */
if (!isTimerCancelled)
return;
isTimerCancelled = 0;
if (down_trylock(&sem_mutex))
return;
if (thz_dev != NULL && interval != 0)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue),
round_jiffies(msecs_to_jiffies(1000)));
up(&sem_mutex);
}
static int mt6357tsbuck1_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register(
"sysrst.6357buck1", NULL, &mt6357tsbuck1_cooling_sysrst_ops);
return 0;
}
static int mt6357tsbuck1_register_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register(
"mt6357tsbuck1", num_trip, NULL, &mt6357tsbuck1_dev_ops,
0, 0, 0, interval * 1000);
return 0;
}
static void mt6357tsbuck1_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6357tsbuck1_unregister_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
if (thz_dev) {
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
}
}
static int mt6357tsbuck1_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6357tsbuck1_read, NULL);
}
static const struct file_operations mt6357tsbuck1_fops = {
.owner = THIS_MODULE,
.open = mt6357tsbuck1_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6357tsbuck1_write,
.release = single_release,
};
static int mt6357_ts_buck1_probe(struct platform_device *pdev)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6357tsbuck1_dir = NULL;
struct mt6397_chip *chip;
chip = (struct mt6397_chip *)dev_get_drvdata(pdev->dev.parent);
mtktspmic_info("[%s]\n", __func__);
mtktspmic_cali_prepare(chip->regmap);
mtktspmic_cali_prepare2();
err = mt6357tsbuck1_register_cooler();
if (err)
return err;
err = mt6357tsbuck1_register_thermal();
if (err)
goto err_unreg;
mt6357tsbuck1_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6357tsbuck1_dir) {
mtktspmic_info("[%s]: mkdir /proc/driver/thermal failed\n",
__func__);
} else {
entry =
proc_create("tz6357buck1", 0664,
mt6357tsbuck1_dir, &mt6357tsbuck1_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6357tsbuck1",
mt6357tsbuck1_start_thermal_timer,
mt6357tsbuck1_cancel_thermal_timer);
return 0;
err_unreg:
mt6357tsbuck1_unregister_cooler();
return err;
}
static const struct of_device_id mt6357_ts_buck1_of_match[] = {
{.compatible = "mediatek,mt6357_ts_buck1",},
{},
};
MODULE_DEVICE_TABLE(of, mt6357_ts_buck1_of_match);
static struct platform_driver mt6357_ts_buck1_driver = {
.probe = mt6357_ts_buck1_probe,
.driver = {
.name = "mt6357_ts_buck1",
.of_match_table = mt6357_ts_buck1_of_match,
},
};
static int __init mt6357tsbuck1_init(void)
{
return platform_driver_register(&mt6357_ts_buck1_driver);
}
static void __exit mt6357tsbuck1_exit(void)
{
mtktspmic_info("[%s]\n", __func__);
mt6357tsbuck1_unregister_thermal();
mt6357tsbuck1_unregister_cooler();
mtkTTimer_unregister("mt6357tsbuck1");
platform_driver_unregister(&mt6357_ts_buck1_driver);
}
module_init(mt6357tsbuck1_init);
module_exit(mt6357tsbuck1_exit);
MODULE_DESCRIPTION("MEDIATEK Thermal zone PMIC buck1 temperature sensor");
MODULE_LICENSE("GPL v2");

626
drivers/misc/mediatek/thermal/mt6761/src/mtk_ts_6357buck2.c
View File

@@ -1,626 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
//#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
#include <linux/mfd/mt6397/core.h>/* PMIC MFD core header */
#include <linux/regmap.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int isTimerCancelled;
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2 && curr_temp < polling_trip_temp1,
* use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 150000, 110000, 100000, 90000,
80000, 70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = "sysrst.6357buck2";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long mt6357tsbuck2_cur_temp;
/*
*static long int mt6357tsbuck2_start_temp;
*static long int mt6357tsbuck2_end_temp;
*/
/*=============================================================*/
static int mt6357tsbuck2_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6357tsbuck2_get_hw_temp();
mt6357tsbuck2_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6357tsbuck2_bind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[%s] error binding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] binding OK, %d\n", __func__, table_val);
return 0;
}
static int mt6357tsbuck2_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[%s] error unbinding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] unbinding OK\n", __func__);
return 0;
}
static int mt6357tsbuck2_get_mode(struct thermal_zone_device *thermal,
enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6357tsbuck2_set_mode(struct thermal_zone_device *thermal,
enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6357tsbuck2_get_trip_type(struct thermal_zone_device *thermal,
int trip, enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6357tsbuck2_get_trip_temp(struct thermal_zone_device *thermal,
int trip, int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6357tsbuck2_get_crit_temp(struct thermal_zone_device *thermal,
int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6357tsbuck2_dev_ops = {
.bind = mt6357tsbuck2_bind,
.unbind = mt6357tsbuck2_unbind,
.get_temp = mt6357tsbuck2_get_temp,
.get_mode = mt6357tsbuck2_get_mode,
.set_mode = mt6357tsbuck2_set_mode,
.get_trip_type = mt6357tsbuck2_get_trip_type,
.get_trip_temp = mt6357tsbuck2_get_trip_temp,
.get_crit_temp = mt6357tsbuck2_get_crit_temp,
};
static int mt6357tsbuck2_sysrst_get_max_state(struct thermal_cooling_device
*cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6357tsbuck2_sysrst_get_cur_state(struct thermal_cooling_device
*cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6357tsbuck2_sysrst_set_cur_state(struct thermal_cooling_device
*cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("MT6357TSBUCK2 OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
}
return 0;
}
static struct thermal_cooling_device_ops mt6357tsbuck2_cooling_sysrst_ops = {
.get_max_state = mt6357tsbuck2_sysrst_get_max_state,
.get_cur_state = mt6357tsbuck2_sysrst_get_cur_state,
.set_cur_state = mt6357tsbuck2_sysrst_set_cur_state,
};
static int mt6357tsbuck2_read(struct seq_file *m, void *v)
{
seq_printf(m,
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
__func__, trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
seq_printf(m,
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8], trip_temp[9]);
seq_printf(m,
"g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d, g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2],
g_THERMAL_TRIP[3]);
seq_printf(m,
"g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d, g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6],
g_THERMAL_TRIP[7]);
seq_printf(m,
"g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
seq_printf(m,
"cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m,
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s, time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6357tsbuck2_register_thermal(void);
static void mt6357tsbuck2_unregister_thermal(void);
static ssize_t mt6357tsbuck2_write(struct file *file,
const char __user *buffer, size_t count, loff_t *data)
{
int len = 0;
int i;
struct mt6357tsbuck2_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6357tsbuck2_data *ptr_mt6357tsbuck2_data;
ptr_mt6357tsbuck2_data = kmalloc(sizeof(*ptr_mt6357tsbuck2_data),
GFP_KERNEL);
if (ptr_mt6357tsbuck2_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6357tsbuck2_data->desc) - 1)) ? count :
(sizeof(ptr_mt6357tsbuck2_data->desc) - 1);
if (copy_from_user(ptr_mt6357tsbuck2_data->desc, buffer, len)) {
kfree(ptr_mt6357tsbuck2_data);
return 0;
}
ptr_mt6357tsbuck2_data->desc[len] = '\0';
if (sscanf
(ptr_mt6357tsbuck2_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6357tsbuck2_data->trip[0],
&ptr_mt6357tsbuck2_data->t_type[0],
ptr_mt6357tsbuck2_data->bind0,
&ptr_mt6357tsbuck2_data->trip[1],
&ptr_mt6357tsbuck2_data->t_type[1],
ptr_mt6357tsbuck2_data->bind1,
&ptr_mt6357tsbuck2_data->trip[2],
&ptr_mt6357tsbuck2_data->t_type[2],
ptr_mt6357tsbuck2_data->bind2,
&ptr_mt6357tsbuck2_data->trip[3],
&ptr_mt6357tsbuck2_data->t_type[3],
ptr_mt6357tsbuck2_data->bind3,
&ptr_mt6357tsbuck2_data->trip[4],
&ptr_mt6357tsbuck2_data->t_type[4],
ptr_mt6357tsbuck2_data->bind4,
&ptr_mt6357tsbuck2_data->trip[5],
&ptr_mt6357tsbuck2_data->t_type[5],
ptr_mt6357tsbuck2_data->bind5,
&ptr_mt6357tsbuck2_data->trip[6],
&ptr_mt6357tsbuck2_data->t_type[6],
ptr_mt6357tsbuck2_data->bind6,
&ptr_mt6357tsbuck2_data->trip[7],
&ptr_mt6357tsbuck2_data->t_type[7],
ptr_mt6357tsbuck2_data->bind7,
&ptr_mt6357tsbuck2_data->trip[8],
&ptr_mt6357tsbuck2_data->t_type[8],
ptr_mt6357tsbuck2_data->bind8,
&ptr_mt6357tsbuck2_data->trip[9],
&ptr_mt6357tsbuck2_data->t_type[9],
ptr_mt6357tsbuck2_data->bind9,
&ptr_mt6357tsbuck2_data->time_msec) == 32) {
down(&sem_mutex);
mtktspmic_dprintk(
"[%s]mt6357tsbuck2_unregister_thermal\n", __func__);
mt6357tsbuck2_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(
__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6357tsbuck2_write", "Bad argument");
#endif
mtktspmic_dprintk(
"[%s] bad argument\n", __func__);
kfree(ptr_mt6357tsbuck2_data);
up(&sem_mutex);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6357tsbuck2_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] = g_bind4[0] =
g_bind5[0] =
g_bind6[0] = g_bind7[0] = g_bind8[0] = g_bind9[0] = '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6357tsbuck2_data->bind0[i];
g_bind1[i] = ptr_mt6357tsbuck2_data->bind1[i];
g_bind2[i] = ptr_mt6357tsbuck2_data->bind2[i];
g_bind3[i] = ptr_mt6357tsbuck2_data->bind3[i];
g_bind4[i] = ptr_mt6357tsbuck2_data->bind4[i];
g_bind5[i] = ptr_mt6357tsbuck2_data->bind5[i];
g_bind6[i] = ptr_mt6357tsbuck2_data->bind6[i];
g_bind7[i] = ptr_mt6357tsbuck2_data->bind7[i];
g_bind8[i] = ptr_mt6357tsbuck2_data->bind8[i];
g_bind9[i] = ptr_mt6357tsbuck2_data->bind9[i];
}
mtktspmic_dprintk(
"[%s] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
__func__, g_THERMAL_TRIP[0], g_THERMAL_TRIP[1],
g_THERMAL_TRIP[2]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4],
g_THERMAL_TRIP[5],
g_THERMAL_TRIP[6]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
mtktspmic_dprintk(
"[%s] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
__func__, g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk(
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6357tsbuck2_data->trip[i];
interval = ptr_mt6357tsbuck2_data->time_msec / 1000;
mtktspmic_dprintk(
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
__func__,
trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
mtktspmic_dprintk(
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8]);
mtktspmic_dprintk(
"trip_9_temp=%d,time_ms=%d\n", trip_temp[9],
interval * 1000);
mtktspmic_dprintk(
"[%s]mt6357tsbuck2_register_thermal\n", __func__);
mt6357tsbuck2_register_thermal();
up(&sem_mutex);
kfree(ptr_mt6357tsbuck2_data);
return count;
}
mtktspmic_dprintk("[%s] bad argument\n", __func__);
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6357tsbuck2_write", "Bad argument");
#endif
kfree(ptr_mt6357tsbuck2_data);
return -EINVAL;
}
static void mt6357tsbuck2_cancel_thermal_timer(void)
{
/* cancel timer */
/* pr_debug("mtkts_pmic_cancel_thermal_timer\n"); */
/* stop thermal framework polling when entering deep idle */
if (down_trylock(&sem_mutex))
return;
if (thz_dev) {
cancel_delayed_work(&(thz_dev->poll_queue));
isTimerCancelled = 1;
}
up(&sem_mutex);
}
static void mt6357tsbuck2_start_thermal_timer(void)
{
/* pr_debug("mtkts_pmic_start_thermal_timer\n"); */
/* resume thermal framework polling when leaving deep idle */
if (!isTimerCancelled)
return;
isTimerCancelled = 0;
if (down_trylock(&sem_mutex))
return;
if (thz_dev != NULL && interval != 0)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue), round_jiffies(msecs_to_jiffies(1000)));
up(&sem_mutex);
}
static int mt6357tsbuck2_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register(
"sysrst.6357buck2", NULL, &mt6357tsbuck2_cooling_sysrst_ops);
return 0;
}
static int mt6357tsbuck2_register_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register("mt6357tsbuck2",
num_trip, NULL, &mt6357tsbuck2_dev_ops,
0, 0, 0, interval * 1000);
return 0;
}
static void mt6357tsbuck2_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6357tsbuck2_unregister_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
if (thz_dev) {
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
}
}
static int mt6357tsbuck2_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6357tsbuck2_read, NULL);
}
static const struct file_operations mt6357tsbuck2_fops = {
.owner = THIS_MODULE,
.open = mt6357tsbuck2_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6357tsbuck2_write,
.release = single_release,
};
static int mt6357_ts_buck2_probe(struct platform_device *pdev)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6357tsbuck2_dir = NULL;
struct mt6397_chip *chip;
chip = (struct mt6397_chip *)dev_get_drvdata(pdev->dev.parent);
mtktspmic_info("[%s]\n", __func__);
mtktspmic_cali_prepare(chip->regmap);
mtktspmic_cali_prepare2();
err = mt6357tsbuck2_register_cooler();
if (err)
return err;
err = mt6357tsbuck2_register_thermal();
if (err)
goto err_unreg;
mt6357tsbuck2_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6357tsbuck2_dir) {
mtktspmic_info("[%s]: mkdir /proc/driver/thermal failed\n",
__func__);
} else {
entry =
proc_create("tz6357buck2", 0664,
mt6357tsbuck2_dir, &mt6357tsbuck2_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6357tsbuck2", mt6357tsbuck2_start_thermal_timer,
mt6357tsbuck2_cancel_thermal_timer);
return 0;
err_unreg:
mt6357tsbuck2_unregister_cooler();
return err;
}
static const struct of_device_id mt6357_ts_buck2_of_match[] = {
{.compatible = "mediatek,mt6357_ts_buck2",},
{},
};
MODULE_DEVICE_TABLE(of, mt6357_ts_buck2_of_match);
static struct platform_driver mt6357_ts_buck2_driver = {
.probe = mt6357_ts_buck2_probe,
.driver = {
.name = "mt6357_ts_buck2",
.of_match_table = mt6357_ts_buck2_of_match,
},
};
static int __init mt6357tsbuck2_init(void)
{
return platform_driver_register(&mt6357_ts_buck2_driver);
}
static void __exit mt6357tsbuck2_exit(void)
{
mtktspmic_info("[%s]\n", __func__);
mt6357tsbuck2_unregister_thermal();
mt6357tsbuck2_unregister_cooler();
mtkTTimer_unregister("mt6357tsbuck2");
platform_driver_unregister(&mt6357_ts_buck2_driver);
}
module_init(mt6357tsbuck2_init);
module_exit(mt6357tsbuck2_exit);

14
drivers/misc/mediatek/thermal/mt6765/Makefile
View File

@@ -1,14 +0,0 @@
#
# Copyright (C) 2017 MediaTek Inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
obj-y += src/

56
drivers/misc/mediatek/thermal/mt6765/inc/clatm_initcfg.h
View File

@@ -1,56 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __CLATM_INITCFG_H__
#define __CLATM_INITCFG_H__
#define CLATM_SET_INIT_CFG (1)
#define CLATM_INIT_CFG_0_TARGET_TJ (75000)
#define CLATM_INIT_CFG_0_EXIT_POINT (10000)
#define CLATM_INIT_CFG_0_FIRST_STEP (2000)
#define CLATM_INIT_CFG_0_THETA_RISE (2)
#define CLATM_INIT_CFG_0_THETA_FALL (8)
#define CLATM_INIT_CFG_0_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_0_MIN_CPU_PWR (400)
#define CLATM_INIT_CFG_0_MAX_CPU_PWR (2000)
#define CLATM_INIT_CFG_0_MIN_GPU_PWR (200)
#define CLATM_INIT_CFG_0_MAX_GPU_PWR (700)
#define CLATM_INIT_CFG_1_TARGET_TJ (65000)
#define CLATM_INIT_CFG_1_EXIT_POINT (10000)
#define CLATM_INIT_CFG_1_FIRST_STEP (3000)
#define CLATM_INIT_CFG_1_THETA_RISE (2)
#define CLATM_INIT_CFG_1_THETA_FALL (8)
#define CLATM_INIT_CFG_1_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_1_MIN_CPU_PWR (300)
#define CLATM_INIT_CFG_1_MAX_CPU_PWR (3000)
#define CLATM_INIT_CFG_1_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_1_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_2_TARGET_TJ (75000)
#define CLATM_INIT_CFG_2_EXIT_POINT (10000)
#define CLATM_INIT_CFG_2_FIRST_STEP (3960)
#define CLATM_INIT_CFG_2_THETA_RISE (2)
#define CLATM_INIT_CFG_2_THETA_FALL (8)
#define CLATM_INIT_CFG_2_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_2_MIN_CPU_PWR (600)
#define CLATM_INIT_CFG_2_MAX_CPU_PWR (3960)
#define CLATM_INIT_CFG_2_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_2_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_ACTIVE_ATM_COOLER (0)
#define CLATM_INIT_CFG_CATM (0)
#define CLATM_INIT_CFG_PHPB_CPU_TT (10)
#define CLATM_INIT_CFG_PHPB_CPU_TP (10)
#define CLATM_INIT_CFG_PHPB_GPU_TT (80)
#define CLATM_INIT_CFG_PHPB_GPU_TP (80)
#define CLATM_INIT_HRTIMER_POLLING_DELAY (100)
#endif /* __CLATM_INITCFG_H__ */

144
drivers/misc/mediatek/thermal/mt6765/inc/mach/mtk_thermal.h
View File

@@ -1,144 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MT6765_THERMAL_H__
#define __MT6765_THERMAL_H__
#include <linux/module.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include "mt-plat/sync_write.h"
#include "mtk_gpufreq.h"
/*
* Bank0: CPU-L (TS_MCU1)
* Bank1: CPU-LL (TS_MCU2)
* Bank2: CCI (TS_MCU1 + TS_MCU2)
* Bank3: GPU (TS_MCU3)
* Bank4: SoC (TS_MCU4 + TS_MCU5)
*/
enum thermal_sensor {
TS_MCU1 = 0,
TS_MCU2,
TS_MCU3,
TS_MCU4,
TS_MCU5,
TS_ENUM_MAX,
};
enum thermal_bank_name {
THERMAL_BANK0 = 0,
THERMAL_BANK1 = 1,
THERMAL_BANK2 = 2,
THERMAL_BANK3 = 3,
THERMAL_BANK4 = 4,
THERMAL_BANK_NUM
};
struct TS_PTPOD {
unsigned int ts_MTS;
unsigned int ts_BTS;
};
extern int mtktscpu_limited_dmips;
extern int tscpu_get_temperature_range(void);
/* Valid if it returns 1, invalid if it returns 0. */
extern int tscpu_is_temp_valid(void);
extern void get_thermal_slope_intercept
(struct TS_PTPOD *ts_info, enum thermal_bank_name ts_bank);
extern void set_taklking_flag(bool flag);
extern int tscpu_get_cpu_temp(void);
extern int tscpu_get_temp_by_bank(enum thermal_bank_name ts_bank);
#define THERMAL_WRAP_WR32(val, addr) \
mt_reg_sync_writel((val), ((void *)addr))
extern int get_immediate_gpu_wrap(void);
extern int get_immediate_cpuL_wrap(void);
extern int get_immediate_cpuLL_wrap(void);
extern int get_immediate_mcucci_wrap(void);
/* Added for DLPT. */
extern int tscpu_get_min_cpu_pwr(void);
extern int tscpu_get_min_gpu_pwr(void);
/* Five thermal sensors. */
enum mtk_thermal_sensor_cpu_id_met {
MTK_THERMAL_SENSOR_TS1 = 0,
MTK_THERMAL_SENSOR_TS2,
MTK_THERMAL_SENSOR_TS3,
MTK_THERMAL_SENSOR_TS4,
MTK_THERMAL_SENSOR_TS5,
ATM_CPU_LIMIT,
ATM_GPU_LIMIT,
MTK_THERMAL_SENSOR_CPU_COUNT
};
extern int tscpu_get_cpu_temp_met(enum mtk_thermal_sensor_cpu_id_met id);
typedef void (*met_thermalsampler_funcMET)(void);
extern void mt_thermalsampler_registerCB(met_thermalsampler_funcMET pCB);
extern void mtkTTimer_cancel_timer(void);
extern void mtkTTimer_start_timer(void);
extern int mtkts_bts_get_hw_temp(void);
extern int get_immediate_ts1_wrap(void);
extern int get_immediate_ts2_wrap(void);
extern int get_immediate_ts3_wrap(void);
extern int get_immediate_ts4_wrap(void);
extern int get_immediate_ts5_wrap(void);
extern int (*get_immediate_tsX[TS_ENUM_MAX])(void);
extern int is_cpu_power_unlimit(void); /* in mtk_ts_cpu.c */
extern int is_cpu_power_min(void); /* in mtk_ts_cpu.c */
extern int get_cpu_target_tj(void);
extern int get_cpu_target_offset(void);
extern int mtk_gpufreq_register
(struct mt_gpufreq_power_table_info *freqs, int num);
extern int get_target_tj(void);
extern int mtk_thermal_get_tpcb_target(void);
extern void thermal_set_big_core_speed
(unsigned int tempMonCtl1, unsigned int tempMonCtl2, unsigned int tempAhbPoll);
/* return value(1): cooler of abcct/abcct_lcmoff is deactive,
* and no thermal current limit.
*/
extern int mtk_cooler_is_abcct_unlimit(void);
#endif /* __MT6765_THERMAL_H__ */

11
drivers/misc/mediatek/thermal/mt6765/inc/mtk_cl_amddulthro.h
View File

@@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MT_CL_AMDDULTHRO_H__
#define __MT_CL_AMDDULTHRO_H__
extern int amddulthro_backoff(int level);
#endif /* __MT_CL_AMDDULTHRO_H__ */

29
drivers/misc/mediatek/thermal/mt6765/inc/mtk_cooler_setting.h
View File

@@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef _MTK_COOLER_SETTING_H
#define _MTK_COOLER_SETTING_H
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/* mtk_cooler_mutt.c */
/* 1: turn on MD throttle V2 cooler; 0: turn off */
#define FEATURE_MUTT_V2 (1)
/* mtk_cooler_mutt.c */
/* 1: turn on MD Thermal Warning Notification; 0: turn off */
#define FEATURE_THERMAL_DIAG (1)
/* mtk_cooler_mutt.c */
/* 1: turn on adaptive MD throttle cooler; 0: turn off */
#define FEATURE_ADAPTIVE_MUTT (1)
/* mtk_ta.c */
/* 1: turn on SPA; 0: turn off */
#define FEATURE_SPA (0)
#endif /* _MTK_COOLER_SETTING_H */

59
drivers/misc/mediatek/thermal/mt6765/inc/mtk_thermal_ipi.h
View File

@@ -1,59 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_THERMAL_IPI_H__
#define __MTK_THERMAL_IPI_H__
#ifdef CONFIG_MTK_TINYSYS_SSPM_SUPPORT
#define THERMAL_ENABLE_TINYSYS_SSPM (0)
#else
#define THERMAL_ENABLE_TINYSYS_SSPM (0)
#endif
#if THERMAL_ENABLE_TINYSYS_SSPM
#include "sspm_ipi.h"
#include <sspm_reservedmem_define.h>
#define THERMAL_SLOT_NUM (4)
/* IPI Msg type */
enum {
THERMAL_IPI_INIT_GRP1,
THERMAL_IPI_INIT_GRP2,
THERMAL_IPI_INIT_GRP3,
THERMAL_IPI_INIT_GRP4,
THERMAL_IPI_INIT_GRP5,
THERMAL_IPI_INIT_GRP6,
THERMAL_IPI_GET_TEMP,
THERMAL_IPI_SET_ATM_CFG_GRP1,
THERMAL_IPI_SET_ATM_CFG_GRP2,
THERMAL_IPI_SET_ATM_CFG_GRP3,
THERMAL_IPI_SET_ATM_CFG_GRP4,
THERMAL_IPI_SET_ATM_CFG_GRP5,
THERMAL_IPI_SET_ATM_CFG_GRP6,
THERMAL_IPI_SET_ATM_CFG_GRP7,
THERMAL_IPI_SET_ATM_CFG_GRP8,
THERMAL_IPI_SET_ATM_TTJ,
THERMAL_IPI_SET_ATM_EN,
THERMAL_IPI_GET_ATM_CPU_LIMIT,
THERMAL_IPI_GET_ATM_GPU_LIMIT,
NR_THERMAL_IPI
};
/* IPI Msg data structure */
struct thermal_ipi_data {
unsigned int cmd;
union {
struct {
int arg[THERMAL_SLOT_NUM - 1];
} data;
} u;
};
extern unsigned int thermal_to_sspm(unsigned int cmd,
struct thermal_ipi_data *thermal_data);
extern int atm_to_sspm(unsigned int cmd, int data_len,
struct thermal_ipi_data *thermal_data, int *ackData);
#endif /* THERMAL_ENABLE_TINYSYS_SSPM */
#endif

32
drivers/misc/mediatek/thermal/mt6765/inc/mtk_ts_setting.h
View File

@@ -1,32 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef _MTK_TS_SETTING_H
#define _MTK_TS_SETTING_H
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/* mtk_ts_pa.c */
/* 1: turn on MD UL throughput update; 0: turn off */
#define Feature_Thro_update (1)
/*
* Request HPM in Low temperature condition
*/
#define THERMAL_LT_SET_HPM (1)
#if THERMAL_LT_SET_HPM
extern int enter_hpm_temp;
extern int leave_hpm_temp;
extern int enable_hpm_temp;
#endif
/*In src/mtk_tc.c*/
extern int get_immediate_ts4_wrap(void);
#endif /* _MTK_TS_SETTING_H */

11
drivers/misc/mediatek/thermal/mt6765/inc/tmp_6311buck.h
View File

@@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TMP_6311BUCK_H__
#define __TMP_6311BUCK_H__
extern int is_ext_buck_exist(void);
#endif /* __TMP_6311BUCK_H__ */

31
drivers/misc/mediatek/thermal/mt6765/inc/tmp_battery.h
View File

@@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TMP_BATTERY_H__
#define __TMP_BATTERY_H__
#include <charging.h>
/* Extern two API functions from battery driver
* to limit max charging current.
*/
/**
* return value means charging current in mA
* -1 means error
* Implementation in mt_battery.c and mt_battery_fan5405.c
*/
extern int get_bat_charging_current_level(void);
/**
* current_limit means limit of charging current in mA
* -1 means no limit
* Implementation in mt_battery.c and mt_battery_fan5405.c
*/
extern int set_bat_charging_current_limit(int current_limit);
extern enum charger_type mt_get_charger_type(void);
extern int read_tbat_value(void);
#endif /* __TMP_BATTERY_H__ */

44
drivers/misc/mediatek/thermal/mt6765/inc/tmp_bts.h
View File

@@ -1,44 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TMP_BTS_H__
#define __TMP_BTS_H__
/* chip dependent */
#define APPLY_PRECISE_NTC_TABLE
#define APPLY_AUXADC_CALI_DATA
#define AUX_IN0_NTC (0)
#define AUX_IN1_NTC (1)
#define BTS_RAP_PULL_UP_R 390000 /* 390K, pull up resister */
#define BTS_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp
* default value -40 deg
*/
#define BTS_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTS_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTS_RAP_ADC_CHANNEL AUX_IN0_NTC /* default is 0 */
#define BTSMDPA_RAP_PULL_UP_R 390000 /* 390K, pull up resister */
#define BTSMDPA_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp
* default value -40 deg
*/
#define BTSMDPA_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTSMDPA_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTSMDPA_RAP_ADC_CHANNEL AUX_IN1_NTC /* default is 1 */
extern int IMM_GetOneChannelValue(int dwChannel, int data[4], int *rawdata);
extern int IMM_IsAdcInitReady(void);
#endif /* __TMP_BTS_H__ */

30
drivers/misc/mediatek/thermal/mt6765/inc/tmp_btscharger.h
View File

@@ -1,30 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TMP_BTS_CHARGER_H__
#define __TMP_BTS_CHARGER_H__
/* chip dependent */
#define APPLY_PRECISE_NTC_TABLE
#define APPLY_AUXADC_CALI_DATA
#define AUX_IN2_NTC (2)
/* 390K, pull up resister */
#define BTSCHARGER_RAP_PULL_UP_R 390000
/* base on 100K NTC temp
* default value -40 deg
*/
#define BTSCHARGER_TAP_OVER_CRITICAL_LOW 4397119
/* 1.8V ,pull up voltage */
#define BTSCHARGER_RAP_PULL_UP_VOLTAGE 1800
/* default is NCP15WF104F03RC(100K) */
#define BTSCHARGER_RAP_NTC_TABLE 7
#define BTSCHARGER_RAP_ADC_CHANNEL AUX_IN2_NTC /* default is 2 */
extern int IMM_GetOneChannelValue(int dwChannel, int data[4], int *rawdata);
extern int IMM_IsAdcInitReady(void);
#endif /* __TMP_BTS_CHARGER_H__ */

725
drivers/misc/mediatek/thermal/mt6765/inc/tscpu_settings.h
View File

@@ -1,725 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TSCPU_SETTINGS_H__
#define __TSCPU_SETTINGS_H__
#include <linux/of.h>
#include <linux/of_address.h>
#include "mach/mtk_thermal.h"
#include "tzcpu_initcfg.h"
#include "clatm_initcfg.h"
#include <linux/platform_device.h>
/*=============================================================
* Genernal
*=============================================================
*/
#define MIN(_a_, _b_) ((_a_) > (_b_) ? (_b_) : (_a_))
#define MAX(_a_, _b_) ((_a_) > (_b_) ? (_a_) : (_b_))
#define _BIT_(_bit_) (unsigned int)(1 << (_bit_))
#define _BITMASK_(_bits_) (((unsigned int) -1 >> (31 - ((1) ? \
_bits_))) & ~((1U << ((0) ? _bits_)) - 1))
#define THERMAL_TPROFILE_INIT() long long thermal_pTime_us, \
thermal_cTime_us, thermal_diff_us
#define THERMAL_GET_PTIME() {thermal_pTime_us = thermal_get_current_time_us()}
#define THERMAL_GET_CTIME() {thermal_cTime_us = thermal_get_current_time_us()}
#define THERMAL_TIME_TH 3000
#define THERMAL_IS_TOO_LONG() \
do { \
thermal_diff_us = thermal_cTime_us - thermal_pTime_us; \
if (thermal_diff_us > THERMAL_TIME_TH) { \
pr_notice(TSCPU_LOG_TAG "%s: %llu us\n", \
__func__, thermal_diff_us); \
} else if (thermal_diff_us < 0) { \
pr_notice(TSCPU_LOG_TAG "Warning: tProfiling " \
"uses incorrect %s %d\n", __func__, __LINE__); \
} \
} while (0)
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/*Enable thermal controller CG*/
#define THERMAL_EBABLE_TC_CG
#define ENALBE_UART_LIMIT (0)
#define TEMP_EN_UART (80000)
#define TEMP_DIS_UART (85000)
#define TEMP_TOLERANCE (0)
#define ENALBE_SW_FILTER (0)
#define ATM_USES_PPM (1)
#define THERMAL_GET_AHB_BUS_CLOCK (0)
#define THERMAL_PERFORMANCE_PROFILE (0)
/* 1: turn on GPIO toggle monitor; 0: turn off */
#define THERMAL_GPIO_OUT_TOGGLE (0)
/* 1: turn on adaptive AP cooler; 0: turn off */
#define CPT_ADAPTIVE_AP_COOLER (1)
/* 1: turn on supports to MET logging; 0: turn off */
#define CONFIG_SUPPORT_MET_MTKTSCPU (0)
/* Thermal controller HW filtering function.
* Only 1, 2, 4, 8, 16 are valid values,
* they means one reading is a avg of X samples
*/
#define THERMAL_CONTROLLER_HW_FILTER (2) /* 1, 2, 4, 8, 16 */
/* 1: turn on thermal controller HW thermal protection; 0: turn off */
#define THERMAL_CONTROLLER_HW_TP (1)
/* 1: turn on fast polling in this sw module; 0: turn off */
#define MTKTSCPU_FAST_POLLING (1)
#if CPT_ADAPTIVE_AP_COOLER
#define MAX_CPT_ADAPTIVE_COOLERS (3)
#define THERMAL_HEADROOM (0)
#define CONTINUOUS_TM (1)
#define DYNAMIC_GET_GPU_POWER (1)
/* 1: turn on precise power budgeting; 0: turn off */
#define PRECISE_HYBRID_POWER_BUDGET (1)
#define PHPB_DEFAULT_ON (1)
#endif
/* 1: thermal driver fast polling, use hrtimer; 0: turn off */
/*#define THERMAL_DRV_FAST_POLL_HRTIMER (1)*/
/* 1: thermal driver update temp to MET directly, use hrtimer; 0: turn off */
#define THERMAL_DRV_UPDATE_TEMP_DIRECT_TO_MET (1)
#define FAST_RESPONSE_ATM (1)
#define THERMAL_INIT_VALUE (0xDA1)
/* 1: mtk_tc.c supports LVTS; 0: o.w. */
#define CFG_THERM_LVTS (0)
/*=============================================================
* Chip related
*=============================================================
*/
/* double check */
//#define TS_CONFIGURE TS_CON1_TM /* depend on CPU design*/
#define TS_CONFIGURE TS_CON0_TM /* depend on CPU design*/
#define TS_CONFIGURE_P TS_CON1_P /* depend on CPU design*/
#define TS_TURN_ON 0xFFFFFFCF /* turn on TS_CON1[5:4] 2'b 00
* 11001111 -> 0xCF ~(0x30
*/
//#define TS_TURN_OFF 0x00000030 /* turn off thermal*/
#define TS_TURN_OFF 0x30000000 /* turn off thermal*/
/*chip dependent*/
#define ADDRESS_INDEX_0 101
#define ADDRESS_INDEX_1 100
#define ADDRESS_INDEX_2 102
#define ADDRESS_INDEX_3 111
#define ADDRESS_INDEX_4 112
#define CLEAR_TEMP 26111
/* TSCON1 bit table */
#define TSCON0_bit_6_7_00 0x00 /* TSCON0[7:6]=2'b00*/
#define TSCON0_bit_6_7_01 0x40 /* TSCON0[7:6]=2'b01*/
#define TSCON0_bit_6_7_10 0x80 /* TSCON0[7:6]=2'b10*/
#define TSCON0_bit_6_7_11 0xc0 /* TSCON0[7:6]=2'b11*/
#define TSCON0_bit_6_7_MASK 0xc0
#define TSCON1_bit_4_5_00 0x00 /* TSCON1[5:4]=2'b00*/
#define TSCON1_bit_4_5_01 0x10 /* TSCON1[5:4]=2'b01*/
#define TSCON1_bit_4_5_10 0x20 /* TSCON1[5:4]=2'b10*/
#define TSCON1_bit_4_5_11 0x30 /* TSCON1[5:4]=2'b11*/
#define TSCON1_bit_4_5_MASK 0x30
#define TSCON1_bit_0_2_000 0x00 /*TSCON1[2:0]=3'b000*/
#define TSCON1_bit_0_2_001 0x01 /*TSCON1[2:0]=3'b001*/
#define TSCON1_bit_0_2_010 0x02 /*TSCON1[2:0]=3'b010*/
#define TSCON1_bit_0_2_011 0x03 /*TSCON1[2:0]=3'b011*/
#define TSCON1_bit_0_2_100 0x04 /*TSCON1[2:0]=3'b100*/
#define TSCON1_bit_0_2_101 0x05 /*TSCON1[2:0]=3'b101*/
#define TSCON1_bit_0_2_110 0x06 /*TSCON1[2:0]=3'b110*/
#define TSCON1_bit_0_2_111 0x07 /*TSCON1[2:0]=3'b111*/
#define TSCON1_bit_0_2_MASK 0x07
#define TSCON0_bit_29_28_00 0x00000000 /* TSCON0[29:28]=2'b00*/
#define TSCON0_bit_29_28_01 0x10000000 /* TSCON0[29:28]=2'b01*/
#define TSCON0_bit_29_28_10 0x20000000 /* TSCON0[29:28]=2'b10*/
#define TSCON0_bit_29_28_11 0x30000000 /* TSCON0[29:28]=2'b11*/
#define TSCON0_bit_29_28_MASK 0x30000000
/* ADC value to mcu */
/*chip dependent*/
#define TEMPADC_MCU1 \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_00)|(0x07&TSCON1_bit_0_2_000))
#define TEMPADC_MCU2 \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_00)|(0x07&TSCON1_bit_0_2_001))
#define TEMPADC_MCU3 \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_00)|(0x07&TSCON1_bit_0_2_010))
#define TEMPADC_MCU4 \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_00)|(0x07&TSCON1_bit_0_2_011))
#define TEMPADC_MCU5 \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_00)|(0x07&TSCON1_bit_0_2_100))
#define TEMPADC_ABB \
((TSCON0_bit_29_28_MASK&TSCON0_bit_29_28_01)|(0x07&TSCON1_bit_0_2_000))
#define TS_FILL(n) {#n, n}
/*#define TS_LEN_ARRAY(name) (sizeof(name)/sizeof(name[0]))*/
#define MAX_TS_NAME 20
#define CPU_COOLER_NUM 34
#define MTK_TS_CPU_RT (0)
#ifdef CONFIG_MTK_AEE_IPANIC
#define CONFIG_THERMAL_AEE_RR_REC (1)
#else
#define CONFIG_THERMAL_AEE_RR_REC (0)
#endif
#define CFG_THERMAL_KERNEL_IGNORE_HOT_SENSOR (0)
/*=============================================================
*REG ACCESS
*=============================================================
*/
#define thermal_setl(addr, val) mt_reg_sync_writel(readl(addr) | \
(val), ((void *)addr))
#define thermal_clrl(addr, val) mt_reg_sync_writel(readl(addr) & \
~(val), ((void *)addr))
#define MTKTSCPU_TEMP_CRIT 120000 /* 120.000 degree Celsius */
#define y_curr_repeat_times 1
#define THERMAL_NAME "mtk-thermal-legacy"
#define TS_MS_TO_NS(x) (x * 1000 * 1000)
#if THERMAL_GET_AHB_BUS_CLOCK
#define THERMAL_MODULE_SW_CG_SET (therm_clk_infracfg_ao_base + 0x88)
#define THERMAL_MODULE_SW_CG_CLR (therm_clk_infracfg_ao_base + 0x8C)
#define THERMAL_MODULE_SW_CG_STA (therm_clk_infracfg_ao_base + 0x94)
#define THERMAL_CG (therm_clk_infracfg_ao_base + 0x80)
#define THERMAL_DCM (therm_clk_infracfg_ao_base + 0x70)
#endif
/*=============================================================
*LOG
*=============================================================
*/
#define TSCPU_LOG_TAG "[Thermal/TZ/CPU]"
#define tscpu_dprintk(fmt, args...) \
do { \
if (tscpu_debug_log == 1) { \
pr_notice(TSCPU_LOG_TAG fmt, ##args); \
} \
} while (0)
#define tscpu_printk(fmt, args...) pr_notice(TSCPU_LOG_TAG fmt, ##args)
#define tscpu_warn(fmt, args...) pr_notice(TSCPU_LOG_TAG fmt, ##args)
/*=============================================================
* Structures
*=============================================================
*/
enum thermal_controller_name {
THERMAL_CONTROLLER0 = 0,
THERMAL_CONTROLLER1,
THERMAL_CONTROLLER_NUM
};
struct thermal_controller_speed {
unsigned int tempMonCtl1;
unsigned int tempMonCtl2;
unsigned int tempAhbPoll;
};
struct thermal_controller {
enum thermal_sensor ts[TS_ENUM_MAX];
int ts_number;
int tc_offset;
struct thermal_controller_speed tc_speed;
};
#if (CONFIG_THERMAL_AEE_RR_REC == 1)
enum thermal_state {
TSCPU_SUSPEND = 0,
TSCPU_RESUME = 1,
TSCPU_NORMAL = 2,
TSCPU_INIT = 3,
TSCPU_PAUSE = 4,
TSCPU_RELEASE = 5
};
enum atm_state {
ATM_WAKEUP = 0,
ATM_CPULIMIT = 1,
ATM_GPULIMIT = 2,
ATM_DONE = 3,
};
#endif
struct mtk_cpu_power_info {
unsigned int cpufreq_khz;
unsigned int cpufreq_ncpu;
unsigned int cpufreq_power;
};
/*=============================================================
* Shared variables
*=============================================================
*/
/*In src/mtk_tc.c*/
extern int temp_eUART;
extern int temp_dUART;
extern int tscpu_debug_log;
extern const struct of_device_id mt_thermal_of_match[2];
extern int tscpu_ts_temp[TS_ENUM_MAX];
extern int tscpu_ts_temp_r[TS_ENUM_MAX]; /* raw data */
extern struct thermal_controller tscpu_g_tc[THERMAL_CONTROLLER_NUM];
extern int tscpu_polling_trip_temp1;
extern int tscpu_polling_trip_temp2;
extern int tscpu_polling_factor1;
extern int tscpu_polling_factor2;
#if MTKTSCPU_FAST_POLLING
/* Combined fast_polling_trip_temp and fast_polling_factor,
*it means polling_delay will be 1/5 of original interval
*after mtktscpu reports > 65C w/o exit point
*/
extern int fast_polling_trip_temp;
extern int fast_polling_trip_temp_high;
extern int fast_polling_factor;
extern int tscpu_cur_fp_factor;
extern int tscpu_next_fp_factor;
#endif
extern struct platform_device *tscpu_pdev;
/*In common/thermal_zones/mtk_ts_cpu.c*/
extern long long thermal_get_current_time_us(void);
extern void tscpu_workqueue_cancel_timer(void);
extern void tscpu_workqueue_start_timer(void);
extern void __iomem *therm_clk_infracfg_ao_base;
extern int Num_of_GPU_OPP;
extern int gpu_max_opp;
extern struct mt_gpufreq_power_table_info *mtk_gpu_power;
extern int tscpu_read_curr_temp;
#if MTKTSCPU_FAST_POLLING
extern int tscpu_cur_fp_factor;
#endif
#if !defined(CONFIG_MTK_CLKMGR)
extern struct clk *therm_main; /* main clock for Thermal*/
#endif
#if CPT_ADAPTIVE_AP_COOLER
extern int tscpu_g_curr_temp;
extern int tscpu_g_prev_temp;
#if (THERMAL_HEADROOM == 1) || (CONTINUOUS_TM == 1)
extern int bts_cur_temp; /* in mtk_ts_bts.c */
#endif
#if PRECISE_HYBRID_POWER_BUDGET
/* tscpu_prev_cpu_temp: previous CPUSYS temperature
* tscpu_curr_cpu_temp: current CPUSYS temperature
* tscpu_prev_gpu_temp: previous GPUSYS temperature
* tscpu_curr_gpu_temp: current GPUSYS temperature
*/
extern int tscpu_prev_cpu_temp, tscpu_prev_gpu_temp;
extern int tscpu_curr_cpu_temp, tscpu_curr_gpu_temp;
#endif
#endif
#ifdef CONFIG_OF
extern u32 thermal_irq_number;
extern void __iomem *thermal_base;
extern void __iomem *auxadc_ts_base;
extern void __iomem *infracfg_ao_base;
extern void __iomem *th_apmixed_base;
extern void __iomem *INFRACFG_AO_base;
extern int thermal_phy_base;
extern int auxadc_ts_phy_base;
extern int apmixed_phy_base;
extern int pericfg_phy_base;
#endif
extern char *adaptive_cooler_name;
/*common/coolers/mtk_cooler_atm.c*/
extern unsigned int adaptive_cpu_power_limit;
extern unsigned int adaptive_gpu_power_limit;
extern int TARGET_TJS[MAX_CPT_ADAPTIVE_COOLERS];
#ifdef FAST_RESPONSE_ATM
extern void atm_cancel_hrtimer(void);
extern void atm_restart_hrtimer(void);
#endif
/*common/coolers/mtk_cooler_dtm.c*/
extern unsigned int static_cpu_power_limit;
extern unsigned int static_gpu_power_limit;
extern int tscpu_cpu_dmips[CPU_COOLER_NUM];
/*=============================================================
* Shared functions
*=============================================================
*/
/*In common/thermal_zones/mtk_ts_cpu.c*/
extern void thermal_init_interrupt_for_UART(int temp_e, int temp_d);
extern void tscpu_update_tempinfo(void);
#if THERMAL_GPIO_OUT_TOGGLE
void tscpu_set_GPIO_toggle_for_monitor(void);
#endif
extern void tscpu_update_tempinfo(void);
extern int tscpu_max_temperature(void);
/*In src/mtk_tc.c*/
extern int get_io_reg_base(void);
extern void tscpu_config_all_tc_hw_protect(int temperature, int temperature2);
extern void tscpu_reset_thermal(void);
extern void tscpu_thermal_initial_all_tc(void);
extern void tscpu_thermal_read_tc_temp
(int tc_num, enum thermal_sensor type, int order);
extern void tscpu_thermal_cal_prepare(void);
extern void tscpu_thermal_cal_prepare_2(unsigned int ret);
extern irqreturn_t tscpu_thermal_all_tc_interrupt_handler
(int irq, void *dev_id);
extern int tscpu_thermal_clock_on(void);
extern int tscpu_thermal_clock_off(void);
extern int tscpu_read_temperature_info(struct seq_file *m, void *v);
extern int tscpu_thermal_fast_init(int tc_num);
extern int tscpu_get_curr_temp(void);
extern int tscpu_get_curr_max_ts_temp(void);
extern void thermal_get_AHB_clk_info(void);
extern void print_risky_temps(char *prefix, int offset, int printLevel);
extern void thermal_pause_all_periodoc_temp_sensing(void);
extern void thermal_release_all_periodoc_temp_sensing(void);
extern int (*max_temperature_in_bank[THERMAL_BANK_NUM])(void);
extern void thermal_disable_all_periodoc_temp_sensing(void);
/*
*In drivers/misc/mediatek/gpu/hal/mtk_gpu_utility.c
*It's not our api, ask them to provide header file
*/
extern bool mtk_get_gpu_loading(unsigned int *pLoading);
/*
*In drivers/misc/mediatek/auxadc/mt_auxadc.c
*It's not our api, ask them to provide header file
*/
extern int IMM_IsAdcInitReady(void);
/*aee related*/
#if (CONFIG_THERMAL_AEE_RR_REC == 1)
extern int aee_rr_init_thermal_temp(int num);
extern int aee_rr_rec_thermal_temp(int index, s8 val);
extern void aee_rr_rec_thermal_status(u8 val);
extern void aee_rr_rec_thermal_ATM_status(u8 val);
extern void aee_rr_rec_thermal_ktime(u64 val);
extern s8 aee_rr_curr_thermal_temp(int index);
extern u8 aee_rr_curr_thermal_status(void);
extern u8 aee_rr_curr_thermal_ATM_status(void);
extern u64 aee_rr_curr_thermal_ktime(void);
#endif
/*=============================================================
* Register macro for internal use
*=============================================================
*/
extern void __iomem *thermal_base;
extern void __iomem *auxadc_base;
extern void __iomem *infracfg_ao_base;
extern void __iomem *th_apmixed_base;
extern void __iomem *INFRACFG_AO_base;
#define THERM_CTRL_BASE_2 thermal_base
#define AUXADC_BASE_2 auxadc_ts_base
#define INFRACFG_AO_BASE_2 infracfg_ao_base
#define APMIXED_BASE_2 th_apmixed_base
/*******************************************************************************
* AUXADC Register Definition
*****************************************************************************
*/
#define AUXADC_CON0_V (AUXADC_BASE_2 + 0x000)
#define AUXADC_CON1_V (AUXADC_BASE_2 + 0x004)
#define AUXADC_CON1_SET_V (AUXADC_BASE_2 + 0x008)
#define AUXADC_CON1_CLR_V (AUXADC_BASE_2 + 0x00C)
#define AUXADC_CON2_V (AUXADC_BASE_2 + 0x010)
/*#define AUXADC_CON3_V (AUXADC_BASE_2 + 0x014)*/
#define AUXADC_DAT0_V (AUXADC_BASE_2 + 0x014)
#define AUXADC_DAT1_V (AUXADC_BASE_2 + 0x018)
#define AUXADC_DAT2_V (AUXADC_BASE_2 + 0x01C)
#define AUXADC_DAT3_V (AUXADC_BASE_2 + 0x020)
#define AUXADC_DAT4_V (AUXADC_BASE_2 + 0x024)
#define AUXADC_DAT5_V (AUXADC_BASE_2 + 0x028)
#define AUXADC_DAT6_V (AUXADC_BASE_2 + 0x02C)
#define AUXADC_DAT7_V (AUXADC_BASE_2 + 0x030)
#define AUXADC_DAT8_V (AUXADC_BASE_2 + 0x034)
#define AUXADC_DAT9_V (AUXADC_BASE_2 + 0x038)
#define AUXADC_DAT10_V (AUXADC_BASE_2 + 0x03C)
#define AUXADC_DAT11_V (AUXADC_BASE_2 + 0x040)
#define AUXADC_MISC_V (AUXADC_BASE_2 + 0x094)
#define AUXADC_CON0_P (auxadc_ts_phy_base + 0x000)
#define AUXADC_CON1_P (auxadc_ts_phy_base + 0x004)
#define AUXADC_CON1_SET_P (auxadc_ts_phy_base + 0x008)
#define AUXADC_CON1_CLR_P (auxadc_ts_phy_base + 0x00C)
#define AUXADC_CON2_P (auxadc_ts_phy_base + 0x010)
/*#define AUXADC_CON3_P (auxadc_ts_phy_base + 0x014)*/
#define AUXADC_DAT0_P (auxadc_ts_phy_base + 0x014)
#define AUXADC_DAT1_P (auxadc_ts_phy_base + 0x018)
#define AUXADC_DAT2_P (auxadc_ts_phy_base + 0x01C)
#define AUXADC_DAT3_P (auxadc_ts_phy_base + 0x020)
#define AUXADC_DAT4_P (auxadc_ts_phy_base + 0x024)
#define AUXADC_DAT5_P (auxadc_ts_phy_base + 0x028)
#define AUXADC_DAT6_P (auxadc_ts_phy_base + 0x02C)
#define AUXADC_DAT7_P (auxadc_ts_phy_base + 0x030)
#define AUXADC_DAT8_P (auxadc_ts_phy_base + 0x034)
#define AUXADC_DAT9_P (auxadc_ts_phy_base + 0x038)
#define AUXADC_DAT10_P (auxadc_ts_phy_base + 0x03C)
#define AUXADC_DAT11_P (auxadc_ts_phy_base + 0x040)
#define AUXADC_MISC_P (auxadc_ts_phy_base + 0x094)
/*******************************************************************************
* Peripheral Configuration Register Definition
*****************************************************************************
*/
/*APB Module infracfg_ao*/
/*yes, 0x10000000*/
#define INFRA_GLOBALCON_RST_0_SET (INFRACFG_AO_BASE_2 + 0x120)
/*yes, 0x10000000*/
#define INFRA_GLOBALCON_RST_0_CLR (INFRACFG_AO_BASE_2 + 0x124)
/*yes, 0x10000000*/
#define INFRA_GLOBALCON_RST_0_STA (INFRACFG_AO_BASE_2 + 0x128)
/*******************************************************************************
* APMixedSys Configuration Register Definition
*****************************************************************************
*/
/* TODO: check base addr. */
#define TS_CON0_TM (APMIXED_BASE_2 + 0x600) /*yes 0x10212000*/
#define TS_CON1_TM (APMIXED_BASE_2 + 0x604)
#define TS_CON0_P (apmixed_phy_base + 0x600)
#define TS_CON1_P (apmixed_phy_base + 0x604)
/*******************************************************************************
* Thermal Controller Register Definition
*****************************************************************************
*/
#define TEMPMONCTL0 (THERM_CTRL_BASE_2 + 0x000)
#define TEMPMONCTL1 (THERM_CTRL_BASE_2 + 0x004)
#define TEMPMONCTL2 (THERM_CTRL_BASE_2 + 0x008)
#define TEMPMONINT (THERM_CTRL_BASE_2 + 0x00C)
#define TEMPMONINTSTS (THERM_CTRL_BASE_2 + 0x010)
#define TEMPMONIDET0 (THERM_CTRL_BASE_2 + 0x014)
#define TEMPMONIDET1 (THERM_CTRL_BASE_2 + 0x018)
#define TEMPMONIDET2 (THERM_CTRL_BASE_2 + 0x01C)
#define TEMPH2NTHRE (THERM_CTRL_BASE_2 + 0x024)
#define TEMPHTHRE (THERM_CTRL_BASE_2 + 0x028)
#define TEMPCTHRE (THERM_CTRL_BASE_2 + 0x02C)
#define TEMPOFFSETH (THERM_CTRL_BASE_2 + 0x030)
#define TEMPOFFSETL (THERM_CTRL_BASE_2 + 0x034)
#define TEMPMSRCTL0 (THERM_CTRL_BASE_2 + 0x038)
#define TEMPMSRCTL1 (THERM_CTRL_BASE_2 + 0x03C)
#define TEMPAHBPOLL (THERM_CTRL_BASE_2 + 0x040)
#define TEMPAHBTO (THERM_CTRL_BASE_2 + 0x044)
#define TEMPADCPNP0 (THERM_CTRL_BASE_2 + 0x048)
#define TEMPADCPNP1 (THERM_CTRL_BASE_2 + 0x04C)
#define TEMPADCPNP2 (THERM_CTRL_BASE_2 + 0x050)
#define TEMPADCMUX (THERM_CTRL_BASE_2 + 0x054)
#define TEMPADCEXT (THERM_CTRL_BASE_2 + 0x058)
#define TEMPADCEXT1 (THERM_CTRL_BASE_2 + 0x05C)
#define TEMPADCEN (THERM_CTRL_BASE_2 + 0x060)
#define TEMPPNPMUXADDR (THERM_CTRL_BASE_2 + 0x064)
#define TEMPADCMUXADDR (THERM_CTRL_BASE_2 + 0x068)
#define TEMPADCEXTADDR (THERM_CTRL_BASE_2 + 0x06C)
#define TEMPADCEXT1ADDR (THERM_CTRL_BASE_2 + 0x070)
#define TEMPADCENADDR (THERM_CTRL_BASE_2 + 0x074)
#define TEMPADCVALIDADDR (THERM_CTRL_BASE_2 + 0x078)
#define TEMPADCVOLTADDR (THERM_CTRL_BASE_2 + 0x07C)
#define TEMPRDCTRL (THERM_CTRL_BASE_2 + 0x080)
#define TEMPADCVALIDMASK (THERM_CTRL_BASE_2 + 0x084)
#define TEMPADCVOLTAGESHIFT (THERM_CTRL_BASE_2 + 0x088)
#define TEMPADCWRITECTRL (THERM_CTRL_BASE_2 + 0x08C)
#define TEMPMSR0 (THERM_CTRL_BASE_2 + 0x090)
#define TEMPMSR1 (THERM_CTRL_BASE_2 + 0x094)
#define TEMPMSR2 (THERM_CTRL_BASE_2 + 0x098)
#define TEMPADCHADDR (THERM_CTRL_BASE_2 + 0x09C)
#define TEMPIMMD0 (THERM_CTRL_BASE_2 + 0x0A0)
#define TEMPIMMD1 (THERM_CTRL_BASE_2 + 0x0A4)
#define TEMPIMMD2 (THERM_CTRL_BASE_2 + 0x0A8)
#define TEMPMONIDET3 (THERM_CTRL_BASE_2 + 0x0B0)
#define TEMPADCPNP3 (THERM_CTRL_BASE_2 + 0x0B4)
#define TEMPMSR3 (THERM_CTRL_BASE_2 + 0x0B8)
#define TEMPIMMD3 (THERM_CTRL_BASE_2 + 0x0BC)
#define TEMPPROTCTL (THERM_CTRL_BASE_2 + 0x0C0)
#define TEMPPROTTA (THERM_CTRL_BASE_2 + 0x0C4)
#define TEMPPROTTB (THERM_CTRL_BASE_2 + 0x0C8)
#define TEMPPROTTC (THERM_CTRL_BASE_2 + 0x0CC)
#define TEMPSPARE0 (THERM_CTRL_BASE_2 + 0x0F0)
#define TEMPSPARE1 (THERM_CTRL_BASE_2 + 0x0F4)
#define TEMPSPARE2 (THERM_CTRL_BASE_2 + 0x0F8)
#define TEMPSPARE3 (THERM_CTRL_BASE_2 + 0x0FC)
#define TEMPMONCTL0_1 (THERM_CTRL_BASE_2 + 0x100)
#define TEMPMONCTL1_1 (THERM_CTRL_BASE_2 + 0x104)
#define TEMPMONCTL2_1 (THERM_CTRL_BASE_2 + 0x108)
#define TEMPMONINT_1 (THERM_CTRL_BASE_2 + 0x10C)
#define TEMPMONINTSTS_1 (THERM_CTRL_BASE_2 + 0x110)
#define TEMPMONIDET0_1 (THERM_CTRL_BASE_2 + 0x114)
#define TEMPMONIDET1_1 (THERM_CTRL_BASE_2 + 0x118)
#define TEMPMONIDET2_1 (THERM_CTRL_BASE_2 + 0x11C)
#define TEMPH2NTHRE_1 (THERM_CTRL_BASE_2 + 0x124)
#define TEMPHTHRE_1 (THERM_CTRL_BASE_2 + 0x128)
#define TEMPCTHRE_1 (THERM_CTRL_BASE_2 + 0x12C)
#define TEMPOFFSETH_1 (THERM_CTRL_BASE_2 + 0x130)
#define TEMPOFFSETL_1 (THERM_CTRL_BASE_2 + 0x134)
#define TEMPMSRCTL0_1 (THERM_CTRL_BASE_2 + 0x138)
#define TEMPMSRCTL1_1 (THERM_CTRL_BASE_2 + 0x13C)
#define TEMPAHBPOLL_1 (THERM_CTRL_BASE_2 + 0x140)
#define TEMPAHBTO_1 (THERM_CTRL_BASE_2 + 0x144)
#define TEMPADCPNP0_1 (THERM_CTRL_BASE_2 + 0x148)
#define TEMPADCPNP1_1 (THERM_CTRL_BASE_2 + 0x14C)
#define TEMPADCPNP2_1 (THERM_CTRL_BASE_2 + 0x150)
#define TEMPADCMUX_1 (THERM_CTRL_BASE_2 + 0x154)
#define TEMPADCEXT_1 (THERM_CTRL_BASE_2 + 0x158)
#define TEMPADCEXT1_1 (THERM_CTRL_BASE_2 + 0x15C)
#define TEMPADCEN_1 (THERM_CTRL_BASE_2 + 0x160)
#define TEMPPNPMUXADDR_1 (THERM_CTRL_BASE_2 + 0x164)
#define TEMPADCMUXADDR_1 (THERM_CTRL_BASE_2 + 0x168)
#define TEMPADCEXTADDR_1 (THERM_CTRL_BASE_2 + 0x16C)
#define TEMPADCEXT1ADDR_1 (THERM_CTRL_BASE_2 + 0x170)
#define TEMPADCENADDR_1 (THERM_CTRL_BASE_2 + 0x174)
#define TEMPADCVALIDADDR_1 (THERM_CTRL_BASE_2 + 0x178)
#define TEMPADCVOLTADDR_1 (THERM_CTRL_BASE_2 + 0x17C)
#define TEMPRDCTRL_1 (THERM_CTRL_BASE_2 + 0x180)
#define TEMPADCVALIDMASK_1 (THERM_CTRL_BASE_2 + 0x184)
#define TEMPADCVOLTAGESHIFT_1 (THERM_CTRL_BASE_2 + 0x188)
#define TEMPADCWRITECTRL_1 (THERM_CTRL_BASE_2 + 0x18C)
#define TEMPMSR0_1 (THERM_CTRL_BASE_2 + 0x190)
#define TEMPMSR1_1 (THERM_CTRL_BASE_2 + 0x194)
#define TEMPMSR2_1 (THERM_CTRL_BASE_2 + 0x198)
#define TEMPADCHADDR_1 (THERM_CTRL_BASE_2 + 0x19C)
#define TEMPIMMD0_1 (THERM_CTRL_BASE_2 + 0x1A0)
#define TEMPIMMD1_1 (THERM_CTRL_BASE_2 + 0x1A4)
#define TEMPIMMD2_1 (THERM_CTRL_BASE_2 + 0x1A8)
#define TEMPMONIDET3_1 (THERM_CTRL_BASE_2 + 0x1B0)
#define TEMPADCPNP3_1 (THERM_CTRL_BASE_2 + 0x1B4)
#define TEMPMSR3_1 (THERM_CTRL_BASE_2 + 0x1B8)
#define TEMPIMMD3_1 (THERM_CTRL_BASE_2 + 0x1BC)
#define TEMPPROTCTL_1 (THERM_CTRL_BASE_2 + 0x1C0)
#define TEMPPROTTA_1 (THERM_CTRL_BASE_2 + 0x1C4)
#define TEMPPROTTB_1 (THERM_CTRL_BASE_2 + 0x1C8)
#define TEMPPROTTC_1 (THERM_CTRL_BASE_2 + 0x1CC)
#define TEMPSPARE0_1 (THERM_CTRL_BASE_2 + 0x1F0)
#define TEMPSPARE1_1 (THERM_CTRL_BASE_2 + 0x1F4)
#define TEMPSPARE2_1 (THERM_CTRL_BASE_2 + 0x1F8)
#define TEMPSPARE3_1 (THERM_CTRL_BASE_2 + 0x1FC)
#define PTPCORESEL (THERM_CTRL_BASE_2 + 0xF00)
#define THERMINTST (THERM_CTRL_BASE_2 + 0xF04)
#define PTPODINTST (THERM_CTRL_BASE_2 + 0xF08)
#define THSTAGE0ST (THERM_CTRL_BASE_2 + 0xF0C)
#define THSTAGE1ST (THERM_CTRL_BASE_2 + 0xF10)
#define THSTAGE2ST (THERM_CTRL_BASE_2 + 0xF14)
#define THAHBST0 (THERM_CTRL_BASE_2 + 0xF18)
#define THAHBST1 (THERM_CTRL_BASE_2 + 0xF1C)
#define PTPSPARE0 (THERM_CTRL_BASE_2 + 0xF20)
#define PTPSPARE1 (THERM_CTRL_BASE_2 + 0xF24)
#define PTPSPARE2 (THERM_CTRL_BASE_2 + 0xF28)
#define PTPSPARE3 (THERM_CTRL_BASE_2 + 0xF2C)
#define THSLPEVEB (THERM_CTRL_BASE_2 + 0xF30)
#define PTPSPARE0_P (thermal_phy_base + 0xF20)
#define PTPSPARE1_P (thermal_phy_base + 0xF24)
#define PTPSPARE2_P (thermal_phy_base + 0xF28)
#define PTPSPARE3_P (thermal_phy_base + 0xF2C)
/*******************************************************************************
* Thermal Controller Register Mask Definition
*****************************************************************************
*/
#define THERMAL_ENABLE_SEN0 0x1
#define THERMAL_ENABLE_SEN1 0x2
#define THERMAL_ENABLE_SEN2 0x4
#define THERMAL_MONCTL0_MASK 0x00000007
#define THERMAL_PUNT_MASK 0x00000FFF
#define THERMAL_FSINTVL_MASK 0x03FF0000
#define THERMAL_SPINTVL_MASK 0x000003FF
#define THERMAL_MON_INT_MASK 0x0007FFFF
#define THERMAL_MON_CINTSTS0 0x000001
#define THERMAL_MON_HINTSTS0 0x000002
#define THERMAL_MON_LOINTSTS0 0x000004
#define THERMAL_MON_HOINTSTS0 0x000008
#define THERMAL_MON_NHINTSTS0 0x000010
#define THERMAL_MON_CINTSTS1 0x000020
#define THERMAL_MON_HINTSTS1 0x000040
#define THERMAL_MON_LOINTSTS1 0x000080
#define THERMAL_MON_HOINTSTS1 0x000100
#define THERMAL_MON_NHINTSTS1 0x000200
#define THERMAL_MON_CINTSTS2 0x000400
#define THERMAL_MON_HINTSTS2 0x000800
#define THERMAL_MON_LOINTSTS2 0x001000
#define THERMAL_MON_HOINTSTS2 0x002000
#define THERMAL_MON_NHINTSTS2 0x004000
#define THERMAL_MON_TOINTSTS 0x008000
#define THERMAL_MON_IMMDINTSTS0 0x010000
#define THERMAL_MON_IMMDINTSTS1 0x020000
#define THERMAL_MON_IMMDINTSTS2 0x040000
#define THERMAL_MON_FILTINTSTS0 0x080000
#define THERMAL_MON_FILTINTSTS1 0x100000
#define THERMAL_MON_FILTINTSTS2 0x200000
#define THERMAL_tri_SPM_State0 0x20000000
#define THERMAL_tri_SPM_State1 0x40000000
#define THERMAL_tri_SPM_State2 0x80000000
#define THERMAL_MSRCTL0_MASK 0x00000007
#define THERMAL_MSRCTL1_MASK 0x00000038
#define THERMAL_MSRCTL2_MASK 0x000001C0
/*cpu core nums*/
#define TZCPU_NO_CPU_CORES CONFIG_NR_CPUS
#endif /* __TSCPU_SETTINGS_H__ */

45
drivers/misc/mediatek/thermal/mt6765/inc/tzbatt_initcfg.h
View File

@@ -1,45 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TZBATT_INITCFG_H__
#define __TZBATT_INITCFG_H__
#define TZBATT_SET_INIT_CFG (1)
#define TZBATT_INITCFG_INTERVAL (1)
#define TZBATT_INITCFG_NUM_TRIPS (3)
#define TZBATT_INITCFG_TRIP_0_TEMP (49000)
#define TZBATT_INITCFG_TRIP_0_COOLER "mtk-cl-bcct02"
#define TZBATT_INITCFG_TRIP_1_TEMP (48000)
#define TZBATT_INITCFG_TRIP_1_COOLER "mtk-cl-bcct01"
#define TZBATT_INITCFG_TRIP_2_TEMP (46000)
#define TZBATT_INITCFG_TRIP_2_COOLER "mtk-cl-bcct00"
#define TZBATT_INITCFG_TRIP_3_TEMP (45000)
#define TZBATT_INITCFG_TRIP_3_COOLER ""
#define TZBATT_INITCFG_TRIP_4_TEMP (44000)
#define TZBATT_INITCFG_TRIP_4_COOLER ""
#define TZBATT_INITCFG_TRIP_5_TEMP (43000)
#define TZBATT_INITCFG_TRIP_5_COOLER ""
#define TZBATT_INITCFG_TRIP_6_TEMP (42000)
#define TZBATT_INITCFG_TRIP_6_COOLER ""
#define TZBATT_INITCFG_TRIP_7_TEMP (41000)
#define TZBATT_INITCFG_TRIP_7_COOLER ""
#define TZBATT_INITCFG_TRIP_8_TEMP (40000)
#define TZBATT_INITCFG_TRIP_8_COOLER ""
#define TZBATT_INITCFG_TRIP_9_TEMP (39000)
#define TZBATT_INITCFG_TRIP_9_COOLER ""
#endif /* __TZBATT_INITCFG_H__ */

47
drivers/misc/mediatek/thermal/mt6765/inc/tzcpu_initcfg.h
View File

@@ -1,47 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TZCPU_INITCFG_H__
#define __TZCPU_INITCFG_H__
#define TZCPU_SET_INIT_CFG (1)
#define TZCPU_INITCFG_INTERVAL (40)
#define TZCPU_INITCFG_NUM_TRIPS (4)
#define TZCPU_INITCFG_TRIP_0_TEMP (117000)
#define TZCPU_INITCFG_TRIP_0_COOLER "mtktscpu-sysrst"
#define TZCPU_INITCFG_TRIP_1_TEMP (95000)
#define TZCPU_INITCFG_TRIP_1_COOLER "cpu00"
#define TZCPU_INITCFG_TRIP_2_TEMP (85000)
#define TZCPU_INITCFG_TRIP_2_COOLER "cpu03"
#define TZCPU_INITCFG_TRIP_3_TEMP (65000)
#define TZCPU_INITCFG_TRIP_3_COOLER "cpu_adaptive_0"
#define TZCPU_INITCFG_TRIP_4_TEMP (63000)
#define TZCPU_INITCFG_TRIP_4_COOLER ""
#define TZCPU_INITCFG_TRIP_5_TEMP (60000)
#define TZCPU_INITCFG_TRIP_5_COOLER ""
#define TZCPU_INITCFG_TRIP_6_TEMP (55000)
#define TZCPU_INITCFG_TRIP_6_COOLER ""
#define TZCPU_INITCFG_TRIP_7_TEMP (50000)
#define TZCPU_INITCFG_TRIP_7_COOLER ""
#define TZCPU_INITCFG_TRIP_8_TEMP (45000)
#define TZCPU_INITCFG_TRIP_8_COOLER ""
#define TZCPU_INITCFG_TRIP_9_TEMP (40000)
#define TZCPU_INITCFG_TRIP_9_COOLER ""
#endif /* __TZCPU_INITCFG_H__ */

32
drivers/misc/mediatek/thermal/mt6765/src/Makefile
View File

@@ -1,32 +0,0 @@
#
# Copyright (C) 2017 MediaTek Inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
THERMAL_CHIP_DRIVER_DIR := $(srctree)/drivers/misc/mediatek/thermal/$(MTK_PLATFORM)
ccflags-y += -I$(THERMAL_CHIP_DRIVER_DIR)/inc
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/$(MTK_PLATFORM)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/gpu/hal/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/thermal/fakeHeader/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/$(MTK_PLATFORM)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/eem_v2/mt6765/inc/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/pmic/include/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/thermal/common/inc/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/include/
ccflags-y += -I$(srctree)/include/dt-bindings/
ccflags-y += -I$(srctree)/drivers/gpu/mediatek/gpufreq/include/
obj-$(CONFIG_THERMAL) += mtk_tc.o
#obj-$(CONFIG_THERMAL) += mtk_thermal_ipi.o
obj-$(CONFIG_THERMAL) += mtk_pmic_efuse.o
obj-$(CONFIG_THERMAL) += mtk_ts_6357buck1.o
obj-$(CONFIG_THERMAL) += mtk_ts_6357buck2.o

1740
drivers/misc/mediatek/thermal/mt6765/src/mtk_tc.c
View File

File diff suppressed because it is too large Load Diff

621
drivers/misc/mediatek/thermal/mt6765/src/mtk_ts_6357buck1.c
View File

@@ -1,621 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
//#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
#include <linux/mfd/mt6397/core.h>/* PMIC MFD core header */
#include <linux/regmap.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int isTimerCancelled;
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2
*&& curr_temp < polling_trip_temp1, use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = {150000, 110000, 100000, 90000, 80000,
70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = "sysrst.6357buck1";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long mt6357tsbuck1_cur_temp;
/*
*static long int mt6357tsbuck1_start_temp;
*static long int mt6357tsbuck1_end_temp;
*/
/*=============================================================*/
static int mt6357tsbuck1_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6357tsbuck1_get_hw_temp();
mt6357tsbuck1_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6357tsbuck1_bind
(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[%s] error binding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] binding OK, %d\n", __func__, table_val);
return 0;
}
static int mt6357tsbuck1_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[%s] error unbinding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] unbinding OK\n", __func__);
return 0;
}
static int mt6357tsbuck1_get_mode
(struct thermal_zone_device *thermal,
enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6357tsbuck1_set_mode
(struct thermal_zone_device *thermal,
enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6357tsbuck1_get_trip_type
(struct thermal_zone_device *thermal, int trip,
enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6357tsbuck1_get_trip_temp
(struct thermal_zone_device *thermal, int trip,
int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6357tsbuck1_get_crit_temp(
struct thermal_zone_device *thermal, int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6357tsbuck1_dev_ops = {
.bind = mt6357tsbuck1_bind,
.unbind = mt6357tsbuck1_unbind,
.get_temp = mt6357tsbuck1_get_temp,
.get_mode = mt6357tsbuck1_get_mode,
.set_mode = mt6357tsbuck1_set_mode,
.get_trip_type = mt6357tsbuck1_get_trip_type,
.get_trip_temp = mt6357tsbuck1_get_trip_temp,
.get_crit_temp = mt6357tsbuck1_get_crit_temp,
};
static int mt6357tsbuck1_sysrst_get_max_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6357tsbuck1_sysrst_get_cur_state(
struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6357tsbuck1_sysrst_set_cur_state(
struct thermal_cooling_device *cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("MT6357TSBUCK1 OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
}
return 0;
}
static struct thermal_cooling_device_ops mt6357tsbuck1_cooling_sysrst_ops = {
.get_max_state = mt6357tsbuck1_sysrst_get_max_state,
.get_cur_state = mt6357tsbuck1_sysrst_get_cur_state,
.set_cur_state = mt6357tsbuck1_sysrst_set_cur_state,
};
static int mt6357tsbuck1_read(struct seq_file *m, void *v)
{
seq_printf(m,
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
__func__,
trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
seq_printf(m,
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d, trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8], trip_temp[9]);
seq_printf(m,
"g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d, g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2],
g_THERMAL_TRIP[3]);
seq_printf(m,
"g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d, g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6],
g_THERMAL_TRIP[7]);
seq_printf(m,
"g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n", g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
seq_printf(m,
"cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m,
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s, time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6357tsbuck1_register_thermal(void);
static void mt6357tsbuck1_unregister_thermal(void);
static ssize_t mt6357tsbuck1_write(struct file *file,
const char __user *buffer, size_t count, loff_t *data)
{
int len = 0;
int i;
struct mt6357tsbuck1_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6357tsbuck1_data *ptr_mt6357tsbuck1_data;
ptr_mt6357tsbuck1_data = kmalloc(sizeof(*ptr_mt6357tsbuck1_data),
GFP_KERNEL);
if (ptr_mt6357tsbuck1_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6357tsbuck1_data->desc) - 1)) ? count :
(sizeof(ptr_mt6357tsbuck1_data->desc) - 1);
if (copy_from_user(ptr_mt6357tsbuck1_data->desc, buffer, len)) {
kfree(ptr_mt6357tsbuck1_data);
return 0;
}
ptr_mt6357tsbuck1_data->desc[len] = '\0';
if (sscanf
(ptr_mt6357tsbuck1_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6357tsbuck1_data->trip[0], &ptr_mt6357tsbuck1_data->t_type[0],
ptr_mt6357tsbuck1_data->bind0,
&ptr_mt6357tsbuck1_data->trip[1], &ptr_mt6357tsbuck1_data->t_type[1],
ptr_mt6357tsbuck1_data->bind1,
&ptr_mt6357tsbuck1_data->trip[2], &ptr_mt6357tsbuck1_data->t_type[2],
ptr_mt6357tsbuck1_data->bind2,
&ptr_mt6357tsbuck1_data->trip[3], &ptr_mt6357tsbuck1_data->t_type[3],
ptr_mt6357tsbuck1_data->bind3,
&ptr_mt6357tsbuck1_data->trip[4], &ptr_mt6357tsbuck1_data->t_type[4],
ptr_mt6357tsbuck1_data->bind4,
&ptr_mt6357tsbuck1_data->trip[5], &ptr_mt6357tsbuck1_data->t_type[5],
ptr_mt6357tsbuck1_data->bind5,
&ptr_mt6357tsbuck1_data->trip[6], &ptr_mt6357tsbuck1_data->t_type[6],
ptr_mt6357tsbuck1_data->bind6,
&ptr_mt6357tsbuck1_data->trip[7], &ptr_mt6357tsbuck1_data->t_type[7],
ptr_mt6357tsbuck1_data->bind7,
&ptr_mt6357tsbuck1_data->trip[8], &ptr_mt6357tsbuck1_data->t_type[8],
ptr_mt6357tsbuck1_data->bind8,
&ptr_mt6357tsbuck1_data->trip[9], &ptr_mt6357tsbuck1_data->t_type[9],
ptr_mt6357tsbuck1_data->bind9,
&ptr_mt6357tsbuck1_data->time_msec) == 32) {
down(&sem_mutex);
mtktspmic_dprintk(
"[%s] mt6357tsbuck1_unregister_thermal\n", __func__);
mt6357tsbuck1_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(
__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6357tsbuck1_write", "Bad argument");
#endif
mtktspmic_dprintk(
"[%s] bad argument\n", __func__);
kfree(ptr_mt6357tsbuck1_data);
up(&sem_mutex);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6357tsbuck1_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] =
g_bind4[0] = g_bind5[0] = g_bind6[0] = g_bind7[0] =
g_bind8[0] = g_bind9[0] = '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6357tsbuck1_data->bind0[i];
g_bind1[i] = ptr_mt6357tsbuck1_data->bind1[i];
g_bind2[i] = ptr_mt6357tsbuck1_data->bind2[i];
g_bind3[i] = ptr_mt6357tsbuck1_data->bind3[i];
g_bind4[i] = ptr_mt6357tsbuck1_data->bind4[i];
g_bind5[i] = ptr_mt6357tsbuck1_data->bind5[i];
g_bind6[i] = ptr_mt6357tsbuck1_data->bind6[i];
g_bind7[i] = ptr_mt6357tsbuck1_data->bind7[i];
g_bind8[i] = ptr_mt6357tsbuck1_data->bind8[i];
g_bind9[i] = ptr_mt6357tsbuck1_data->bind9[i];
}
mtktspmic_dprintk(
"[%s] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
__func__, g_THERMAL_TRIP[0], g_THERMAL_TRIP[1],
g_THERMAL_TRIP[2]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4],
g_THERMAL_TRIP[5],
g_THERMAL_TRIP[6]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
mtktspmic_dprintk(
"[%s] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
__func__, g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk(
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6357tsbuck1_data->trip[i];
interval = ptr_mt6357tsbuck1_data->time_msec / 1000;
mtktspmic_dprintk(
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
__func__,
trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
mtktspmic_dprintk(
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8]);
mtktspmic_dprintk(
"trip_9_temp=%d,time_ms=%d\n", trip_temp[9],
interval * 1000);
mtktspmic_dprintk(
"[%s]mt6357tsbuck1_register_thermal\n", __func__);
mt6357tsbuck1_register_thermal();
up(&sem_mutex);
kfree(ptr_mt6357tsbuck1_data);
return count;
}
mtktspmic_dprintk("[%s] bad argument\n", __func__);
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6357tsbuck1_write", "Bad argument");
#endif
kfree(ptr_mt6357tsbuck1_data);
return -EINVAL;
}
static void mt6357tsbuck1_cancel_thermal_timer(void)
{
/* cancel timer */
/* pr_debug("mtkts_pmic_cancel_thermal_timer\n"); */
/* stop thermal framework polling when entering deep idle */
if (down_trylock(&sem_mutex))
return;
if (thz_dev) {
cancel_delayed_work(&(thz_dev->poll_queue));
isTimerCancelled = 1;
}
up(&sem_mutex);
}
static void mt6357tsbuck1_start_thermal_timer(void)
{
/* pr_debug("mtkts_pmic_start_thermal_timer\n"); */
/* resume thermal framework polling when leaving deep idle */
if (!isTimerCancelled)
return;
isTimerCancelled = 0;
if (down_trylock(&sem_mutex))
return;
if (thz_dev != NULL && interval != 0)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue),
round_jiffies(msecs_to_jiffies(1000)));
up(&sem_mutex);
}
static int mt6357tsbuck1_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register(
"sysrst.6357buck1", NULL, &mt6357tsbuck1_cooling_sysrst_ops);
return 0;
}
static int mt6357tsbuck1_register_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register(
"mt6357tsbuck1", num_trip, NULL, &mt6357tsbuck1_dev_ops,
0, 0, 0, interval * 1000);
return 0;
}
static void mt6357tsbuck1_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6357tsbuck1_unregister_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
if (thz_dev) {
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
}
}
static int mt6357tsbuck1_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6357tsbuck1_read, NULL);
}
static const struct file_operations mt6357tsbuck1_fops = {
.owner = THIS_MODULE,
.open = mt6357tsbuck1_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6357tsbuck1_write,
.release = single_release,
};
static int mt6357_ts_buck1_probe(struct platform_device *pdev)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6357tsbuck1_dir = NULL;
struct mt6397_chip *chip;
chip = (struct mt6397_chip *)dev_get_drvdata(pdev->dev.parent);
mtktspmic_info("[%s]\n", __func__);
mtktspmic_cali_prepare(chip->regmap);
mtktspmic_cali_prepare2();
err = mt6357tsbuck1_register_cooler();
if (err)
return err;
err = mt6357tsbuck1_register_thermal();
if (err)
goto err_unreg;
mt6357tsbuck1_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6357tsbuck1_dir) {
mtktspmic_info("[%s]: mkdir /proc/driver/thermal failed\n",
__func__);
} else {
entry =
proc_create("tz6357buck1", 0664,
mt6357tsbuck1_dir, &mt6357tsbuck1_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6357tsbuck1",
mt6357tsbuck1_start_thermal_timer,
mt6357tsbuck1_cancel_thermal_timer);
return 0;
err_unreg:
mt6357tsbuck1_unregister_cooler();
return err;
}
static const struct of_device_id mt6357_ts_buck1_of_match[] = {
{.compatible = "mediatek,mt6357_ts_buck1",},
{},
};
MODULE_DEVICE_TABLE(of, mt6357_ts_buck1_of_match);
static struct platform_driver mt6357_ts_buck1_driver = {
.probe = mt6357_ts_buck1_probe,
.driver = {
.name = "mt6357_ts_buck1",
.of_match_table = mt6357_ts_buck1_of_match,
},
};
static int __init mt6357tsbuck1_init(void)
{
return platform_driver_register(&mt6357_ts_buck1_driver);
}
static void __exit mt6357tsbuck1_exit(void)
{
mtktspmic_info("[%s]\n", __func__);
mt6357tsbuck1_unregister_thermal();
mt6357tsbuck1_unregister_cooler();
mtkTTimer_unregister("mt6357tsbuck1");
platform_driver_unregister(&mt6357_ts_buck1_driver);
}
module_init(mt6357tsbuck1_init);
module_exit(mt6357tsbuck1_exit);
MODULE_DESCRIPTION("MEDIATEK Thermal zone PMIC buck1 temperature sensor");
MODULE_LICENSE("GPL v2");

626
drivers/misc/mediatek/thermal/mt6765/src/mtk_ts_6357buck2.c
View File

@@ -1,626 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
//#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
#include <linux/mfd/mt6397/core.h>/* PMIC MFD core header */
#include <linux/regmap.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int isTimerCancelled;
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2 && curr_temp < polling_trip_temp1,
* use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 150000, 110000, 100000, 90000,
80000, 70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = "sysrst.6357buck2";
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long mt6357tsbuck2_cur_temp;
/*
*static long int mt6357tsbuck2_start_temp;
*static long int mt6357tsbuck2_end_temp;
*/
/*=============================================================*/
static int mt6357tsbuck2_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6357tsbuck2_get_hw_temp();
mt6357tsbuck2_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6357tsbuck2_bind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[%s] error binding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] binding OK, %d\n", __func__, table_val);
return 0;
}
static int mt6357tsbuck2_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info("[%s] error unbinding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] unbinding OK\n", __func__);
return 0;
}
static int mt6357tsbuck2_get_mode(struct thermal_zone_device *thermal,
enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6357tsbuck2_set_mode(struct thermal_zone_device *thermal,
enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6357tsbuck2_get_trip_type(struct thermal_zone_device *thermal,
int trip, enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6357tsbuck2_get_trip_temp(struct thermal_zone_device *thermal,
int trip, int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6357tsbuck2_get_crit_temp(struct thermal_zone_device *thermal,
int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6357tsbuck2_dev_ops = {
.bind = mt6357tsbuck2_bind,
.unbind = mt6357tsbuck2_unbind,
.get_temp = mt6357tsbuck2_get_temp,
.get_mode = mt6357tsbuck2_get_mode,
.set_mode = mt6357tsbuck2_set_mode,
.get_trip_type = mt6357tsbuck2_get_trip_type,
.get_trip_temp = mt6357tsbuck2_get_trip_temp,
.get_crit_temp = mt6357tsbuck2_get_crit_temp,
};
static int mt6357tsbuck2_sysrst_get_max_state(struct thermal_cooling_device
*cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6357tsbuck2_sysrst_get_cur_state(struct thermal_cooling_device
*cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6357tsbuck2_sysrst_set_cur_state(struct thermal_cooling_device
*cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("MT6357TSBUCK2 OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
}
return 0;
}
static struct thermal_cooling_device_ops mt6357tsbuck2_cooling_sysrst_ops = {
.get_max_state = mt6357tsbuck2_sysrst_get_max_state,
.get_cur_state = mt6357tsbuck2_sysrst_get_cur_state,
.set_cur_state = mt6357tsbuck2_sysrst_set_cur_state,
};
static int mt6357tsbuck2_read(struct seq_file *m, void *v)
{
seq_printf(m,
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
__func__, trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
seq_printf(m,
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8], trip_temp[9]);
seq_printf(m,
"g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d, g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2],
g_THERMAL_TRIP[3]);
seq_printf(m,
"g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d, g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6],
g_THERMAL_TRIP[7]);
seq_printf(m,
"g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
seq_printf(m,
"cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m,
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s, time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6357tsbuck2_register_thermal(void);
static void mt6357tsbuck2_unregister_thermal(void);
static ssize_t mt6357tsbuck2_write(struct file *file,
const char __user *buffer, size_t count, loff_t *data)
{
int len = 0;
int i;
struct mt6357tsbuck2_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6357tsbuck2_data *ptr_mt6357tsbuck2_data;
ptr_mt6357tsbuck2_data = kmalloc(sizeof(*ptr_mt6357tsbuck2_data),
GFP_KERNEL);
if (ptr_mt6357tsbuck2_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6357tsbuck2_data->desc) - 1)) ? count :
(sizeof(ptr_mt6357tsbuck2_data->desc) - 1);
if (copy_from_user(ptr_mt6357tsbuck2_data->desc, buffer, len)) {
kfree(ptr_mt6357tsbuck2_data);
return 0;
}
ptr_mt6357tsbuck2_data->desc[len] = '\0';
if (sscanf
(ptr_mt6357tsbuck2_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6357tsbuck2_data->trip[0],
&ptr_mt6357tsbuck2_data->t_type[0],
ptr_mt6357tsbuck2_data->bind0,
&ptr_mt6357tsbuck2_data->trip[1],
&ptr_mt6357tsbuck2_data->t_type[1],
ptr_mt6357tsbuck2_data->bind1,
&ptr_mt6357tsbuck2_data->trip[2],
&ptr_mt6357tsbuck2_data->t_type[2],
ptr_mt6357tsbuck2_data->bind2,
&ptr_mt6357tsbuck2_data->trip[3],
&ptr_mt6357tsbuck2_data->t_type[3],
ptr_mt6357tsbuck2_data->bind3,
&ptr_mt6357tsbuck2_data->trip[4],
&ptr_mt6357tsbuck2_data->t_type[4],
ptr_mt6357tsbuck2_data->bind4,
&ptr_mt6357tsbuck2_data->trip[5],
&ptr_mt6357tsbuck2_data->t_type[5],
ptr_mt6357tsbuck2_data->bind5,
&ptr_mt6357tsbuck2_data->trip[6],
&ptr_mt6357tsbuck2_data->t_type[6],
ptr_mt6357tsbuck2_data->bind6,
&ptr_mt6357tsbuck2_data->trip[7],
&ptr_mt6357tsbuck2_data->t_type[7],
ptr_mt6357tsbuck2_data->bind7,
&ptr_mt6357tsbuck2_data->trip[8],
&ptr_mt6357tsbuck2_data->t_type[8],
ptr_mt6357tsbuck2_data->bind8,
&ptr_mt6357tsbuck2_data->trip[9],
&ptr_mt6357tsbuck2_data->t_type[9],
ptr_mt6357tsbuck2_data->bind9,
&ptr_mt6357tsbuck2_data->time_msec) == 32) {
down(&sem_mutex);
mtktspmic_dprintk(
"[%s]mt6357tsbuck2_unregister_thermal\n", __func__);
mt6357tsbuck2_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(
__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6357tsbuck2_write", "Bad argument");
#endif
mtktspmic_dprintk(
"[%s] bad argument\n", __func__);
kfree(ptr_mt6357tsbuck2_data);
up(&sem_mutex);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6357tsbuck2_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] = g_bind4[0] =
g_bind5[0] =
g_bind6[0] = g_bind7[0] = g_bind8[0] = g_bind9[0] = '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6357tsbuck2_data->bind0[i];
g_bind1[i] = ptr_mt6357tsbuck2_data->bind1[i];
g_bind2[i] = ptr_mt6357tsbuck2_data->bind2[i];
g_bind3[i] = ptr_mt6357tsbuck2_data->bind3[i];
g_bind4[i] = ptr_mt6357tsbuck2_data->bind4[i];
g_bind5[i] = ptr_mt6357tsbuck2_data->bind5[i];
g_bind6[i] = ptr_mt6357tsbuck2_data->bind6[i];
g_bind7[i] = ptr_mt6357tsbuck2_data->bind7[i];
g_bind8[i] = ptr_mt6357tsbuck2_data->bind8[i];
g_bind9[i] = ptr_mt6357tsbuck2_data->bind9[i];
}
mtktspmic_dprintk(
"[%s] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
__func__, g_THERMAL_TRIP[0], g_THERMAL_TRIP[1],
g_THERMAL_TRIP[2]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4],
g_THERMAL_TRIP[5],
g_THERMAL_TRIP[6]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
mtktspmic_dprintk(
"[%s] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
__func__, g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk(
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6357tsbuck2_data->trip[i];
interval = ptr_mt6357tsbuck2_data->time_msec / 1000;
mtktspmic_dprintk(
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
__func__,
trip_temp[0], trip_temp[1], trip_temp[2], trip_temp[3]);
mtktspmic_dprintk(
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8]);
mtktspmic_dprintk(
"trip_9_temp=%d,time_ms=%d\n", trip_temp[9],
interval * 1000);
mtktspmic_dprintk(
"[%s]mt6357tsbuck2_register_thermal\n", __func__);
mt6357tsbuck2_register_thermal();
up(&sem_mutex);
kfree(ptr_mt6357tsbuck2_data);
return count;
}
mtktspmic_dprintk("[%s] bad argument\n", __func__);
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6357tsbuck2_write", "Bad argument");
#endif
kfree(ptr_mt6357tsbuck2_data);
return -EINVAL;
}
static void mt6357tsbuck2_cancel_thermal_timer(void)
{
/* cancel timer */
/* pr_debug("mtkts_pmic_cancel_thermal_timer\n"); */
/* stop thermal framework polling when entering deep idle */
if (down_trylock(&sem_mutex))
return;
if (thz_dev) {
cancel_delayed_work(&(thz_dev->poll_queue));
isTimerCancelled = 1;
}
up(&sem_mutex);
}
static void mt6357tsbuck2_start_thermal_timer(void)
{
/* pr_debug("mtkts_pmic_start_thermal_timer\n"); */
/* resume thermal framework polling when leaving deep idle */
if (!isTimerCancelled)
return;
isTimerCancelled = 0;
if (down_trylock(&sem_mutex))
return;
if (thz_dev != NULL && interval != 0)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue), round_jiffies(msecs_to_jiffies(1000)));
up(&sem_mutex);
}
static int mt6357tsbuck2_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register(
"sysrst.6357buck2", NULL, &mt6357tsbuck2_cooling_sysrst_ops);
return 0;
}
static int mt6357tsbuck2_register_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register("mt6357tsbuck2",
num_trip, NULL, &mt6357tsbuck2_dev_ops,
0, 0, 0, interval * 1000);
return 0;
}
static void mt6357tsbuck2_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6357tsbuck2_unregister_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
if (thz_dev) {
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
}
}
static int mt6357tsbuck2_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6357tsbuck2_read, NULL);
}
static const struct file_operations mt6357tsbuck2_fops = {
.owner = THIS_MODULE,
.open = mt6357tsbuck2_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6357tsbuck2_write,
.release = single_release,
};
static int mt6357_ts_buck2_probe(struct platform_device *pdev)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6357tsbuck2_dir = NULL;
struct mt6397_chip *chip;
chip = (struct mt6397_chip *)dev_get_drvdata(pdev->dev.parent);
mtktspmic_info("[%s]\n", __func__);
mtktspmic_cali_prepare(chip->regmap);
mtktspmic_cali_prepare2();
err = mt6357tsbuck2_register_cooler();
if (err)
return err;
err = mt6357tsbuck2_register_thermal();
if (err)
goto err_unreg;
mt6357tsbuck2_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6357tsbuck2_dir) {
mtktspmic_info("[%s]: mkdir /proc/driver/thermal failed\n",
__func__);
} else {
entry =
proc_create("tz6357buck2", 0664,
mt6357tsbuck2_dir, &mt6357tsbuck2_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6357tsbuck2", mt6357tsbuck2_start_thermal_timer,
mt6357tsbuck2_cancel_thermal_timer);
return 0;
err_unreg:
mt6357tsbuck2_unregister_cooler();
return err;
}
static const struct of_device_id mt6357_ts_buck2_of_match[] = {
{.compatible = "mediatek,mt6357_ts_buck2",},
{},
};
MODULE_DEVICE_TABLE(of, mt6357_ts_buck2_of_match);
static struct platform_driver mt6357_ts_buck2_driver = {
.probe = mt6357_ts_buck2_probe,
.driver = {
.name = "mt6357_ts_buck2",
.of_match_table = mt6357_ts_buck2_of_match,
},
};
static int __init mt6357tsbuck2_init(void)
{
return platform_driver_register(&mt6357_ts_buck2_driver);
}
static void __exit mt6357tsbuck2_exit(void)
{
mtktspmic_info("[%s]\n", __func__);
mt6357tsbuck2_unregister_thermal();
mt6357tsbuck2_unregister_cooler();
mtkTTimer_unregister("mt6357tsbuck2");
platform_driver_unregister(&mt6357_ts_buck2_driver);
}
module_init(mt6357tsbuck2_init);
module_exit(mt6357tsbuck2_exit);

42
drivers/misc/mediatek/thermal/mt6779/inc/tmp_bts.h
View File

@@ -1,42 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __TMP_BTS_H__
#define __TMP_BTS_H__
#define APPLY_PRECISE_NTC_TABLE
#define APPLY_AUXADC_CALI_DATA
#define AUX_IN0_NTC (0)
#define AUX_IN1_NTC (1)
#define BTS_RAP_PULL_UP_R 390000 /* 390K, pull up resister */
#define BTS_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp
* default value -40 deg
*/
#define BTS_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTS_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTS_RAP_ADC_CHANNEL AUX_IN0_NTC /* default is 0 */
#define BTSMDPA_RAP_PULL_UP_R 390000 /* 390K, pull up resister */
#define BTSMDPA_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp
* default value -40 deg
*/
#define BTSMDPA_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTSMDPA_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTSMDPA_RAP_ADC_CHANNEL AUX_IN1_NTC /* default is 1 */
extern int IMM_GetOneChannelValue(int dwChannel, int data[4], int *rawdata);
extern int IMM_IsAdcInitReady(void);
#endif /* __TMP_BTS_H__ */

17
drivers/misc/mediatek/thermal/mt6781/inc/clatm_initcfg.h
View File

@@ -15,9 +15,9 @@
#define CLATM_INIT_CFG_0_THETA_RISE (2)
#define CLATM_INIT_CFG_0_THETA_FALL (8)
#define CLATM_INIT_CFG_0_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_0_MIN_CPU_PWR (300)
#define CLATM_INIT_CFG_0_MIN_CPU_PWR (500)
#define CLATM_INIT_CFG_0_MAX_CPU_PWR (3960)
#define CLATM_INIT_CFG_0_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_0_MIN_GPU_PWR (300)
#define CLATM_INIT_CFG_0_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_1_TARGET_TJ (65000)
@@ -44,7 +44,7 @@
#define CLATM_INIT_CFG_ACTIVE_ATM_COOLER (0)
#define CLATM_INIT_CFG_CATM (0)
#define CLATM_INIT_CFG_CATM (2)
#define CLATM_INIT_CFG_PHPB_CPU_TT (10)
#define CLATM_INIT_CFG_PHPB_CPU_TP (50)
@@ -55,6 +55,17 @@
#define CLATM_INIT_HRTIMER_POLLING_DELAY (50)
#define CLATM_USE_MIN_CPU_OPP (1)
#define CLCTM_TARGET_TJ (90000)
#define CLCTM_TPCB_1 (47000)
#define CLCTM_TPCB_2 (51000)
#define CLCTM_EXIT_TJ (CLCTM_TARGET_TJ - 10000)
#define CLCTM_AE (CLCTM_TARGET_TJ)
#define CLCTM_BE (0)
#define CLCTM_AX (CLCTM_EXIT_TJ)
#define CLCTM_BX (0)
#define CLCTM_TT_HIGH (500)
#define CLCTM_TT_LOW (500)
#define CLCTM_STEADY_TTJ_DELTA (13500)
#define CLATM_CONFIGURABLE_TIMER

5
drivers/misc/mediatek/thermal/mt6781/inc/tmp_bts.h
View File

@@ -37,7 +37,10 @@
#define BTSMDPA_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTSMDPA_RAP_ADC_CHANNEL AUX_IN1_NTC /* default is 1 */
#define BTS_BLKNTC_RAP_PULL_UP_R 390000 /*390k PULL UP resister*/
#define BTS_BLKNTC_TAP_OVER_CRITICAL_LOW 4397119 /*BASE ON 100K NTC TEMP DEFAULT VALUE - 40 DEG*/
#define BTS_BLKNTC_RAP_PULL_UP_VOLTAGE 1800 /*1.8v PULL UP VOLTAGE*/
#define BTS_BLKNTC_RAP_NTC_TABLE 7 /*default is ncp 15wf104f03rc 100k*/
#define BTSNRPA_RAP_PULL_UP_R 100000 /* 100K,pull up resister */
#define BTSNRPA_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp

10
drivers/misc/mediatek/thermal/mt6781/inc/tzbatt_initcfg.h
View File

@@ -9,16 +9,16 @@
#define TZBATT_SET_INIT_CFG (1)
#define TZBATT_INITCFG_INTERVAL (1)
#define TZBATT_INITCFG_NUM_TRIPS (3)
#define TZBATT_INITCFG_NUM_TRIPS (1)
#define TZBATT_INITCFG_TRIP_0_TEMP (49000)
#define TZBATT_INITCFG_TRIP_0_COOLER "mtk-cl-bcct02"
#define TZBATT_INITCFG_TRIP_0_TEMP (60000)
#define TZBATT_INITCFG_TRIP_0_COOLER "mtktsbattery-sysrst"
#define TZBATT_INITCFG_TRIP_1_TEMP (48000)
#define TZBATT_INITCFG_TRIP_1_COOLER "mtk-cl-bcct01"
#define TZBATT_INITCFG_TRIP_1_COOLER ""
#define TZBATT_INITCFG_TRIP_2_TEMP (46000)
#define TZBATT_INITCFG_TRIP_2_COOLER "mtk-cl-bcct00"
#define TZBATT_INITCFG_TRIP_2_COOLER ""
#define TZBATT_INITCFG_TRIP_3_TEMP (45000)
#define TZBATT_INITCFG_TRIP_3_COOLER ""

18
drivers/misc/mediatek/thermal/mt6781/inc/tzcpu_initcfg.h
View File

@@ -9,22 +9,22 @@
#define TZCPU_SET_INIT_CFG (1)
#define TZCPU_INITCFG_INTERVAL (40)
#define TZCPU_INITCFG_NUM_TRIPS (4)
#define TZCPU_INITCFG_INTERVAL (200)
#define TZCPU_INITCFG_NUM_TRIPS (2)
#define TZCPU_INITCFG_TRIP_0_TEMP (113500)
#define TZCPU_INITCFG_TRIP_0_COOLER "mtktscpu-sysrst"
#define TZCPU_INITCFG_TRIP_1_TEMP (95000)
#define TZCPU_INITCFG_TRIP_1_COOLER "cpu00"
#define TZCPU_INITCFG_TRIP_1_TEMP (65000)
#define TZCPU_INITCFG_TRIP_1_COOLER "cpu_adaptive_0"
#define TZCPU_INITCFG_TRIP_2_TEMP (85000)
#define TZCPU_INITCFG_TRIP_2_COOLER "cpu03"
#define TZCPU_INITCFG_TRIP_2_TEMP (64000)
#define TZCPU_INITCFG_TRIP_2_COOLER ""
#define TZCPU_INITCFG_TRIP_3_TEMP (65000)
#define TZCPU_INITCFG_TRIP_3_COOLER "cpu_adaptive_0"
#define TZCPU_INITCFG_TRIP_3_TEMP (63000)
#define TZCPU_INITCFG_TRIP_3_COOLER ""
#define TZCPU_INITCFG_TRIP_4_TEMP (63000)
#define TZCPU_INITCFG_TRIP_4_TEMP (62000)
#define TZCPU_INITCFG_TRIP_4_COOLER ""
#define TZCPU_INITCFG_TRIP_5_TEMP (60000)

14
drivers/misc/mediatek/thermal/mt6873/Makefile
View File

@@ -1,14 +0,0 @@
#
# Copyright (C) 2018 MediaTek Inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
obj-y += src/

57
drivers/misc/mediatek/thermal/mt6873/inc/clatm_initcfg.h
View File

@@ -1,57 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __CLATM_INITCFG_H__
#define __CLATM_INITCFG_H__
#define CLATM_SET_INIT_CFG (1)
#define CLATM_INIT_CFG_0_TARGET_TJ (75000)
#define CLATM_INIT_CFG_0_EXIT_POINT (10000)
#define CLATM_INIT_CFG_0_FIRST_STEP (3960)
#define CLATM_INIT_CFG_0_THETA_RISE (2)
#define CLATM_INIT_CFG_0_THETA_FALL (8)
#define CLATM_INIT_CFG_0_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_0_MIN_CPU_PWR (300)
#define CLATM_INIT_CFG_0_MAX_CPU_PWR (3960)
#define CLATM_INIT_CFG_0_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_0_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_1_TARGET_TJ (65000)
#define CLATM_INIT_CFG_1_EXIT_POINT (10000)
#define CLATM_INIT_CFG_1_FIRST_STEP (3000)
#define CLATM_INIT_CFG_1_THETA_RISE (2)
#define CLATM_INIT_CFG_1_THETA_FALL (8)
#define CLATM_INIT_CFG_1_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_1_MIN_CPU_PWR (300)
#define CLATM_INIT_CFG_1_MAX_CPU_PWR (3000)
#define CLATM_INIT_CFG_1_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_1_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_2_TARGET_TJ (75000)
#define CLATM_INIT_CFG_2_EXIT_POINT (10000)
#define CLATM_INIT_CFG_2_FIRST_STEP (3960)
#define CLATM_INIT_CFG_2_THETA_RISE (2)
#define CLATM_INIT_CFG_2_THETA_FALL (8)
#define CLATM_INIT_CFG_2_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_2_MIN_CPU_PWR (600)
#define CLATM_INIT_CFG_2_MAX_CPU_PWR (3960)
#define CLATM_INIT_CFG_2_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_2_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_ACTIVE_ATM_COOLER (0)
#define CLATM_INIT_CFG_CATM (0)
#define CLATM_INIT_CFG_PHPB_CPU_TT (10)
#define CLATM_INIT_CFG_PHPB_CPU_TP (10)
#define CLATM_INIT_CFG_PHPB_GPU_TT (80)
#define CLATM_INIT_CFG_PHPB_GPU_TP (80)
#define CLATM_INIT_HRTIMER_POLLING_DELAY (50)
#define CLATM_USE_MIN_CPU_OPP (1)
#endif /* __CLATM_INITCFG_H__ */

251
drivers/misc/mediatek/thermal/mt6873/inc/mach/mtk_thermal.h
View File

@@ -1,251 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT6785_THERMAL_H__
#define __MT6785_THERMAL_H__
#include <linux/module.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include "mt-plat/sync_write.h"
#include "mtk_thermal_typedefs.h"
/* TODO: remove this! */
/*#define GPUFREQ_NOT_READY*/
#ifdef GPUFREQ_NOT_READY
struct mt_gpufreq_power_table_info {
unsigned int gpufreq_khz;
unsigned int gpufreq_volt;
unsigned int gpufreq_power;
};
#else
#include "mtk_gpufreq.h"
#endif
/*=============================================================
* LVTS SW Configs
*=============================================================
*/
#define CFG_THERM_LVTS (1)
#define CFG_THERM_NO_AUXADC (1)
#if CFG_THERM_LVTS
#define CFG_LVTS_DOMINATOR (1)
#define LVTS_THERMAL_CONTROLLER_HW_FILTER (1) /* 1, 2, 4, 8, 16 */
#define LVTS_DEVICE_AUTO_RCK (1)
/*Use bootup "count RC", no need to get "count RC" again after resume*/
#define CFG_THERM_USE_BOOTUP_COUNT_RC
#else
#define CFG_LVTS_DOMINATOR (0)
#define LVTS_THERMAL_CONTROLLER_HW_FILTER (0)
#define LVTS_DEVICE_AUTO_RCK (1)
#endif
/*
*There is no idle code in kernel since mt6885(big sw).
*Thus, kernel only can use "cpu pm notifier" to do idle scenario things.
*
*Release LVTS in thermal kernel driver
*1. SPM will pause LVTS thermal controllers before closing 26M
*2. After leaving SODI3, SPM will release LVTS thermal controllers
* if controllers were paused properly.
*3. After leaving SODI3, Thermal driver will release LVTS thermal
* controllers if SPM didn't release controller successfully
*/
#define LVTS_CPU_PM_NTFY_CALLBACK
#if defined(LVTS_CPU_PM_NTFY_CALLBACK)
#define CFG_THERM_SODI3_RELEASE
//#define LVTS_CPU_PM_NTFY_PROFILE
#endif
/* public thermal sensor enum */
enum thermal_sensor {
#if CFG_THERM_LVTS
TS_LVTS1_0 = 0,
TS_LVTS1_1,
TS_LVTS2_0,
TS_LVTS2_1,
TS_LVTS3_0,
TS_LVTS3_1,
TS_LVTS3_2,
TS_LVTS3_3,
TS_LVTS4_0,
TS_LVTS4_1,
TS_LVTS5_0,
TS_LVTS5_1,
TS_LVTS6_0,
TS_LVTS6_1,
TS_LVTS7_0,
TS_LVTS7_1,
TS_LVTS7_2,
#endif
TS_ENUM_MAX
};
enum thermal_bank_name {
THERMAL_BANK0 = 0,
THERMAL_BANK1,
THERMAL_BANK2,
THERMAL_BANK3,
THERMAL_BANK4,
THERMAL_BANK5,
THERMAL_BANK_NUM
};
struct TS_PTPOD {
unsigned int ts_MTS;
unsigned int ts_BTS;
};
extern int mtktscpu_limited_dmips;
extern int tscpu_get_temperature_range(void);
/* Valid if it returns 1, invalid if it returns 0. */
extern int tscpu_is_temp_valid(void);
extern void get_thermal_slope_intercept(
struct TS_PTPOD *ts_info, enum thermal_bank_name ts_bank);
#if CFG_THERM_LVTS
extern void get_lvts_slope_intercept(
struct TS_PTPOD *ts_info, enum thermal_bank_name ts_bank);
#endif
extern void set_taklking_flag(bool flag);
extern int tscpu_get_cpu_temp(void);
extern int tscpu_get_temp_by_bank(enum thermal_bank_name ts_bank);
#define THERMAL_WRAP_WR32(val, addr) \
mt_reg_sync_writel((val), ((void *)addr))
extern int get_immediate_cpuL_wrap(void);
extern int get_immediate_cpuB_wrap(void);
extern int get_immediate_mcucci_wrap(void);
extern int get_immediate_gpu_wrap(void);
extern int get_immediate_vpu_wrap(void);
extern int get_immediate_top_wrap(void);
extern int get_immediate_md_wrap(void);
/* Added for DLPT/EARA */
extern int tscpu_get_min_cpu_pwr(void);
extern int tscpu_get_min_gpu_pwr(void);
extern int tscpu_get_min_vpu_pwr(void);
extern int tscpu_get_min_mdla_pwr(void);
extern void lvts_ipi_send_efuse_data(void);
extern void lvts_ipi_send_sspm_thermal_thtottle(void);
extern void lvts_ipi_send_sspm_thermal_suspend_resume(int is_suspend);
/* Five thermal sensors. */
enum mtk_thermal_sensor_cpu_id_met {
#if CFG_THERM_LVTS
MTK_THERMAL_SENSOR_LVTS1_0,
MTK_THERMAL_SENSOR_LVTS1_1,
MTK_THERMAL_SENSOR_LVTS2_0,
MTK_THERMAL_SENSOR_LVTS2_1,
MTK_THERMAL_SENSOR_LVTS3_0,
MTK_THERMAL_SENSOR_LVTS3_1,
MTK_THERMAL_SENSOR_LVTS3_2,
MTK_THERMAL_SENSOR_LVTS3_3,
MTK_THERMAL_SENSOR_LVTS4_0,
MTK_THERMAL_SENSOR_LVTS4_1,
MTK_THERMAL_SENSOR_LVTS5_0,
MTK_THERMAL_SENSOR_LVTS5_1,
MTK_THERMAL_SENSOR_LVTS6_0,
MTK_THERMAL_SENSOR_LVTS6_1,
MTK_THERMAL_SENSOR_LVTS7_0,
MTK_THERMAL_SENSOR_LVTS7_1,
MTK_THERMAL_SENSOR_LVTS7_2,
#endif
ATM_CPU_LIMIT,
ATM_GPU_LIMIT,
MTK_THERMAL_SENSOR_CPU_COUNT
};
extern int tscpu_get_cpu_temp_met(enum mtk_thermal_sensor_cpu_id_met id);
typedef void (*met_thermalsampler_funcMET)(void);
extern void mt_thermalsampler_registerCB(met_thermalsampler_funcMET pCB);
extern void mtkTTimer_cancel_timer(void);
extern void mtkTTimer_start_timer(void);
extern int mtkts_bts_get_hw_temp(void);
extern int get_immediate_ts0_wrap(void);
extern int get_immediate_ts1_wrap(void);
extern int get_immediate_ts2_wrap(void);
extern int get_immediate_ts3_wrap(void);
extern int get_immediate_ts4_wrap(void);
extern int get_immediate_ts5_wrap(void);
extern int get_immediate_ts6_wrap(void);
extern int get_immediate_ts7_wrap(void);
extern int get_immediate_ts8_wrap(void);
extern int get_immediate_ts9_wrap(void);
#if CFG_THERM_LVTS
extern int get_immediate_tslvts1_0_wrap(void);
extern int get_immediate_tslvts1_1_wrap(void);
extern int get_immediate_tslvts2_0_wrap(void);
extern int get_immediate_tslvts2_1_wrap(void);
extern int get_immediate_tslvts3_0_wrap(void);
extern int get_immediate_tslvts3_1_wrap(void);
extern int get_immediate_tslvts3_2_wrap(void);
extern int get_immediate_tslvts3_3_wrap(void);
extern int get_immediate_tslvts4_0_wrap(void);
extern int get_immediate_tslvts4_1_wrap(void);
extern int get_immediate_tslvts5_0_wrap(void);
extern int get_immediate_tslvts5_1_wrap(void);
extern int get_immediate_tslvts6_0_wrap(void);
extern int get_immediate_tslvts6_1_wrap(void);
extern int get_immediate_tslvts7_0_wrap(void);
extern int get_immediate_tslvts7_1_wrap(void);
extern int get_immediate_tslvts7_2_wrap(void);
#endif
extern int get_immediate_tsabb_wrap(void);
extern int (*get_immediate_tsX[TS_ENUM_MAX])(void);
extern int is_cpu_power_unlimit(void); /* in mtk_ts_cpu.c */
extern int is_cpu_power_min(void); /* in mtk_ts_cpu.c */
extern int get_cpu_target_tj(void);
extern int get_cpu_target_offset(void);
extern int mtk_gpufreq_register(
struct mt_gpufreq_power_table_info *freqs, int num);
extern int get_target_tj(void);
extern int mtk_thermal_get_tpcb_target(void);
extern void thermal_set_big_core_speed(
unsigned int tempMonCtl1, unsigned int tempMonCtl2, unsigned int tempAhbPoll);
/*
* return value(1): cooler of abcct/abcct_lcmoff is deactive,
* and no thermal current limit.
*/
extern int mtk_cooler_is_abcct_unlimit(void);
extern int tscpu_kernel_status(void);
#endif /* __MT6785_THERMAL_H__ */

11
drivers/misc/mediatek/thermal/mt6873/inc/mtk_cl_amddulthro.h
View File

@@ -1,11 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_CL_AMDDULTHRO_H__
#define __MT_CL_AMDDULTHRO_H__
extern int amddulthro_backoff(int level);
#endif /* __MT_CL_AMDDULTHRO_H__ */

33
drivers/misc/mediatek/thermal/mt6873/inc/mtk_cooler_setting.h
View File

@@ -1,33 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MTK_COOLER_SETTING_H
#define _MTK_COOLER_SETTING_H
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/* mtk_cooler_mutt_gen97.c */
/* 1: turn on MD Thermal Warning Notification; 0: turn off */
#define FEATURE_THERMAL_DIAG (1)
/* mtk_cooler_mutt_gen97.c */
/* 1: turn on adaptive MD throttle cooler; 0: turn off */
#define FEATURE_ADAPTIVE_MUTT (1)
/* mtk_ta.c */
/* 1: turn on SPA; 0: turn off */
#define FEATURE_SPA (0)
/*APU(mdla/vpu) throttle*/
#define THERMAL_APU_UNLIMIT
#if defined(THERMAL_APU_UNLIMIT)
extern unsigned int cl_get_apu_status(void);
extern void cl_set_apu_status(int vv);
#endif
#endif /* _MTK_COOLER_SETTING_H */

86
drivers/misc/mediatek/thermal/mt6873/inc/mtk_thermal_ipi.h
View File

@@ -1,86 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MTK_THERMAL_IPI_H__
#define __MTK_THERMAL_IPI_H__
#ifdef CONFIG_MTK_TINYSYS_SSPM_SUPPORT
#define THERMAL_ENABLE_TINYSYS_SSPM (0)
#define THERMAL_ENABLE_ONLY_TZ_SSPM (1)
#define THERMAL_SSPM_THERMAL_THROTTLE_SWITCH
/*Only Big SW need to enable this definition
*Big SW suspend/resume flow:
* suspend: kernel suspend => SSPM suspend
* resume: SSPM resume => kernel resume
*/
/* THERMAL_KERNEL_SUSPEND_RESUME_NOTIFY means notify tinysys
* to start/stop reading temperature when kernel suspend/resume/shutdown
*/
#define THERMAL_KERNEL_SUSPEND_RESUME_NOTIFY
/* THERMAL_KERNEL_SUSPEND_RESUME_NOTIFY_ONLY_AT_SHUTDOWN means
* notify tinysys to stop reading temperature only when kernel shutodown
*/
#ifdef THERMAL_KERNEL_SUSPEND_RESUME_NOTIFY
#define THERMAL_KERNEL_SUSPEND_RESUME_NOTIFY_ONLY_AT_SHUTDOWN
#endif
#define THERMAL_CPUTOEB_USE_PLATFORM_IPI
#else
#define THERMAL_ENABLE_TINYSYS_SSPM (0)
#define THERMAL_ENABLE_ONLY_TZ_SSPM (1)
#endif
#if THERMAL_ENABLE_TINYSYS_SSPM || THERMAL_ENABLE_ONLY_TZ_SSPM
#include <mcupm_ipi_id.h>
#define THERMAL_SLOT_NUM (4)
#define BIG_CORE_THRESHOLD_ARRAY_SIZE (3)
/* IPI Msg type */
enum {
THERMAL_IPI_INIT_GRP1,
THERMAL_IPI_INIT_GRP2,
THERMAL_IPI_INIT_GRP3,
THERMAL_IPI_INIT_GRP4,
THERMAL_IPI_INIT_GRP5,
THERMAL_IPI_INIT_GRP6,
THERMAL_IPI_LVTS_INIT_GRP1,
THERMAL_IPI_GET_TEMP,
THERMAL_IPI_SET_ATM_CFG_GRP1,
THERMAL_IPI_SET_ATM_CFG_GRP2,
THERMAL_IPI_SET_ATM_CFG_GRP3,
THERMAL_IPI_SET_ATM_CFG_GRP4,
THERMAL_IPI_SET_ATM_CFG_GRP5,
THERMAL_IPI_SET_ATM_CFG_GRP6,
THERMAL_IPI_SET_ATM_CFG_GRP7,
THERMAL_IPI_SET_ATM_CFG_GRP8,
THERMAL_IPI_SET_ATM_TTJ,
THERMAL_IPI_SET_ATM_EN,
THERMAL_IPI_GET_ATM_CPU_LIMIT,
THERMAL_IPI_GET_ATM_GPU_LIMIT,
THERMAL_IPI_SET_BIG_FREQ_THRESHOLD,
THERMAL_IPI_GET_BIG_FREQ_THRESHOLD,
THERMAL_IPI_SET_DIS_THERMAL_THROTTLE,
THERMAL_IPI_SUSPEND_RESUME_NOTIFY,
NR_THERMAL_IPI
};
/* IPI Msg data structure */
struct thermal_ipi_data {
unsigned int cmd;
union {
struct {
int arg[THERMAL_SLOT_NUM - 1];
} data;
} u;
};
extern unsigned int thermal_to_mcupm(unsigned int cmd,
struct thermal_ipi_data *thermal_data);
extern int atm_to_sspm(unsigned int cmd, int data_len,
struct thermal_ipi_data *thermal_data, int *ackData);
#endif /* THERMAL_ENABLE_TINYSYS_SSPM */
#endif

16
drivers/misc/mediatek/thermal/mt6873/inc/mtk_ts_setting.h
View File

@@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MTK_TS_SETTING_H
#define _MTK_TS_SETTING_H
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/* mtk_ts_pa.c */
/* 1: turn on MD UL throughput update; 0: turn off */
#define Feature_Thro_update (1)
#endif /* _MTK_TS_SETTING_H */

11
drivers/misc/mediatek/thermal/mt6873/inc/tmp_6311buck.h
View File

@@ -1,11 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TMP_6311BUCK_H__
#define __TMP_6311BUCK_H__
extern int is_ext_buck_exist(void);
#endif /* __TMP_6311BUCK_H__ */

31
drivers/misc/mediatek/thermal/mt6873/inc/tmp_battery.h
View File

@@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TMP_BATTERY_H__
#define __TMP_BATTERY_H__
#include <charging.h>
/* Extern two API functions from battery driver
* to limit max charging current.
*/
/**
* return value means charging current in mA
* -1 means error
* Implementation in mt_battery.c and mt_battery_fan5405.c
*/
extern int get_bat_charging_current_level(void);
/**
* current_limit means limit of charging current in mA
* -1 means no limit
* Implementation in mt_battery.c and mt_battery_fan5405.c
*/
extern int set_bat_charging_current_limit(int current_limit);
extern enum charger_type mt_get_charger_type(void);
extern int read_tbat_value(void);
#endif /* __TMP_BATTERY_H__ */

55
drivers/misc/mediatek/thermal/mt6873/inc/tmp_bts.h
View File

@@ -1,55 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TMP_BTS_H__
#define __TMP_BTS_H__
#define APPLY_PRECISE_NTC_TABLE
#define APPLY_AUXADC_CALI_DATA
#define AUX_IN0_NTC (0)
#define AUX_IN1_NTC (1)
#define AUX_IN2_NTC (2)
#define BTS_RAP_PULL_UP_R 100000 /* 100K, pull up resister */
#define BTS_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp
* default value -40 deg
*/
#define BTS_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTS_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTS_RAP_ADC_CHANNEL AUX_IN0_NTC /* default is 0 */
#define BTSMDPA_RAP_PULL_UP_R 100000 /* 100K, pull up resister */
#define BTSMDPA_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp
* default value -40 deg
*/
#define BTSMDPA_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTSMDPA_RAP_NTC_TABLE 7 /* default is NCP15WF104F03RC(100K) */
#define BTSMDPA_RAP_ADC_CHANNEL AUX_IN1_NTC /* default is 1 */
#define BTSNRPA_RAP_PULL_UP_R 100000 /* 100K,pull up resister */
#define BTSNRPA_TAP_OVER_CRITICAL_LOW 4397119 /* base on 100K NTC temp
*default value -40 deg
*/
#define BTSNRPA_RAP_PULL_UP_VOLTAGE 1800 /* 1.8V ,pull up voltage */
#define BTSNRPA_RAP_NTC_TABLE 7
#define BTSNRPA_RAP_ADC_CHANNEL AUX_IN2_NTC
extern int IMM_GetOneChannelValue(int dwChannel, int data[4], int *rawdata);
extern int IMM_IsAdcInitReady(void);
#endif /* __TMP_BTS_H__ */

94
drivers/misc/mediatek/thermal/mt6873/inc/tscpu_lvts_config.h
View File

@@ -1,94 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TSCPU_LVTS_SETTINGS_H__
#define __TSCPU_LVTS_SETTINGS_H__
/*=============================================================
* Chip related
*=============================================================
*/
/* chip dependent */
/* TODO: change to new reg addr. */
#define LVTS_ADDRESS_INDEX_1 116 /* 0x11C101C0 */
#define LVTS_ADDRESS_INDEX_2 117 /* 0x11C101C4 */
#define LVTS_ADDRESS_INDEX_3 118 /* 0x11C101C8 */
#define LVTS_ADDRESS_INDEX_4 119 /* 0x11C101CC */
#define LVTS_ADDRESS_INDEX_5 190 /* 0x11C101D0 */
#define LVTS_ADDRESS_INDEX_6 191 /* 0x11C101D4 */
#define LVTS_ADDRESS_INDEX_7 192 /* 0x11C101D8 */
#define LVTS_ADDRESS_INDEX_8 193 /* 0x11C101DC */
#define LVTS_ADDRESS_INDEX_9 194 /* 0x11C101E0 */
#define LVTS_ADDRESS_INDEX_10 195 /* 0x11C101E4 */
#define LVTS_ADDRESS_INDEX_11 196 /* 0x11C101E8 */
#define LVTS_ADDRESS_INDEX_12 197 /* 0x11C101EC */
#define LVTS_ADDRESS_INDEX_13 198 /* 0x11C101F0 */
#define LVTS_ADDRESS_INDEX_14 199 /* 0x11C101F4 */
#define LVTS_ADDRESS_INDEX_15 200 /* 0x11C101F8 */
#define LVTS_ADDRESS_INDEX_16 201 /* 0x11C101FC */
#define LVTS_ADDRESS_INDEX_17 202 /* 0x11C10200 */
#define LVTS_ADDRESS_INDEX_18 203 /* 0x11C10204 */
#define LVTS_ADDRESS_INDEX_19 204 /* 0x11C10208 */
#define LVTS_ADDRESS_INDEX_20 205 /* 0x11C1020C */
#define LVTS_ADDRESS_INDEX_21 206 /* 0x11C10210 */
#define LVTS_ADDRESS_INDEX_22 207 /* 0x11C10214 */
/**************************************************************************** */
/* LVTS related registers. */
/**************************************************************************** */
#define LVTSMONCTL0_0 (THERM_CTRL_BASE_2 + 0x000)
#define LVTSMONCTL1_0 (THERM_CTRL_BASE_2 + 0x004)
#define LVTSMONCTL2_0 (THERM_CTRL_BASE_2 + 0x008)
#define LVTSMONINT_0 (THERM_CTRL_BASE_2 + 0x00C)
#define LVTSMONINTSTS_0 (THERM_CTRL_BASE_2 + 0x010)
#define LVTSMONIDET0_0 (THERM_CTRL_BASE_2 + 0x014)
#define LVTSMONIDET1_0 (THERM_CTRL_BASE_2 + 0x018)
#define LVTSMONIDET2_0 (THERM_CTRL_BASE_2 + 0x01C)
#define LVTSMONIDET3_0 (THERM_CTRL_BASE_2 + 0x020)
#define LVTSH2NTHRE_0 (THERM_CTRL_BASE_2 + 0x024)
#define LVTSHTHRE_0 (THERM_CTRL_BASE_2 + 0x028)
#define LVTSCTHRE_0 (THERM_CTRL_BASE_2 + 0x02C)
#define LVTSOFFSETH_0 (THERM_CTRL_BASE_2 + 0x030)
#define LVTSOFFSETL_0 (THERM_CTRL_BASE_2 + 0x034)
#define LVTSMSRCTL0_0 (THERM_CTRL_BASE_2 + 0x038)
#define LVTSMSRCTL1_0 (THERM_CTRL_BASE_2 + 0x03C)
#define LVTSTSSEL_0 (THERM_CTRL_BASE_2 + 0x040)
#define LVTSDEVICETO_0 (THERM_CTRL_BASE_2 + 0x044)
#define LVTSCALSCALE_0 (THERM_CTRL_BASE_2 + 0x048)
#define LVTS_ID_0 (THERM_CTRL_BASE_2 + 0x04C)
#define LVTS_CONFIG_0 (THERM_CTRL_BASE_2 + 0x050)
#define LVTSEDATA00_0 (THERM_CTRL_BASE_2 + 0x054)
#define LVTSEDATA01_0 (THERM_CTRL_BASE_2 + 0x058)
#define LVTSEDATA02_0 (THERM_CTRL_BASE_2 + 0x05C)
#define LVTSEDATA03_0 (THERM_CTRL_BASE_2 + 0x060)
#define LVTSMSR0_0 (THERM_CTRL_BASE_2 + 0x090)
#define LVTSMSR1_0 (THERM_CTRL_BASE_2 + 0x094)
#define LVTSMSR2_0 (THERM_CTRL_BASE_2 + 0x098)
#define LVTSMSR3_0 (THERM_CTRL_BASE_2 + 0x09C)
#define LVTSIMMD0_0 (THERM_CTRL_BASE_2 + 0x0A0)
#define LVTSIMMD1_0 (THERM_CTRL_BASE_2 + 0x0A4)
#define LVTSIMMD2_0 (THERM_CTRL_BASE_2 + 0x0A8)
#define LVTSIMMD3_0 (THERM_CTRL_BASE_2 + 0x0AC)
#define LVTSRDATA0_0 (THERM_CTRL_BASE_2 + 0x0B0)
#define LVTSRDATA1_0 (THERM_CTRL_BASE_2 + 0x0B4)
#define LVTSRDATA2_0 (THERM_CTRL_BASE_2 + 0x0B8)
#define LVTSRDATA3_0 (THERM_CTRL_BASE_2 + 0x0BC)
#define LVTSPROTCTL_0 (THERM_CTRL_BASE_2 + 0x0C0)
#define LVTSPROTTA_0 (THERM_CTRL_BASE_2 + 0x0C4)
#define LVTSPROTTB_0 (THERM_CTRL_BASE_2 + 0x0C8)
#define LVTSPROTTC_0 (THERM_CTRL_BASE_2 + 0x0CC)
#define LVTSCLKEN_0 (THERM_CTRL_BASE_2 + 0x0E4)
#define LVTSDBGSEL_0 (THERM_CTRL_BASE_2 + 0x0E8)
#define LVTSDBGSIG_0 (THERM_CTRL_BASE_2 + 0x0EC)
#define LVTSSPARE0_0 (THERM_CTRL_BASE_2 + 0x0F0)
#define LVTSSPARE1_0 (THERM_CTRL_BASE_2 + 0x0F4)
#define LVTSSPARE2_0 (THERM_CTRL_BASE_2 + 0x0F8)
#define LVTSSPARE3_0 (THERM_CTRL_BASE_2 + 0x0FC)
#define THERMINTST (THERM_CTRL_BASE_2 + 0xF04)
#endif /* __TSCPU_LVTS_SETTINGS_H__ */

791
drivers/misc/mediatek/thermal/mt6873/inc/tscpu_settings.h
View File

@@ -1,791 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TSCPU_SETTINGS_H__
#define __TSCPU_SETTINGS_H__
#include "mach/mtk_thermal.h"
#include <linux/of.h>
#include <linux/of_address.h>
#include "tzcpu_initcfg.h"
#include "clatm_initcfg.h"
#include "tscpu_tsense_config.h"
#include "tscpu_lvts_config.h"
/*=============================================================
* Genernal
*=============================================================
*/
#define MIN(_a_, _b_) ((_a_) > (_b_) ? (_b_) : (_a_))
#define MAX(_a_, _b_) ((_a_) > (_b_) ? (_a_) : (_b_))
#define _BIT_(_bit_) (unsigned int)(1 << (_bit_))
#define _BITMASK_(_bits_) (((unsigned int) -1 >> (31 - ((1) ? _bits_))) \
& ~((1U << ((0) ? _bits_)) - 1))
#define THERMAL_TPROFILE_INIT() \
long long thermal_pTime_us, thermal_cTime_us, thermal_diff_us
#define THERMAL_GET_PTIME() {thermal_pTime_us = thermal_get_current_time_us()}
#define THERMAL_GET_CTIME() {thermal_cTime_us = thermal_get_current_time_us()}
#define THERMAL_TIME_TH 3000
#define THERMAL_IS_TOO_LONG() \
do { \
thermal_diff_us = thermal_cTime_us - thermal_pTime_us; \
if (thermal_diff_us > THERMAL_TIME_TH) { \
pr_notice(TSCPU_LOG_TAG "%s: %llu us\n", __func__, \
thermal_diff_us); \
} else if (thermal_diff_us < 0) { \
pr_notice(TSCPU_LOG_TAG \
"Warning: tProfiling uses incorrect %s %d\n", \
__func__, __LINE__); \
} \
} while (0)
/*=============================================================
* CONFIG (SW related)
*=============================================================
*/
/*Enable thermal controller CG*/
#define THERMAL_EBABLE_TC_CG
#define ENALBE_UART_LIMIT (0)
#define TEMP_EN_UART (80000)
#define TEMP_DIS_UART (85000)
#define TEMP_TOLERANCE (0)
#define ENALBE_SW_FILTER (0)
#define ATM_USES_PPM (1)
#define THERMAL_GET_AHB_BUS_CLOCK (0)
#define THERMAL_PERFORMANCE_PROFILE (0)
/* 1: turn on GPIO toggle monitor; 0: turn off */
#define THERMAL_GPIO_OUT_TOGGLE (0)
/* 1: turn on adaptive AP cooler; 0: turn off */
#define CPT_ADAPTIVE_AP_COOLER (1)
/* 1: turn on supports to MET logging; 0: turn off */
#define CONFIG_SUPPORT_MET_MTKTSCPU (0)
/* Thermal controller HW filtering function.
* Only 1, 2, 4, 8, 16 are valid values,
* they means one reading is a avg of X samples
*/
#define THERMAL_CONTROLLER_HW_FILTER (2) /* 1, 2, 4, 8, 16 */
/* 1: turn on thermal controller HW thermal protection; 0: turn off */
#define THERMAL_CONTROLLER_HW_TP (1)
/* 1: turn on fast polling in this sw module; 0: turn off */
#define MTKTSCPU_FAST_POLLING (1)
#if CPT_ADAPTIVE_AP_COOLER
#define MAX_CPT_ADAPTIVE_COOLERS (3)
#define THERMAL_HEADROOM (0)
#define CONTINUOUS_TM (1)
#define DYNAMIC_GET_GPU_POWER (1)
/* 1: turn on precise power budgeting; 0: turn off */
#define PRECISE_HYBRID_POWER_BUDGET (1)
#define PHPB_DEFAULT_ON (1)
#endif
/* 1: thermal driver fast polling, use hrtimer; 0: turn off */
/*#define THERMAL_DRV_FAST_POLL_HRTIMER (1)*/
/* 1: thermal driver update temp to MET directly, use hrtimer; 0: turn off */
#define THERMAL_DRV_UPDATE_TEMP_DIRECT_TO_MET (1)
/* Define this in tscpu_settings.h enables this feature.
* It polls CPU TS in hrtimer and
* run ATM in RT 98 kthread. This is for MT6799 only.
*/
#define FAST_RESPONSE_ATM (1)
#define THERMAL_INIT_VALUE (0xDA1)
#define CLEAR_TEMP 26111
/* Thermal VPU throttling support */
#ifdef CONFIG_MTK_APUSYS_VPU
#define THERMAL_VPU_SUPPORT
#endif
/* Thermal MDLA throttling support */
#ifdef CONFIG_MTK_APUSYS_MDLA_SUPPORT
#define THERMAL_MDLA_SUPPORT
#endif
/* EARA_Thermal power budget allocation support */
#define EARA_THERMAL_SUPPORT
#define TS_FILL(n) {#n, n}
/*#define TS_LEN_ARRAY(name) (sizeof(name)/sizeof(name[0]))*/
#define MAX_TS_NAME 20
#define CPU_COOLER_NUM 34
#define MTK_TS_CPU_RT (0)
#ifdef CONFIG_MTK_RAM_CONSOLE
#define CONFIG_THERMAL_AEE_RR_REC (1)
#else
#define CONFIG_THERMAL_AEE_RR_REC (0)
#endif
#if CFG_THERM_LVTS
#define CONFIG_LVTS_ERROR_AEE_WARNING (0)
#define CONFIG_LVTS_DYNAMIC_ENABLE_REBOOT (1)
#define DYNAMIC_REBOOT_TRIP_TEMP (35000)
#define DYNAMIC_REBOOT_EXIT_TEMP (30000)
#else
#define CONFIG_LVTS_ERROR_AEE_WARNING (0)
#endif
#define DUMP_LVTS_REGISTER_FOR_ZERO_RAW_ISSUE (1)
#if CONFIG_LVTS_ERROR_AEE_WARNING
#define LVTS_FORCE_ERROR_TRIGGER (0)
#define LVTS_NUM_SKIP_SAMPLE (500)
#define HISTORY_SAMPLES (10)
#define FUTURE_SAMPLES (10)
#define R_BUFFER_SIZE (HISTORY_SAMPLES + FUTURE_SAMPLES + 1)
#define LVTS_ERROR_THRESHOLD (10000)
#define DUMP_LVTS_REGISTER (0)
#define DUMP_VCORE_VOLTAGE (0)
#endif
#define LVTS_VALID_DATA_TIME_PROFILING (0)
#define LVTS_USE_DOMINATOR_SENSING_POINT (1)
#define CFG_THERMAL_KERNEL_IGNORE_HOT_SENSOR (1)
/*=============================================================
*REG ACCESS
*=============================================================
*/
/* double check */
#define TS_CONFIGURE TS_CON1_TM /* depend on CPU design*/
#define TS_CONFIGURE_P TS_CON1_P /* depend on CPU design*/
/* turn on TS_CON1[5:4] 2'b 00 11001111 -> 0xCF ~(0x30)*/
#define TS_TURN_ON 0xFFFFFFCF
#define TS_TURN_OFF 0x00000030 /* turn off thermal*/
#define thermal_setl(addr, val) mt_reg_sync_writel(readl(addr) | (val), \
((void *)addr))
#define thermal_clrl(addr, val) mt_reg_sync_writel(readl(addr) & ~(val), \
((void *)addr))
#define MTKTSCPU_TEMP_CRIT 120000 /* 120.000 degree Celsius */
#define y_curr_repeat_times 1
#define THERMAL_NAME "mtk-thermal"
#define TS_MS_TO_NS(x) (x * 1000 * 1000)
/*cpu core nums*/
#define TZCPU_NO_CPU_CORES (8)
#if THERMAL_GET_AHB_BUS_CLOCK
#define THERMAL_MODULE_SW_CG_SET (therm_clk_infracfg_ao_base + 0x80)
#define THERMAL_MODULE_SW_CG_CLR (therm_clk_infracfg_ao_base + 0x84)
#define THERMAL_MODULE_SW_CG_STA (therm_clk_infracfg_ao_base + 0x90)
#define THERMAL_CG (therm_clk_infracfg_ao_base + 0x80)
#define THERMAL_DCM (therm_clk_infracfg_ao_base + 0x70)
#endif
/*=============================================================
* Common Structure and Enum
*=============================================================
*/
#if (CONFIG_THERMAL_AEE_RR_REC == 1)
enum thermal_state {
TSCPU_SUSPEND = 0,
TSCPU_RESUME = 1,
TSCPU_NORMAL = 2,
TSCPU_INIT = 3,
TSCPU_PAUSE = 4,
TSCPU_RELEASE = 5
};
enum atm_state {
ATM_WAKEUP = 0,
ATM_CPULIMIT = 1,
ATM_GPULIMIT = 2,
ATM_DONE = 3,
};
#endif
struct mtk_cpu_power_info {
unsigned int cpufreq_khz;
unsigned int cpufreq_ncpu;
unsigned int cpufreq_power;
};
/*=============================================================
* LVTS Structure and Enum
*=============================================================
*/
#if CFG_THERM_LVTS
/*
* module LVTS Plan
*=====================================================
* MCU_BIG(T1,T2) LVTS1-0, LVTS1-1
* MCU_BIG(T3,T4) LVTS2-0, LVTS2-1
* MCU_LITTLE(T5,T6,T7,T8) LVTS3-0, LVTS3-1, LVTS3-2, LVTS3-3
* VPU_MLDA(T9,T10) LVTS4-0, LVTS4-1
* GPU(T11,T12) LVTS5-0, LVTS5-1
* INFA(T13) LVTS6-0
* CAMSYS(T18) LVTS6-1
* MDSYS(T14,T15,T20) LVTS7-0, LVTS7-1, LVTS7-2
*/
/* private thermal sensor enum */
enum lvts_sensor_enum {
L_TS_LVTS1_0 = 0, /* LVTS1-0 1*/
L_TS_LVTS1_1, /* LVTS1-1 2*/
L_TS_LVTS2_0, /* LVTS2-0 3*/
L_TS_LVTS2_1, /* LVTS2-1 4*/
L_TS_LVTS3_0, /* LVTS3-0 5*/
L_TS_LVTS3_1, /* LVTS3-1 6*/
L_TS_LVTS3_2, /* LVTS3-2 7*/
L_TS_LVTS3_3, /* LVTS3-3 8*/
L_TS_LVTS4_0, /* LVTS4-0 9*/
L_TS_LVTS4_1, /* LVTS4-1 10*/
L_TS_LVTS5_0, /* LVTS5-0 11*/
L_TS_LVTS5_1, /* LVTS5-1 12*/
L_TS_LVTS6_0, /* LVTS6-0 13*/
L_TS_LVTS6_1, /* LVTS6-1 14*/
L_TS_LVTS7_0, /* LVTS7-0 15*/
L_TS_LVTS7_1, /* LVTS7-1 16*/
L_TS_LVTS7_2, /* LVTS7-2 17*/
L_TS_LVTS_NUM
};
enum lvts_tc_enum {
LVTS_MCU_CONTROLLER0 = 0,/* LVTSMONCTL0 */
LVTS_MCU_CONTROLLER1, /* LVTSMONCTL0_1 */
LVTS_MCU_CONTROLLER2, /* LVTSMONCTL0_2 */
LVTS_AP_CONTROLLER0, /* LVTSMONCTL0 */
LVTS_AP_CONTROLLER1, /* LVTSMONCTL0_1 */
LVTS_AP_CONTROLLER2, /* LVTSMONCTL0_2 */
LVTS_AP_CONTROLLER3, /* LVTSMONCTL0_3 */
LVTS_CONTROLLER_NUM
};
struct lvts_thermal_controller_speed {
unsigned int group_interval_delay;
unsigned int period_unit;
unsigned int filter_interval_delay;
unsigned int sensor_interval_delay;
};
struct lvts_thermal_controller {
enum lvts_sensor_enum ts[4]; /* sensor point 0 ~ 3 */
int ts_number;
int dominator_ts_idx; /* hw protection ref TS (index of the ts array) */
int tc_offset;
struct lvts_thermal_controller_speed tc_speed;
};
#endif
/*=============================================================
* Tsense Structure and Enum
*=============================================================
*/
#if !defined(CFG_THERM_NO_AUXADC)
/* private thermal sensor enum */
enum tsmcu_sensor_enum {
L_TS_MCU0 = 0,
L_TS_MCU1,
L_TS_MCU2,
/* There is no TSMCU3 in MT6785 compared with MT6779 */
L_TS_MCU4,
L_TS_MCU5,
L_TS_MCU6,
L_TS_MCU7,
L_TS_MCU8,
L_TS_MCU9,
L_TS_ABB,
L_TS_MCU_NUM
};
enum thermal_controller_name {
THERMAL_CONTROLLER0 = 0, /* TEMPMONCTL0 */
THERMAL_CONTROLLER1, /* TEMPMONCTL0_1 */
THERMAL_CONTROLLER2, /* TEMPMONCTL0_2 */
THERMAL_CONTROLLER_NUM
};
#endif
struct thermal_controller_speed {
unsigned int period_unit;
unsigned int filter_interval_delay;
unsigned int sensor_interval_delay;
unsigned int ahb_polling_interval;
};
#if CFG_THERM_LVTS
struct thermal_controller {
enum lvts_sensor_enum ts[4]; /* Sensor point 0 ~ 3 */
int ts_number;
int dominator_ts_idx; //hw protection ref TS (index of the ts array)
int tc_offset;
struct thermal_controller_speed tc_speed;
};
#else
struct thermal_controller {
enum tsmcu_sensor_enum ts[4]; /* Sensor point 0 ~ 3 */
int ts_number;
int dominator_ts_idx; //hw protection ref TS (index of the ts array)
int tc_offset;
struct thermal_controller_speed tc_speed;
};
#endif
/*=============================================================
* Shared variables
*=============================================================
*/
#ifdef CONFIG_OF
extern u32 thermal_irq_number;
extern u32 thermal_mcu_irq_number;
extern void __iomem *thermal_base;
extern void __iomem *auxadc_ts_base;
extern void __iomem *infracfg_ao_base;
extern void __iomem *th_apmixed_base;
extern void __iomem *INFRACFG_AO_base;
extern int thermal_phy_base;
extern int auxadc_ts_phy_base;
extern int apmixed_phy_base;
extern int pericfg_phy_base;
#endif
#if PRECISE_HYBRID_POWER_BUDGET
/* tscpu_prev_cpu_temp: previous CPUSYS temperature
* tscpu_curr_cpu_temp: current CPUSYS temperature
* tscpu_prev_gpu_temp: previous GPUSYS temperature
* tscpu_curr_gpu_temp: current GPUSYS temperature
*/
extern int tscpu_curr_cpu_temp;
extern int tscpu_curr_gpu_temp;
#endif
/*
* In src/mtk_tc.c
*/
extern int temp_eUART;
extern int temp_dUART;
extern int tscpu_sspm_thermal_throttle;
extern int tscpu_debug_log;
extern const struct of_device_id mt_thermal_of_match[2];
#if !defined(CFG_THERM_NO_AUXADC)
extern struct thermal_controller tscpu_g_tc[THERMAL_CONTROLLER_NUM];
#endif
extern int tscpu_polling_trip_temp1;
extern int tscpu_polling_trip_temp2;
extern int tscpu_polling_factor1;
extern int tscpu_polling_factor2;
extern int lvts_hw_protect_enabled;
#if !defined(CFG_THERM_NO_AUXADC)
/*
* temperature array to store both tsmcu and lvts (if exist) and export them
*/
extern int tscpu_ts_temp[TS_ENUM_MAX];
extern int tscpu_ts_temp_r[TS_ENUM_MAX]; /* raw data */
/*
* temperature array to store temp of tsmcu sensor
*/
extern int tscpu_ts_mcu_temp[L_TS_MCU_NUM];
extern int tscpu_ts_mcu_temp_r[L_TS_MCU_NUM]; /* raw data */
#endif
#if CFG_THERM_LVTS
/*
* temperature array to store temp of lvts sensor
*/
extern int tscpu_ts_lvts_temp[L_TS_LVTS_NUM];
extern int tscpu_ts_lvts_temp_r[L_TS_LVTS_NUM]; /* raw data */
#endif
#if CONFIG_LVTS_ERROR_AEE_WARNING
extern int tscpu_ts_mcu_temp_v[L_TS_MCU_NUM];
extern int tscpu_ts_lvts_temp_v[L_TS_LVTS_NUM];
#if DUMP_VCORE_VOLTAGE
extern struct regulator *vcore_reg_id;
#endif
#endif
#if LVTS_VALID_DATA_TIME_PROFILING
extern unsigned long long int SODI3_count, noValid_count;
/* If isTempValid is 0, it means no valid temperature data
* between two SODI3 entry points.
*/
extern int isTempValid;
extern long long int start_timestamp;
/* count if start_timestamp is bigger than end_timestamp */
extern int diff_error_count;
#endif
/*
* support LVTS
*/
#if CFG_THERM_LVTS
extern int lvts_rawdata_debug_log;
extern int lvts_debug_log;
extern struct lvts_thermal_controller
lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM];
#endif
#if MTKTSCPU_FAST_POLLING
/* Combined fast_polling_trip_temp and fast_polling_factor,
* it means polling_delay will be 1/5 of original interval
* after mtktscpu reports > 65C w/o exit point
*/
extern int fast_polling_trip_temp;
extern int fast_polling_trip_temp_high;
extern int fast_polling_factor;
extern int tscpu_cur_fp_factor;
extern int tscpu_next_fp_factor;
#endif
/*In common/thermal_zones/mtk_ts_cpu.c*/
extern long long int thermal_get_current_time_us(void);
extern void tscpu_workqueue_cancel_timer(void);
extern void tscpu_workqueue_start_timer(void);
extern void __iomem *therm_clk_infracfg_ao_base;
extern int Num_of_GPU_OPP;
extern int gpu_max_opp;
extern struct mt_gpufreq_power_table_info *mtk_gpu_power;
extern int tscpu_read_curr_temp;
#if MTKTSCPU_FAST_POLLING
extern int tscpu_cur_fp_factor;
#endif
#if !defined(CONFIG_MTK_CLKMGR)
extern struct clk *therm_main; /* main clock for Thermal*/
#endif
#if CPT_ADAPTIVE_AP_COOLER
extern int tscpu_g_curr_temp;
extern int tscpu_g_prev_temp;
#if (THERMAL_HEADROOM == 1) || (CONTINUOUS_TM == 1)
extern int bts_cur_temp; /* in mtk_ts_bts.c */
#endif
#endif
extern char *adaptive_cooler_name;
/* common/coolers/mtk_cooler_atm.c */
extern unsigned int adaptive_cpu_power_limit;
extern unsigned int adaptive_gpu_power_limit;
extern int TARGET_TJS[MAX_CPT_ADAPTIVE_COOLERS];
#ifdef FAST_RESPONSE_ATM
extern void atm_cancel_hrtimer(void);
extern void atm_restart_hrtimer(void);
#endif
/* common/coolers/mtk_cooler_dtm.c */
extern unsigned int static_cpu_power_limit;
extern unsigned int static_gpu_power_limit;
extern int tscpu_cpu_dmips[CPU_COOLER_NUM];
/*=============================================================
* Shared functions
*=============================================================
*/
/*In mtk_tc_wrapper.c */
extern int tscpu_get_curr_max_ts_temp(void);
extern int tscpu_max_temperature(void);
extern int tscpu_get_curr_temp(void);
extern int combine_lvts_tsmcu_temp(void);
extern int tscpu_read_temperature_info(struct seq_file *m, void *v);
extern int get_io_reg_base(void);
/*In common/thermal_zones/mtk_ts_cpu.c*/
extern void thermal_init_interrupt_for_UART(int temp_e, int temp_d);
extern void tscpu_update_tempinfo(void);
#if THERMAL_GPIO_OUT_TOGGLE
void tscpu_set_GPIO_toggle_for_monitor(void);
#endif
extern void tscpu_update_tempinfo(void);
#if !defined(CFG_THERM_NO_AUXADC)
/*In src/mtk_tc.c*/
extern void tscpu_config_all_tc_hw_protect(int temperature, int temperature2);
extern void tscpu_reset_thermal(void);
extern void tscpu_thermal_initial_all_tc(void);
extern void tscpu_thermal_read_tc_temp(
int tc_num, enum tsmcu_sensor_enum type, int order);
extern void tscpu_thermal_cal_prepare(void);
extern void tscpu_thermal_cal_prepare_2(unsigned int ret);
extern int tscpu_dump_cali_info(struct seq_file *m, void *v);
extern int tscpu_thermal_fast_init(int tc_num);
extern void thermal_get_AHB_clk_info(void);
extern void print_risky_temps(char *prefix, int offset, int printLevel);
extern void thermal_pause_all_periodoc_temp_sensing(void);
extern void thermal_release_all_periodoc_temp_sensing(void);
extern void thermal_disable_all_periodoc_temp_sensing(void);
extern void read_all_tc_tsmcu_temperature(void);
extern irqreturn_t tscpu_thermal_all_tc_interrupt_handler(
int irq, void *dev_id);
#endif
extern int (*max_temperature_in_bank[THERMAL_BANK_NUM])(void);
extern int tscpu_thermal_clock_on(void);
extern int tscpu_thermal_clock_off(void);
extern void lvts_tscpu_reset_thermal(void);
/*
* Support LVTS
*/
#if CFG_THERM_LVTS
extern int lvts_get_io_reg_base(void);
extern int lvts_max_temperature(void);
extern void lvts_config_all_tc_hw_protect(int temperature, int temperature2);
extern void lvts_thermal_read_tc_temp(
int tc_num, enum lvts_sensor_enum type, int order);
extern void lvts_read_all_tc_temperature(void);
extern void lvts_reset_and_initial(int tc_num);
extern int (*lvts_max_temperature_in_bank[THERMAL_BANK_NUM])(void);
extern void lvts_thermal_lvts_device_init(void);
extern void lvts_read_temperature(void);
//extern void lvts_read_temperature(int temp0, int temp1);
#if DUMP_LVTS_REGISTER_FOR_ZERO_RAW_ISSUE
extern void clear_lvts_register_value_array(void);
extern void dump_lvts_error_info(void);
#endif
extern void lvts_thermal_cal_prepare(void);
extern void lvts_device_identification(void);
extern void lvts_reset_device_and_stop_clk(void);
extern void lvts_read_device_id_rev(void);
extern void lvts_Device_Enable_Init_all_Devices(void);
extern void lvts_device_read_count_RC_N(void);
#if defined(CFG_THERM_USE_BOOTUP_COUNT_RC)
extern void lvts_device_read_count_RC_N_resume(void);
#endif
extern void lvts_device_enable_auto_rck(void);
extern void lvts_efuse_setting(void);
extern void lvts_tscpu_thermal_initial_all_tc(void);
extern void lvts_pause_all_sensing_points(void);
extern void lvts_release_all_sensing_points(void);
extern void lvts_disable_all_sensing_points(void);
extern void lvts_enable_all_sensing_points(void);
extern void read_all_tc_lvts_temperature(void);
extern void lvts_wait_for_all_sensing_point_idle(void);
extern irqreturn_t lvts_tscpu_thermal_all_tc_interrupt_handler(
int irq, void *dev_id);
extern int lvts_tscpu_dump_cali_info(struct seq_file *m, void *v);
extern void lvts_sodi3_release_thermal_controller(void);
#ifdef CONFIG_LVTS_DYNAMIC_ENABLE_REBOOT
extern void lvts_enable_all_hw_protect(void);
extern void lvts_disable_all_hw_protect(void);
#endif
#endif
/*
* In drivers/misc/mediatek/gpu/hal/mtk_gpu_utility.c
* It's not our api, ask them to provide header file
*/
extern bool mtk_get_gpu_loading(unsigned int *pLoading);
/*
* In drivers/misc/mediatek/auxadc/mt_auxadc.c
* It's not our api, ask them to provide header file
*/
extern int IMM_IsAdcInitReady(void);
#if CONFIG_LVTS_ERROR_AEE_WARNING
extern void dump_efuse_data(void);
extern int check_lvts_mcu_efuse(void);
extern int check_auxadc_mcu_efuse(void);
#if DUMP_LVTS_REGISTER
extern void read_controller_reg_before_active(void);
extern void read_controller_reg_when_error(void);
extern void read_device_reg_before_active(void);
extern void read_device_reg_when_error(void);
extern void clear_lvts_register_value_array(void);
extern void dump_lvts_register_value(void);
#endif
#endif
#if LVTS_VALID_DATA_TIME_PROFILING
extern void lvts_dump_time_profiling_result(struct seq_file *m);
#endif
#if CFG_THERMAL_KERNEL_IGNORE_HOT_SENSOR
extern int tscpu_check_cpu_segment(void);
#endif
/*=============================================================
*LOG
*=============================================================
*/
#define TSCPU_LOG_TAG "[Thermal/TZ/CPU]"
#define tscpu_dprintk(fmt, args...) \
do { \
if (tscpu_debug_log == 1) { \
pr_notice(TSCPU_LOG_TAG fmt, ##args); \
} \
} while (0)
#define tscpu_printk(fmt, args...) pr_notice(TSCPU_LOG_TAG fmt, ##args)
#define tscpu_warn(fmt, args...) pr_notice(TSCPU_LOG_TAG fmt, ##args)
/*
* Support LVTS
*/
#if CFG_THERM_LVTS
#define LVTS_LOG_TAG "[Thermal/TZ/LVTS]"
#define LVTS_LOG_REG_TAG "[Thermal/TZ/LVTSREG]"
#define lvts_reg_print(fmt, args...) pr_notice(LVTS_LOG_REG_TAG fmt, ##args)
#define lvts_printk(fmt, args...) pr_notice(LVTS_LOG_TAG fmt, ##args)
#define lvts_warn(fmt, args...) pr_notice(LVTS_LOG_TAG fmt, ##args)
#if 0
#define lvts_dbg_printk(fmt, args...) pr_notice(LVTS_LOG_TAG fmt, ##args)
#else
#define lvts_dbg_printk(fmt, args...) \
do { \
if (lvts_debug_log == 1) { \
pr_notice(LVTS_LOG_TAG fmt, ##args); \
} \
} while (0)
#endif
#endif
/*=============================================================
* Register macro for internal use
*=============================================================
*/
#if 1
#define THERM_CTRL_BASE_2 thermal_base
#define AUXADC_BASE_2 auxadc_ts_base
#define INFRACFG_AO_BASE_2 infracfg_ao_base
#define APMIXED_BASE_2 th_apmixed_base
#else
#include <mach/mt_reg_base.h>
#define AUXADC_BASE_2 AUXADC_BASE
#define THERM_CTRL_BASE_2 THERM_CTRL_BASE
#define PERICFG_BASE_2 PERICFG_BASE
#define APMIXED_BASE_2 APMIXED_BASE
#endif
/*******************************************************************************
* AUXADC Register Definition
*****************************************************************************
*/
#define AUXADC_CON0_V (AUXADC_BASE_2 + 0x000)
#define AUXADC_CON1_V (AUXADC_BASE_2 + 0x004)
#define AUXADC_CON1_SET_V (AUXADC_BASE_2 + 0x008)
#define AUXADC_CON1_CLR_V (AUXADC_BASE_2 + 0x00C)
#define AUXADC_CON2_V (AUXADC_BASE_2 + 0x010)
/*#define AUXADC_CON3_V (AUXADC_BASE_2 + 0x014)*/
#define AUXADC_DAT0_V (AUXADC_BASE_2 + 0x014)
#define AUXADC_DAT1_V (AUXADC_BASE_2 + 0x018)
#define AUXADC_DAT2_V (AUXADC_BASE_2 + 0x01C)
#define AUXADC_DAT3_V (AUXADC_BASE_2 + 0x020)
#define AUXADC_DAT4_V (AUXADC_BASE_2 + 0x024)
#define AUXADC_DAT5_V (AUXADC_BASE_2 + 0x028)
#define AUXADC_DAT6_V (AUXADC_BASE_2 + 0x02C)
#define AUXADC_DAT7_V (AUXADC_BASE_2 + 0x030)
#define AUXADC_DAT8_V (AUXADC_BASE_2 + 0x034)
#define AUXADC_DAT9_V (AUXADC_BASE_2 + 0x038)
#define AUXADC_DAT10_V (AUXADC_BASE_2 + 0x03C)
#define AUXADC_DAT11_V (AUXADC_BASE_2 + 0x040)
#define AUXADC_MISC_V (AUXADC_BASE_2 + 0x094)
#define AUXADC_CON0_P (auxadc_ts_phy_base + 0x000)
#define AUXADC_CON1_P (auxadc_ts_phy_base + 0x004)
#define AUXADC_CON1_SET_P (auxadc_ts_phy_base + 0x008)
#define AUXADC_CON1_CLR_P (auxadc_ts_phy_base + 0x00C)
#define AUXADC_CON2_P (auxadc_ts_phy_base + 0x010)
/*#define AUXADC_CON3_P (auxadc_ts_phy_base + 0x014)*/
#define AUXADC_DAT0_P (auxadc_ts_phy_base + 0x014)
#define AUXADC_DAT1_P (auxadc_ts_phy_base + 0x018)
#define AUXADC_DAT2_P (auxadc_ts_phy_base + 0x01C)
#define AUXADC_DAT3_P (auxadc_ts_phy_base + 0x020)
#define AUXADC_DAT4_P (auxadc_ts_phy_base + 0x024)
#define AUXADC_DAT5_P (auxadc_ts_phy_base + 0x028)
#define AUXADC_DAT6_P (auxadc_ts_phy_base + 0x02C)
#define AUXADC_DAT7_P (auxadc_ts_phy_base + 0x030)
#define AUXADC_DAT8_P (auxadc_ts_phy_base + 0x034)
#define AUXADC_DAT9_P (auxadc_ts_phy_base + 0x038)
#define AUXADC_DAT10_P (auxadc_ts_phy_base + 0x03C)
#define AUXADC_DAT11_P (auxadc_ts_phy_base + 0x040)
#define AUXADC_MISC_P (auxadc_ts_phy_base + 0x094)
/*******************************************************************************
* Peripheral Configuration Register Definition
*****************************************************************************
*/
/*APB Module infracfg_ao*/
#define INFRA_GLOBALCON_RST_0_SET (INFRACFG_AO_BASE_2 + 0x120)
#define INFRA_GLOBALCON_RST_0_CLR (INFRACFG_AO_BASE_2 + 0x124)
#define INFRA_GLOBALCON_RST_0_STA (INFRACFG_AO_BASE_2 + 0x128)
#define INFRA_GLOBALCON_RST_4_SET (INFRACFG_AO_BASE_2 + 0x730)
#define INFRA_GLOBALCON_RST_4_CLR (INFRACFG_AO_BASE_2 + 0x734)
/*******************************************************************************
* APMixedSys Configuration Register Definition
*****************************************************************************
*/
/* TODO: check base addr. */
#define TS_CON0_TM (APMIXED_BASE_2 + 0x600) /*yes 0x10212000*/
#define TS_CON1_TM (APMIXED_BASE_2 + 0x604)
#define TS_CON0_P (apmixed_phy_base + 0x600)
#define TS_CON1_P (apmixed_phy_base + 0x604)
/*******************************************************************************
* Thermal Controller Register Mask Definition
*****************************************************************************
*/
#define THERMAL_COLD_INTERRUPT_0 0x00000001
#define THERMAL_HOT_INTERRUPT_0 0x00000002
#define THERMAL_LOW_OFFSET_INTERRUPT_0 0x00000004
#define THERMAL_HIGH_OFFSET_INTERRUPT_0 0x00000008
#define THERMAL_HOT2NORMAL_INTERRUPT_0 0x00000010
#define THERMAL_COLD_INTERRUPT_1 0x00000020
#define THERMAL_HOT_INTERRUPT_1 0x00000040
#define THERMAL_LOW_OFFSET_INTERRUPT_1 0x00000080
#define THERMAL_HIGH_OFFSET_INTERRUPT_1 0x00000100
#define THERMAL_HOT2NORMAL_INTERRUPT_1 0x00000200
#define THERMAL_COLD_INTERRUPT_2 0x00000400
#define THERMAL_HOT_INTERRUPT_2 0x00000800
#define THERMAL_LOW_OFFSET_INTERRUPT_2 0x00001000
#define THERMAL_HIGH_OFFSET_INTERRUPT_2 0x00002000
#define THERMAL_HOT2NORMAL_INTERRUPT_2 0x00004000
#define THERMAL_AHB_TIMEOUT_INTERRUPT 0x00008000
#define THERMAL_DEVICE_TIMEOUT_INTERRUPT 0x00008000
#define THERMAL_IMMEDIATE_INTERRUPT_0 0x00010000
#define THERMAL_IMMEDIATE_INTERRUPT_1 0x00020000
#define THERMAL_IMMEDIATE_INTERRUPT_2 0x00040000
#define THERMAL_FILTER_INTERRUPT_0 0x00080000
#define THERMAL_FILTER_INTERRUPT_1 0x00100000
#define THERMAL_FILTER_INTERRUPT_2 0x00200000
#define THERMAL_COLD_INTERRUPT_3 0x00400000
#define THERMAL_HOT_INTERRUPT_3 0x00800000
#define THERMAL_LOW_OFFSET_INTERRUPT_3 0x01000000
#define THERMAL_HIGH_OFFSET_INTERRUPT_3 0x02000000
#define THERMAL_HOT2NORMAL_INTERRUPT_3 0x04000000
#define THERMAL_IMMEDIATE_INTERRUPT_3 0x08000000
#define THERMAL_FILTER_INTERRUPT_3 0x10000000
#define THERMAL_PROTECTION_STAGE_1 0x20000000
#define THERMAL_PROTECTION_STAGE_2 0x40000000
#define THERMAL_PROTECTION_STAGE_3 0x80000000
#endif /* __TSCPU_SETTINGS_H__ */

151
drivers/misc/mediatek/thermal/mt6873/inc/tscpu_tsense_config.h
View File

@@ -1,151 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TSCPU_TSENSE_SETTINGS_H__
#define __TSCPU_TSENSE_SETTINGS_H__
/*=============================================================
* Chip related
*=============================================================
*/
/* chip dependent */
/* TODO: change to new reg addr. */
#define ADDRESS_INDEX_0 101 /* 184 */
#define ADDRESS_INDEX_1 100 /* 180 */
#define ADDRESS_INDEX_2 102 /* 188 */
#define ADDRESS_INDEX_3 111 /* 1AC */
#define ADDRESS_INDEX_4 112 /* 1B0 */
/* TSCON1 bit table */
#define TSCON0_bit_6_7_00 0x00 /* TSCON0[7:6]=2'b00*/
#define TSCON0_bit_6_7_01 0x40 /* TSCON0[7:6]=2'b01*/
#define TSCON0_bit_6_7_10 0x80 /* TSCON0[7:6]=2'b10*/
#define TSCON0_bit_6_7_11 0xc0 /* TSCON0[7:6]=2'b11*/
#define TSCON0_bit_6_7_MASK 0xc0
#define TSCON1_bit_4_5_00 0x00 /* TSCON1[5:4]=2'b00*/
#define TSCON1_bit_4_5_01 0x10 /* TSCON1[5:4]=2'b01*/
#define TSCON1_bit_4_5_10 0x20 /* TSCON1[5:4]=2'b10*/
#define TSCON1_bit_4_5_11 0x30 /* TSCON1[5:4]=2'b11*/
#define TSCON1_bit_4_5_MASK 0x30
#define TSCON1_bit_0_2_000 0x00 /*TSCON1[2:0]=3'b000*/
#define TSCON1_bit_0_2_001 0x01 /*TSCON1[2:0]=3'b001*/
#define TSCON1_bit_0_2_010 0x02 /*TSCON1[2:0]=3'b010*/
#define TSCON1_bit_0_2_011 0x03 /*TSCON1[2:0]=3'b011*/
#define TSCON1_bit_0_2_100 0x04 /*TSCON1[2:0]=3'b100*/
#define TSCON1_bit_0_2_101 0x05 /*TSCON1[2:0]=3'b101*/
#define TSCON1_bit_0_2_110 0x06 /*TSCON1[2:0]=3'b110*/
#define TSCON1_bit_0_2_111 0x07 /*TSCON1[2:0]=3'b111*/
#define TSCON1_bit_0_2_MASK 0x07
#define TSCON1_bit_0_3_0000 0x00 /*TSCON1[3:0]=4'b0000*/
#define TSCON1_bit_0_3_0001 0x01 /*TSCON1[3:0]=4'b0001*/
#define TSCON1_bit_0_3_0010 0x02 /*TSCON1[3:0]=4'b0010*/
#define TSCON1_bit_0_3_0011 0x03 /*TSCON1[3:0]=4'b0011*/
#define TSCON1_bit_0_3_0100 0x04 /*TSCON1[3:0]=4'b0100*/
#define TSCON1_bit_0_3_0101 0x05 /*TSCON1[3:0]=4'b0101*/
#define TSCON1_bit_0_3_0110 0x06 /*TSCON1[3:0]=4'b0110*/
#define TSCON1_bit_0_3_0111 0x07 /*TSCON1[3:0]=4'b0111*/
#define TSCON1_bit_0_3_1000 0x08 /*TSCON1[3:0]=4'b1000*/
#define TSCON1_bit_0_3_1001 0x09 /*TSCON1[3:0]=4'b1001*/
#define TSCON1_bit_0_3_1010 0x0A /*TSCON1[3:0]=4'b1010*/
#define TSCON1_bit_0_3_1011 0x0B /*TSCON1[3:0]=4'b1011*/
#define TSCON1_bit_0_3_1100 0x0C /*TSCON1[3:0]=4'b1100*/
#define TSCON1_bit_0_3_1101 0x0D /*TSCON1[3:0]=4'b1101*/
#define TSCON1_bit_0_3_1110 0x0E /*TSCON1[3:0]=4'b1110*/
#define TSCON1_bit_0_3_1111 0x0F /*TSCON1[3:0]=4'b1111*/
#define TSCON1_bit_0_3_MASK 0x0F
/* ADC value to mcu */
/*chip dependent*/
#define TEMPADC_MCU0 ((0x30&TSCON1_bit_4_5_00)|(0x0F&TSCON1_bit_0_3_0000))
#define TEMPADC_MCU1 ((0x30&TSCON1_bit_4_5_00)|(0x0F&TSCON1_bit_0_3_0001))
#define TEMPADC_MCU2 ((0x30&TSCON1_bit_4_5_00)|(0x0F&TSCON1_bit_0_3_0010))
#define TEMPADC_MCU4 ((0x30&TSCON1_bit_4_5_00)|(0x0F&TSCON1_bit_0_3_0100))
#define TEMPADC_MCU5 ((0x30&TSCON1_bit_4_5_00)|(0x0F&TSCON1_bit_0_3_0101))
#define TEMPADC_MCU6 ((0x30&TSCON1_bit_4_5_00)|(0x0F&TSCON1_bit_0_3_0110))
#define TEMPADC_MCU7 ((0x30&TSCON1_bit_4_5_00)|(0x0F&TSCON1_bit_0_3_0111))
#define TEMPADC_MCU8 ((0x30&TSCON1_bit_4_5_00)|(0x0F&TSCON1_bit_0_3_1000))
#define TEMPADC_MCU9 ((0x30&TSCON1_bit_4_5_00)|(0x0F&TSCON1_bit_0_3_1001))
#define TEMPADC_ABB ((0x30&TSCON1_bit_4_5_01)|(0x0F&TSCON1_bit_0_3_0000))
/*******************************************************************************
* Thermal Controller Register Definition
*****************************************************************************
*/
#define TEMPMONCTL0 (THERM_CTRL_BASE_2 + 0x800)
#define TEMPMONCTL1 (THERM_CTRL_BASE_2 + 0x804)
#define TEMPMONCTL2 (THERM_CTRL_BASE_2 + 0x808)
#define TEMPMONINT (THERM_CTRL_BASE_2 + 0x80C)
#define TEMPMONINTSTS (THERM_CTRL_BASE_2 + 0x810)
#define TEMPMONIDET0 (THERM_CTRL_BASE_2 + 0x814)
#define TEMPMONIDET1 (THERM_CTRL_BASE_2 + 0x818)
#define TEMPMONIDET2 (THERM_CTRL_BASE_2 + 0x81C)
#define TEMPH2NTHRE (THERM_CTRL_BASE_2 + 0x824)
#define TEMPHTHRE (THERM_CTRL_BASE_2 + 0x828)
#define TEMPCTHRE (THERM_CTRL_BASE_2 + 0x82C)
#define TEMPOFFSETH (THERM_CTRL_BASE_2 + 0x830)
#define TEMPOFFSETL (THERM_CTRL_BASE_2 + 0x834)
#define TEMPMSRCTL0 (THERM_CTRL_BASE_2 + 0x838)
#define TEMPMSRCTL1 (THERM_CTRL_BASE_2 + 0x83C)
#define TEMPAHBPOLL (THERM_CTRL_BASE_2 + 0x840)
#define TEMPAHBTO (THERM_CTRL_BASE_2 + 0x844)
#define TEMPADCPNP0 (THERM_CTRL_BASE_2 + 0x848)
#define TEMPADCPNP1 (THERM_CTRL_BASE_2 + 0x84C)
#define TEMPADCPNP2 (THERM_CTRL_BASE_2 + 0x850)
#define TEMPADCMUX (THERM_CTRL_BASE_2 + 0x854)
#define TEMPADCEXT (THERM_CTRL_BASE_2 + 0x858)
#define TEMPADCEXT1 (THERM_CTRL_BASE_2 + 0x85C)
#define TEMPADCEN (THERM_CTRL_BASE_2 + 0x860)
#define TEMPPNPMUXADDR (THERM_CTRL_BASE_2 + 0x864)
#define TEMPADCMUXADDR (THERM_CTRL_BASE_2 + 0x868)
#define TEMPADCEXTADDR (THERM_CTRL_BASE_2 + 0x86C)
#define TEMPADCEXT1ADDR (THERM_CTRL_BASE_2 + 0x870)
#define TEMPADCENADDR (THERM_CTRL_BASE_2 + 0x874)
#define TEMPADCVALIDADDR (THERM_CTRL_BASE_2 + 0x878)
#define TEMPADCVOLTADDR (THERM_CTRL_BASE_2 + 0x87C)
#define TEMPRDCTRL (THERM_CTRL_BASE_2 + 0x880)
#define TEMPADCVALIDMASK (THERM_CTRL_BASE_2 + 0x884)
#define TEMPADCVOLTAGESHIFT (THERM_CTRL_BASE_2 + 0x888)
#define TEMPADCWRITECTRL (THERM_CTRL_BASE_2 + 0x88C)
#define TEMPMSR0 (THERM_CTRL_BASE_2 + 0x890)
#define TEMPMSR1 (THERM_CTRL_BASE_2 + 0x894)
#define TEMPMSR2 (THERM_CTRL_BASE_2 + 0x898)
#define TEMPADCHADDR (THERM_CTRL_BASE_2 + 0x89C)
#define TEMPIMMD0 (THERM_CTRL_BASE_2 + 0x8A0)
#define TEMPIMMD1 (THERM_CTRL_BASE_2 + 0x8A4)
#define TEMPIMMD2 (THERM_CTRL_BASE_2 + 0x8A8)
#define TEMPMONIDET3 (THERM_CTRL_BASE_2 + 0x8B0)
#define TEMPADCPNP3 (THERM_CTRL_BASE_2 + 0x8B4)
#define TEMPMSR3 (THERM_CTRL_BASE_2 + 0x8B8)
#define TEMPIMMD3 (THERM_CTRL_BASE_2 + 0x8BC)
#define TEMPPROTCTL (THERM_CTRL_BASE_2 + 0x8C0)
#define TEMPPROTTA (THERM_CTRL_BASE_2 + 0x8C4)
#define TEMPPROTTB (THERM_CTRL_BASE_2 + 0x8C8)
#define TEMPPROTTC (THERM_CTRL_BASE_2 + 0x8CC)
#define TEMPSPARE0 (THERM_CTRL_BASE_2 + 0x8F0)
#define TEMPSPARE1 (THERM_CTRL_BASE_2 + 0x8F4)
#define TEMPSPARE2 (THERM_CTRL_BASE_2 + 0x8F8)
#define TEMPSPARE3 (THERM_CTRL_BASE_2 + 0x8FC)
#define PTPCORESEL (THERM_CTRL_BASE_2 + 0xF00)
#define THERMINTST (THERM_CTRL_BASE_2 + 0xF04)
#define PTPODINTST (THERM_CTRL_BASE_2 + 0xF08)
#define THSTAGE0ST (THERM_CTRL_BASE_2 + 0xF0C)
#define THSTAGE1ST (THERM_CTRL_BASE_2 + 0xF10)
#define THSTAGE2ST (THERM_CTRL_BASE_2 + 0xF14)
#define THAHBST0 (THERM_CTRL_BASE_2 + 0xF18)
#define THAHBST1 (THERM_CTRL_BASE_2 + 0xF1C)
#define PTPSPARE0 (THERM_CTRL_BASE_2 + 0xF20)
#define PTPSPARE1 (THERM_CTRL_BASE_2 + 0xF24)
#define PTPSPARE2 (THERM_CTRL_BASE_2 + 0xF28)
#define PTPSPARE3 (THERM_CTRL_BASE_2 + 0xF2C)
#define THSLPEVEB (THERM_CTRL_BASE_2 + 0xF30)
#define PTPSPARE0_P (thermal_phy_base + 0xF20)
#define PTPSPARE1_P (thermal_phy_base + 0xF24)
#define PTPSPARE2_P (thermal_phy_base + 0xF28)
#define PTPSPARE3_P (thermal_phy_base + 0xF2C)
#endif /* __TSCPU_TSENSE_SETTINGS_H__ */

44
drivers/misc/mediatek/thermal/mt6873/inc/tzbatt_initcfg.h
View File

@@ -1,44 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TZBATT_INITCFG_H__
#define __TZBATT_INITCFG_H__
#define TZBATT_SET_INIT_CFG (1)
#define TZBATT_INITCFG_INTERVAL (1)
#define TZBATT_INITCFG_NUM_TRIPS (3)
#define TZBATT_INITCFG_TRIP_0_TEMP (49000)
#define TZBATT_INITCFG_TRIP_0_COOLER "mtk-cl-bcct02"
#define TZBATT_INITCFG_TRIP_1_TEMP (48000)
#define TZBATT_INITCFG_TRIP_1_COOLER "mtk-cl-bcct01"
#define TZBATT_INITCFG_TRIP_2_TEMP (46000)
#define TZBATT_INITCFG_TRIP_2_COOLER "mtk-cl-bcct00"
#define TZBATT_INITCFG_TRIP_3_TEMP (45000)
#define TZBATT_INITCFG_TRIP_3_COOLER ""
#define TZBATT_INITCFG_TRIP_4_TEMP (44000)
#define TZBATT_INITCFG_TRIP_4_COOLER ""
#define TZBATT_INITCFG_TRIP_5_TEMP (43000)
#define TZBATT_INITCFG_TRIP_5_COOLER ""
#define TZBATT_INITCFG_TRIP_6_TEMP (42000)
#define TZBATT_INITCFG_TRIP_6_COOLER ""
#define TZBATT_INITCFG_TRIP_7_TEMP (41000)
#define TZBATT_INITCFG_TRIP_7_COOLER ""
#define TZBATT_INITCFG_TRIP_8_TEMP (40000)
#define TZBATT_INITCFG_TRIP_8_COOLER ""
#define TZBATT_INITCFG_TRIP_9_TEMP (39000)
#define TZBATT_INITCFG_TRIP_9_COOLER ""
#endif /* __TZBATT_INITCFG_H__ */

47
drivers/misc/mediatek/thermal/mt6873/inc/tzcpu_initcfg.h
View File

@@ -1,47 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TZCPU_INITCFG_H__
#define __TZCPU_INITCFG_H__
#define TZCPU_SET_INIT_CFG (1)
#define TZCPU_INITCFG_INTERVAL (40)
#define TZCPU_INITCFG_NUM_TRIPS (4)
#define TZCPU_INITCFG_TRIP_0_TEMP (117000)
#define TZCPU_INITCFG_TRIP_0_COOLER "mtktscpu-sysrst"
#define TZCPU_INITCFG_TRIP_1_TEMP (95000)
#define TZCPU_INITCFG_TRIP_1_COOLER "cpu00"
#define TZCPU_INITCFG_TRIP_2_TEMP (85000)
#define TZCPU_INITCFG_TRIP_2_COOLER "cpu03"
#define TZCPU_INITCFG_TRIP_3_TEMP (65000)
#define TZCPU_INITCFG_TRIP_3_COOLER "cpu_adaptive_0"
#define TZCPU_INITCFG_TRIP_4_TEMP (63000)
#define TZCPU_INITCFG_TRIP_4_COOLER ""
#define TZCPU_INITCFG_TRIP_5_TEMP (60000)
#define TZCPU_INITCFG_TRIP_5_COOLER ""
#define TZCPU_INITCFG_TRIP_6_TEMP (55000)
#define TZCPU_INITCFG_TRIP_6_COOLER ""
#define TZCPU_INITCFG_TRIP_7_TEMP (50000)
#define TZCPU_INITCFG_TRIP_7_COOLER ""
#define TZCPU_INITCFG_TRIP_8_TEMP (45000)
#define TZCPU_INITCFG_TRIP_8_COOLER ""
#define TZCPU_INITCFG_TRIP_9_TEMP (40000)
#define TZCPU_INITCFG_TRIP_9_COOLER ""
#endif /* __TZCPU_INITCFG_H__ */

41
drivers/misc/mediatek/thermal/mt6873/src/Makefile
View File

@@ -1,41 +0,0 @@
#
# Copyright (C) 2018 MediaTek Inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
THERMAL_CHIP_DRIVER_DIR := $(srctree)/drivers/misc/mediatek/thermal/$(MTK_PLATFORM)
ccflags-y += -I$(THERMAL_CHIP_DRIVER_DIR)/inc
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/$(MTK_PLATFORM)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/gpu/hal/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/thermal/fakeHeader/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/mcupm/$(MTK_PLATFORM)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/include/mt-plat/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/include/spm/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/eem_v2/mt3967/inc/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/pmic/include/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/thermal/common/inc/
ccflags-y += -I$(srctree)/include/dt-bindings/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/base/power/include/gpufreq_v1/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/include/mt-plat/$(MTK_PLATFORM)/include/
ccflags-y += -I$(srctree)/drivers/gpu/mediatek/gpufreq/
ccflags-y += -I$(srctree)/drivers/gpu/mediatek/mt-plat/
obj-$(CONFIG_THERMAL) += mtk_lvts_tc.o
#obj-$(CONFIG_THERMAL) += mtk_tc.o
obj-$(CONFIG_THERMAL) += mtk_tc_wrapper.o
obj-$(CONFIG_THERMAL) += mtk_thermal_ipi.o
obj-$(CONFIG_THERMAL) += mtk_pmic_efuse.o
obj-$(CONFIG_THERMAL) += mtk_ts_6359vcore.o
obj-$(CONFIG_THERMAL) += mtk_ts_6359vproc.o
obj-$(CONFIG_THERMAL) += mtk_ts_6359vgpu.o
obj-$(CONFIG_THERMAL) += mtk_ts_6359tsx.o
obj-$(CONFIG_THERMAL) += mtk_ts_6359dcxo.o
#obj-$(CONFIG_THERMAL) += mtk_ti_6315.o

2082
drivers/misc/mediatek/thermal/mt6873/src/mtk_lvts_tc.c
View File

File diff suppressed because it is too large Load Diff

824
drivers/misc/mediatek/thermal/mt6873/src/mtk_pmic_efuse.c
View File

@@ -1,824 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include <mt-plat/upmu_common.h>
#include <mt-plat/mtk_auxadc_intf.h>
#include <mach/mtk_pmic.h>
#include <tspmic_settings.h>
#if defined(THERMAL_USE_IIO_CHANNEL)
#include <iio/mt635x-auxadc.h>
#include <linux/iio/consumer.h>
#endif
/*=============================================================
*Local variable definition
*=============================================================
*/
int mtktspmic_debug_log;
/* Cali */
static __s32 g_o_vts;
static __s32 g_o_vts_2;
static __s32 g_o_vts_3;
static __s32 g_o_vts_4;
static __s32 g_degc_cali;
static __s32 g_adc_cali_en;
static __s32 g_o_slope;
static __s32 g_o_slope_sign;
static __s32 g_id;
static __s32 g_slope1 = 1;
static __s32 g_slope2 = 1;
static __s32 g_intercept;
static __s32 g_tsbuck1_slope1 = 1;
static __s32 g_tsbuck1_slope2 = 1;
static __s32 g_tsbuck1_intercept;
static __s32 g_tsbuck2_slope1 = 1;
static __s32 g_tsbuck2_slope2 = 1;
static __s32 g_tsbuck2_intercept;
static __s32 g_tsbuck3_slope1 = 1;
static __s32 g_tsbuck3_slope2 = 1;
static __s32 g_tsbuck3_intercept;
static DEFINE_MUTEX(TSPMIC_lock);
static int pre_temp1 = 0, PMIC_counter;
static int pre_tsbuck1_temp1 = 0, tsbuck1_cnt;
static int pre_tsbuck2_temp1 = 0, tsbuck2_cnt;
static int pre_tsbuck3_temp1 = 0, tsbuck3_cnt;
static int pre_tstsx_temp1 = 0, tstsx_cnt;
static int pre_tsdcxo_temp1 = 0, tsdcxo_cnt;
#if defined(THERMAL_USE_IIO_CHANNEL)
struct iio_channel *chan_chip_temp;
struct iio_channel *chan_vcore_temp;
struct iio_channel *chan_vproc_temp;
struct iio_channel *chan_vgpu_temp;
struct iio_channel *chan_tsx_temp;
struct iio_channel *chan_dcxo_temp;
#endif
/*=============================================================*/
static __s32 pmic_raw_to_temp(__u32 ret)
{
__s32 t_current;
__s32 y_curr = ret;
t_current = g_intercept + ((g_slope1 * y_curr) / (g_slope2));
mtktspmic_dprintk("[%s] t_current=%d\n", __func__, t_current);
return t_current;
}
static __s32 tsbuck1_raw_to_temp(__u32 ret)
{
__s32 t_current;
__s32 y_curr = ret;
t_current = g_tsbuck1_intercept +
((g_tsbuck1_slope1 * y_curr) / (g_tsbuck1_slope2));
mtktspmic_dprintk("[%s] t_current=%d\n", __func__, t_current);
return t_current;
}
static __s32 tsbuck2_raw_to_temp(__u32 ret)
{
__s32 t_current;
__s32 y_curr = ret;
t_current = g_tsbuck2_intercept +
((g_tsbuck2_slope1 * y_curr) / (g_tsbuck2_slope2));
mtktspmic_dprintk("[%s] t_current=%d\n", __func__, t_current);
return t_current;
}
static __s32 tsbuck3_raw_to_temp(__u32 ret)
{
__s32 t_current;
__s32 y_curr = ret;
t_current = g_tsbuck3_intercept +
((g_tsbuck3_slope1 * y_curr) / (g_tsbuck3_slope2));
mtktspmic_dprintk("[%s] t_current=%d\n", __func__, t_current);
return t_current;
}
static void mtktspmic_read_efuse(void)
{
mtktspmic_info("[pmic_debug] start\n");
/* MT6359 */
g_o_vts = pmic_get_register_value(PMIC_AUXADC_EFUSE_O_VTS);
g_o_vts_2 = pmic_get_register_value(PMIC_AUXADC_EFUSE_O_VTS_2);
g_o_vts_3 = pmic_get_register_value(PMIC_AUXADC_EFUSE_O_VTS_3);
g_o_vts_4 = pmic_get_register_value(PMIC_AUXADC_EFUSE_O_VTS_4);
g_degc_cali = pmic_get_register_value(PMIC_AUXADC_EFUSE_DEGC_CALI);
g_adc_cali_en = pmic_get_register_value(PMIC_AUXADC_EFUSE_ADC_CALI_EN);
g_o_slope_sign =
pmic_get_register_value(PMIC_AUXADC_EFUSE_O_SLOPE_SIGN);
g_o_slope = pmic_get_register_value(PMIC_AUXADC_EFUSE_O_SLOPE);
g_id = pmic_get_register_value(PMIC_AUXADC_EFUSE_ID);
mtktspmic_info("[pmic_debug] 6359_efuse: g_o_vts = %d\n",
g_o_vts);
mtktspmic_info("[pmic_debug] 6359_efuse: g_o_vts_2 = %d\n",
g_o_vts_2);
mtktspmic_info("[pmic_debug] 6359_efuse: g_o_vts_3 = %d\n",
g_o_vts_3);
mtktspmic_info("[pmic_debug] 6359_efuse: g_o_vts_4 = %d\n",
g_o_vts_4);
mtktspmic_info("[pmic_debug] 6359_efuse: g_degc_cali = %d\n",
g_degc_cali);
mtktspmic_info("[pmic_debug] 6359_efuse: g_adc_cali_en = %d\n",
g_adc_cali_en);
mtktspmic_info("[pmic_debug] 6359_efuse: g_o_slope_sign = %d\n",
g_o_slope_sign);
mtktspmic_info("[pmic_debug] 6359_efuse: g_o_slope = %d\n",
g_o_slope);
mtktspmic_info("[pmic_debug] 6359_efuse: g_id = %d\n",
g_id);
mtktspmic_info("[pmic_debug] end\n");
}
void mtktspmic_cali_prepare(void)
{
mtktspmic_read_efuse();
if (g_id == 0)
g_o_slope = 0;
/* g_adc_cali_en=0;//FIX ME */
if (g_adc_cali_en == 0) { /* no calibration */
mtktspmic_info("[pmic_debug] It isn't calibration values\n");
g_o_vts = 1600;
g_o_vts_2 = 1600;
g_o_vts_3 = 1600;
g_o_vts_4 = 1600;
g_degc_cali = 50;
g_o_slope_sign = 0;
g_o_slope = 0;
}
if (g_degc_cali < 38 || g_degc_cali > 60)
g_degc_cali = 53;
mtktspmic_info("[pmic_debug] g_o_vts = 0x%x\n", g_o_vts);
mtktspmic_info("[pmic_debug] g_o_vts_2 = 0x%x\n", g_o_vts_2);
mtktspmic_info("[pmic_debug] g_o_vts_3 = 0x%x\n", g_o_vts_3);
mtktspmic_info("[pmic_debug] g_o_vts_4 = 0x%x\n", g_o_vts_4);
mtktspmic_info("[pmic_debug] g_degc_cali = 0x%x\n", g_degc_cali);
mtktspmic_info("[pmic_debug] g_adc_cali_en = 0x%x\n", g_adc_cali_en);
mtktspmic_info("[pmic_debug] g_o_slope = 0x%x\n", g_o_slope);
mtktspmic_info("[pmic_debug] g_o_slope_sign = 0x%x\n", g_o_slope_sign);
mtktspmic_info("[pmic_debug] g_id = 0x%x\n", g_id);
}
void mtktspmic_cali_prepare2(void)
{
__s32 vbe_t;
int factor;
factor = 1681;
g_slope1 = (100 * 1000 * 10); /* 1000 is for 0.001 degree */
if (g_o_slope_sign == 0)
g_slope2 = -(factor + g_o_slope);
else
g_slope2 = -(factor - g_o_slope);
vbe_t = (-1) * ((((g_o_vts) * 1800)) / 4096) * 1000;
if (g_o_slope_sign == 0)
g_intercept = (vbe_t * 1000) / (-(factor + g_o_slope * 10));
/*0.001 degree */
else
g_intercept = (vbe_t * 1000) / (-(factor - g_o_slope * 10));
/*0.001 degree */
g_intercept = g_intercept + (g_degc_cali * (1000 / 2));
/* 1000 is for 0.1 degree */
mtktspmic_info(
"[Thermal calibration] SLOPE1=%d SLOPE2=%d INTERCEPT=%d, Vbe = %d\n",
g_slope1, g_slope2, g_intercept, vbe_t);
factor = 1863;
g_tsbuck1_slope1 = (100 * 1000 * 10); /* 1000 is for 0.001 degree */
if (g_o_slope_sign == 0)
g_tsbuck1_slope2 = -(factor + g_o_slope);
else
g_tsbuck1_slope2 = -(factor - g_o_slope);
vbe_t = (-1) * ((((g_o_vts_2) * 1800)) / 4096) * 1000;
if (g_o_slope_sign == 0)
g_tsbuck1_intercept =
(vbe_t * 1000) / (-(factor + g_o_slope * 10));
/*0.001 degree */
else
g_tsbuck1_intercept =
(vbe_t * 1000) / (-(factor - g_o_slope * 10));
/*0.001 degree */
g_tsbuck1_intercept = g_tsbuck1_intercept + (g_degc_cali * (1000 / 2));
/* 1000 is for 0.1 degree */
mtktspmic_info(
"[Thermal calibration] SLOPE1=%d SLOPE2=%d INTERCEPT=%d, Vbe = %d\n",
g_tsbuck1_slope1, g_tsbuck1_slope2, g_tsbuck1_intercept, vbe_t);
factor = 1863;
g_tsbuck2_slope1 = (100 * 1000 * 10);
/* 1000 is for 0.001 degree */
if (g_o_slope_sign == 0)
g_tsbuck2_slope2 = -(factor + g_o_slope);
else
g_tsbuck2_slope2 = -(factor - g_o_slope);
vbe_t = (-1) * ((((g_o_vts_3) * 1800)) / 4096) * 1000;
if (g_o_slope_sign == 0)
g_tsbuck2_intercept =
(vbe_t * 1000) / (-(factor + g_o_slope * 10));
/*0.001 degree */
else
g_tsbuck2_intercept =
(vbe_t * 1000) / (-(factor - g_o_slope * 10));
/*0.001 degree */
g_tsbuck2_intercept = g_tsbuck2_intercept + (g_degc_cali * (1000 / 2));
/* 1000 is for 0.1 degree */
mtktspmic_info(
"[Thermal calibration] SLOPE1=%d SLOPE2=%d INTERCEPT=%d, Vbe = %d\n",
g_tsbuck2_slope1, g_tsbuck2_slope2, g_tsbuck2_intercept, vbe_t);
factor = 1863;
g_tsbuck3_slope1 = (100 * 1000 * 10);
/* 1000 is for 0.001 degree */
if (g_o_slope_sign == 0)
g_tsbuck3_slope2 = -(factor + g_o_slope);
else
g_tsbuck3_slope2 = -(factor - g_o_slope);
vbe_t = (-1) * ((((g_o_vts_4) * 1800)) / 4096) * 1000;
if (g_o_slope_sign == 0)
g_tsbuck3_intercept =
(vbe_t * 1000) / (-(factor + g_o_slope * 10));
/*0.001 degree */
else
g_tsbuck3_intercept =
(vbe_t * 1000) / (-(factor - g_o_slope * 10));
/*0.001 degree */
g_tsbuck3_intercept = g_tsbuck3_intercept + (g_degc_cali * (1000 / 2));
/* 1000 is for 0.1 degree */
mtktspmic_info(
"[Thermal calibration] SLOPE1=%d SLOPE2=%d INTERCEPT=%d, Vbe = %d\n",
g_tsbuck3_slope1, g_tsbuck3_slope2, g_tsbuck3_intercept, vbe_t);
}
#if defined(THERMAL_USE_IIO_CHANNEL)
void mtktspmic_get_from_dts(struct platform_device *pdev)
{
int ret;
chan_chip_temp = iio_channel_get(NULL, "AUXADC_CHIP_TEMP");
if (IS_ERR(chan_chip_temp)) {
ret = PTR_ERR(chan_chip_temp);
pr_notice("AUXADC_CHIP_TEMP get fail, ret=%d\n", ret);
}
chan_vcore_temp = iio_channel_get(NULL, "AUXADC_VCORE_TEMP");
if (IS_ERR(chan_vcore_temp)) {
ret = PTR_ERR(chan_vcore_temp);
pr_notice("AUXADC_VCORE_TEMP get fail, ret=%d\n", ret);
}
chan_vproc_temp = iio_channel_get(NULL, "AUXADC_VPROC_TEMP");
if (IS_ERR(chan_vproc_temp)) {
ret = PTR_ERR(chan_vproc_temp);
pr_notice("AUXADC_VPROC_TEMP get fail, ret=%d\n", ret);
}
chan_vgpu_temp = iio_channel_get(NULL, "AUXADC_VGPU_TEMP");
if (IS_ERR(chan_vgpu_temp)) {
ret = PTR_ERR(chan_vgpu_temp);
pr_notice("AUXADC_VGPU_TEMP get fail, ret=%d\n", ret);
}
chan_tsx_temp = iio_channel_get(NULL, "AUXADC_TSX_TEMP");
if (IS_ERR(chan_tsx_temp)) {
ret = PTR_ERR(chan_tsx_temp);
pr_notice("AUXADC_TSX_TEMP get fail, ret=%d\n", ret);
}
chan_dcxo_temp = iio_channel_get(NULL, "AUXADC_DCXO_TEMP");
if (IS_ERR(chan_dcxo_temp)) {
ret = PTR_ERR(chan_dcxo_temp);
pr_notice("AUXADC_DCXO_TEMP get fail, ret=%d\n", ret);
}
}
#endif
int mtktspmic_get_hw_temp(void)
{
int temp = 0, temp1 = 0;
#if defined(THERMAL_USE_IIO_CHANNEL)
int ret;
#endif
mutex_lock(&TSPMIC_lock);
#if defined(THERMAL_USE_IIO_CHANNEL)
if (!IS_ERR(chan_chip_temp)) {
ret = iio_read_channel_processed(chan_chip_temp, &temp);
if (ret < 0)
pr_notice("pmic_chip_temp read fail, ret=%d\n", ret);
}
#else
temp = pmic_get_auxadc_value(AUXADC_LIST_CHIP_TEMP);
#endif
temp1 = pmic_raw_to_temp(temp);
mutex_unlock(&TSPMIC_lock);
mtktspmic_dprintk("[pmic_debug] Raw=%d, T=%d\n", temp, temp1);
if ((temp1 > 100000) || (temp1 < -30000))
mtktspmic_info("[%s] raw=%d, PMIC T=%d", __func__, temp, temp1);
if ((temp1 > 150000) || (temp1 < -50000)) {
mtktspmic_info("[%s] temp(%d) too high, drop this data!\n",
__func__, temp1);
temp1 = pre_temp1;
} else if ((PMIC_counter != 0)
&& (((pre_temp1 - temp1) > 30000)
|| ((temp1 - pre_temp1) > 30000))) {
mtktspmic_info("[%s] temp diff too large, drop this data\n",
__func__);
temp1 = pre_temp1;
} else {
/* update previous temp */
pre_temp1 = temp1;
mtktspmic_dprintk("[%s] pre_temp1=%d\n", __func__, pre_temp1);
if (PMIC_counter == 0)
PMIC_counter++;
}
return temp1;
}
int mt6359vcore_get_hw_temp(void)
{
int temp = 0, temp1 = 0;
#if defined(THERMAL_USE_IIO_CHANNEL)
int ret;
#endif
mutex_lock(&TSPMIC_lock);
#if defined(THERMAL_USE_IIO_CHANNEL)
if (!IS_ERR(chan_vcore_temp)) {
ret = iio_read_channel_processed(chan_vcore_temp, &temp);
if (ret < 0)
pr_notice("pmic_vcore_temp read fail, ret=%d\n", ret);
}
#else
temp = pmic_get_auxadc_value(AUXADC_LIST_VCORE_TEMP);
#endif
temp1 = tsbuck1_raw_to_temp(temp);
mutex_unlock(&TSPMIC_lock);
mtktspmic_dprintk("%s raw=%d T=%d\n", __func__, temp, temp1);
if ((temp1 > 100000) || (temp1 < -30000))
mtktspmic_info("%s raw=%d T=%d\n", __func__, temp, temp1);
if ((temp1 > 150000) || (temp1 < -50000)) {
mtktspmic_info("%s T=%d too high, drop it!\n", __func__,
temp1);
temp1 = pre_tsbuck1_temp1;
} else if ((tsbuck1_cnt != 0)
&& (((pre_tsbuck1_temp1 - temp1) > 30000)
|| ((temp1 - pre_tsbuck1_temp1) > 30000))) {
mtktspmic_info("%s delta temp too large, drop it!\n", __func__);
temp1 = pre_tsbuck1_temp1;
} else {
/* update previous temp */
pre_tsbuck1_temp1 = temp1;
mtktspmic_dprintk(
"%s pre_tsbuck1_temp1=%d\n", __func__,
pre_tsbuck1_temp1);
if (tsbuck1_cnt == 0)
tsbuck1_cnt++;
}
return temp1;
}
int mt6359vproc_get_hw_temp(void)
{
int temp = 0, temp1 = 0;
#if defined(THERMAL_USE_IIO_CHANNEL)
int ret;
#endif
mutex_lock(&TSPMIC_lock);
#if defined(THERMAL_USE_IIO_CHANNEL)
if (!IS_ERR(chan_vproc_temp)) {
ret = iio_read_channel_processed(chan_vproc_temp, &temp);
if (ret < 0)
pr_notice("pmic_vproc_temp read fail, ret=%d\n", ret);
}
#else
temp = pmic_get_auxadc_value(AUXADC_LIST_VPROC_TEMP);
#endif
temp1 = tsbuck2_raw_to_temp(temp);
mutex_unlock(&TSPMIC_lock);
mtktspmic_dprintk("%s raw=%d T=%d\n", __func__, temp, temp1);
if ((temp1 > 100000) || (temp1 < -30000))
mtktspmic_info("%s raw=%d T=%d\n", __func__, temp, temp1);
if ((temp1 > 150000) || (temp1 < -50000)) {
mtktspmic_info("%s T=%d too high, drop it!\n", __func__,
temp1);
temp1 = pre_tsbuck2_temp1;
} else if ((tsbuck2_cnt != 0)
&& (((pre_tsbuck2_temp1 - temp1) > 30000)
|| ((temp1 - pre_tsbuck2_temp1) > 30000))) {
mtktspmic_info("%s delta temp too large, drop it!\n", __func__);
temp1 = pre_tsbuck2_temp1;
} else {
/* update previous temp */
pre_tsbuck2_temp1 = temp1;
mtktspmic_dprintk("%s pre_tsbuck2_temp1=%d\n", __func__,
pre_tsbuck2_temp1);
if (tsbuck2_cnt == 0)
tsbuck2_cnt++;
}
return temp1;
}
int mt6359vgpu_get_hw_temp(void)
{
int temp = 0, temp1 = 0;
#if defined(THERMAL_USE_IIO_CHANNEL)
int ret;
#endif
mutex_lock(&TSPMIC_lock);
#if defined(THERMAL_USE_IIO_CHANNEL)
if (!IS_ERR(chan_vgpu_temp)) {
ret = iio_read_channel_processed(chan_vgpu_temp, &temp);
if (ret < 0)
pr_notice("pmic_vgpu_temp read fail, ret=%d\n", ret);
}
#else
temp = pmic_get_auxadc_value(AUXADC_LIST_VGPU_TEMP);
#endif
temp1 = tsbuck3_raw_to_temp(temp);
mutex_unlock(&TSPMIC_lock);
mtktspmic_dprintk("%s raw=%d T=%d\n", __func__, temp, temp1);
if ((temp1 > 100000) || (temp1 < -30000))
mtktspmic_info("%s raw=%d T=%d\n", __func__, temp, temp1);
if ((temp1 > 150000) || (temp1 < -50000)) {
mtktspmic_info("%s T=%d too high, drop it!\n", __func__,
temp1);
temp1 = pre_tsbuck3_temp1;
} else if ((tsbuck3_cnt != 0)
&& (((pre_tsbuck3_temp1 - temp1) > 30000)
|| ((temp1 - pre_tsbuck3_temp1) > 30000))) {
mtktspmic_info("%s delta temp too large, drop it!\n", __func__);
temp1 = pre_tsbuck3_temp1;
} else {
/* update previous temp */
pre_tsbuck3_temp1 = temp1;
mtktspmic_dprintk(
"%s pre_tsbuck2_temp1=%d\n", __func__,
pre_tsbuck3_temp1);
if (tsbuck3_cnt == 0)
tsbuck3_cnt++;
}
return temp1;
}
static int u_table[126] = {
64078,
63972,
63860,
63741,
63614,
63480,
63338,
63188,
63029,
62860,
62683,
62495,
62297,
62089,
61870,
61639,
61396,
61140,
60872,
60591,
60297,
59989,
59667,
59330,
58978,
58612,
58230,
57833,
57420,
56991,
56546,
56083,
55605,
55110,
54598,
54071,
53528,
52968,
52393,
51802,
51195,
50573,
49936,
49285,
48620,
47942,
47251,
46548,
45834,
45110,
44375,
43632,
42880,
42121,
41355,
40584,
39808,
39027,
38245,
37460,
36675,
35891,
35106,
34323,
33543,
32768,
31996,
31229,
30469,
29716,
28968,
28231,
27502,
26780,
26070,
25371,
24683,
24004,
23339,
22682,
22042,
21412,
20795,
20191,
19600,
19023,
18458,
17908,
17369,
16846,
16331,
15834,
15347,
14878,
14415,
13969,
13535,
13111,
12701,
12302,
11914,
11539,
11176,
10822,
10482,
10147,
9827,
9517,
9214,
8922,
8637,
8364,
8098,
7840,
7590,
7354,
7120,
6896,
6674,
6467,
6264,
6065,
5876,
5691,
5510,
5339
};
#define MIN_TSX_TEMP (-40000)
#define MAX_TSX_TEMP (+85000)
/* Original formula is
* u = auxadc raw * 2^16 / (2^32 - 1)
* Because kernel is not able to deal with floating point
* we changed the formula to
* u = auxadc raw * 2^16 / 2^32
* => u = auxadc raw / 2^16
* => u * 2^16 = auxadc raw
*/
static int tsx_u2t(int auxadc_raw)
{
int i;
int ret = 0;
int u_upper, u_low, t_upper, t_low;
if (auxadc_raw > u_table[0])
return (int) MIN_TSX_TEMP;
if (auxadc_raw < u_table[125])
return (int) MAX_TSX_TEMP;
for (i = 0; i < 125; i++) {
if (auxadc_raw < u_table[i] && auxadc_raw >= u_table[i+1]) {
u_upper = u_table[i+1];
u_low = u_table[i];
t_upper = (int) MIN_TSX_TEMP + (i+1) * 1000;
t_low = (int) MIN_TSX_TEMP + i * 1000;
if ((u_upper - u_low) == 0)
/* This case should not happen */
ret = t_low;
else
ret = t_low + ((t_upper - t_low) *
(auxadc_raw - u_low)) /
(u_upper - u_low);
break;
}
}
return ret;
}
int mt6359tsx_get_hw_temp(void)
{
int raw = 0, temp1 = 0;
#if defined(THERMAL_USE_IIO_CHANNEL)
int ret;
#endif
mutex_lock(&TSPMIC_lock);
#if defined(THERMAL_USE_IIO_CHANNEL)
if (!IS_ERR(chan_tsx_temp)) {
ret = iio_read_channel_raw(chan_tsx_temp, &raw);
if (ret < 0)
pr_notice("pmic_tsx_temp read fail, ret=%d\n", ret);
}
temp1 = tsx_u2t(raw);
#else
temp1 = 25000;
#endif
mutex_unlock(&TSPMIC_lock);
mtktspmic_dprintk("%s raw=%d T=%d\n", __func__, raw, temp1);
if ((temp1 > 100000) || (temp1 < -30000))
mtktspmic_info("%s raw=%d T=%d\n", __func__, raw, temp1);
if ((temp1 > 150000) || (temp1 < -50000)) {
mtktspmic_info("%s T=%d too high, drop it!\n", __func__,
temp1);
temp1 = pre_tstsx_temp1;
} else if ((tstsx_cnt != 0)
&& (((pre_tstsx_temp1 - temp1) > 30000)
|| ((temp1 - pre_tstsx_temp1) > 30000))) {
mtktspmic_info("%s delta temp too large, drop it!\n", __func__);
temp1 = pre_tstsx_temp1;
} else {
/* update previous temp */
pre_tstsx_temp1 = temp1;
mtktspmic_dprintk(
"%s pre_tsx_temp1=%d\n", __func__,
pre_tstsx_temp1);
if (tstsx_cnt == 0)
tstsx_cnt++;
}
return temp1;
}
int mt6359dcxo_get_hw_temp(void)
{
int raw = 0, temp1 = 0;
#if defined(THERMAL_USE_IIO_CHANNEL)
int ret;
#endif
mutex_lock(&TSPMIC_lock);
#if defined(THERMAL_USE_IIO_CHANNEL)
if (!IS_ERR(chan_dcxo_temp)) {
ret = iio_read_channel_raw(chan_dcxo_temp, &raw);
if (ret < 0)
pr_notice("pmic_dcxo_temp read fail, ret=%d\n", ret);
}
/* Temperature (C) = ((auxadc raw/32768*1.8)-0.545)/(-0.0017)+120 */
/* From dcxo desiger John Chiang */
temp1 = (((18000000/32768)*raw) - 5450000) / -17 + 120000;
if (temp1 < -40000)
temp1 = -40000;
else if (temp1 > 120000)
temp1 = 120000;
#else
temp1 = 25000;
#endif
mutex_unlock(&TSPMIC_lock);
mtktspmic_dprintk("%s raw=%d T=%d\n", __func__, raw, temp1);
if ((temp1 > 100000) || (temp1 < -30000))
mtktspmic_info("%s raw=%d T=%d\n", __func__, raw, temp1);
if ((temp1 > 150000) || (temp1 < -50000)) {
mtktspmic_info("%s T=%d too high, drop it!\n", __func__,
temp1);
temp1 = pre_tsdcxo_temp1;
} else if ((tsdcxo_cnt != 0)
&& (((pre_tsdcxo_temp1 - temp1) > 30000)
|| ((temp1 - pre_tsdcxo_temp1) > 30000))) {
mtktspmic_info("%s delta temp too large, drop it!\n", __func__);
temp1 = pre_tsdcxo_temp1;
} else {
/* update previous temp */
pre_tsdcxo_temp1 = temp1;
mtktspmic_dprintk(
"%s pre_dcxo_temp1=%d\n", __func__,
pre_tsdcxo_temp1);
if (tsdcxo_cnt == 0)
tsdcxo_cnt++;
}
return temp1;
}

1490
drivers/misc/mediatek/thermal/mt6873/src/mtk_tc.c
View File

File diff suppressed because it is too large Load Diff

1032
drivers/misc/mediatek/thermal/mt6873/src/mtk_tc_wrapper.c
View File

File diff suppressed because it is too large Load Diff

404
drivers/misc/mediatek/thermal/mt6873/src/mtk_thermal_ipi.c
View File

@@ -1,404 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include "mtk_thermal_ipi.h"
#include "mach/mtk_thermal.h"
#include "tscpu_settings.h"
#include "linux/mutex.h"
#include <linux/proc_fs.h>
#include <linux/uidgid.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#if THERMAL_ENABLE_TINYSYS_SSPM || THERMAL_ENABLE_ONLY_TZ_SSPM
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
/* ipi_send() return code
* IPI_DONE 0
* IPI_RETURN 1
* IPI_BUSY -1
* IPI_TIMEOUT_AVL -2
* IPI_TIMEOUT_ACK -3
* IPI_MODULE_ID_ERROR -4
* IPI_HW_ERROR -5
*/
static DEFINE_MUTEX(thermo_sspm_mutex);
static int is_thermal_ipi_registered;
static int ack_data;
static int register_thermal_ipi(void)
{
#ifndef THERMAL_CPUTOEB_USE_PLATFORM_IPI
int ret;
ret = mtk_ipi_register(&mcupm_ipidev, CH_S_PLATFORM, NULL, NULL,
(void *)&ack_data);
if (ret != 0) {
tscpu_printk("%s error ret:%d\n", __func__, ret);
return -1;
}
#endif
is_thermal_ipi_registered = 1;
return 0;
}
unsigned int thermal_to_mcupm(
unsigned int cmd, struct thermal_ipi_data *thermal_data)
{
int ackData = -1;
int ret;
mutex_lock(&thermo_sspm_mutex);
if (!is_thermal_ipi_registered) {
if (register_thermal_ipi() != 0)
goto end;
}
switch (cmd) {
case THERMAL_IPI_INIT_GRP1:
case THERMAL_IPI_INIT_GRP2:
case THERMAL_IPI_INIT_GRP3:
case THERMAL_IPI_INIT_GRP4:
case THERMAL_IPI_INIT_GRP5:
case THERMAL_IPI_INIT_GRP6:
thermal_data->cmd = cmd;
ret = mtk_ipi_send_compl(&mcupm_ipidev, CH_S_PLATFORM,
IPI_SEND_WAIT, thermal_data, THERMAL_SLOT_NUM, 2000);
if (ret != 0)
tscpu_printk("send init cmd(%d) error ret:%d\n",
cmd, ret);
else if (ack_data < 0)
tscpu_printk("cmd(%d) return error(%d)\n",
cmd, ack_data);
ackData = ack_data;
break;
case THERMAL_IPI_LVTS_INIT_GRP1:
thermal_data->cmd = cmd;
tscpu_printk("cmd(%d) lvts efuse to MCUPM (%d)\n",
cmd, ack_data);
ackData = ack_data;
ret = mtk_ipi_send_compl(&mcupm_ipidev, CH_S_PLATFORM,
IPI_SEND_WAIT, thermal_data, THERMAL_SLOT_NUM, 2000);
if (ret != 0)
tscpu_printk("sspm_ipi_send err cmd %d,ret:%d - %d\n",
cmd, ret, ackData);
else if (ackData < 0)
tscpu_printk("cmd(%d) return error(%d)\n",
cmd, ackData);
break;
case THERMAL_IPI_GET_TEMP:
thermal_data->cmd = cmd;
ret = mtk_ipi_send_compl(&mcupm_ipidev, CH_S_PLATFORM,
IPI_SEND_WAIT, thermal_data, THERMAL_SLOT_NUM, 2000);
if (ret != 0)
tscpu_printk("send get_temp cmd(%d) error ret:%d\n",
cmd, ret);
else if (ack_data < 0)
tscpu_printk("cmd(%d) return error(%d)\n",
cmd, ack_data);
ackData = ack_data;
break;
case THERMAL_IPI_SET_BIG_FREQ_THRESHOLD:
case THERMAL_IPI_GET_BIG_FREQ_THRESHOLD:
thermal_data->cmd = cmd;
ret = mtk_ipi_send_compl(&mcupm_ipidev, CH_S_PLATFORM,
IPI_SEND_WAIT, thermal_data, THERMAL_SLOT_NUM, 2000);
if (ret != 0)
tscpu_printk("mtk_ipi_send_compl error ret:%d - %d\n",
cmd, ret);
else if (ackData < 0)
tscpu_printk("cmd(%d) return error(%d)\n",
cmd, ackData);
break;
case THERMAL_IPI_SET_DIS_THERMAL_THROTTLE:
thermal_data->cmd = cmd;
tscpu_printk("cmd(%d) disable SSPM thermal throttle(%d)\n",
cmd, ack_data);
ackData = ack_data;
ret = mtk_ipi_send_compl(&mcupm_ipidev, CH_S_PLATFORM,
IPI_SEND_WAIT, thermal_data, THERMAL_SLOT_NUM, 2000);
if (ret != 0)
tscpu_printk("sspm_ipi_send err cmd %d,ret:%d - %d\n",
cmd, ret, ackData);
else if (ackData < 0)
tscpu_printk("cmd(%d) return error(%d)\n",
cmd, ackData);
break;
case THERMAL_IPI_SUSPEND_RESUME_NOTIFY:
thermal_data->cmd = cmd;
//tscpu_printk("cmd(%d) kernel suspend/resume(%d)\n",
// cmd, ack_data);
ackData = ack_data;
ret = mtk_ipi_send_compl(&mcupm_ipidev, CH_S_PLATFORM,
IPI_SEND_WAIT, thermal_data, THERMAL_SLOT_NUM, 2000);
if (ret != 0)
tscpu_printk("sspm_ipi_send err cmd %d,ret:%d - %d\n",
cmd, ret, ackData);
else if (ackData < 0)
tscpu_printk("cmd(%d) return error(%d)\n",
cmd, ackData);
break;
default:
tscpu_printk("cmd(%d) wrong!!\n", cmd);
break;
}
end:
mutex_unlock(&thermo_sspm_mutex);
return ackData; /** It's weird here. What should be returned? */
}
/* ipi_send() return code
* IPI_DONE 0
* IPI_RETURN 1
* IPI_BUSY -1
* IPI_TIMEOUT_AVL -2
* IPI_TIMEOUT_ACK -3
* IPI_MODULE_ID_ERROR -4
* IPI_HW_ERROR -5
*/
int atm_to_sspm(unsigned int cmd, int data_len,
struct thermal_ipi_data *thermal_data, int *ackData)
{
int ret = -1;
if (data_len < 1 || data_len > 3) {
*ackData = -1;
return ret;
}
mutex_lock(&thermo_sspm_mutex);
if (!is_thermal_ipi_registered) {
if (register_thermal_ipi() != 0)
goto end;
}
switch (cmd) {
case THERMAL_IPI_SET_ATM_CFG_GRP1:
case THERMAL_IPI_SET_ATM_CFG_GRP2:
case THERMAL_IPI_SET_ATM_CFG_GRP3:
case THERMAL_IPI_SET_ATM_CFG_GRP4:
case THERMAL_IPI_SET_ATM_CFG_GRP5:
case THERMAL_IPI_SET_ATM_CFG_GRP6:
case THERMAL_IPI_SET_ATM_CFG_GRP7:
case THERMAL_IPI_SET_ATM_CFG_GRP8:
case THERMAL_IPI_SET_ATM_TTJ:
case THERMAL_IPI_SET_ATM_EN:
case THERMAL_IPI_GET_ATM_CPU_LIMIT:
case THERMAL_IPI_GET_ATM_GPU_LIMIT:
thermal_data->cmd = cmd;
ret = mtk_ipi_send_compl(&mcupm_ipidev, CH_S_PLATFORM,
IPI_SEND_WAIT, thermal_data, (data_len+1), 2000);
if ((ret != 0) || (ack_data < 0))
tscpu_printk("%s cmd %d ret %d ack %d\n",
__func__, cmd, ret, ack_data);
*ackData = ack_data;
break;
default:
tscpu_printk("%s cmd %d err!\n", __func__, cmd);
break;
}
end:
mutex_unlock(&thermo_sspm_mutex);
return ret;
}
static int get_sspm_tz_temp_read(struct seq_file *m, void *v)
{
struct thermal_ipi_data thermal_data;
thermal_data.u.data.arg[0] = 0;
thermal_data.u.data.arg[1] = 0;
thermal_data.u.data.arg[2] = 0;
while (thermal_to_mcupm(THERMAL_IPI_GET_TEMP, &thermal_data) != 0)
udelay(500);
seq_puts(m, "Show current temperature in SSPM UART log\n");
return 0;
}
static int get_sspm_tz_temp_open(struct inode *inode, struct file *file)
{
return single_open(file, get_sspm_tz_temp_read, NULL);
}
static const struct file_operations get_sspm_tz_temp_fops = {
.owner = THIS_MODULE,
.open = get_sspm_tz_temp_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static ssize_t set_sspm_big_limit_threshold_write
(struct file *file, const char __user *buffer, size_t count, loff_t *data)
{
char desc[128];
int len = 0;
int arrayIndex, bigCoreTj, bigCoreExitTj, bigCoreFreqUpperBound;
struct thermal_ipi_data thermal_data;
len = (count < (sizeof(desc) - 1)) ? count : (sizeof(desc) - 1);
if (copy_from_user(desc, buffer, len))
return 0;
desc[len] = '\0';
if (sscanf(desc, "%d %d %d", &arrayIndex, &bigCoreTj,
&bigCoreFreqUpperBound) == 3) {
if ((arrayIndex >= BIG_CORE_THRESHOLD_ARRAY_SIZE) ||
(arrayIndex < 0)) {
tscpu_printk("%s invalid array index: %s\n",
__func__, desc);
return -EINVAL;
}
thermal_data.u.data.arg[0] = arrayIndex;
thermal_data.u.data.arg[1] = bigCoreTj;
thermal_data.u.data.arg[2] = bigCoreFreqUpperBound;
while (thermal_to_mcupm(THERMAL_IPI_SET_BIG_FREQ_THRESHOLD,
&thermal_data) != 0)
udelay(500);
return count;
} else if (sscanf(desc, "%d %d", &arrayIndex, &bigCoreExitTj) == 2) {
if (arrayIndex != -1) {
tscpu_printk("%s invalid array index: %s\n",
__func__, desc);
return -EINVAL;
}
thermal_data.u.data.arg[0] = arrayIndex;
thermal_data.u.data.arg[1] = bigCoreExitTj;
thermal_data.u.data.arg[2] = 0;
while (thermal_to_mcupm(THERMAL_IPI_SET_BIG_FREQ_THRESHOLD,
&thermal_data) != 0)
udelay(500);
return count;
}
tscpu_printk("%s bad argument: %s\n", __func__, desc);
return -EINVAL;
}
static int set_sspm_big_limit_threshold_read(struct seq_file *m, void *v)
{
struct thermal_ipi_data thermal_data;
seq_puts(m, "Use this command to change big core freq limit threshold\n");
seq_puts(m, " echo arrayIndex BigCoreTj bigCoreFreqUpperBound >\n");
seq_puts(m, " /proc/driver/thermal/set_sspm_big_limit_threshold\n");
seq_printf(m, " arrayIndex is not larger than or equal to %d\n",
BIG_CORE_THRESHOLD_ARRAY_SIZE);
seq_puts(m, " BigCoreTj is in m'C\n");
seq_puts(m, " BigCoreFreqUpperBound is in MHz\n");
seq_puts(m, " For example:\n");
seq_puts(m, " echo 0 85000 2050 > /proc/driver/thermal/set_sspm_big_limit_threshold\n");
seq_puts(m, "Use this command to change exit point\n");
seq_puts(m, " echo -1 BigCoreExitTj > /proc/driver/thermal/set_sspm_big_limit_threshold\n");
seq_puts(m, " BigCoreExitTj is in m'C\n");
seq_puts(m, " For example:\n");
seq_puts(m, " echo -1 75000 > /proc/driver/thermal/set_sspm_big_limit_threshold\n");
thermal_data.u.data.arg[0] = 0;
thermal_data.u.data.arg[1] = 0;
thermal_data.u.data.arg[2] = 0;
while (thermal_to_mcupm(THERMAL_IPI_GET_BIG_FREQ_THRESHOLD,
&thermal_data) != 0)
udelay(500);
seq_puts(m, "Show big core frequency thresholds in SSPM UART log\n");
return 0;
}
static int set_sspm_big_limit_threshold_open(struct inode *inode,
struct file *file)
{
return single_open(file, set_sspm_big_limit_threshold_read, NULL);
}
static const struct file_operations set_sspm_big_limit_threshold_fops = {
.owner = THIS_MODULE,
.open = set_sspm_big_limit_threshold_open,
.read = seq_read,
.llseek = seq_lseek,
.write = set_sspm_big_limit_threshold_write,
.release = single_release,
};
static int __init thermal_ipi_init(void)
{
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *thermal_ipi_dir = NULL;
tscpu_printk("[%s]\n", __func__);
thermal_ipi_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!thermal_ipi_dir) {
tscpu_printk(
"[%s]: mkdir /proc/driver/thermal failed\n", __func__);
} else {
entry =
proc_create("get_sspm_tz_temp", 444, thermal_ipi_dir,
&get_sspm_tz_temp_fops);
if (entry)
proc_set_user(entry, uid, gid);
entry =
proc_create("set_sspm_big_limit_threshold", 664,
thermal_ipi_dir, &set_sspm_big_limit_threshold_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
return 0;
}
static void __exit thermal_ipi_exit(void)
{
tscpu_printk("[%s]\n", __func__);
}
module_init(thermal_ipi_init);
module_exit(thermal_ipi_exit);
#endif

328
drivers/misc/mediatek/thermal/mt6873/src/mtk_ti_6315.c
View File

@@ -1,328 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/uaccess.h>
#include <linux/proc_fs.h>
#include <ap_thermal_limit.h>
#include "mt-plat/mtk_thermal_monitor.h"
/* #define INTR_UT */
/* #define OT_THROTTLE_CPU */
/* #define OT_THROTTLE_GPU */
#define DEFAULT_6315OT_CPU_LIMIT (800)
#define DEFAULT_6315OT_GPU_LIMIT (1000)
static struct apthermolmt_user ap_6315ot;
static char *ap_6315ot_log = "ap_6315ot";
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
static unsigned int cpu_limit = DEFAULT_6315OT_CPU_LIMIT;
static unsigned int gpu_limit = DEFAULT_6315OT_GPU_LIMIT;
static int virq_tempL_6;
static int virq_tempH_6;
static int virq_tempL_7;
static int virq_tempH_7;
#ifdef INTR_UT
static int virq_rcs0_6;
static int virq_rcs0_7;
#endif
static int tpmic6315_intr_probe(struct platform_device *dev);
static const struct of_device_id tpmic_intr_of_match[] = {
{ .compatible = "mediatek,mt6315_therm_intr", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, tpmic_intr_of_match);
static struct platform_driver tpmic_intr_pdrv = {
.probe = tpmic6315_intr_probe,
.remove = NULL,
.driver = {
.name = "tpmic6315_intr",
.owner = THIS_MODULE,
.of_match_table = tpmic_intr_of_match,
},
};
static irqreturn_t mt6315_6_temp_l_int_handler(int irq, void *data)
{
pr_info("%s 6315_6 CPU under 110D, irq=%d\n", __func__, irq);
disable_irq_nosync(virq_tempL_6);
enable_irq(virq_tempH_6);
#ifdef OT_THROTTLE_CPU
pr_info("%s release cpu limit\n", __func__);
apthermolmt_set_cpu_power_limit(&ap_6315ot, 0x7FFFFFFF);
#endif
return IRQ_HANDLED;
}
static irqreturn_t mt6315_6_temp_h_int_handler(int irq, void *data)
{
pr_info("%s 6315_6 CPU over 125D, irq=%d\n", __func__, irq);
disable_irq_nosync(virq_tempH_6);
enable_irq(virq_tempL_6);
#ifdef OT_THROTTLE_CPU
pr_info("%s set cpu limit=%d\n", __func__, cpu_limit);
apthermolmt_set_cpu_power_limit(&ap_6315ot, cpu_limit);
#endif
return IRQ_HANDLED;
}
#ifdef INTR_UT
static irqreturn_t mt6315_6_rcs0_handler(int irq, void *data)
{
pr_info("%s irq=%d\n", __func__, irq);
#ifdef OT_THROTTLE_CPU
pr_info("%s set cpu limit=%d\n", __func__, cpu_limit);
apthermolmt_set_cpu_power_limit(&ap_6315ot, cpu_limit);
#endif
return IRQ_HANDLED;
}
#endif
static irqreturn_t mt6315_7_temp_l_int_handler(int irq, void *data)
{
pr_info("%s 6315_7 GPU under 110D, irq=%d\n", __func__, irq);
disable_irq_nosync(virq_tempL_7);
enable_irq(virq_tempH_7);
#ifdef OT_THROTTLE_GPU
pr_info("%s release gpu limit\n", __func__);
apthermolmt_set_gpu_power_limit(&ap_6315ot, 0x7FFFFFFF);
#endif
return IRQ_HANDLED;
}
static irqreturn_t mt6315_7_temp_h_int_handler(int irq, void *data)
{
pr_info("%s 6315_7 GPU over 125D, irq=%d\n", __func__, irq);
disable_irq_nosync(virq_tempH_7);
enable_irq(virq_tempL_7);
#ifdef OT_THROTTLE_GPU
pr_info("%s set gpu limit=%d\n", __func__, gpu_limit);
apthermolmt_set_gpu_power_limit(&ap_6315ot, gpu_limit);
#endif
return IRQ_HANDLED;
}
#ifdef INTR_UT
static irqreturn_t mt6315_7_rcs0_handler(int irq, void *data)
{
pr_info("%s irq=%d\n", __func__, irq);
#ifdef OT_THROTTLE_GPU
pr_info("%s set gpu limit=%d\n", __func__, gpu_limit);
apthermolmt_set_gpu_power_limit(&ap_6315ot, gpu_limit);
#endif
return IRQ_HANDLED;
}
#endif
static int tpmic6315_intr_probe(struct platform_device *pdev)
{
struct device_node *node;
int ret = 0;
node = of_find_matching_node(NULL, tpmic_intr_of_match);
if (!node)
pr_info("@%s: find tpmic_intr node failed\n", __func__);
virq_tempL_6 = platform_get_irq(pdev, 0);
virq_tempH_6 = platform_get_irq(pdev, 1);
virq_tempL_7 = platform_get_irq(pdev, 3);
virq_tempH_7 = platform_get_irq(pdev, 4);
#ifdef INTR_UT
virq_rcs0_6 = platform_get_irq(pdev, 2);
virq_rcs0_7 = platform_get_irq(pdev, 5);
#endif
#ifdef INTR_UT
if (virq_tempL_6 <= 0 || virq_tempH_6 <= 0 || virq_rcs0_6 <= 0 ||
virq_tempL_7 <= 0 || virq_tempH_7 <= 0 || virq_rcs0_7 <= 0) {
#else
if (virq_tempL_6 <= 0 || virq_tempH_6 <= 0 ||
virq_tempL_7 <= 0 || virq_tempH_7 <= 0) {
#endif
pr_info("%s: get irq error\n", __func__);
return 0;
}
pr_info("%s: 6_temp_back_110D = %d(%d)\n"
, __func__
, platform_get_irq(pdev, 0)
, platform_get_irq_byname(pdev, "6315_6_temp_l"));
pr_info("%s: 6_temp_over_125D = %d(%d)\n"
, __func__
, platform_get_irq(pdev, 1)
, platform_get_irq_byname(pdev, "6315_6_temp_h"));
pr_info("%s: 7_temp_back_110D = %d(%d)\n"
, __func__
, platform_get_irq(pdev, 3)
, platform_get_irq_byname(pdev, "6315_7_temp_l"));
pr_info("%s: 7_temp_over_125D = %d(%d)\n"
, __func__
, platform_get_irq(pdev, 4)
, platform_get_irq_byname(pdev, "6315_7_temp_h"));
#ifdef INTR_UT
pr_info("%s: 6_rcs0 = %d(%d)\n"
, __func__
, platform_get_irq(pdev, 2)
, platform_get_irq_byname(pdev, "6315_6_rcs0"));
pr_info("%s: 7_rcs0 = %d(%d)\n"
, __func__
, platform_get_irq(pdev, 5)
, platform_get_irq_byname(pdev, "6315_7_rcs0"));
#endif
ret = devm_request_threaded_irq(&pdev->dev,
platform_get_irq_byname(pdev, "6315_6_temp_l"),
NULL, mt6315_6_temp_l_int_handler, IRQF_TRIGGER_NONE,
"6315_S6_TEMP_L", NULL);
if (ret < 0)
dev_notice(&pdev->dev, "request test irq fail\n");
ret = devm_request_threaded_irq(&pdev->dev,
platform_get_irq_byname(pdev, "6315_6_temp_h"),
NULL, mt6315_6_temp_h_int_handler, IRQF_TRIGGER_NONE,
"6315_S6_TEMP_H", NULL);
if (ret < 0)
dev_notice(&pdev->dev, "request test irq fail\n");
ret = devm_request_threaded_irq(&pdev->dev,
platform_get_irq_byname(pdev, "6315_7_temp_l"),
NULL, mt6315_7_temp_l_int_handler, IRQF_TRIGGER_NONE,
"6315_S7_TEMP_L", NULL);
if (ret < 0)
dev_notice(&pdev->dev, "request test irq fail\n");
ret = devm_request_threaded_irq(&pdev->dev,
platform_get_irq_byname(pdev, "6315_7_temp_h"),
NULL, mt6315_7_temp_h_int_handler, IRQF_TRIGGER_NONE,
"6315_S7_TEMP_H", NULL);
if (ret < 0)
dev_notice(&pdev->dev, "request test irq fail\n");
#ifdef INTR_UT
ret = devm_request_threaded_irq(&pdev->dev,
platform_get_irq_byname(pdev, "6315_6_rcs0"),
NULL, mt6315_6_rcs0_handler, IRQF_TRIGGER_NONE,
"6315_S6_RCS0", NULL);
if (ret < 0)
dev_notice(&pdev->dev, "request test irq fail\n");
ret = devm_request_threaded_irq(&pdev->dev,
platform_get_irq_byname(pdev, "6315_7_rcs0"),
NULL, mt6315_7_rcs0_handler, IRQF_TRIGGER_NONE,
"6315_S7_RCS0", NULL);
if (ret < 0)
dev_notice(&pdev->dev, "request test irq fail\n");
#endif
disable_irq_nosync(virq_tempL_6);
disable_irq_nosync(virq_tempL_7);
return 0;
}
static int cl_6315ot_read(struct seq_file *m, void *v)
{
seq_printf(m, "[%s] C/G limit = %d/%d\n",
__func__, cpu_limit, gpu_limit);
return 0;
}
static ssize_t cl_6315ot_write(
struct file *file, const char __user *buffer, size_t count, loff_t *data)
{
char desc[128];
int len = 0;
int c_limit, g_limit;
len = (count < (sizeof(desc) - 1)) ? count : (sizeof(desc) - 1);
if (copy_from_user(desc, buffer, len))
return 0;
desc[len] = '\0';
if (sscanf(desc, "%d %d", &c_limit, &g_limit) == 2) {
pr_info("[%s] set C/G limit = %d/%d\n",
__func__, c_limit, g_limit);
cpu_limit = (c_limit != 0) ? c_limit : 0x7FFFFFFF;
gpu_limit = (g_limit != 0) ? g_limit : 0x7FFFFFFF;
return count;
}
pr_info("%s bad argument\n", __func__);
return -EINVAL;
}
static int cl_6315ot_open(struct inode *inode, struct file *file)
{
return single_open(file, cl_6315ot_read, NULL);
}
static const struct file_operations cl_6315ot_fops = {
.owner = THIS_MODULE,
.open = cl_6315ot_open,
.read = seq_read,
.llseek = seq_lseek,
.write = cl_6315ot_write,
.release = single_release,
};
static int __init mtk_ti_6315_init(void)
{
int ret = 0;
/* register platform driver */
ret = platform_driver_register(&tpmic_intr_pdrv);
if (ret) {
pr_info("fail to register %s driver ~~~\n", __func__);
goto end;
}
/* create a proc file */
{
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *dir_entry = NULL;
dir_entry = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!dir_entry) {
pr_info(
"[%s]: mkdir /proc/driver/thermal failed\n", __func__);
} else {
entry = proc_create("cl6315ot_limit", 0664,
dir_entry,
&cl_6315ot_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
}
/* register user to thermal */
apthermolmt_register_user(&ap_6315ot, ap_6315ot_log);
end:
return 0;
}
static void __exit mtk_ti_6315_exit(void)
{
apthermolmt_unregister_user(&ap_6315ot);
platform_driver_unregister(&tpmic_intr_pdrv);
pr_info("%s\n", __func__);
}
late_initcall(mtk_ti_6315_init);
module_exit(mtk_ti_6315_exit);

597
drivers/misc/mediatek/thermal/mt6873/src/mtk_ts_6359dcxo.c
View File

@@ -1,597 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int isTimerCancelled;
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2 && curr_temp < polling_trip_temp1,
* use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 150000, 110000, 100000, 90000, 80000,
70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = { 0 };
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long int mt6359dcxo_cur_temp;
/*
*static long int mt6359dcxo_start_temp;
*static long int mt6359dcxo_end_temp;
*/
/*=============================================================*/
static int mt6359dcxo_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6359dcxo_get_hw_temp();
mt6359dcxo_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6359dcxo_bind
(struct thermal_zone_device *thermal, struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info(
"[%s] error binding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] binding OK, %d\n", __func__, table_val);
return 0;
}
static int mt6359dcxo_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info(
"[%s] error unbinding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] unbinding OK\n", __func__);
return 0;
}
static int mt6359dcxo_get_mode
(struct thermal_zone_device *thermal, enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6359dcxo_set_mode
(struct thermal_zone_device *thermal, enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6359dcxo_get_trip_type
(struct thermal_zone_device *thermal, int trip, enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6359dcxo_get_trip_temp
(struct thermal_zone_device *thermal, int trip, int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6359dcxo_get_crit_temp
(struct thermal_zone_device *thermal, int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6359dcxo_dev_ops = {
.bind = mt6359dcxo_bind,
.unbind = mt6359dcxo_unbind,
.get_temp = mt6359dcxo_get_temp,
.get_mode = mt6359dcxo_get_mode,
.set_mode = mt6359dcxo_set_mode,
.get_trip_type = mt6359dcxo_get_trip_type,
.get_trip_temp = mt6359dcxo_get_trip_temp,
.get_crit_temp = mt6359dcxo_get_crit_temp,
};
static int mt6359dcxo_sysrst_get_max_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6359dcxo_sysrst_get_cur_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6359dcxo_sysrst_set_cur_state
(struct thermal_cooling_device *cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("mt6359dcxo OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
#if 0 /* temp marked off to check temperature correctness. */
*(unsigned int *)0x0 = 0xdead;
/* To trigger data abort to reset the system for thermal protection. */
#endif
}
return 0;
}
static struct thermal_cooling_device_ops mt6359dcxo_cooling_sysrst_ops = {
.get_max_state = mt6359dcxo_sysrst_get_max_state,
.get_cur_state = mt6359dcxo_sysrst_get_cur_state,
.set_cur_state = mt6359dcxo_sysrst_set_cur_state,
};
static int mt6359dcxo_read(struct seq_file *m, void *v)
{
seq_printf(m,
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
__func__, trip_temp[0], trip_temp[1], trip_temp[2],
trip_temp[3]);
seq_printf(m,
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6],
trip_temp[7], trip_temp[8], trip_temp[9]);
seq_printf(m,
"g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2],
g_THERMAL_TRIP[3]);
seq_printf(m,
"g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6],
g_THERMAL_TRIP[7]);
seq_printf(m, "g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
seq_printf(m,
"cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m,
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s,time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6359dcxo_register_thermal(void);
static void mt6359dcxo_unregister_thermal(void);
static ssize_t mt6359dcxo_write
(struct file *file, const char __user *buffer, size_t count, loff_t *data)
{
int len = 0;
int i;
struct mt6359dcxo_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6359dcxo_data *ptr_mt6359dcxo_data;
ptr_mt6359dcxo_data =
kmalloc(sizeof(*ptr_mt6359dcxo_data), GFP_KERNEL);
if (ptr_mt6359dcxo_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6359dcxo_data->desc) - 1)) ?
count : (sizeof(ptr_mt6359dcxo_data->desc) - 1);
if (copy_from_user(ptr_mt6359dcxo_data->desc, buffer, len)) {
kfree(ptr_mt6359dcxo_data);
return 0;
}
ptr_mt6359dcxo_data->desc[len] = '\0';
if (sscanf
(ptr_mt6359dcxo_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6359dcxo_data->trip[0],
&ptr_mt6359dcxo_data->t_type[0],
ptr_mt6359dcxo_data->bind0,
&ptr_mt6359dcxo_data->trip[1],
&ptr_mt6359dcxo_data->t_type[1],
ptr_mt6359dcxo_data->bind1,
&ptr_mt6359dcxo_data->trip[2],
&ptr_mt6359dcxo_data->t_type[2],
ptr_mt6359dcxo_data->bind2,
&ptr_mt6359dcxo_data->trip[3],
&ptr_mt6359dcxo_data->t_type[3],
ptr_mt6359dcxo_data->bind3,
&ptr_mt6359dcxo_data->trip[4],
&ptr_mt6359dcxo_data->t_type[4],
ptr_mt6359dcxo_data->bind4,
&ptr_mt6359dcxo_data->trip[5],
&ptr_mt6359dcxo_data->t_type[5],
ptr_mt6359dcxo_data->bind5,
&ptr_mt6359dcxo_data->trip[6],
&ptr_mt6359dcxo_data->t_type[6],
ptr_mt6359dcxo_data->bind6,
&ptr_mt6359dcxo_data->trip[7],
&ptr_mt6359dcxo_data->t_type[7],
ptr_mt6359dcxo_data->bind7,
&ptr_mt6359dcxo_data->trip[8],
&ptr_mt6359dcxo_data->t_type[8],
ptr_mt6359dcxo_data->bind8,
&ptr_mt6359dcxo_data->trip[9],
&ptr_mt6359dcxo_data->t_type[9],
ptr_mt6359dcxo_data->bind9,
&ptr_mt6359dcxo_data->time_msec) == 32) {
down(&sem_mutex);
mtktspmic_dprintk(
"[%s] mt6359dcxo_unregister_thermal\n", __func__);
mt6359dcxo_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__,
DB_OPT_DEFAULT, "mt6359dcxo_write",
"Bad argument");
#endif
mtktspmic_dprintk(
"[%s] bad argument\n", __func__);
kfree(ptr_mt6359dcxo_data);
up(&sem_mutex);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6359dcxo_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] = g_bind4[0]
= g_bind5[0] = g_bind6[0] = g_bind7[0] = g_bind8[0] = g_bind9[0]
= '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6359dcxo_data->bind0[i];
g_bind1[i] = ptr_mt6359dcxo_data->bind1[i];
g_bind2[i] = ptr_mt6359dcxo_data->bind2[i];
g_bind3[i] = ptr_mt6359dcxo_data->bind3[i];
g_bind4[i] = ptr_mt6359dcxo_data->bind4[i];
g_bind5[i] = ptr_mt6359dcxo_data->bind5[i];
g_bind6[i] = ptr_mt6359dcxo_data->bind6[i];
g_bind7[i] = ptr_mt6359dcxo_data->bind7[i];
g_bind8[i] = ptr_mt6359dcxo_data->bind8[i];
g_bind9[i] = ptr_mt6359dcxo_data->bind9[i];
}
mtktspmic_dprintk(
"[%s] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
__func__, g_THERMAL_TRIP[0], g_THERMAL_TRIP[1],
g_THERMAL_TRIP[2]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4], g_THERMAL_TRIP[5],
g_THERMAL_TRIP[6]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
mtktspmic_dprintk(
"[%s] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
__func__, g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk(
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6359dcxo_data->trip[i];
interval = ptr_mt6359dcxo_data->time_msec / 1000;
mtktspmic_dprintk(
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
__func__, trip_temp[0], trip_temp[1], trip_temp[2],
trip_temp[3]);
mtktspmic_dprintk(
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8]);
mtktspmic_dprintk("trip_9_temp=%d,time_ms=%d\n",
trip_temp[9], interval * 1000);
mtktspmic_dprintk(
"[%s] mt6359dcxo_register_thermal\n", __func__);
mt6359dcxo_register_thermal();
up(&sem_mutex);
kfree(ptr_mt6359dcxo_data);
return count;
}
mtktspmic_dprintk("[%s] bad argument\n", __func__);
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6359dcxo_write", "Bad argument");
#endif
kfree(ptr_mt6359dcxo_data);
return -EINVAL;
}
static void mt6359dcxo_cancel_thermal_timer(void)
{
/* stop thermal framework polling when entering deep idle */
if (down_trylock(&sem_mutex))
return;
if (thz_dev) {
cancel_delayed_work(&(thz_dev->poll_queue));
isTimerCancelled = 1;
}
up(&sem_mutex);
}
static void mt6359dcxo_start_thermal_timer(void)
{
/* resume thermal framework polling when leaving deep idle */
if (!isTimerCancelled)
return;
isTimerCancelled = 0;
if (down_trylock(&sem_mutex))
return;
if (thz_dev != NULL && interval != 0)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue),
round_jiffies(msecs_to_jiffies(1000)));
up(&sem_mutex);
}
static int mt6359dcxo_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register(
"mt6359dcxo-sysrst", NULL,
&mt6359dcxo_cooling_sysrst_ops);
return 0;
}
static int mt6359dcxo_register_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register(
"mt6359dcxo", num_trip, NULL,
&mt6359dcxo_dev_ops, 0, 0, 0, interval * 1000);
return 0;
}
static void mt6359dcxo_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6359dcxo_unregister_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
if (thz_dev) {
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
}
}
static int mt6359dcxo_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6359dcxo_read, NULL);
}
static const struct file_operations mt6359dcxo_fops = {
.owner = THIS_MODULE,
.open = mt6359dcxo_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6359dcxo_write,
.release = single_release,
};
static int __init mt6359dcxo_init(void)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6359dcxo_dir = NULL;
mtktspmic_info("[%s]\n", __func__);
err = mt6359dcxo_register_cooler();
if (err)
return err;
mt6359dcxo_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6359dcxo_dir) {
mtktspmic_info(
"[%s]: mkdir /proc/driver/thermal failed\n", __func__);
} else {
entry =
proc_create("tz6359dcxo", 664, mt6359dcxo_dir,
&mt6359dcxo_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6359dcxo", mt6359dcxo_start_thermal_timer,
mt6359dcxo_cancel_thermal_timer);
return 0;
}
static void __exit mt6359dcxo_exit(void)
{
mtktspmic_info("[%s]\n", __func__);
mt6359dcxo_unregister_thermal();
mt6359dcxo_unregister_cooler();
mtkTTimer_unregister("mt6359dcxo");
}
module_init(mt6359dcxo_init);
module_exit(mt6359dcxo_exit);

597
drivers/misc/mediatek/thermal/mt6873/src/mtk_ts_6359tsx.c
View File

@@ -1,597 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int isTimerCancelled;
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2 && curr_temp < polling_trip_temp1,
* use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 150000, 110000, 100000, 90000, 80000,
70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = { 0 };
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long int mt6359tsx_cur_temp;
/*
*static long int mt6359tsx_start_temp;
*static long int mt6359tsx_end_temp;
*/
/*=============================================================*/
static int mt6359tsx_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6359tsx_get_hw_temp();
mt6359tsx_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6359tsx_bind
(struct thermal_zone_device *thermal, struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info(
"[%s] error binding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] binding OK, %d\n", __func__, table_val);
return 0;
}
static int mt6359tsx_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info(
"[%s] error unbinding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] unbinding OK\n", __func__);
return 0;
}
static int mt6359tsx_get_mode
(struct thermal_zone_device *thermal, enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6359tsx_set_mode
(struct thermal_zone_device *thermal, enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6359tsx_get_trip_type
(struct thermal_zone_device *thermal, int trip, enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6359tsx_get_trip_temp
(struct thermal_zone_device *thermal, int trip, int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6359tsx_get_crit_temp
(struct thermal_zone_device *thermal, int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6359tsx_dev_ops = {
.bind = mt6359tsx_bind,
.unbind = mt6359tsx_unbind,
.get_temp = mt6359tsx_get_temp,
.get_mode = mt6359tsx_get_mode,
.set_mode = mt6359tsx_set_mode,
.get_trip_type = mt6359tsx_get_trip_type,
.get_trip_temp = mt6359tsx_get_trip_temp,
.get_crit_temp = mt6359tsx_get_crit_temp,
};
static int mt6359tsx_sysrst_get_max_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6359tsx_sysrst_get_cur_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6359tsx_sysrst_set_cur_state
(struct thermal_cooling_device *cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("mt6359tsx OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
#if 0 /* temp marked off to check temperature correctness. */
*(unsigned int *)0x0 = 0xdead;
/* To trigger data abort to reset the system for thermal protection. */
#endif
}
return 0;
}
static struct thermal_cooling_device_ops mt6359tsx_cooling_sysrst_ops = {
.get_max_state = mt6359tsx_sysrst_get_max_state,
.get_cur_state = mt6359tsx_sysrst_get_cur_state,
.set_cur_state = mt6359tsx_sysrst_set_cur_state,
};
static int mt6359tsx_read(struct seq_file *m, void *v)
{
seq_printf(m,
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
__func__, trip_temp[0], trip_temp[1], trip_temp[2],
trip_temp[3]);
seq_printf(m,
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6],
trip_temp[7], trip_temp[8], trip_temp[9]);
seq_printf(m,
"g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2],
g_THERMAL_TRIP[3]);
seq_printf(m,
"g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6],
g_THERMAL_TRIP[7]);
seq_printf(m, "g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
seq_printf(m,
"cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m,
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s,time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6359tsx_register_thermal(void);
static void mt6359tsx_unregister_thermal(void);
static ssize_t mt6359tsx_write
(struct file *file, const char __user *buffer, size_t count, loff_t *data)
{
int len = 0;
int i;
struct mt6359tsx_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6359tsx_data *ptr_mt6359tsx_data;
ptr_mt6359tsx_data =
kmalloc(sizeof(*ptr_mt6359tsx_data), GFP_KERNEL);
if (ptr_mt6359tsx_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6359tsx_data->desc) - 1)) ?
count : (sizeof(ptr_mt6359tsx_data->desc) - 1);
if (copy_from_user(ptr_mt6359tsx_data->desc, buffer, len)) {
kfree(ptr_mt6359tsx_data);
return 0;
}
ptr_mt6359tsx_data->desc[len] = '\0';
if (sscanf
(ptr_mt6359tsx_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6359tsx_data->trip[0],
&ptr_mt6359tsx_data->t_type[0],
ptr_mt6359tsx_data->bind0,
&ptr_mt6359tsx_data->trip[1],
&ptr_mt6359tsx_data->t_type[1],
ptr_mt6359tsx_data->bind1,
&ptr_mt6359tsx_data->trip[2],
&ptr_mt6359tsx_data->t_type[2],
ptr_mt6359tsx_data->bind2,
&ptr_mt6359tsx_data->trip[3],
&ptr_mt6359tsx_data->t_type[3],
ptr_mt6359tsx_data->bind3,
&ptr_mt6359tsx_data->trip[4],
&ptr_mt6359tsx_data->t_type[4],
ptr_mt6359tsx_data->bind4,
&ptr_mt6359tsx_data->trip[5],
&ptr_mt6359tsx_data->t_type[5],
ptr_mt6359tsx_data->bind5,
&ptr_mt6359tsx_data->trip[6],
&ptr_mt6359tsx_data->t_type[6],
ptr_mt6359tsx_data->bind6,
&ptr_mt6359tsx_data->trip[7],
&ptr_mt6359tsx_data->t_type[7],
ptr_mt6359tsx_data->bind7,
&ptr_mt6359tsx_data->trip[8],
&ptr_mt6359tsx_data->t_type[8],
ptr_mt6359tsx_data->bind8,
&ptr_mt6359tsx_data->trip[9],
&ptr_mt6359tsx_data->t_type[9],
ptr_mt6359tsx_data->bind9,
&ptr_mt6359tsx_data->time_msec) == 32) {
down(&sem_mutex);
mtktspmic_dprintk(
"[%s] mt6359tsx_unregister_thermal\n", __func__);
mt6359tsx_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__,
DB_OPT_DEFAULT, "mt6359tsx_write",
"Bad argument");
#endif
mtktspmic_dprintk(
"[%s] bad argument\n", __func__);
kfree(ptr_mt6359tsx_data);
up(&sem_mutex);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6359tsx_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] = g_bind4[0]
= g_bind5[0] = g_bind6[0] = g_bind7[0] = g_bind8[0] = g_bind9[0]
= '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6359tsx_data->bind0[i];
g_bind1[i] = ptr_mt6359tsx_data->bind1[i];
g_bind2[i] = ptr_mt6359tsx_data->bind2[i];
g_bind3[i] = ptr_mt6359tsx_data->bind3[i];
g_bind4[i] = ptr_mt6359tsx_data->bind4[i];
g_bind5[i] = ptr_mt6359tsx_data->bind5[i];
g_bind6[i] = ptr_mt6359tsx_data->bind6[i];
g_bind7[i] = ptr_mt6359tsx_data->bind7[i];
g_bind8[i] = ptr_mt6359tsx_data->bind8[i];
g_bind9[i] = ptr_mt6359tsx_data->bind9[i];
}
mtktspmic_dprintk(
"[%s] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
__func__, g_THERMAL_TRIP[0], g_THERMAL_TRIP[1],
g_THERMAL_TRIP[2]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4], g_THERMAL_TRIP[5],
g_THERMAL_TRIP[6]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
mtktspmic_dprintk(
"[%s] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
__func__, g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk(
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6359tsx_data->trip[i];
interval = ptr_mt6359tsx_data->time_msec / 1000;
mtktspmic_dprintk(
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
__func__, trip_temp[0], trip_temp[1], trip_temp[2],
trip_temp[3]);
mtktspmic_dprintk(
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8]);
mtktspmic_dprintk("trip_9_temp=%d,time_ms=%d\n",
trip_temp[9], interval * 1000);
mtktspmic_dprintk(
"[%s] mt6359tsx_register_thermal\n", __func__);
mt6359tsx_register_thermal();
up(&sem_mutex);
kfree(ptr_mt6359tsx_data);
return count;
}
mtktspmic_dprintk("[%s] bad argument\n", __func__);
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6359tsx_write", "Bad argument");
#endif
kfree(ptr_mt6359tsx_data);
return -EINVAL;
}
static void mt6359tsx_cancel_thermal_timer(void)
{
/* stop thermal framework polling when entering deep idle */
if (down_trylock(&sem_mutex))
return;
if (thz_dev) {
cancel_delayed_work(&(thz_dev->poll_queue));
isTimerCancelled = 1;
}
up(&sem_mutex);
}
static void mt6359tsx_start_thermal_timer(void)
{
/* resume thermal framework polling when leaving deep idle */
if (!isTimerCancelled)
return;
isTimerCancelled = 0;
if (down_trylock(&sem_mutex))
return;
if (thz_dev != NULL && interval != 0)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue),
round_jiffies(msecs_to_jiffies(1000)));
up(&sem_mutex);
}
static int mt6359tsx_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register(
"mt6359tsx-sysrst", NULL,
&mt6359tsx_cooling_sysrst_ops);
return 0;
}
static int mt6359tsx_register_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register(
"mt6359tsx", num_trip, NULL,
&mt6359tsx_dev_ops, 0, 0, 0, interval * 1000);
return 0;
}
static void mt6359tsx_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6359tsx_unregister_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
if (thz_dev) {
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
}
}
static int mt6359tsx_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6359tsx_read, NULL);
}
static const struct file_operations mt6359tsx_fops = {
.owner = THIS_MODULE,
.open = mt6359tsx_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6359tsx_write,
.release = single_release,
};
static int __init mt6359tsx_init(void)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6359tsx_dir = NULL;
mtktspmic_info("[%s]\n", __func__);
err = mt6359tsx_register_cooler();
if (err)
return err;
mt6359tsx_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6359tsx_dir) {
mtktspmic_info(
"[%s]: mkdir /proc/driver/thermal failed\n", __func__);
} else {
entry =
proc_create("tz6359tsx", 664, mt6359tsx_dir,
&mt6359tsx_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6359tsx", mt6359tsx_start_thermal_timer,
mt6359tsx_cancel_thermal_timer);
return 0;
}
static void __exit mt6359tsx_exit(void)
{
mtktspmic_info("[%s]\n", __func__);
mt6359tsx_unregister_thermal();
mt6359tsx_unregister_cooler();
mtkTTimer_unregister("mt6359tsx");
}
module_init(mt6359tsx_init);
module_exit(mt6359tsx_exit);

595
drivers/misc/mediatek/thermal/mt6873/src/mtk_ts_6359vcore.c
View File

@@ -1,595 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int isTimerCancelled;
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2 && curr_temp < polling_trip_temp1,
* use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 150000, 110000, 100000, 90000, 80000,
70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = { 0 };
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long int mt6359vcore_cur_temp;
/*
*static long int mt6359vcore_start_temp;
*static long int mt6359vcore_end_temp;
*/
/*=============================================================*/
static int mt6359vcore_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6359vcore_get_hw_temp();
mt6359vcore_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6359vcore_bind
(struct thermal_zone_device *thermal, struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info(
"[%s] error binding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] binding OK, %d\n", __func__, table_val);
return 0;
}
static int mt6359vcore_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info(
"[%s] error unbinding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] unbinding OK\n", __func__);
return 0;
}
static int mt6359vcore_get_mode
(struct thermal_zone_device *thermal, enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6359vcore_set_mode
(struct thermal_zone_device *thermal, enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6359vcore_get_trip_type
(struct thermal_zone_device *thermal, int trip, enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6359vcore_get_trip_temp
(struct thermal_zone_device *thermal, int trip, int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6359vcore_get_crit_temp
(struct thermal_zone_device *thermal, int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6359vcore_dev_ops = {
.bind = mt6359vcore_bind,
.unbind = mt6359vcore_unbind,
.get_temp = mt6359vcore_get_temp,
.get_mode = mt6359vcore_get_mode,
.set_mode = mt6359vcore_set_mode,
.get_trip_type = mt6359vcore_get_trip_type,
.get_trip_temp = mt6359vcore_get_trip_temp,
.get_crit_temp = mt6359vcore_get_crit_temp,
};
static int mt6359vcore_sysrst_get_max_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6359vcore_sysrst_get_cur_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6359vcore_sysrst_set_cur_state
(struct thermal_cooling_device *cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("mt6359vcore OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
#if 0 /* temp marked off to check temperature correctness. */
*(unsigned int *)0x0 = 0xdead;
/* To trigger data abort to reset the system for thermal protection. */
#endif
}
return 0;
}
static struct thermal_cooling_device_ops mt6359vcore_cooling_sysrst_ops = {
.get_max_state = mt6359vcore_sysrst_get_max_state,
.get_cur_state = mt6359vcore_sysrst_get_cur_state,
.set_cur_state = mt6359vcore_sysrst_set_cur_state,
};
static int mt6359vcore_read(struct seq_file *m, void *v)
{
seq_printf(m,
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
__func__, trip_temp[0], trip_temp[1], trip_temp[2],
trip_temp[3]);
seq_printf(m,
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6],
trip_temp[7], trip_temp[8], trip_temp[9]);
seq_printf(m,
"g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2],
g_THERMAL_TRIP[3]);
seq_printf(m,
"g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6],
g_THERMAL_TRIP[7]);
seq_printf(m, "g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
seq_printf(m,
"cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m,
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s,time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6359vcore_register_thermal(void);
static void mt6359vcore_unregister_thermal(void);
static ssize_t mt6359vcore_write
(struct file *file, const char __user *buffer, size_t count, loff_t *data)
{
int len = 0;
int i;
struct mt6359vcore_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6359vcore_data *ptr_mt6359vcore_data;
ptr_mt6359vcore_data =
kmalloc(sizeof(*ptr_mt6359vcore_data), GFP_KERNEL);
if (ptr_mt6359vcore_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6359vcore_data->desc) - 1)) ?
count : (sizeof(ptr_mt6359vcore_data->desc) - 1);
if (copy_from_user(ptr_mt6359vcore_data->desc, buffer, len)) {
kfree(ptr_mt6359vcore_data);
return 0;
}
ptr_mt6359vcore_data->desc[len] = '\0';
if (sscanf
(ptr_mt6359vcore_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6359vcore_data->trip[0],
&ptr_mt6359vcore_data->t_type[0],
ptr_mt6359vcore_data->bind0,
&ptr_mt6359vcore_data->trip[1],
&ptr_mt6359vcore_data->t_type[1],
ptr_mt6359vcore_data->bind1,
&ptr_mt6359vcore_data->trip[2],
&ptr_mt6359vcore_data->t_type[2],
ptr_mt6359vcore_data->bind2,
&ptr_mt6359vcore_data->trip[3],
&ptr_mt6359vcore_data->t_type[3],
ptr_mt6359vcore_data->bind3,
&ptr_mt6359vcore_data->trip[4],
&ptr_mt6359vcore_data->t_type[4],
ptr_mt6359vcore_data->bind4,
&ptr_mt6359vcore_data->trip[5],
&ptr_mt6359vcore_data->t_type[5],
ptr_mt6359vcore_data->bind5,
&ptr_mt6359vcore_data->trip[6],
&ptr_mt6359vcore_data->t_type[6],
ptr_mt6359vcore_data->bind6,
&ptr_mt6359vcore_data->trip[7],
&ptr_mt6359vcore_data->t_type[7],
ptr_mt6359vcore_data->bind7,
&ptr_mt6359vcore_data->trip[8],
&ptr_mt6359vcore_data->t_type[8],
ptr_mt6359vcore_data->bind8,
&ptr_mt6359vcore_data->trip[9],
&ptr_mt6359vcore_data->t_type[9],
ptr_mt6359vcore_data->bind9,
&ptr_mt6359vcore_data->time_msec) == 32) {
down(&sem_mutex);
mtktspmic_dprintk(
"[%s] mt6359vcore_unregister_thermal\n", __func__);
mt6359vcore_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__,
DB_OPT_DEFAULT, "mt6359vcore_write",
"Bad argument");
#endif
mtktspmic_dprintk("[%s] bad argument\n", __func__);
kfree(ptr_mt6359vcore_data);
up(&sem_mutex);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6359vcore_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] = g_bind4[0]
= g_bind5[0] = g_bind6[0] = g_bind7[0] = g_bind8[0] = g_bind9[0]
= '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6359vcore_data->bind0[i];
g_bind1[i] = ptr_mt6359vcore_data->bind1[i];
g_bind2[i] = ptr_mt6359vcore_data->bind2[i];
g_bind3[i] = ptr_mt6359vcore_data->bind3[i];
g_bind4[i] = ptr_mt6359vcore_data->bind4[i];
g_bind5[i] = ptr_mt6359vcore_data->bind5[i];
g_bind6[i] = ptr_mt6359vcore_data->bind6[i];
g_bind7[i] = ptr_mt6359vcore_data->bind7[i];
g_bind8[i] = ptr_mt6359vcore_data->bind8[i];
g_bind9[i] = ptr_mt6359vcore_data->bind9[i];
}
mtktspmic_dprintk(
"[%s] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
__func__, g_THERMAL_TRIP[0], g_THERMAL_TRIP[1],
g_THERMAL_TRIP[2]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4], g_THERMAL_TRIP[5],
g_THERMAL_TRIP[6]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
mtktspmic_dprintk(
"[%s] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
__func__, g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk(
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6359vcore_data->trip[i];
interval = ptr_mt6359vcore_data->time_msec / 1000;
mtktspmic_dprintk(
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
__func__, trip_temp[0], trip_temp[1], trip_temp[2],
trip_temp[3]);
mtktspmic_dprintk(
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8]);
mtktspmic_dprintk("trip_9_temp=%d,time_ms=%d\n",
trip_temp[9], interval * 1000);
mtktspmic_dprintk(
"[%s] mt6359vcore_register_thermal\n", __func__);
mt6359vcore_register_thermal();
up(&sem_mutex);
kfree(ptr_mt6359vcore_data);
return count;
}
mtktspmic_dprintk("[%s] bad argument\n", __func__);
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6359vcore_write", "Bad argument");
#endif
kfree(ptr_mt6359vcore_data);
return -EINVAL;
}
static void mt6359vcore_cancel_thermal_timer(void)
{
/* stop thermal framework polling when entering deep idle */
if (down_trylock(&sem_mutex))
return;
if (thz_dev) {
cancel_delayed_work(&(thz_dev->poll_queue));
isTimerCancelled = 1;
}
up(&sem_mutex);
}
static void mt6359vcore_start_thermal_timer(void)
{
/* resume thermal framework polling when leaving deep idle */
if (!isTimerCancelled)
return;
isTimerCancelled = 0;
if (down_trylock(&sem_mutex))
return;
if (thz_dev != NULL && interval != 0)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue),
round_jiffies(msecs_to_jiffies(1000)));
up(&sem_mutex);
}
static int mt6359vcore_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register(
"mt6359vcore-sysrst", NULL,
&mt6359vcore_cooling_sysrst_ops);
return 0;
}
static int mt6359vcore_register_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register(
"mt6359vcore", num_trip, NULL,
&mt6359vcore_dev_ops, 0, 0, 0, interval * 1000);
return 0;
}
static void mt6359vcore_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6359vcore_unregister_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
if (thz_dev) {
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
}
}
static int mt6359vcore_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6359vcore_read, NULL);
}
static const struct file_operations mt6359vcore_fops = {
.owner = THIS_MODULE,
.open = mt6359vcore_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6359vcore_write,
.release = single_release,
};
static int __init mt6359vcore_init(void)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6359vcore_dir = NULL;
mtktspmic_info("[%s]\n", __func__);
err = mt6359vcore_register_cooler();
if (err)
return err;
mt6359vcore_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6359vcore_dir) {
mtktspmic_info(
"[%s]: mkdir /proc/driver/thermal failed\n", __func__);
} else {
entry =
proc_create("tz6359vcore", 664, mt6359vcore_dir,
&mt6359vcore_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6359vcore", mt6359vcore_start_thermal_timer,
mt6359vcore_cancel_thermal_timer);
return 0;
}
static void __exit mt6359vcore_exit(void)
{
mtktspmic_info("[%s]\n", __func__);
mt6359vcore_unregister_thermal();
mt6359vcore_unregister_cooler();
mtkTTimer_unregister("mt6359vcore");
}
module_init(mt6359vcore_init);
module_exit(mt6359vcore_exit);

606
drivers/misc/mediatek/thermal/mt6873/src/mtk_ts_6359vgpu.c
View File

@@ -1,606 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int isTimerCancelled;
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2 && curr_temp < polling_trip_temp1,
use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 150000, 110000, 100000, 90000, 80000,
70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = { 0 };
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long int mt6359vgpu_cur_temp;
/*
*static long int mt6359vgpu_start_temp;
*static long int mt6359vgpu_end_temp;
*/
/*=============================================================*/
static int mt6359vgpu_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6359vgpu_get_hw_temp();
mt6359vgpu_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6359vgpu_bind
(struct thermal_zone_device *thermal, struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info(
"[%s] error binding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] binding OK, %d\n", __func__, table_val);
return 0;
}
static int mt6359vgpu_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info(
"[%s] error unbinding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] unbinding OK\n", __func__);
return 0;
}
static int mt6359vgpu_get_mode
(struct thermal_zone_device *thermal, enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6359vgpu_set_mode
(struct thermal_zone_device *thermal, enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6359vgpu_get_trip_type
(struct thermal_zone_device *thermal, int trip, enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6359vgpu_get_trip_temp
(struct thermal_zone_device *thermal, int trip, int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6359vgpu_get_crit_temp
(struct thermal_zone_device *thermal, int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6359vgpu_dev_ops = {
.bind = mt6359vgpu_bind,
.unbind = mt6359vgpu_unbind,
.get_temp = mt6359vgpu_get_temp,
.get_mode = mt6359vgpu_get_mode,
.set_mode = mt6359vgpu_set_mode,
.get_trip_type = mt6359vgpu_get_trip_type,
.get_trip_temp = mt6359vgpu_get_trip_temp,
.get_crit_temp = mt6359vgpu_get_crit_temp,
};
static int mt6359vgpu_sysrst_get_max_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6359vgpu_sysrst_get_cur_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6359vgpu_sysrst_set_cur_state
(struct thermal_cooling_device *cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("mt6359vgpu OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
#if 0 /* temp marked off to check temperature correctness. */
*(unsigned int *)0x0 = 0xdead;
/* To trigger data abort to reset the system for thermal protection. */
#endif
}
return 0;
}
static struct thermal_cooling_device_ops mt6359vgpu_cooling_sysrst_ops = {
.get_max_state = mt6359vgpu_sysrst_get_max_state,
.get_cur_state = mt6359vgpu_sysrst_get_cur_state,
.set_cur_state = mt6359vgpu_sysrst_set_cur_state,
};
static int mt6359vgpu_read(struct seq_file *m, void *v)
{
seq_printf(m,
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
__func__, trip_temp[0], trip_temp[1], trip_temp[2],
trip_temp[3]);
seq_printf(m,
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8], trip_temp[9]);
seq_printf(m,
"g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2],
g_THERMAL_TRIP[3]);
seq_printf(m,
"g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6],
g_THERMAL_TRIP[7]);
seq_printf(m, "g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
seq_printf(m,
"cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m,
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s,time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6359vgpu_register_thermal(void);
static void mt6359vgpu_unregister_thermal(void);
static ssize_t mt6359vgpu_write
(struct file *file, const char __user *buffer, size_t count, loff_t *data)
{
int len = 0;
int i;
struct mt6359vgpu_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6359vgpu_data *ptr_mt6359vgpu_data;
ptr_mt6359vgpu_data =
kmalloc(sizeof(*ptr_mt6359vgpu_data), GFP_KERNEL);
if (ptr_mt6359vgpu_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6359vgpu_data->desc) - 1)) ?
count : (sizeof(ptr_mt6359vgpu_data->desc) - 1);
if (copy_from_user(ptr_mt6359vgpu_data->desc, buffer, len)) {
kfree(ptr_mt6359vgpu_data);
return 0;
}
ptr_mt6359vgpu_data->desc[len] = '\0';
if (sscanf
(ptr_mt6359vgpu_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6359vgpu_data->trip[0],
&ptr_mt6359vgpu_data->t_type[0],
ptr_mt6359vgpu_data->bind0,
&ptr_mt6359vgpu_data->trip[1],
&ptr_mt6359vgpu_data->t_type[1],
ptr_mt6359vgpu_data->bind1,
&ptr_mt6359vgpu_data->trip[2],
&ptr_mt6359vgpu_data->t_type[2],
ptr_mt6359vgpu_data->bind2,
&ptr_mt6359vgpu_data->trip[3],
&ptr_mt6359vgpu_data->t_type[3],
ptr_mt6359vgpu_data->bind3,
&ptr_mt6359vgpu_data->trip[4],
&ptr_mt6359vgpu_data->t_type[4],
ptr_mt6359vgpu_data->bind4,
&ptr_mt6359vgpu_data->trip[5],
&ptr_mt6359vgpu_data->t_type[5],
ptr_mt6359vgpu_data->bind5,
&ptr_mt6359vgpu_data->trip[6],
&ptr_mt6359vgpu_data->t_type[6],
ptr_mt6359vgpu_data->bind6,
&ptr_mt6359vgpu_data->trip[7],
&ptr_mt6359vgpu_data->t_type[7],
ptr_mt6359vgpu_data->bind7,
&ptr_mt6359vgpu_data->trip[8],
&ptr_mt6359vgpu_data->t_type[8],
ptr_mt6359vgpu_data->bind8,
&ptr_mt6359vgpu_data->trip[9],
&ptr_mt6359vgpu_data->t_type[9],
ptr_mt6359vgpu_data->bind9,
&ptr_mt6359vgpu_data->time_msec) == 32) {
down(&sem_mutex);
mtktspmic_dprintk(
"[%s] mt6359vgpu_unregister_thermal\n", __func__);
mt6359vgpu_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__,
DB_OPT_DEFAULT, "mt6359vgpu_write",
"Bad argument");
#endif
mtktspmic_dprintk(
"[%s] bad argument\n", __func__);
kfree(ptr_mt6359vgpu_data);
up(&sem_mutex);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6359vgpu_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] = g_bind4[0]
= g_bind5[0] = g_bind6[0] = g_bind7[0] = g_bind8[0] = g_bind9[0]
= '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6359vgpu_data->bind0[i];
g_bind1[i] = ptr_mt6359vgpu_data->bind1[i];
g_bind2[i] = ptr_mt6359vgpu_data->bind2[i];
g_bind3[i] = ptr_mt6359vgpu_data->bind3[i];
g_bind4[i] = ptr_mt6359vgpu_data->bind4[i];
g_bind5[i] = ptr_mt6359vgpu_data->bind5[i];
g_bind6[i] = ptr_mt6359vgpu_data->bind6[i];
g_bind7[i] = ptr_mt6359vgpu_data->bind7[i];
g_bind8[i] = ptr_mt6359vgpu_data->bind8[i];
g_bind9[i] = ptr_mt6359vgpu_data->bind9[i];
}
mtktspmic_dprintk(
"[%s] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
__func__, g_THERMAL_TRIP[0], g_THERMAL_TRIP[1],
g_THERMAL_TRIP[2]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4], g_THERMAL_TRIP[5],
g_THERMAL_TRIP[6]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
mtktspmic_dprintk(
"[%s] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
__func__, g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk(
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6359vgpu_data->trip[i];
interval = ptr_mt6359vgpu_data->time_msec / 1000;
mtktspmic_dprintk(
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
__func__, trip_temp[0], trip_temp[1], trip_temp[2],
trip_temp[3]);
mtktspmic_dprintk(
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8]);
mtktspmic_dprintk("trip_9_temp=%d,time_ms=%d\n",
trip_temp[9], interval * 1000);
mtktspmic_dprintk(
"[%s] mt6359vgpu_register_thermal\n", __func__);
mt6359vgpu_register_thermal();
up(&sem_mutex);
kfree(ptr_mt6359vgpu_data);
return count;
}
mtktspmic_dprintk("[%s] bad argument\n", __func__);
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6359vgpu_write", "Bad argument");
#endif
kfree(ptr_mt6359vgpu_data);
return -EINVAL;
}
static void mt6359vgpu_cancel_thermal_timer(void)
{
/* stop thermal framework polling when entering deep idle */
if (down_trylock(&sem_mutex))
return;
if (thz_dev) {
cancel_delayed_work(&(thz_dev->poll_queue));
isTimerCancelled = 1;
}
up(&sem_mutex);
}
static void mt6359vgpu_start_thermal_timer(void)
{
/* resume thermal framework polling when leaving deep idle */
if (!isTimerCancelled)
return;
isTimerCancelled = 0;
if (down_trylock(&sem_mutex))
return;
if (thz_dev != NULL && interval != 0)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue),
round_jiffies(msecs_to_jiffies(1000)));
up(&sem_mutex);
}
static int mt6359vgpu_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register(
"mt6359vgpu-sysrst", NULL,
&mt6359vgpu_cooling_sysrst_ops);
return 0;
}
static int mt6359vgpu_register_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register(
"mt6359vgpu", num_trip, NULL,
&mt6359vgpu_dev_ops, 0, 0, 0, interval * 1000);
return 0;
}
static void mt6359vgpu_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6359vgpu_unregister_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
if (thz_dev) {
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
}
}
static int mt6359vgpu_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6359vgpu_read, NULL);
}
static const struct file_operations mt6359vgpu_fops = {
.owner = THIS_MODULE,
.open = mt6359vgpu_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6359vgpu_write,
.release = single_release,
};
static int __init mt6359vgpu_init(void)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6359vgpu_dir = NULL;
mtktspmic_info("[%s]\n", __func__);
err = mt6359vgpu_register_cooler();
if (err)
return err;
mt6359vgpu_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6359vgpu_dir) {
mtktspmic_info("[%s]: mkdir /proc/driver/thermal failed\n",
__func__);
} else {
entry =
proc_create("tz6359vgpu", 664, mt6359vgpu_dir,
&mt6359vgpu_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6359vgpu", mt6359vgpu_start_thermal_timer,
mt6359vgpu_cancel_thermal_timer);
return 0;
}
static void __exit mt6359vgpu_exit(void)
{
mtktspmic_info("[%s]\n", __func__);
mt6359vgpu_unregister_thermal();
mt6359vgpu_unregister_cooler();
mtkTTimer_unregister("mt6359vgpu");
}
module_init(mt6359vgpu_init);
module_exit(mt6359vgpu_exit);

604
drivers/misc/mediatek/thermal/mt6873/src/mtk_ts_6359vproc.c
View File

@@ -1,604 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
#include <mt-plat/aee.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "mt-plat/mtk_thermal_monitor.h"
#include "mach/mtk_thermal.h"
#include "mtk_thermal_timer.h"
#include <mt-plat/upmu_common.h>
#include <tspmic_settings.h>
#include <linux/uidgid.h>
#include <linux/slab.h>
/*=============================================================
*Local variable definition
*=============================================================
*/
static kuid_t uid = KUIDT_INIT(0);
static kgid_t gid = KGIDT_INIT(1000);
static DEFINE_SEMAPHORE(sem_mutex);
static int isTimerCancelled;
/**
* If curr_temp >= polling_trip_temp1, use interval
* else if cur_temp >= polling_trip_temp2 && curr_temp < polling_trip_temp1,
* use interval*polling_factor1
* else, use interval*polling_factor2
*/
static int polling_trip_temp1 = 40000;
static int polling_trip_temp2 = 20000;
static int polling_factor1 = 5000;
static int polling_factor2 = 10000;
static unsigned int interval = 1; /* seconds, 0 : no auto polling */
static unsigned int trip_temp[10] = { 150000, 110000, 100000, 90000, 80000,
70000, 65000, 60000, 55000, 50000 };
static unsigned int cl_dev_sysrst_state;
static struct thermal_zone_device *thz_dev;
static struct thermal_cooling_device *cl_dev_sysrst;
static int kernelmode;
static int g_THERMAL_TRIP[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
static int num_trip = 1;
static char g_bind0[20] = { 0 };
static char g_bind1[20] = { 0 };
static char g_bind2[20] = { 0 };
static char g_bind3[20] = { 0 };
static char g_bind4[20] = { 0 };
static char g_bind5[20] = { 0 };
static char g_bind6[20] = { 0 };
static char g_bind7[20] = { 0 };
static char g_bind8[20] = { 0 };
static char g_bind9[20] = { 0 };
static long int mt6359vproc_cur_temp;
/*
*static long int mt6359vproc_start_temp;
*static long int mt6359vproc_end_temp;
*/
/*=============================================================*/
static int mt6359vproc_get_temp(struct thermal_zone_device *thermal, int *t)
{
*t = mt6359vproc_get_hw_temp();
mt6359vproc_cur_temp = *t;
if ((int)*t >= polling_trip_temp1)
thermal->polling_delay = interval * 1000;
else if ((int)*t < polling_trip_temp2)
thermal->polling_delay = interval * polling_factor2;
else
thermal->polling_delay = interval * polling_factor1;
return 0;
}
static int mt6359vproc_bind
(struct thermal_zone_device *thermal, struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else {
return 0;
}
if (mtk_thermal_zone_bind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info(
"[%s] error binding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] binding OK, %d\n", __func__, table_val);
return 0;
}
static int mt6359vproc_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
int table_val = 0;
if (!strcmp(cdev->type, g_bind0)) {
table_val = 0;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind1)) {
table_val = 1;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind2)) {
table_val = 2;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind3)) {
table_val = 3;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind4)) {
table_val = 4;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind5)) {
table_val = 5;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind6)) {
table_val = 6;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind7)) {
table_val = 7;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind8)) {
table_val = 8;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else if (!strcmp(cdev->type, g_bind9)) {
table_val = 9;
mtktspmic_dprintk("[%s] %s\n", __func__, cdev->type);
} else
return 0;
if (thermal_zone_unbind_cooling_device(thermal, table_val, cdev)) {
mtktspmic_info(
"[%s] error unbinding cooling dev\n", __func__);
return -EINVAL;
}
mtktspmic_dprintk("[%s] unbinding OK\n", __func__);
return 0;
}
static int mt6359vproc_get_mode
(struct thermal_zone_device *thermal, enum thermal_device_mode *mode)
{
*mode = (kernelmode) ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED;
return 0;
}
static int mt6359vproc_set_mode
(struct thermal_zone_device *thermal, enum thermal_device_mode mode)
{
kernelmode = mode;
return 0;
}
static int mt6359vproc_get_trip_type
(struct thermal_zone_device *thermal, int trip, enum thermal_trip_type *type)
{
*type = g_THERMAL_TRIP[trip];
return 0;
}
static int mt6359vproc_get_trip_temp
(struct thermal_zone_device *thermal, int trip, int *temp)
{
*temp = trip_temp[trip];
return 0;
}
static int mt6359vproc_get_crit_temp
(struct thermal_zone_device *thermal, int *temperature)
{
*temperature = mtktspmic_TEMP_CRIT;
return 0;
}
/* bind callback functions to thermalzone */
static struct thermal_zone_device_ops mt6359vproc_dev_ops = {
.bind = mt6359vproc_bind,
.unbind = mt6359vproc_unbind,
.get_temp = mt6359vproc_get_temp,
.get_mode = mt6359vproc_get_mode,
.set_mode = mt6359vproc_set_mode,
.get_trip_type = mt6359vproc_get_trip_type,
.get_trip_temp = mt6359vproc_get_trip_temp,
.get_crit_temp = mt6359vproc_get_crit_temp,
};
static int mt6359vproc_sysrst_get_max_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = 1;
return 0;
}
static int mt6359vproc_sysrst_get_cur_state
(struct thermal_cooling_device *cdev, unsigned long *state)
{
*state = cl_dev_sysrst_state;
return 0;
}
static int mt6359vproc_sysrst_set_cur_state
(struct thermal_cooling_device *cdev, unsigned long state)
{
cl_dev_sysrst_state = state;
if (cl_dev_sysrst_state == 1) {
mtktspmic_info("mt6359vproc OT: reset, reset, reset!!!");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
mtktspmic_info("*****************************************");
mtktspmic_info("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
#if 0 /* temp marked off to check temperature correctness. */
*(unsigned int *)0x0 = 0xdead;
/* To trigger data abort to reset the system for thermal protection. */
#endif
}
return 0;
}
static struct thermal_cooling_device_ops mt6359vproc_cooling_sysrst_ops = {
.get_max_state = mt6359vproc_sysrst_get_max_state,
.get_cur_state = mt6359vproc_sysrst_get_cur_state,
.set_cur_state = mt6359vproc_sysrst_set_cur_state,
};
static int mt6359vproc_read(struct seq_file *m, void *v)
{
seq_printf(m,
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,\n",
__func__, trip_temp[0], trip_temp[1], trip_temp[2],
trip_temp[3]);
seq_printf(m,
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,trip_9_temp=%d,\n",
trip_temp[4], trip_temp[5], trip_temp[6],
trip_temp[7], trip_temp[8], trip_temp[9]);
seq_printf(m,
"g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,g_THERMAL_TRIP_3=%d,\n",
g_THERMAL_TRIP[0], g_THERMAL_TRIP[1], g_THERMAL_TRIP[2],
g_THERMAL_TRIP[3]);
seq_printf(m,
"g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,g_THERMAL_TRIP_7=%d,\n",
g_THERMAL_TRIP[4], g_THERMAL_TRIP[5], g_THERMAL_TRIP[6],
g_THERMAL_TRIP[7]);
seq_printf(m, "g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[8], g_THERMAL_TRIP[9]);
seq_printf(m,
"cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,\n",
g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
seq_printf(m,
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s,time_ms=%d\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9, interval * 1000);
return 0;
}
static int mt6359vproc_register_thermal(void);
static void mt6359vproc_unregister_thermal(void);
static ssize_t mt6359vproc_write
(struct file *file, const char __user *buffer, size_t count, loff_t *data)
{
int len = 0;
int i;
struct mt6359vproc_data {
int trip[10];
int t_type[10];
char bind0[20], bind1[20], bind2[20], bind3[20], bind4[20];
char bind5[20], bind6[20], bind7[20], bind8[20], bind9[20];
int time_msec;
char desc[512];
};
struct mt6359vproc_data *ptr_mt6359vproc_data;
ptr_mt6359vproc_data =
kmalloc(sizeof(*ptr_mt6359vproc_data), GFP_KERNEL);
if (ptr_mt6359vproc_data == NULL)
return -ENOMEM;
len = (count < (sizeof(ptr_mt6359vproc_data->desc) - 1)) ?
count : (sizeof(ptr_mt6359vproc_data->desc) - 1);
if (copy_from_user(ptr_mt6359vproc_data->desc, buffer, len)) {
kfree(ptr_mt6359vproc_data);
return 0;
}
ptr_mt6359vproc_data->desc[len] = '\0';
if (sscanf
(ptr_mt6359vproc_data->desc,
"%d %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d %d %19s %d",
&num_trip,
&ptr_mt6359vproc_data->trip[0],
&ptr_mt6359vproc_data->t_type[0],
ptr_mt6359vproc_data->bind0,
&ptr_mt6359vproc_data->trip[1],
&ptr_mt6359vproc_data->t_type[1],
ptr_mt6359vproc_data->bind1,
&ptr_mt6359vproc_data->trip[2],
&ptr_mt6359vproc_data->t_type[2],
ptr_mt6359vproc_data->bind2,
&ptr_mt6359vproc_data->trip[3],
&ptr_mt6359vproc_data->t_type[3],
ptr_mt6359vproc_data->bind3,
&ptr_mt6359vproc_data->trip[4],
&ptr_mt6359vproc_data->t_type[4],
ptr_mt6359vproc_data->bind4,
&ptr_mt6359vproc_data->trip[5],
&ptr_mt6359vproc_data->t_type[5],
ptr_mt6359vproc_data->bind5,
&ptr_mt6359vproc_data->trip[6],
&ptr_mt6359vproc_data->t_type[6],
ptr_mt6359vproc_data->bind6,
&ptr_mt6359vproc_data->trip[7],
&ptr_mt6359vproc_data->t_type[7],
ptr_mt6359vproc_data->bind7,
&ptr_mt6359vproc_data->trip[8],
&ptr_mt6359vproc_data->t_type[8],
ptr_mt6359vproc_data->bind8,
&ptr_mt6359vproc_data->trip[9],
&ptr_mt6359vproc_data->t_type[9],
ptr_mt6359vproc_data->bind9,
&ptr_mt6359vproc_data->time_msec) == 32) {
down(&sem_mutex);
mtktspmic_dprintk("[%s] mt6359vproc_unregister_thermal\n",
__func__);
mt6359vproc_unregister_thermal();
if (num_trip < 0 || num_trip > 10) {
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__,
DB_OPT_DEFAULT, "mt6359vproc_write",
"Bad argument");
#endif
mtktspmic_dprintk("[%s] bad argument\n", __func__);
kfree(ptr_mt6359vproc_data);
up(&sem_mutex);
return -EINVAL;
}
for (i = 0; i < num_trip; i++)
g_THERMAL_TRIP[i] = ptr_mt6359vproc_data->t_type[i];
g_bind0[0] = g_bind1[0] = g_bind2[0] = g_bind3[0] = g_bind4[0]
= g_bind5[0] = g_bind6[0] = g_bind7[0] = g_bind8[0] = g_bind9[0]
= '\0';
for (i = 0; i < 20; i++) {
g_bind0[i] = ptr_mt6359vproc_data->bind0[i];
g_bind1[i] = ptr_mt6359vproc_data->bind1[i];
g_bind2[i] = ptr_mt6359vproc_data->bind2[i];
g_bind3[i] = ptr_mt6359vproc_data->bind3[i];
g_bind4[i] = ptr_mt6359vproc_data->bind4[i];
g_bind5[i] = ptr_mt6359vproc_data->bind5[i];
g_bind6[i] = ptr_mt6359vproc_data->bind6[i];
g_bind7[i] = ptr_mt6359vproc_data->bind7[i];
g_bind8[i] = ptr_mt6359vproc_data->bind8[i];
g_bind9[i] = ptr_mt6359vproc_data->bind9[i];
}
mtktspmic_dprintk(
"[%s] g_THERMAL_TRIP_0=%d,g_THERMAL_TRIP_1=%d,g_THERMAL_TRIP_2=%d,",
__func__, g_THERMAL_TRIP[0], g_THERMAL_TRIP[1],
g_THERMAL_TRIP[2]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_3=%d,g_THERMAL_TRIP_4=%d,g_THERMAL_TRIP_5=%d,g_THERMAL_TRIP_6=%d,",
g_THERMAL_TRIP[3], g_THERMAL_TRIP[4], g_THERMAL_TRIP[5],
g_THERMAL_TRIP[6]);
mtktspmic_dprintk(
"g_THERMAL_TRIP_7=%d,g_THERMAL_TRIP_8=%d,g_THERMAL_TRIP_9=%d,\n",
g_THERMAL_TRIP[7], g_THERMAL_TRIP[8],
g_THERMAL_TRIP[9]);
mtktspmic_dprintk(
"[%s] cooldev0=%s,cooldev1=%s,cooldev2=%s,cooldev3=%s,cooldev4=%s,",
__func__, g_bind0, g_bind1, g_bind2, g_bind3, g_bind4);
mtktspmic_dprintk(
"cooldev5=%s,cooldev6=%s,cooldev7=%s,cooldev8=%s,cooldev9=%s\n",
g_bind5, g_bind6, g_bind7, g_bind8, g_bind9);
for (i = 0; i < num_trip; i++)
trip_temp[i] = ptr_mt6359vproc_data->trip[i];
interval = ptr_mt6359vproc_data->time_msec / 1000;
mtktspmic_dprintk(
"[%s] trip_0_temp=%d,trip_1_temp=%d,trip_2_temp=%d,trip_3_temp=%d,",
__func__, trip_temp[0], trip_temp[1], trip_temp[2],
trip_temp[3]);
mtktspmic_dprintk(
"trip_4_temp=%d,trip_5_temp=%d,trip_6_temp=%d,trip_7_temp=%d,trip_8_temp=%d,",
trip_temp[4], trip_temp[5], trip_temp[6], trip_temp[7],
trip_temp[8]);
mtktspmic_dprintk("trip_9_temp=%d,time_ms=%d\n",
trip_temp[9], interval * 1000);
mtktspmic_dprintk("[%s] mt6359vproc_register_thermal\n",
__func__);
mt6359vproc_register_thermal();
up(&sem_mutex);
kfree(ptr_mt6359vproc_data);
return count;
}
mtktspmic_dprintk("[%s] bad argument\n", __func__);
#ifdef CONFIG_MTK_AEE_FEATURE
aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT,
"mt6359vproc_write", "Bad argument");
#endif
kfree(ptr_mt6359vproc_data);
return -EINVAL;
}
static void mt6359vproc_cancel_thermal_timer(void)
{
/* stop thermal framework polling when entering deep idle */
if (down_trylock(&sem_mutex))
return;
if (thz_dev) {
cancel_delayed_work(&(thz_dev->poll_queue));
isTimerCancelled = 1;
}
up(&sem_mutex);
}
static void mt6359vproc_start_thermal_timer(void)
{
/* resume thermal framework polling when leaving deep idle */
if (!isTimerCancelled)
return;
isTimerCancelled = 0;
if (down_trylock(&sem_mutex))
return;
if (thz_dev != NULL && interval != 0)
mod_delayed_work(system_freezable_power_efficient_wq,
&(thz_dev->poll_queue),
round_jiffies(msecs_to_jiffies(1000)));
up(&sem_mutex);
}
static int mt6359vproc_register_cooler(void)
{
cl_dev_sysrst = mtk_thermal_cooling_device_register(
"mt6359vproc-sysrst", NULL,
&mt6359vproc_cooling_sysrst_ops);
return 0;
}
static int mt6359vproc_register_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
/* trips : trip 0~2 */
thz_dev = mtk_thermal_zone_device_register(
"mt6359vproc", num_trip, NULL,
&mt6359vproc_dev_ops, 0, 0, 0, interval * 1000);
return 0;
}
static void mt6359vproc_unregister_cooler(void)
{
if (cl_dev_sysrst) {
mtk_thermal_cooling_device_unregister(cl_dev_sysrst);
cl_dev_sysrst = NULL;
}
}
static void mt6359vproc_unregister_thermal(void)
{
mtktspmic_dprintk("[%s]\n", __func__);
if (thz_dev) {
mtk_thermal_zone_device_unregister(thz_dev);
thz_dev = NULL;
}
}
static int mt6359vproc_open(struct inode *inode, struct file *file)
{
return single_open(file, mt6359vproc_read, NULL);
}
static const struct file_operations mt6359vproc_fops = {
.owner = THIS_MODULE,
.open = mt6359vproc_open,
.read = seq_read,
.llseek = seq_lseek,
.write = mt6359vproc_write,
.release = single_release,
};
static int __init mt6359vproc_init(void)
{
int err = 0;
struct proc_dir_entry *entry = NULL;
struct proc_dir_entry *mt6359vproc_dir = NULL;
mtktspmic_info("[%s]\n", __func__);
err = mt6359vproc_register_cooler();
if (err)
return err;
mt6359vproc_dir = mtk_thermal_get_proc_drv_therm_dir_entry();
if (!mt6359vproc_dir) {
mtktspmic_info("[%s]: mkdir /proc/driver/thermal failed\n",
__func__);
} else {
entry =
proc_create("tz6359vproc", 664, mt6359vproc_dir,
&mt6359vproc_fops);
if (entry)
proc_set_user(entry, uid, gid);
}
mtkTTimer_register("mt6359vproc", mt6359vproc_start_thermal_timer,
mt6359vproc_cancel_thermal_timer);
return 0;
}
static void __exit mt6359vproc_exit(void)
{
mtktspmic_info("[%s]\n", __func__);
mt6359vproc_unregister_thermal();
mt6359vproc_unregister_cooler();
mtkTTimer_unregister("mt6359vproc");
}
module_init(mt6359vproc_init);
module_exit(mt6359vproc_exit);

14
drivers/misc/mediatek/thermal/mt6877/Makefile
View File

@@ -1,14 +0,0 @@
#
# Copyright (C) 2018 MediaTek Inc.
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
obj-y += src/

71
drivers/misc/mediatek/thermal/mt6877/inc/clatm_initcfg.h
View File

@@ -1,71 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __CLATM_INITCFG_H__
#define __CLATM_INITCFG_H__
#define CLATM_SET_INIT_CFG (1)
#define CLATM_INIT_CFG_0_TARGET_TJ (75000)
#define CLATM_INIT_CFG_0_EXIT_POINT (10000)
#define CLATM_INIT_CFG_0_FIRST_STEP (3960)
#define CLATM_INIT_CFG_0_THETA_RISE (2)
#define CLATM_INIT_CFG_0_THETA_FALL (8)
#define CLATM_INIT_CFG_0_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_0_MIN_CPU_PWR (300)
#define CLATM_INIT_CFG_0_MAX_CPU_PWR (3960)
#define CLATM_INIT_CFG_0_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_0_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_1_TARGET_TJ (65000)
#define CLATM_INIT_CFG_1_EXIT_POINT (10000)
#define CLATM_INIT_CFG_1_FIRST_STEP (3000)
#define CLATM_INIT_CFG_1_THETA_RISE (2)
#define CLATM_INIT_CFG_1_THETA_FALL (8)
#define CLATM_INIT_CFG_1_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_1_MIN_CPU_PWR (300)
#define CLATM_INIT_CFG_1_MAX_CPU_PWR (3000)
#define CLATM_INIT_CFG_1_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_1_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_2_TARGET_TJ (75000)
#define CLATM_INIT_CFG_2_EXIT_POINT (10000)
#define CLATM_INIT_CFG_2_FIRST_STEP (3960)
#define CLATM_INIT_CFG_2_THETA_RISE (2)
#define CLATM_INIT_CFG_2_THETA_FALL (8)
#define CLATM_INIT_CFG_2_MIN_BUDGET_CHG (1)
#define CLATM_INIT_CFG_2_MIN_CPU_PWR (600)
#define CLATM_INIT_CFG_2_MAX_CPU_PWR (3960)
#define CLATM_INIT_CFG_2_MIN_GPU_PWR (800)
#define CLATM_INIT_CFG_2_MAX_GPU_PWR (2000)
#define CLATM_INIT_CFG_ACTIVE_ATM_COOLER (0)
#define CLATM_INIT_CFG_CATM (0)
#define CLATM_INIT_CFG_PHPB_CPU_TT (10)
#define CLATM_INIT_CFG_PHPB_CPU_TP (50)
#define CLATM_INIT_CFG_PHPB_GPU_TT (80)
#define CLATM_INIT_CFG_PHPB_GPU_TP (80)
#define CLATM_INIT_HRTIMER_POLLING_DELAY (50)
#define CLATM_USE_MIN_CPU_OPP (1)
#define CLATM_CONFIGURABLE_TIMER
#define POLLING_TRIP_TEMP0 55000
#define POLLING_TRIP_TEMP1 45000
#define POLLING_TRIP_TEMP2 40000
#define POLLING_FACTOR0 10
#define POLLING_FACTOR1 2
#define POLLING_FACTOR2 4
#endif /* __CLATM_INITCFG_H__ */

Some files were not shown because too many files have changed in this diff Show More