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gpu: Import Xiaomi Changes

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Signed-off-by: claxten10 <claxten10@gmail.com>
This commit is contained in:
claxten10
2024-11-09 15:08:11 +00:00
committed by nisel
parent 044486a957
commit d3428aa37f
136 changed files with 4280 additions and 34442 deletions
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3
drivers/gpu/drm/Makefile
View File

@@ -18,7 +18,8 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \
drm_encoder.o drm_mode_object.o drm_property.o \
drm_plane.o drm_color_mgmt.o drm_print.o \
drm_dumb_buffers.o drm_mode_config.o drm_vblank.o \
drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o
drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o \
drm_notifier_odm.o
drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
drm-$(CONFIG_DRM_VM) += drm_vm.o

56
drivers/gpu/drm/drm_notifier_odm.c Normal file
View File

@@ -0,0 +1,56 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/notifier.h>
static BLOCKING_NOTIFIER_HEAD(odm_drm_notifier_list);
/**
* drm_register_client - register a client notifier
* @nb: notifier block to callback on events
*
* This function registers a notifier callback function
* to msm_drm_notifier_list, which would be called when
* received unblank/power down event.
*/
int drm_register_client(struct notifier_block *nb)
{
return blocking_notifier_chain_register(&odm_drm_notifier_list, nb);
}
EXPORT_SYMBOL(drm_register_client);
/**
* drm_unregister_client - unregister a client notifier
* @nb: notifier block to callback on events
*
* This function unregisters the callback function from
* msm_drm_notifier_list.
*/
int drm_unregister_client(struct notifier_block *nb)
{
return blocking_notifier_chain_unregister(&odm_drm_notifier_list, nb);
}
EXPORT_SYMBOL(drm_unregister_client);
/**
* drm_notifier_call_chain - notify clients of drm_events
* @val: event MSM_DRM_EARLY_EVENT_BLANK or MSM_DRM_EVENT_BLANK
* @v: notifier data, inculde display id and display blank
* event(unblank or power down).
*/
int drm_notifier_call_chain(unsigned long val, void *v)
{
return blocking_notifier_call_chain(&odm_drm_notifier_list, val, v);
}
EXPORT_SYMBOL(drm_notifier_call_chain);

116
drivers/gpu/drm/drm_sysfs.c
View File

@@ -20,6 +20,7 @@
#include <drm/drm_sysfs.h>
#include <drm/drmP.h>
#include <drm/drm_connector.h>
#include "drm_internal.h"
#define to_drm_minor(d) dev_get_drvdata(d)
@@ -229,16 +230,127 @@ static ssize_t modes_show(struct device *device,
return written;
}
static ssize_t panel_event_show(struct device *device,
struct device_attribute *attr,
char *buf)
{
ssize_t ret = 0;
struct drm_connector *connector = to_drm_connector(device);
if (!connector) {
pr_info("%s-%d connector is NULL \r\n",__func__, __LINE__);
return ret;
}
return snprintf(buf, PAGE_SIZE, "%d\n", connector->panel_event);
}
extern ssize_t dsi_display_get_panel_info(struct drm_connector *connector, char *buf);
static ssize_t panel_info_show(struct device *device,
struct device_attribute *attr,
char *buf)
{
struct drm_connector *connector = to_drm_connector(device);
if (!connector) {
pr_err("%s, the connector is null\n", __func__);
return 0;
}
return dsi_display_get_panel_info(connector, buf);
}
extern ssize_t lcm_mipi_reg_write(char *buf, size_t count);
extern ssize_t lcm_mipi_reg_read(char *buf);
static ssize_t mipi_reg_show(struct device *device,
struct device_attribute *attr,
char *buf)
{
pr_info("%s, k7s project \n", __func__);
return lcm_mipi_reg_read(buf);
}
static ssize_t mipi_reg_store(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
int rc = 0;
pr_info("%s, k7s project \n", __func__);
rc = lcm_mipi_reg_write((char *)buf, count);
return rc;
}
static atomic64_t g_param = ATOMIC64_INIT(0);
extern ssize_t dsi_panel_set_disp_param(struct drm_connector* connector, u32 cmd);
ssize_t mi_dsi_display_set_disp_param(struct drm_connector *connector,
u32 param_type)
{
int ret = 0;
if (!connector) {
pr_err("Invalid display ptr\n");
return -EINVAL;
}
atomic64_set(&g_param, param_type);
ret = dsi_panel_set_disp_param(connector, param_type);
return ret;
}
ssize_t mi_dsi_display_get_disp_param(struct drm_connector *connector,
char *buf)
{
u32 param = (u32)atomic64_read(&g_param);
return snprintf(buf, PAGE_SIZE, "0x%08X\n", param);
}
ssize_t mi_drm_sysfs_set_disp_param(struct drm_connector *connector,
u32 param_type)
{
int ret = 0;
ret = mi_dsi_display_set_disp_param(connector, param_type);
return ret;
}
ssize_t mi_drm_sysfs_get_disp_param(struct drm_connector *connector,
char *buf)
{
return mi_dsi_display_get_disp_param(connector, buf);
}
static ssize_t disp_param_store(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
ssize_t ret = 0;
int32_t param;
struct drm_connector *connector = to_drm_connector(device);
if (!connector) {
pr_info("%s-%d connector is NULL \r\n",__func__, __LINE__);
return ret;
}
sscanf(buf, "0x%x", &param);
ret = mi_drm_sysfs_set_disp_param(connector, param);
return count;
}
static ssize_t disp_param_show(struct device *device,
struct device_attribute *attr,
char *buf)
{
ssize_t ret = 0;
struct drm_connector *connector = to_drm_connector(device);
if (!connector) {
pr_info("%s-%d connector is NULL \r\n",__func__, __LINE__);
return ret;
}
return mi_drm_sysfs_get_disp_param(connector, buf);
}
static DEVICE_ATTR_RW(status);
static DEVICE_ATTR_RO(enabled);
static DEVICE_ATTR_RO(dpms);
static DEVICE_ATTR_RO(modes);
static DEVICE_ATTR_RO(panel_event);
static DEVICE_ATTR_RO(panel_info);
static DEVICE_ATTR_RW(mipi_reg);
static DEVICE_ATTR_RW(disp_param);
static struct attribute *connector_dev_attrs[] = {
&dev_attr_status.attr,
&dev_attr_enabled.attr,
&dev_attr_dpms.attr,
&dev_attr_modes.attr,
&dev_attr_panel_info.attr,
&dev_attr_mipi_reg.attr,
&dev_attr_disp_param.attr,
&dev_attr_panel_event.attr,
NULL
};
@@ -383,7 +495,7 @@ int drm_class_device_register(struct device *dev)
return -ENOENT;
dev->class = drm_class;
return device_register(dev);
return device_register(dev);
}
EXPORT_SYMBOL_GPL(drm_class_device_register);

1
drivers/gpu/drm/mediatek/Makefile
View File

@@ -42,6 +42,7 @@ mediatek-drm-y := mtk_drm_drv.o \
mtk_drm_arr.o \
mtk_disp_merge.o \
mtk_dmdp_aal.o \
mi_disp_esd_check.o \
mtk_fbconfig_kdebug.o
ifneq ($(CONFIG_MTK_CMDQ_MBOX), y)
mediatek-drm-y += mtk_cmdq_dummy.o

400
drivers/gpu/drm/mediatek/mi_disp_esd_check.c Normal file
View File

@@ -0,0 +1,400 @@
/*
* Copyright (C) 2019 MediaTek Inc.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/kthread.h>
#include <linux/types.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <linux/sched/clock.h>
#include <uapi/linux/sched/types.h>
#include <drm/drmP.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "../../../../kernel/irq/internals.h"
#include "mtk_drm_drv.h"
#include "mtk_drm_ddp_comp.h"
#include "mtk_drm_crtc.h"
#include "mtk_drm_helper.h"
#include "mtk_drm_assert.h"
#include "mtk_drm_mmp.h"
#include "mtk_drm_fbdev.h"
#include "mtk_drm_trace.h"
//#include "mi_disp_feature.h"
#include "mtk_disp_recovery.h"
#define ESD_CHECK_IRQ_PERIOD 10 /* ms */
/* pinctrl implementation */
static long _set_state(struct drm_crtc *crtc, const char *name)
{
#ifndef CONFIG_FPGA_EARLY_PORTING
struct mtk_drm_private *priv = crtc->dev->dev_private;
struct pinctrl_state *pState = 0;
long ret = 0;
/* TODO: race condition issue for pctrl handle */
/* SO Far _set_state() only process once */
if (!priv->pctrl) {
DDPPR_ERR("this pctrl is null\n");
return -1;
}
pState = pinctrl_lookup_state(priv->pctrl, name);
if (IS_ERR(pState)) {
DDPPR_ERR("lookup state '%s' failed\n", name);
ret = PTR_ERR(pState);
goto exit;
}
/* select state! */
pinctrl_select_state(priv->pctrl, pState);
exit:
return ret; /* Good! */
#else
return 0; /* Good! */
#endif
}
extern int set_panel_dead_flag(int value);
static int mi_drm_esd_recover(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_ddp_comp *output_comp;
int ret = 0;
unsigned int last_hrt_req= 0;
printk("hsc mi_drm_esd_recover\n");
set_panel_dead_flag(1);
CRTC_MMP_EVENT_START(drm_crtc_index(crtc), esd_recovery, 0, 0);
if (crtc->state && !crtc->state->active) {
DDPMSG("%s: crtc is inactive\n", __func__);
return 0;
}
CRTC_MMP_MARK(drm_crtc_index(crtc), esd_recovery, 0, 1);
output_comp = mtk_ddp_comp_request_output(mtk_crtc);
if (unlikely(!output_comp)) {
DDPPR_ERR("%s: invalid output comp\n", __func__);
ret = -EINVAL;
goto done;
}
mtk_drm_idlemgr_kick(__func__, &mtk_crtc->base, 0);
mtk_ddp_comp_io_cmd(output_comp, NULL, CONNECTOR_PANEL_DISABLE, NULL);
mtk_drm_crtc_disable(crtc, true);
CRTC_MMP_MARK(drm_crtc_index(crtc), esd_recovery, 0, 2);
#ifdef MTK_FB_MMDVFS_SUPPORT
if (drm_crtc_index(crtc) == 0)
mtk_disp_set_hrt_bw(mtk_crtc,
mtk_crtc->qos_ctx->last_hrt_req);
last_hrt_req = mtk_crtc->qos_ctx->last_hrt_req;
#endif
mdelay(150);
mtk_drm_crtc_enable(crtc);
mtk_crtc->qos_ctx->last_hrt_req = last_hrt_req;
CRTC_MMP_MARK(drm_crtc_index(crtc), esd_recovery, 0, 3);
mtk_ddp_comp_io_cmd(output_comp, NULL, CONNECTOR_PANEL_ENABLE, NULL);
CRTC_MMP_MARK(drm_crtc_index(crtc), esd_recovery, 0, 4);
mtk_ddp_comp_io_cmd(output_comp, NULL, ESD_RESTORE_BACKLIGHT, NULL);
mtk_crtc_hw_block_ready(crtc);
if (mtk_crtc_is_frame_trigger_mode(crtc)) {
struct cmdq_pkt *cmdq_handle;
mtk_crtc_pkt_create(&cmdq_handle, &mtk_crtc->base,
mtk_crtc->gce_obj.client[CLIENT_CFG]);
cmdq_pkt_set_event(cmdq_handle,
mtk_crtc->gce_obj.event[EVENT_STREAM_DIRTY]);
cmdq_pkt_set_event(cmdq_handle,
mtk_crtc->gce_obj.event[EVENT_CABC_EOF]);
cmdq_pkt_set_event(cmdq_handle,
mtk_crtc->gce_obj.event[EVENT_ESD_EOF]);
cmdq_pkt_flush(cmdq_handle);
cmdq_pkt_destroy(cmdq_handle);
}
mtk_drm_idlemgr_kick(__func__, &mtk_crtc->base, 0);
CRTC_MMP_MARK(drm_crtc_index(crtc), esd_recovery, 0, 5);
done:
set_panel_dead_flag(0);
CRTC_MMP_EVENT_END(drm_crtc_index(crtc), esd_recovery, 0, ret);
return 0;
}
static irqreturn_t _mi_esd_check_err_flag_irq_handler(int irq, void *data)
{
struct mi_esd_ctx *mi_esd_ctx = (struct mi_esd_ctx *)data;
if (((mi_esd_ctx->err_flag_irq_flags & IRQF_TRIGGER_FALLING
|| mi_esd_ctx->err_flag_irq_flags & IRQF_TRIGGER_LOW)
&& gpio_get_value(mi_esd_ctx->err_flag_irq_gpio))
|| ((mi_esd_ctx->err_flag_irq_flags & IRQF_TRIGGER_RISING
|| mi_esd_ctx->err_flag_irq_flags & IRQF_TRIGGER_HIGH)
&& !gpio_get_value(mi_esd_ctx->err_flag_irq_gpio))) {
pr_info("[ESD] err flag pin level is normal\n");
return IRQ_HANDLED;
}
pr_info("%s: [ESD]panel_init: %d\n", __func__, mi_esd_ctx->panel_init);
if (mi_esd_ctx->panel_init) {
atomic_set(&mi_esd_ctx->err_flag_event, 1);
wake_up_interruptible(&mi_esd_ctx->err_flag_wq);
pr_info("[ESD]_esd_check_err_flag_irq_handler is comming\n");
}
else {
pr_info("[ESD]_esd_check_err_flag_irq_handler is comming, but ignore\n");
}
return IRQ_HANDLED;
}
static int mi_disp_request_err_flag(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_panel_ext *panel_ext;
struct mi_esd_ctx *mi_esd_ctx = mtk_crtc->mi_esd_ctx;
int ret = 0;
if (unlikely(!mi_esd_ctx)) {
DDPPR_ERR("%s:invalid ESD context\n", __func__);
return -EINVAL;
}
panel_ext = mtk_crtc->panel_ext;
DDPMSG("%s: err_flag_irq_gpio: %d, err_flag_irq_flags: %d",
__func__, panel_ext->params->err_flag_irq_gpio,
panel_ext->params->err_flag_irq_flags);
mi_esd_ctx->err_flag_irq_gpio = panel_ext->params->err_flag_irq_gpio;
mi_esd_ctx->err_flag_irq_flags = panel_ext->params->err_flag_irq_flags;
if (gpio_is_valid(mi_esd_ctx->err_flag_irq_gpio)) {
mi_esd_ctx->err_flag_irq = gpio_to_irq(mi_esd_ctx->err_flag_irq_gpio);
ret = gpio_request(mi_esd_ctx->err_flag_irq_gpio, "esd_err_irq_gpio");
if (ret)
DDPPR_ERR("Failed to request esd irq gpio %d, ret=%d\n",
mi_esd_ctx->err_flag_irq_gpio, ret);
else
gpio_direction_input(mi_esd_ctx->err_flag_irq_gpio);
} else {
DDPPR_ERR("err_flag_irq_gpio is invalid\n");
ret = -EINVAL;
}
if (mi_esd_ctx->err_flag_irq_gpio > 0) {
ret = request_threaded_irq(mi_esd_ctx->err_flag_irq,
NULL, _mi_esd_check_err_flag_irq_handler,
mi_esd_ctx->err_flag_irq_flags,
"esd_err_irq", mi_esd_ctx);
if (ret) {
DDPPR_ERR("display register esd irq failed\n");
} else {
DDPPR_ERR("display register esd irq success\n");
disable_irq(mi_esd_ctx->err_flag_irq);
}
}
_set_state(crtc, "err_flag_init");
return ret;
}
static int mi_esd_err_flag_irq_check_worker_kthread(void *data)
{
struct sched_param param = { .sched_priority = 87 };
struct drm_crtc *crtc = (struct drm_crtc *)data;
struct mtk_drm_private *private = crtc->dev->dev_private;
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mi_esd_ctx *mi_esd_ctx = mtk_crtc->mi_esd_ctx;
int ret = 0;
//u8 panel_dead = 0;
//struct disp_event event;
sched_setscheduler(current, SCHED_RR, &param);
//event.disp_id = MI_DISP_PRIMARY;
//event.type = MI_DISP_EVENT_PANEL_DEAD;
//event.length = sizeof(panel_dead);
pr_info("start ESD thread\n");
while (1) {
printk("hsc esd\n");
msleep(ESD_CHECK_IRQ_PERIOD); /* 10ms */
ret = wait_event_interruptible(mi_esd_ctx->err_flag_wq,
atomic_read(&mi_esd_ctx->err_flag_event));
if (ret < 0) {
DDPINFO("[ESD]check thread waked up accidently\n");
continue;
}
pr_info("ESD waked up\n");
DDPINFO("[ESD]check thread waked up successfully\n");
mutex_lock(&private->commit.lock);
DDP_MUTEX_LOCK(&mtk_crtc->lock, __func__, __LINE__);
/* 1.esd recovery */
//panel_dead = 1;
//mi_disp_feature_event_notify(&event, &panel_dead);
mi_drm_esd_recover(crtc);
//panel_dead = 0;
//mi_disp_feature_event_notify(&event, &panel_dead);
/* 2.clear atomic ext_te_event */
atomic_set(&mi_esd_ctx->err_flag_event, 0);
DDP_MUTEX_UNLOCK(&mtk_crtc->lock, __func__, __LINE__);
mutex_unlock(&private->commit.lock);
pr_info("[ESD]check thread is over\n");
/* 3.other check & recovery */
if (kthread_should_stop())
break;
}
return 0;
}
static void mi_disp_esd_err_flag_irq_init(struct mi_esd_ctx *mi_esd_ctx, struct drm_crtc *crtc)
{
mi_esd_ctx->disp_esd_irq_chk_task = kthread_create(
mi_esd_err_flag_irq_check_worker_kthread, crtc, "err_flag_chk");
init_waitqueue_head(&mi_esd_ctx->err_flag_wq);
atomic_set(&mi_esd_ctx->err_flag_event, 0);
wake_up_process(mi_esd_ctx->disp_esd_irq_chk_task);
}
int mi_disp_esd_irq_ctrl(struct mi_esd_ctx *mi_esd_ctx,
bool enable)
{
struct irq_desc *desc;
if (gpio_is_valid(mi_esd_ctx->err_flag_irq_gpio)) {
if (mi_esd_ctx->err_flag_irq) {
if (enable) {
if (!mi_esd_ctx->err_flag_enabled) {
desc = irq_to_desc(mi_esd_ctx->err_flag_irq);
if (!irq_settings_is_level(desc)) {
pr_info("clear pending esd irq\n");
desc->istate &= ~IRQS_PENDING;
}
enable_irq_wake(mi_esd_ctx->err_flag_irq);
enable_irq(mi_esd_ctx->err_flag_irq);
mi_esd_ctx->err_flag_enabled = true;
pr_info("panel esd irq is enable\n");
}
} else {
if (mi_esd_ctx->err_flag_enabled) {
disable_irq_wake(mi_esd_ctx->err_flag_irq);
disable_irq_nosync(mi_esd_ctx->err_flag_irq);
mi_esd_ctx->err_flag_enabled = false;
pr_info("panel esd irq is disable\n");
}
}
}
} else {
pr_info("panel esd irq gpio invalid\n");
}
return 0;
}
void mi_disp_err_flag_esd_check_switch(struct drm_crtc *crtc, bool enable)
{
struct mtk_drm_private *priv = crtc->dev->dev_private;
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mi_esd_ctx *mi_esd_ctx = mtk_crtc->mi_esd_ctx;
if (!mtk_drm_helper_get_opt(priv->helper_opt,
MTK_DRM_OPT_ESD_CHECK_RECOVERY))
return;
if (unlikely(!mi_esd_ctx)) {
DDPINFO("%s:invalid ESD context, crtc id:%d\n",
__func__, drm_crtc_index(crtc));
return;
}
if (enable) {
mi_disp_esd_irq_ctrl(mi_esd_ctx, true);
} else {
mi_disp_esd_irq_ctrl(mi_esd_ctx, false);
}
}
void mi_disp_esd_chk_deinit(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mi_esd_ctx *mi_esd_ctx = mtk_crtc->mi_esd_ctx;
if (unlikely(!mi_esd_ctx)) {
DDPPR_ERR("%s:invalid ESD context\n", __func__);
return;
}
/* Stop MI ESD kthread */
kthread_stop(mi_esd_ctx->disp_esd_irq_chk_task);
kfree(mi_esd_ctx);
}
static inline int mi_need_esd_check(struct mtk_panel_ext *panel_ext)
{
int ret = 0;
if (panel_ext->params->mi_esd_check_enable == 1 &&
mtk_drm_lcm_is_connect()) {
ret = 1;
}
return ret;
}
void mi_disp_esd_chk_init(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mi_esd_ctx *mi_esd_ctx;
if (drm_crtc_index(&mtk_crtc->base) != 0)
return;
if (!mi_need_esd_check(mtk_crtc->panel_ext))
return;
mi_esd_ctx = kzalloc(sizeof(*mi_esd_ctx), GFP_KERNEL);
if (!mi_esd_ctx) {
DDPPR_ERR("allocate MI ESD context failed!\n");
return;
}
mtk_crtc->mi_esd_ctx = mi_esd_ctx;
if(!mi_disp_request_err_flag(crtc)) {
mi_disp_esd_err_flag_irq_init(mi_esd_ctx, crtc);
} else {
DDPPR_ERR("%s: mi esd err flag gpio request failed\n", __func__);
kfree(mtk_crtc->mi_esd_ctx);
}
return;
}

28
drivers/gpu/drm/mediatek/mi_disp_esd_check.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* Copyright (c) 2021 Xiaomi Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MI_DISP_ESD_CHECK_H
#define _MI_DISP_ESD_CHECK_H
struct mi_esd_ctx {
struct task_struct *disp_esd_irq_chk_task;
wait_queue_head_t err_flag_wq;
atomic_t err_flag_event;
int err_flag_irq_gpio;
int err_flag_irq_flags;
int err_flag_irq;
bool err_flag_enabled;
bool panel_init;
};
void mi_disp_esd_chk_init(struct drm_crtc *crtc);
void mi_disp_esd_chk_deinit(struct drm_crtc *crtc);
void mi_disp_err_flag_esd_check_switch(struct drm_crtc *crtc, bool enable);
#endif

97
drivers/gpu/drm/mediatek/mi_disp_feature_id.h Normal file
View File

@@ -0,0 +1,97 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _DSI_MI_FEATURE_H_
#define _DSI_MI_FEATURE_H_
enum DISPPARAM_MODE {
DISPPARAM_WARM = 0x1,
DISPPARAM_DEFAULT = 0x2,
DISPPARAM_COLD = 0x3,
DISPPARAM_PAPERMODE8 = 0x5,
DISPPARAM_PAPERMODE1 = 0x6,
DISPPARAM_PAPERMODE2 = 0x7,
DISPPARAM_PAPERMODE3 = 0x8,
DISPPARAM_PAPERMODE4 = 0x9,
DISPPARAM_PAPERMODE5 = 0xA,
DISPPARAM_PAPERMODE6 = 0xB,
DISPPARAM_PAPERMODE7 = 0xC,
DISPPARAM_WHITEPOINT_XY = 0xE,
DISPPARAM_CE_ON = 0x10,
DISPPARAM_CE_OFF = 0xF0,
DISPPARAM_CABCUI_ON = 0x100,
DISPPARAM_CABCSTILL_ON = 0x200,
DISPPARAM_CABCMOVIE_ON = 0x300,
DISPPARAM_CABC_OFF = 0x400,
DISPPARAM_SKIN_CE_CABCUI_ON = 0x500,
DISPPARAM_SKIN_CE_CABCSTILL_ON = 0x600,
DISPPARAM_SKIN_CE_CABCMOVIE_ON = 0x700,
DISPPARAM_SKIN_CE_CABC_OFF = 0x800,
DISPPARAM_DIMMING_OFF = 0xE00,
DISPPARAM_DIMMING = 0xF00,
DISPPARAM_ACL_L1 = 0x1000,
DISPPARAM_ACL_L2 = 0x2000,
DISPPARAM_ACL_L3 = 0x3000,
DISPPARAM_ACL_OFF = 0xF000,
DISPPARAM_HBM_ON = 0x10000,
DISPPARAM_HBM_FOD_ON = 0x20000,
DISPPARAM_HBM_FOD2NORM = 0x30000,
DISPPARAM_DC_ON = 0x40000,
DISPPARAM_DC_OFF = 0x50000,
DISPPARAM_HBM_HDR_ON = 0x60000,
DISPPARAM_FOD_UNLOCK_SUCCESS = 0x70000,
DISPPARAM_FOD_UNLOCK_FAIL = 0x80000,
DISPPARAM_HBM_HDR_OFF = 0xD0000,
DISPPARAM_HBM_FOD_OFF = 0xE0000,
DISPPARAM_HBM_OFF = 0xF0000,
DISPPARAM_NORMALMODE1 = 0x100000,
DISPPARAM_P3 = 0x200000,
DISPPARAM_SRGB = 0x300000,
DISPPARAM_SKIN_CE = 0x400000,
DISPPARAM_SKIN_CE_OFF = 0x500000,
DISPPARAM_DOZE_BRIGHTNESS_HBM = 0x600000,
DISPPARAM_DOZE_BRIGHTNESS_LBM = 0x700000,
DISPPARAM_DOZE_OFF = 0x800000,
DISPPARAM_HBM_BACKLIGHT_RESEND = 0xA00000,
DISPPARAM_FOD_BACKLIGHT = 0xD00000,
DISPPARAM_CRC_P3_D65 = 0xE00000,
DISPPARAM_CRC_OFF = 0xF00000,
DISPPARAM_FOD_BACKLIGHT_ON = 0x1000000,
DISPPARAM_FOD_BACKLIGHT_OFF = 0x2000000,
DISPPARAM_ELVSS_DIMMING_ON = 0x3000000,
DISPPARAM_ELVSS_DIMMING_OFF = 0x4000000,
DISPPARAM_FLAT_MODE_ON = 0x5000000,
DISPPARAM_FLAT_MODE_OFF = 0x6000000,
DISPPARAM_DITHER_ON = 0x7000000,
DISPPARAM_DITHER_OFF = 0x8000000,
DISPPARAM_BACKLIGHT_SET = 0xC000000,
DISPPARAM_PANEL_ID_GET = 0xD000000,
DISPPARAM_DOZE_STATE = 0xE0000000,
DISPPARAM_DFPS_LEVEL1 = 0x10000000,
DISPPARAM_DFPS_LEVEL2 = 0x20000000,
DISPPARAM_DFPS_LEVEL3 = 0x30000000,
DISPPARAM_DFPS_LEVEL4 = 0x40000000,
DISPPARAM_DFPS_LEVEL5 = 0x50000000,
DISPPARAM_DFPS_LEVEL6 = 0x60000000,
};
#endif /* _DSI_MI_FEATURE_H_ */

2
drivers/gpu/drm/mediatek/mtk_disp_aal.c
View File

@@ -64,7 +64,7 @@ struct timeval start, end;
/* To enable debug log: */
/* # echo aal_dbg:1 > /sys/kernel/debug/dispsys */
int aal_dbg_en;
static int g_max_backlight = 1023;
static int g_max_backlight = 2047;
static DECLARE_WAIT_QUEUE_HEAD(g_aal_hist_wq);
static DEFINE_SPINLOCK(g_aal_clock_lock);

1
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
View File

@@ -1287,3 +1287,4 @@ void disp_ccorr_set_bypass(struct drm_crtc *crtc, int bypass)
ret = mtk_crtc_user_cmd(crtc, ccorr1_default_comp, BYPASS_CCORR, &bypass);
DDPFUNC("ret = %d", ret);
}

16
drivers/gpu/drm/mediatek/mtk_disp_recovery.c
View File

@@ -28,7 +28,7 @@
#include "mtk_drm_fbdev.h"
#include "mtk_drm_trace.h"
#include "mtk_dump.h"
#include "mi_disp_esd_check.h"
#ifdef CONFIG_MTK_MT6382_BDG
#include "mtk_disp_bdg.h"
#include "mtk_dsi.h"
@@ -36,7 +36,7 @@
#define ESD_TRY_CNT 5
#define ESD_CHECK_PERIOD 2000 /* ms */
static atomic_t panel_dead;
/* pinctrl implementation */
long _set_state(struct drm_crtc *crtc, const char *name)
{
@@ -488,7 +488,7 @@ done:
return 0;
}
bool esd_check_fail_open_backlight = false;
static int mtk_drm_esd_check_worker_kthread(void *data)
{
struct sched_param param = {.sched_priority = 87};
@@ -684,3 +684,13 @@ void mtk_disp_chk_recover_init(struct drm_crtc *crtc)
drm_crtc_index(&mtk_crtc->base) == 0)
mtk_disp_esd_chk_init(crtc);
}
int get_panel_dead_flag(void)
{
return atomic_read(&panel_dead);
}
EXPORT_SYMBOL(get_panel_dead_flag);
int set_panel_dead_flag(int value)
{
return atomic_set(&panel_dead, value);
}
EXPORT_SYMBOL(set_panel_dead_flag);

2
drivers/gpu/drm/mediatek/mtk_drm_crtc.c
View File

@@ -7525,7 +7525,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
mtk_drm_cwb_init(&mtk_crtc->base);
mtk_disp_chk_recover_init(&mtk_crtc->base);
mi_disp_esd_chk_init(&mtk_crtc->base);
mtk_drm_fake_vsync_init(&mtk_crtc->base);
#ifdef MTK_FB_MMDVFS_SUPPORT

3
drivers/gpu/drm/mediatek/mtk_drm_crtc.h
View File

@@ -22,7 +22,7 @@
#include "mtk_drm_ddp_addon.h"
#include <linux/pm_wakeup.h>
#include "mtk_disp_pmqos.h"
#include "mi_disp_esd_check.h"
#define MAX_CRTC 3
#define OVL_LAYER_NR 12L
@@ -664,6 +664,7 @@ struct mtk_drm_crtc {
wait_queue_head_t crtc_status_wq;
struct mtk_panel_ext *panel_ext;
struct mtk_drm_esd_ctx *esd_ctx;
struct mi_esd_ctx *mi_esd_ctx;
#ifdef CONFIG_MTK_ROUND_CORNER_SUPPORT
struct mtk_drm_gem_obj *round_corner_gem;
struct mtk_drm_gem_obj *round_corner_gem_l;

3
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
View File

@@ -211,6 +211,7 @@ enum mtk_ddp_io_cmd {
PMQOS_UPDATE_BW,
OVL_REPLACE_BOOTUP_MVA,
BACKUP_INFO_CMP,
ESD_RESTORE_BACKLIGHT,
LCM_RESET,
DSI_SET_BL,
DSI_SET_BL_AOD,
@@ -336,6 +337,8 @@ struct mtk_ddp_comp {
u32 qos_bw;
u32 fbdc_bw;
u32 hrt_bw;
struct mutex panel_lock;
};
static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp,

25
drivers/gpu/drm/mediatek/mtk_drm_drv.c
View File

@@ -70,6 +70,9 @@
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
atomic_t resume_pending;
wait_queue_head_t resume_wait_q;
static atomic_t top_isr_ref; /* irq power status protection */
static atomic_t top_clk_ref; /* top clk status protection*/
static spinlock_t top_clk_lock; /* power status protection*/
@@ -3975,6 +3978,20 @@ static int mtk_drm_remove(struct platform_device *pdev)
}
#ifdef CONFIG_PM_SLEEP
static int mtk_drm_sys_prepare(struct device *dev)
{
atomic_inc(&resume_pending);
return 0;
}
static void mtk_drm_sys_complete(struct device *dev)
{
atomic_set(&resume_pending, 0);
wake_up_all(&resume_wait_q);
return;
}
static int mtk_drm_sys_suspend(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
@@ -4017,8 +4034,12 @@ static int mtk_drm_sys_resume(struct device *dev)
}
#endif
static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
mtk_drm_sys_resume);
static const struct dev_pm_ops mtk_drm_pm_ops = {
.prepare = mtk_drm_sys_prepare,
.complete = mtk_drm_sys_complete,
.suspend = mtk_drm_sys_suspend,
.resume = mtk_drm_sys_resume,
};
static const struct of_device_id mtk_drm_of_ids[] = {
{.compatible = "mediatek,mt2701-mmsys",

4
drivers/gpu/drm/mediatek/mtk_drm_drv.h
View File

@@ -259,6 +259,10 @@ extern struct platform_driver mtk_lvds_driver;
extern struct platform_driver mtk_lvds_tx_driver;
extern struct platform_driver mtk_disp_dsc_driver;
extern struct lcm_fps_ctx_t lcm_fps_ctx[MAX_CRTC];
extern atomic_t resume_pending;
extern wait_queue_head_t resume_wait_q;
extern struct platform_driver mtk_disp_merge_driver;
#ifdef CONFIG_MTK_HDMI_SUPPORT
extern struct platform_driver mtk_dp_tx_driver;

921
drivers/gpu/drm/mediatek/mtk_dsi.c
View File

File diff suppressed because it is too large Load Diff

3
drivers/gpu/drm/mediatek/mtk_log.h
View File

@@ -46,7 +46,8 @@ int mtk_dprec_logger_pr(unsigned int type, char *fmt, ...);
#define DDPMSG(fmt, arg...) \
do { \
mtk_dprec_logger_pr(DPREC_LOGGER_DEBUG, fmt, ##arg); \
pr_info(pr_fmt(fmt), ##arg); \
if (g_mobile_log) \
pr_debug(pr_fmt(fmt), ##arg); \
} while (0)
#define DDPDUMP(fmt, arg...) \

19
drivers/gpu/drm/mediatek/mtk_panel_ext.h
View File

@@ -120,6 +120,10 @@ enum FPS_CHANGE_INDEX {
DYNFPS_DSI_MIPI_CLK = 4,
};
enum LCM_SEND_CMD_MODE {
LCM_SEND_IN_CMD = 0,
LCM_SEND_IN_VDO,
};
struct dsc_rc_range_parameters {
/**
* @range_min_qp: Min Quantization Parameters allowed for this range
@@ -218,6 +222,8 @@ struct dynamic_fps_params {
unsigned int vact_timing_fps;
unsigned int data_rate;
struct dfps_switch_cmd dfps_cmd_table[MAX_DYN_CMD_NUM];
enum LCM_SEND_CMD_MODE send_mode;
unsigned int send_cmd_need_delay;
};
struct mtk_panel_params {
@@ -264,6 +270,9 @@ struct mtk_panel_params {
//Settings for LFR Function:
unsigned int lfr_enable;
unsigned int lfr_minimum_fps;
int err_flag_irq_gpio;
int err_flag_irq_flags;
int mi_esd_check_enable;
};
struct mtk_panel_ext {
@@ -281,6 +290,8 @@ struct mtk_panel_ctx {
struct mtk_panel_funcs {
int (*set_backlight_cmdq)(void *dsi_drv, dcs_write_gce cb,
void *handle, unsigned int level);
int (*get_panel_info)(struct drm_panel *panel,char *buf);
int (*set_aod_light_mode)(void *dsi_drv, dcs_write_gce cb,
void *handle, unsigned int mode);
int (*set_backlight_grp_cmdq)(void *dsi_drv, dcs_grp_write_gce cb,
@@ -346,12 +357,18 @@ struct mtk_panel_funcs {
*/
unsigned long (*doze_get_mode_flags)(
struct drm_panel *panel, int aod_en);
void (*esd_restore_backlight)(struct drm_panel *panel);
int (*hbm_set_cmdq)(struct drm_panel *panel, void *dsi_drv,
dcs_write_gce cb, void *handle, bool en);
void (*hbm_get_state)(struct drm_panel *panel, bool *state);
void (*hbm_get_wait_state)(struct drm_panel *panel, bool *wait);
bool (*hbm_set_wait_state)(struct drm_panel *panel, bool wait);
int (*hbm_control)(struct drm_panel *panel, bool en);
int (*aod_control)(bool en);
int (*panel_set_crc_srgb)(struct drm_panel *panel);
int (*panel_set_crc_p3)(struct drm_panel *panel);
int (*panel_set_crc_off)(struct drm_panel *panel);
int (*k7s_dsi_poweron)(struct drm_panel *panel);
};
void mtk_panel_init(struct mtk_panel_ctx *ctx);

16
drivers/gpu/drm/panel/Kconfig
View File

@@ -327,6 +327,22 @@ config DRM_PANEL_TRULY_FT8756_VDO
and uses 24-bits RGB per pixel. It provides a MIPI DSI interface
to host.
config DRM_DSI_PANEL_K7S_38_0C_0A_VIDEO
tristate "Samsung 380C0A DSI video mode panel"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
help
Say Y here if you want to enable support for 380C0A.
config DRM_DSI_PANEL_K7S_38_0C_0B_VIDEO
tristate "Samsung 380C0A DSI video mode panel"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
help
Say Y here if you want to enable support for 380C0A.
config DRM_PANEL_TRULY_ILI9881H_VDO
tristate "TRULY HD+ vdo mode panel"
depends on OF

2
drivers/gpu/drm/panel/Makefile
View File

@@ -63,6 +63,8 @@ obj-$(CONFIG_DRM_PANEL_SC_NT36672C_VDO_120HZ) += panel-sc-nt36672c-vdo-120hz.o
obj-$(CONFIG_DRM_PANEL_SC_NT36672C_VDO_90HZ) += panel-sc-nt36672c-vdo-90hz.o
obj-$(CONFIG_DRM_PANEL_SC_NT36672C_VDO_60HZ) += panel-sc-nt36672c-vdo-60hz.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_S68FC01_VDO_AOD) += panel-samsung-s68fc01-vdo-aod.o
obj-$(CONFIG_DRM_DSI_PANEL_K7S_38_0C_0A_VIDEO) += dsi_panel_k7s_38_0c_0a_video.o
obj-$(CONFIG_DRM_DSI_PANEL_K7S_38_0C_0B_VIDEO) += dsi_panel_k7s_38_0c_0b_video.o
obj-$(CONFIG_DRM_PANEL_TRULY_FT8756_VDO) += panel-truly-ft8756-vdo.o
obj-$(CONFIG_DRM_PANEL_TRULY_NT35595_CMD) += panel-truly-nt35595-cmd.o
obj-$(CONFIG_DRM_PANEL_TRULY_NT35595_VDO) += panel-truly-nt35595-vdo.o

1226
drivers/gpu/drm/panel/dsi_panel_k7s_38_0c_0a_video.c Normal file
View File

File diff suppressed because it is too large Load Diff

1247
drivers/gpu/drm/panel/dsi_panel_k7s_38_0c_0b_video.c Normal file
View File

File diff suppressed because it is too large Load Diff

9
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c
View File

@@ -932,6 +932,15 @@ int kbase_mem_flags_change(struct kbase_context *kctx, u64 gpu_addr, unsigned in
if (kbase_va_region_is_no_user_free(kctx, reg))
goto out_unlock;
/* There is no use case to support MEM_FLAGS_CHANGE ioctl for allocations
* that have NO_USER_FREE flag set, to mark them as evictable/reclaimable.
* This would usually include JIT allocations, Tiler heap related allocations
* & GPU queue ringbuffer and none of them needs to be explicitly marked
* as evictable by Userspace.
*/
if (reg->flags & KBASE_REG_NO_USER_FREE)
goto out_unlock;
/* Is the region being transitioning between not needed and needed? */
prev_needed = (KBASE_REG_DONT_NEED & reg->flags) == KBASE_REG_DONT_NEED;
new_needed = (BASE_MEM_DONT_NEED & flags) == BASE_MEM_DONT_NEED;

39
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6873/Kbuild
View File

@@ -1,39 +0,0 @@
#
# (C) COPYRIGHT 2012-2013, 2016-2017, 2020 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU licence.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
# SPDX-License-Identifier: GPL-2.0
#
#
include $(src)/Kbuild-mtk-custom-env
mali_kbase-y += \
platform/$(MALI_PLATFORM_DIR)/mali_kbase_config_mt6873.o
ccflags-y += \
-I$(srctree)/drivers/misc/mediatek/base/power/include
ccflags-y += \
-I$(srctree)/drivers/gpu/mediatek
ifeq ($(CONFIG_MTK_TINYSYS_SSPM_SUPPORT), y)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/v2/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/$(CONFIG_MTK_PLATFORM)
endif
# /*set interval to 9600-10000us */
ccflags-y += -DDEFAULT_PM_POWEROFF_TICK_SHADER=25

263
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6873/mali_kbase_config_mt6873.c
View File

@@ -1,263 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <mali_kbase.h>
#include <mali_kbase_defs.h>
#include <mali_kbase_config.h>
#include "mali_kbase_config_platform.h"
#include "platform/mtk_platform_common.h"
#include "ged_dvfs.h"
#include "mtk_gpufreq.h"
#include "mtk_idle.h"
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
//#include <mtk_gpu_power_sspm_ipi.h>
#endif
#define MALI_TAG "[GPU/MALI]"
#define mali_pr_info(fmt, args...) pr_info(MALI_TAG"[INFO]"fmt, ##args)
#define mali_pr_debug(fmt, args...) pr_debug(MALI_TAG"[DEBUG]"fmt, ##args)
DEFINE_MUTEX(g_mfg_lock);
//FIXME
static int g_curFreqID;
static int g_is_suspend;
enum gpu_dvfs_status_step {
GPU_DVFS_STATUS_STEP_1 = 0x1,
GPU_DVFS_STATUS_STEP_2 = 0x2,
GPU_DVFS_STATUS_STEP_3 = 0x3,
GPU_DVFS_STATUS_STEP_4 = 0x4,
GPU_DVFS_STATUS_STEP_5 = 0x5,
GPU_DVFS_STATUS_STEP_6 = 0x6,
GPU_DVFS_STATUS_STEP_7 = 0x7,
GPU_DVFS_STATUS_STEP_8 = 0x8,
GPU_DVFS_STATUS_STEP_9 = 0x9,
GPU_DVFS_STATUS_STEP_A = 0xA,
GPU_DVFS_STATUS_STEP_B = 0xB,
GPU_DVFS_STATUS_STEP_C = 0xC,
GPU_DVFS_STATUS_STEP_D = 0xD,
GPU_DVFS_STATUS_STEP_E = 0xE,
GPU_DVFS_STATUS_STEP_F = 0xF,
};
static inline void gpu_dvfs_status_footprint(enum gpu_dvfs_status_step step)
{
#if IS_ENABLED(CONFIG_MTK_RAM_CONSOLE)
aee_rr_rec_gpu_dvfs_status(step |
(aee_rr_curr_gpu_dvfs_status() & 0xF0));
#endif
}
static inline void gpu_dvfs_status_reset_footprint(void)
{
#if IS_ENABLED(CONFIG_MTK_RAM_CONSOLE)
aee_rr_rec_gpu_dvfs_status(0);
#endif
}
static int pm_callback_power_on_nolock(struct kbase_device *kbdev)
{
if (mt_gpufreq_bringup()) {
mtk_common_pm_mfg_active();
return 1;
}
if (!mt_gpufreq_power_ctl_en()) {
mtk_common_pm_mfg_active();
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(1);
#endif
return 1;
}
if (mtk_common_pm_is_mfg_active())
return 0;
mali_pr_debug("@%s: power on ...\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_1);
if (g_is_suspend == 1) {
mali_pr_info("@%s: discard powering on since GPU is suspended\n", __func__);
return 0;
}
/* on,off/ SWCG(BG3D)/ MTCMOS/ BUCK */
mt_gpufreq_power_control(POWER_ON, CG_ON, MTCMOS_ON, BUCK_ON);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_2);
mt_gpufreq_set_timestamp();
/* set a flag to enable GPU DVFS */
mtk_common_pm_mfg_active();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_3);
/* resume frequency */
mtk_common_gpufreq_commit(g_curFreqID);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_4);
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(1);
#endif
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_5);
return 1;
}
static void pm_callback_power_off_nolock(struct kbase_device *kbdev)
{
if (mt_gpufreq_bringup())
return;
if (!mt_gpufreq_power_ctl_en())
return;
if (!mtk_common_pm_is_mfg_active())
return;
mali_pr_debug("@%s: power off ...\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_6);
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(0);
#endif
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_7);
/* set a flag to disable GPU DVFS */
mtk_common_pm_mfg_idle();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_8);
/* suspend frequency */
g_curFreqID = mtk_common_ged_dvfs_get_last_commit_idx();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_9);
/* check MFG bus if idle */
mt_gpufreq_check_bus_idle();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_A);
/* on,off/ SWCG(BG3D)/ MTCMOS/ BUCK */
mt_gpufreq_power_control(POWER_OFF, CG_OFF, MTCMOS_OFF, BUCK_OFF);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_B);
}
static int pm_callback_power_on(struct kbase_device *kbdev)
{
int ret = 0;
mutex_lock(&g_mfg_lock);
ret = pm_callback_power_on_nolock(kbdev);
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
// MTKGPUPower_model_resume();
#endif
mutex_unlock(&g_mfg_lock);
return ret;
}
static void pm_callback_power_off(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
// MTKGPUPower_model_suspend();
#endif
pm_callback_power_off_nolock(kbdev);
mutex_unlock(&g_mfg_lock);
}
static void pm_callback_power_suspend(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
if (mtk_common_pm_is_mfg_active()) {
pm_callback_power_off_nolock(kbdev);
mali_pr_info("@%s: force powering off GPU\n", __func__);
}
g_is_suspend = 1;
mali_pr_info("@%s: gpu_suspend\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_E);
mutex_unlock(&g_mfg_lock);
}
static void pm_callback_power_resume(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
g_is_suspend = 0;
mali_pr_info("@%s: gpu_resume\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_F);
mutex_unlock(&g_mfg_lock);
}
struct kbase_pm_callback_conf pm_callbacks = {
.power_on_callback = pm_callback_power_on,
.power_off_callback = pm_callback_power_off,
.power_suspend_callback = pm_callback_power_suspend,
.power_resume_callback = pm_callback_power_resume,
};
#ifndef CONFIG_OF
static struct kbase_io_resources io_resources = {
.job_irq_number = 68,
.mmu_irq_number = 69,
.gpu_irq_number = 70,
.io_memory_region = {
.start = 0xFC010000,
.end = 0xFC010000 + (4096 * 4) - 1
}
};
#endif /* CONFIG_OF */
static struct kbase_platform_config versatile_platform_config = {
#ifndef CONFIG_OF
.io_resources = &io_resources
#endif
};
struct kbase_platform_config *kbase_get_platform_config(void)
{
return &versatile_platform_config;
}
int mtk_platform_device_init(struct kbase_device *kbdev)
{
if (!kbdev) {
mali_pr_info("@%s: kbdev is NULL\n", __func__);
return -1;
}
gpu_dvfs_status_reset_footprint();
//FIXME
g_is_suspend = -1;
mali_pr_info("@%s: initialize successfully\n", __func__);
return 0;
}
void mtk_platform_device_term(struct kbase_device *kbdev) { }

23
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6873/mali_kbase_config_platform.h
View File

@@ -1,23 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2021 MediaTek Inc.
*/
/**
* Power management configuration
*
* Attached value: pointer to @ref kbase_pm_callback_conf
* Default value: See @ref kbase_pm_callback_conf
*/
#define POWER_MANAGEMENT_CALLBACKS (&pm_callbacks)
/**
* Platform specific configuration functions
*
* Attached value: pointer to @ref kbase_platform_funcs_conf
* Default value: See @ref kbase_platform_funcs_conf
*/
#define PLATFORM_FUNCS (NULL)
extern struct kbase_pm_callback_conf pm_callbacks;

43
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6877/Kbuild
View File

@@ -1,43 +0,0 @@
#
# (C) COPYRIGHT 2012-2013, 2016-2017, 2020 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU licence.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
# SPDX-License-Identifier: GPL-2.0
#
#
include $(src)/Kbuild-mtk-custom-env
mali_kbase-y += \
platform/$(MALI_PLATFORM_DIR)/mali_kbase_config_mt6877.o
ccflags-y += \
-I$(srctree)/drivers/misc/mediatek/base/power/include
ccflags-y += \
-I$(srctree)/drivers/gpu/mediatek
ifeq ($(CONFIG_MTK_TINYSYS_SSPM_SUPPORT), y)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/v2/
# SW ReadyGo, need to include mt6877/ prior to mt6853/ if mt6877/ exists
ifeq ($(CONFIG_MACH_MT6877),y)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/mt6877
endif
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/$(CONFIG_MTK_PLATFORM)
endif
# /*set interval to 9600-10000us */
ccflags-y += -DDEFAULT_PM_POWEROFF_TICK_SHADER=25

263
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6877/mali_kbase_config_mt6877.c
View File

@@ -1,263 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
*
* (C) COPYRIGHT 2011-2017, 2020 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
* SPDX-License-Identifier: GPL-2.0
*
*/
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <mali_kbase.h>
#include <mali_kbase_defs.h>
#include <mali_kbase_config.h>
#include "mali_kbase_config_platform.h"
#include "platform/mtk_platform_common.h"
#include "ged_dvfs.h"
#include "mtk_gpufreq.h"
#include "mtk_idle.h"
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
//#include <mtk_gpu_power_sspm_ipi.h>
#endif
#define MALI_TAG "[GPU/MALI]"
#define mali_pr_info(fmt, args...) pr_info(MALI_TAG"[INFO]"fmt, ##args)
#define mali_pr_debug(fmt, args...) pr_debug(MALI_TAG"[DEBUG]"fmt, ##args)
DEFINE_MUTEX(g_mfg_lock);
static int g_curFreqID;
enum gpu_dvfs_status_step {
GPU_DVFS_STATUS_STEP_1 = 0x1,
GPU_DVFS_STATUS_STEP_2 = 0x2,
GPU_DVFS_STATUS_STEP_3 = 0x3,
GPU_DVFS_STATUS_STEP_4 = 0x4,
GPU_DVFS_STATUS_STEP_5 = 0x5,
GPU_DVFS_STATUS_STEP_6 = 0x6,
GPU_DVFS_STATUS_STEP_7 = 0x7,
GPU_DVFS_STATUS_STEP_8 = 0x8,
GPU_DVFS_STATUS_STEP_9 = 0x9,
GPU_DVFS_STATUS_STEP_A = 0xA,
GPU_DVFS_STATUS_STEP_B = 0xB,
GPU_DVFS_STATUS_STEP_C = 0xC,
GPU_DVFS_STATUS_STEP_D = 0xD,
GPU_DVFS_STATUS_STEP_E = 0xE,
GPU_DVFS_STATUS_STEP_F = 0xF,
};
static inline void gpu_dvfs_status_footprint(enum gpu_dvfs_status_step step)
{
#if IS_ENABLED(CONFIG_MTK_RAM_CONSOLE)
aee_rr_rec_gpu_dvfs_status(step |
(aee_rr_curr_gpu_dvfs_status() & 0xF0));
#endif
}
static inline void gpu_dvfs_status_reset_footprint(void)
{
#if IS_ENABLED(CONFIG_MTK_RAM_CONSOLE)
aee_rr_rec_gpu_dvfs_status(0);
#endif
}
static int pm_callback_power_on_nolock(struct kbase_device *kbdev)
{
if (mt_gpufreq_bringup()) {
mtk_common_pm_mfg_active();
return 1;
}
if (!mt_gpufreq_power_ctl_en()) {
mtk_common_pm_mfg_active();
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(1);
#endif
return 1;
}
if (mtk_common_pm_is_mfg_active())
return 0;
mali_pr_debug("@%s: power on ...\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_1);
/* on,off/ SWCG(BG3D)/ MTCMOS/ BUCK */
mt_gpufreq_power_control(POWER_ON, CG_ON, MTCMOS_ON, BUCK_ON);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_2);
mt_gpufreq_set_timestamp();
mt_gpufreq_set_gpm();
/* set a flag to enable GPU DVFS */
mtk_common_pm_mfg_active();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_3);
/* resume frequency */
mtk_common_gpufreq_commit(g_curFreqID);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_4);
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(1);
#endif
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_5);
return 1;
}
static void pm_callback_power_off_nolock(struct kbase_device *kbdev)
{
if (mt_gpufreq_bringup())
return;
if (!mt_gpufreq_power_ctl_en())
return;
if (!mtk_common_pm_is_mfg_active())
return;
mali_pr_debug("@%s: power off ...\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_6);
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(0);
#endif
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_7);
/* set a flag to disable GPU DVFS */
mtk_common_pm_mfg_idle();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_8);
/* suspend frequency */
g_curFreqID = mtk_common_ged_dvfs_get_last_commit_idx();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_9);
/* check MFG bus if idle */
mt_gpufreq_check_bus_idle();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_A);
/* on,off/ SWCG(BG3D)/ MTCMOS/ BUCK */
mt_gpufreq_power_control(POWER_OFF, CG_OFF, MTCMOS_OFF, BUCK_OFF);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_B);
}
static int pm_callback_power_on(struct kbase_device *kbdev)
{
int ret = 0;
mutex_lock(&g_mfg_lock);
ret = pm_callback_power_on_nolock(kbdev);
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
// MTKGPUPower_model_resume();
#endif
mutex_unlock(&g_mfg_lock);
return ret;
}
static void pm_callback_power_off(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
// MTKGPUPower_model_suspend();
#endif
pm_callback_power_off_nolock(kbdev);
mutex_unlock(&g_mfg_lock);
}
static void pm_callback_power_suspend(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
mali_pr_debug("@%s: gpu_suspend\n", __func__);
if (mtk_common_pm_is_mfg_active()) {
mali_pr_info("@%s: someone power on GPU during suspend\n", __func__);
}
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_E);
mutex_unlock(&g_mfg_lock);
}
static void pm_callback_power_resume(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
mali_pr_debug("@%s: gpu_resume\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_F);
mutex_unlock(&g_mfg_lock);
}
struct kbase_pm_callback_conf pm_callbacks = {
.power_on_callback = pm_callback_power_on,
.power_off_callback = pm_callback_power_off,
.power_suspend_callback = pm_callback_power_suspend,
.power_resume_callback = pm_callback_power_resume,
};
#ifndef CONFIG_OF
static struct kbase_io_resources io_resources = {
.job_irq_number = 68,
.mmu_irq_number = 69,
.gpu_irq_number = 70,
.io_memory_region = {
.start = 0xFC010000,
.end = 0xFC010000 + (4096 * 4) - 1
}
};
#endif /* CONFIG_OF */
static struct kbase_platform_config versatile_platform_config = {
#ifndef CONFIG_OF
.io_resources = &io_resources
#endif
};
struct kbase_platform_config *kbase_get_platform_config(void)
{
return &versatile_platform_config;
}
int mtk_platform_device_init(struct kbase_device *kbdev)
{
if (!kbdev) {
mali_pr_info("@%s: kbdev is NULL\n", __func__);
return -1;
}
gpu_dvfs_status_reset_footprint();
mali_pr_info("@%s: initialize successfully\n", __func__);
return 0;
}
void mtk_platform_device_term(struct kbase_device *kbdev) { }

58
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6877/mali_kbase_config_platform.h
View File

@@ -1,58 +0,0 @@
/*
*
* (C) COPYRIGHT ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
* SPDX-License-Identifier: GPL-2.0
*
*//* SPDX-License-Identifier: GPL-2.0 */
/*
*
* (C) COPYRIGHT 2014-2017, 2020 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU license.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
*/
/**
* Power management configuration
*
* Attached value: pointer to @ref kbase_pm_callback_conf
* Default value: See @ref kbase_pm_callback_conf
*/
#define POWER_MANAGEMENT_CALLBACKS (&pm_callbacks)
/**
* Platform specific configuration functions
*
* Attached value: pointer to @ref kbase_platform_funcs_conf
* Default value: See @ref kbase_platform_funcs_conf
*/
#define PLATFORM_FUNCS (NULL)
extern struct kbase_pm_callback_conf pm_callbacks;

39
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6885/Kbuild
View File

@@ -1,39 +0,0 @@
#
# (C) COPYRIGHT 2012-2013, 2016-2017, 2020 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU licence.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
# SPDX-License-Identifier: GPL-2.0
#
#
include $(src)/Kbuild-mtk-custom-env
mali_kbase-y += \
platform/$(MALI_PLATFORM_DIR)/mali_kbase_config_mt6885.o
ccflags-y += \
-I$(srctree)/drivers/misc/mediatek/base/power/include
ccflags-y += \
-I$(srctree)/drivers/misc/mediatek/include/mt-plat
ifeq ($(CONFIG_MTK_TINYSYS_SSPM_SUPPORT), y)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/v2/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/$(CONFIG_MTK_PLATFORM)
endif
# /*set interval to 9600-10000us */
ccflags-y += -DDEFAULT_PM_POWEROFF_TICK_SHADER=25

262
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6885/mali_kbase_config_mt6885.c
View File

@@ -1,262 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <mali_kbase.h>
#include <mali_kbase_defs.h>
#include <mali_kbase_config.h>
#include "mali_kbase_config_platform.h"
#include "platform/mtk_platform_common.h"
#include "ged_dvfs.h"
#include "mtk_gpufreq.h"
#include "mtk_idle.h"
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
//#include <mtk_gpu_power_sspm_ipi.h>
#endif
#define MALI_TAG "[GPU/MALI]"
#define mali_pr_info(fmt, args...) pr_info(MALI_TAG"[INFO]"fmt, ##args)
#define mali_pr_debug(fmt, args...) pr_debug(MALI_TAG"[DEBUG]"fmt, ##args)
DEFINE_MUTEX(g_mfg_lock);
//FIXME
static int g_curFreqID;
static int g_is_suspend;
enum gpu_dvfs_status_step {
GPU_DVFS_STATUS_STEP_1 = 0x1,
GPU_DVFS_STATUS_STEP_2 = 0x2,
GPU_DVFS_STATUS_STEP_3 = 0x3,
GPU_DVFS_STATUS_STEP_4 = 0x4,
GPU_DVFS_STATUS_STEP_5 = 0x5,
GPU_DVFS_STATUS_STEP_6 = 0x6,
GPU_DVFS_STATUS_STEP_7 = 0x7,
GPU_DVFS_STATUS_STEP_8 = 0x8,
GPU_DVFS_STATUS_STEP_9 = 0x9,
GPU_DVFS_STATUS_STEP_A = 0xA,
GPU_DVFS_STATUS_STEP_B = 0xB,
GPU_DVFS_STATUS_STEP_C = 0xC,
GPU_DVFS_STATUS_STEP_D = 0xD,
GPU_DVFS_STATUS_STEP_E = 0xE,
GPU_DVFS_STATUS_STEP_F = 0xF,
};
static inline void gpu_dvfs_status_footprint(enum gpu_dvfs_status_step step)
{
#if IS_ENABLED(CONFIG_MTK_RAM_CONSOLE)
aee_rr_rec_gpu_dvfs_status(step |
(aee_rr_curr_gpu_dvfs_status() & 0xF0));
#endif
}
static inline void gpu_dvfs_status_reset_footprint(void)
{
#if IS_ENABLED(CONFIG_MTK_RAM_CONSOLE)
aee_rr_rec_gpu_dvfs_status(0);
#endif
}
static int pm_callback_power_on_nolock(struct kbase_device *kbdev)
{
if (mt_gpufreq_bringup()) {
mtk_common_pm_mfg_active();
return 1;
}
if (!mt_gpufreq_power_ctl_en()) {
mtk_common_pm_mfg_active();
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(1);
#endif
return 1;
}
if (mtk_common_pm_is_mfg_active())
return 0;
mali_pr_debug("@%s: power on ...\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_1);
if (g_is_suspend == 1) {
mali_pr_info("@%s: discard powering on since GPU is suspended\n", __func__);
return 0;
}
/* on,off/ SWCG(BG3D)/ MTCMOS/ BUCK */
mt_gpufreq_power_control(POWER_ON, CG_ON, MTCMOS_ON, BUCK_ON);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_2);
mt_gpufreq_set_timestamp();
/* set a flag to enable GPU DVFS */
mtk_common_pm_mfg_active();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_3);
/* resume frequency */
mtk_common_gpufreq_commit(g_curFreqID);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_4);
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(1);
#endif
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_5);
return 1;
}
static void pm_callback_power_off_nolock(struct kbase_device *kbdev)
{
if (mt_gpufreq_bringup())
return;
if (!mt_gpufreq_power_ctl_en())
return;
if (!mtk_common_pm_is_mfg_active())
return;
mali_pr_debug("@%s: power off ...\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_6);
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(0);
#endif
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_7);
/* set a flag to disable GPU DVFS */
mtk_common_pm_mfg_idle();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_8);
/* suspend frequency */
g_curFreqID = mtk_common_ged_dvfs_get_last_commit_idx();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_9);
/* check MFG bus if idle */
mt_gpufreq_check_bus_idle();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_A);
/* on,off/ SWCG(BG3D)/ MTCMOS/ BUCK */
mt_gpufreq_power_control(POWER_OFF, CG_OFF, MTCMOS_OFF, BUCK_OFF);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_B);
}
static int pm_callback_power_on(struct kbase_device *kbdev)
{
int ret = 0;
mutex_lock(&g_mfg_lock);
ret = pm_callback_power_on_nolock(kbdev);
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
// MTKGPUPower_model_resume();
#endif
mutex_unlock(&g_mfg_lock);
return ret;
}
static void pm_callback_power_off(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
// MTKGPUPower_model_suspend();
#endif
pm_callback_power_off_nolock(kbdev);
mutex_unlock(&g_mfg_lock);
}
static void pm_callback_power_suspend(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
if (mtk_common_pm_is_mfg_active()) {
pm_callback_power_off_nolock(kbdev);
mali_pr_info("@%s: force powering off GPU\n", __func__);
}
g_is_suspend = 1;
mali_pr_info("@%s: gpu_suspend\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_E);
mutex_unlock(&g_mfg_lock);
}
static void pm_callback_power_resume(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
g_is_suspend = 0;
mali_pr_info("@%s: gpu_resume\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_F);
mutex_unlock(&g_mfg_lock);
}
struct kbase_pm_callback_conf pm_callbacks = {
.power_on_callback = pm_callback_power_on,
.power_off_callback = pm_callback_power_off,
.power_suspend_callback = pm_callback_power_suspend,
.power_resume_callback = pm_callback_power_resume,
};
#ifndef CONFIG_OF
static struct kbase_io_resources io_resources = {
.job_irq_number = 68,
.mmu_irq_number = 69,
.gpu_irq_number = 70,
.io_memory_region = {
.start = 0xFC010000,
.end = 0xFC010000 + (4096 * 4) - 1
}
};
#endif /* CONFIG_OF */
static struct kbase_platform_config versatile_platform_config = {
#ifndef CONFIG_OF
.io_resources = &io_resources
#endif
};
struct kbase_platform_config *kbase_get_platform_config(void)
{
return &versatile_platform_config;
}
int mtk_platform_device_init(struct kbase_device *kbdev)
{
if (!kbdev) {
mali_pr_info("@%s: kbdev is NULL\n", __func__);
return -1;
}
gpu_dvfs_status_reset_footprint();
//FIXME
g_is_suspend = -1;
mali_pr_info("@%s: initialize successfully\n", __func__);
return 0;
}
void mtk_platform_device_term(struct kbase_device *kbdev) { }

22
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6885/mali_kbase_config_platform.h
View File

@@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
/**
* Power management configuration
*
* Attached value: pointer to @ref kbase_pm_callback_conf
* Default value: See @ref kbase_pm_callback_conf
*/
#define POWER_MANAGEMENT_CALLBACKS (&pm_callbacks)
/**
* Platform specific configuration functions
*
* Attached value: pointer to @ref kbase_platform_funcs_conf
* Default value: See @ref kbase_platform_funcs_conf
*/
#define PLATFORM_FUNCS (NULL)
extern struct kbase_pm_callback_conf pm_callbacks;

39
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6893/Kbuild
View File

@@ -1,39 +0,0 @@
#
# (C) COPYRIGHT 2012-2013, 2016-2017, 2020 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU licence.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
# SPDX-License-Identifier: GPL-2.0
#
#
include $(src)/Kbuild-mtk-custom-env
mali_kbase-y += \
platform/$(MALI_PLATFORM_DIR)/mali_kbase_config_mt6893.o
ccflags-y += \
-I$(srctree)/drivers/misc/mediatek/base/power/include
ccflags-y += \
-I$(srctree)/drivers/gpu/mediatek
ifeq ($(CONFIG_MTK_TINYSYS_SSPM_SUPPORT), y)
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/v2/
ccflags-y += -I$(srctree)/drivers/misc/mediatek/sspm/$(CONFIG_MTK_PLATFORM)
endif
# /*set interval to 9600-10000us */
ccflags-y += -DDEFAULT_PM_POWEROFF_TICK_SHADER=25

260
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6893/mali_kbase_config_mt6893.c
View File

@@ -1,260 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
*
* (C) COPYRIGHT 2011-2017, 2020 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
* SPDX-License-Identifier: GPL-2.0
*
*/
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <mali_kbase.h>
#include <mali_kbase_defs.h>
#include <mali_kbase_config.h>
#include "mali_kbase_config_platform.h"
#include "platform/mtk_platform_common.h"
#include "ged_dvfs.h"
#include "mtk_gpufreq.h"
#include "mtk_idle.h"
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
#include <mtk_gpu_power_sspm_ipi.h>
#endif
#define MALI_TAG "[GPU/MALI]"
#define mali_pr_info(fmt, args...) pr_info(MALI_TAG"[INFO]"fmt, ##args)
#define mali_pr_debug(fmt, args...) pr_debug(MALI_TAG"[DEBUG]"fmt, ##args)
DEFINE_MUTEX(g_mfg_lock);
static int g_curFreqID;
enum gpu_dvfs_status_step {
GPU_DVFS_STATUS_STEP_1 = 0x1,
GPU_DVFS_STATUS_STEP_2 = 0x2,
GPU_DVFS_STATUS_STEP_3 = 0x3,
GPU_DVFS_STATUS_STEP_4 = 0x4,
GPU_DVFS_STATUS_STEP_5 = 0x5,
GPU_DVFS_STATUS_STEP_6 = 0x6,
GPU_DVFS_STATUS_STEP_7 = 0x7,
GPU_DVFS_STATUS_STEP_8 = 0x8,
GPU_DVFS_STATUS_STEP_9 = 0x9,
GPU_DVFS_STATUS_STEP_A = 0xA,
GPU_DVFS_STATUS_STEP_B = 0xB,
GPU_DVFS_STATUS_STEP_C = 0xC,
GPU_DVFS_STATUS_STEP_D = 0xD,
GPU_DVFS_STATUS_STEP_E = 0xE,
GPU_DVFS_STATUS_STEP_F = 0xF,
};
static inline void gpu_dvfs_status_footprint(enum gpu_dvfs_status_step step)
{
#if IS_ENABLED(CONFIG_MTK_RAM_CONSOLE)
aee_rr_rec_gpu_dvfs_status(step |
(aee_rr_curr_gpu_dvfs_status() & 0xF0));
#endif
}
static inline void gpu_dvfs_status_reset_footprint(void)
{
#if IS_ENABLED(CONFIG_MTK_RAM_CONSOLE)
aee_rr_rec_gpu_dvfs_status(0);
#endif
}
static int pm_callback_power_on_nolock(struct kbase_device *kbdev)
{
if (mt_gpufreq_bringup()) {
mtk_common_pm_mfg_active();
return 1;
}
if (!mt_gpufreq_power_ctl_en()) {
mtk_common_pm_mfg_active();
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(1);
#endif
return 1;
}
if (mtk_common_pm_is_mfg_active())
return 0;
mali_pr_debug("@%s: power on ...\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_1);
/* on,off/ SWCG(BG3D)/ MTCMOS/ BUCK */
mt_gpufreq_power_control(POWER_ON, CG_ON, MTCMOS_ON, BUCK_ON);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_2);
mt_gpufreq_set_timestamp();
/* set a flag to enable GPU DVFS */
mtk_common_pm_mfg_active();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_3);
/* resume frequency */
mtk_common_gpufreq_commit(g_curFreqID);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_4);
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(1);
#endif
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_5);
return 1;
}
static void pm_callback_power_off_nolock(struct kbase_device *kbdev)
{
if (mt_gpufreq_bringup())
return;
if (!mt_gpufreq_power_ctl_en())
return;
if (!mtk_common_pm_is_mfg_active())
return;
mali_pr_debug("@%s: power off ...\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_6);
#if IS_ENABLED(CONFIG_MALI_MIDGARD_DVFS) && IS_ENABLED(CONFIG_MTK_GPU_COMMON_DVFS)
ged_dvfs_gpu_clock_switch_notify(0);
#endif
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_7);
/* set a flag to disable GPU DVFS */
mtk_common_pm_mfg_idle();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_8);
/* suspend frequency */
g_curFreqID = mtk_common_ged_dvfs_get_last_commit_idx();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_9);
/* check MFG bus if idle */
mt_gpufreq_check_bus_idle();
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_A);
/* on,off/ SWCG(BG3D)/ MTCMOS/ BUCK */
mt_gpufreq_power_control(POWER_OFF, CG_OFF, MTCMOS_OFF, BUCK_OFF);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_B);
}
static int pm_callback_power_on(struct kbase_device *kbdev)
{
int ret = 0;
mutex_lock(&g_mfg_lock);
ret = pm_callback_power_on_nolock(kbdev);
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
MTKGPUPower_model_resume();
#endif
mutex_unlock(&g_mfg_lock);
return ret;
}
static void pm_callback_power_off(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
#if IS_ENABLED(CONFIG_MTK_GPU_SWPM_SUPPORT)
MTKGPUPower_model_suspend();
#endif
pm_callback_power_off_nolock(kbdev);
mutex_unlock(&g_mfg_lock);
}
static void pm_callback_power_suspend(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
mali_pr_debug("@%s: gpu_suspend\n", __func__);
if (mtk_common_pm_is_mfg_active()) {
mali_pr_info("@%s: someone power on GPU during suspend\n", __func__);
}
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_E);
mutex_unlock(&g_mfg_lock);
}
static void pm_callback_power_resume(struct kbase_device *kbdev)
{
mutex_lock(&g_mfg_lock);
mali_pr_debug("@%s: gpu_resume\n", __func__);
gpu_dvfs_status_footprint(GPU_DVFS_STATUS_STEP_F);
mutex_unlock(&g_mfg_lock);
}
struct kbase_pm_callback_conf pm_callbacks = {
.power_on_callback = pm_callback_power_on,
.power_off_callback = pm_callback_power_off,
.power_suspend_callback = pm_callback_power_suspend,
.power_resume_callback = pm_callback_power_resume,
};
#ifndef CONFIG_OF
static struct kbase_io_resources io_resources = {
.job_irq_number = 68,
.mmu_irq_number = 69,
.gpu_irq_number = 70,
.io_memory_region = {
.start = 0xFC010000,
.end = 0xFC010000 + (4096 * 4) - 1
}
};
#endif /* CONFIG_OF */
static struct kbase_platform_config versatile_platform_config = {
#ifndef CONFIG_OF
.io_resources = &io_resources
#endif
};
struct kbase_platform_config *kbase_get_platform_config(void)
{
return &versatile_platform_config;
}
int mtk_platform_device_init(struct kbase_device *kbdev)
{
if (!kbdev) {
mali_pr_info("@%s: kbdev is NULL\n", __func__);
return -1;
}
gpu_dvfs_status_reset_footprint();
mali_pr_info("@%s: initialize successfully\n", __func__);
return 0;
}
void mtk_platform_device_term(struct kbase_device *kbdev) { }

58
drivers/gpu/mediatek/gpu_mali/mali_valhall/mali-r32p1/drivers/gpu/arm/midgard/platform/mt6893/mali_kbase_config_platform.h
View File

@@ -1,58 +0,0 @@
/*
*
* (C) COPYRIGHT ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
* SPDX-License-Identifier: GPL-2.0
*
*//* SPDX-License-Identifier: GPL-2.0 */
/*
*
* (C) COPYRIGHT 2014-2017, 2020 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU license.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
*/
/**
* Power management configuration
*
* Attached value: pointer to @ref kbase_pm_callback_conf
* Default value: See @ref kbase_pm_callback_conf
*/
#define POWER_MANAGEMENT_CALLBACKS (&pm_callbacks)
/**
* Platform specific configuration functions
*
* Attached value: pointer to @ref kbase_platform_funcs_conf
* Default value: See @ref kbase_platform_funcs_conf
*/
#define PLATFORM_FUNCS (NULL)
extern struct kbase_pm_callback_conf pm_callbacks;

173
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/include/config_kernel_eng_mt6739.h
View File

@@ -1,173 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*/
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define LINUX
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.49.21.16.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.21.16.h"
#define SUPPORT_DBGDRV_EVENT_OBJECTS
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define ENABLE_EMULATED_LARGE_TEXTURES
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define PVRSRV_APPHINT_OSIDREGION0MIN "0x00000000 0x04000000 0x10000000 0x18000000 0x20000000 0x28000000 0x30000000 0x38000000"
#define PVRSRV_APPHINT_OSIDREGION0MAX "0x3FFFFFFF 0x0FFFFFFF 0x17FFFFFF 0x1FFFFFFF 0x27FFFFFF 0x2FFFFFFF 0x37FFFFFF 0x3FFFFFFF"
#define PVRSRV_APPHINT_OSIDREGION1MIN "0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000"
#define PVRSRV_APPHINT_OSIDREGION1MAX "0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF"
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define SUPPORT_MMU_PENDING_FAULT_PROTECTION
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define CACHEFLUSH_NO_KMRBF_USING_UMVA
#define PVR_BLOB_CACHE_SIZE_MEGABYTES 20
#define HWR_DEFAULT_ENABLED
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO_THRESHOLD 90
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_USE_HW_APM
#define MTK_DEBUG
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

175
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/include/config_kernel_eng_mt6761.h
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@@ -1,175 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define LINUX
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define SUPPORT_ALT_REGBASE
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.68.54.30.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.54.30.h"
#define SUPPORT_DBGDRV_EVENT_OBJECTS
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define ENABLE_EMULATED_LARGE_TEXTURES
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define PVRSRV_APPHINT_OSIDREGION0MIN "0x00000000 0x04000000 0x10000000 0x18000000 0x20000000 0x28000000 0x30000000 0x38000000"
#define PVRSRV_APPHINT_OSIDREGION0MAX "0x3FFFFFFF 0x0FFFFFFF 0x17FFFFFF 0x1FFFFFFF 0x27FFFFFF 0x2FFFFFFF 0x37FFFFFF 0x3FFFFFFF"
#define PVRSRV_APPHINT_OSIDREGION1MIN "0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000"
#define PVRSRV_APPHINT_OSIDREGION1MAX "0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF"
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define SUPPORT_MMU_PENDING_FAULT_PROTECTION
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define CACHEFLUSH_NO_KMRBF_USING_UMVA
#define PVR_BLOB_CACHE_SIZE_MEGABYTES 20
#define HWR_DEFAULT_ENABLED
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO_THRESHOLD 90
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_PMR_TRANSLATE_UMA_ADDRESSES
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_USE_HW_APM
#define MTK_DEBUG
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

173
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/include/config_kernel_eng_mt6779.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*/
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define LINUX
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_24.50.208.504.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_24.V.208.504.h"
#define SUPPORT_DBGDRV_EVENT_OBJECTS
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define ENABLE_EMULATED_LARGE_TEXTURES
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define PVRSRV_APPHINT_OSIDREGION0MIN "0x00000000 0x04000000 0x10000000 0x18000000 0x20000000 0x28000000 0x30000000 0x38000000"
#define PVRSRV_APPHINT_OSIDREGION0MAX "0x3FFFFFFF 0x0FFFFFFF 0x17FFFFFF 0x1FFFFFFF 0x27FFFFFF 0x2FFFFFFF 0x37FFFFFF 0x3FFFFFFF"
#define PVRSRV_APPHINT_OSIDREGION1MIN "0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000"
#define PVRSRV_APPHINT_OSIDREGION1MAX "0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF"
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define SUPPORT_MMU_PENDING_FAULT_PROTECTION
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define CACHEFLUSH_NO_KMRBF_USING_UMVA
#define PVR_BLOB_CACHE_SIZE_MEGABYTES 20
#define HWR_DEFAULT_ENABLED
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO_THRESHOLD 90
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_USE_HW_APM
#define MTK_DEBUG
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS
#define MTK_GPU_BM_SUPPORT

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drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/include/config_kernel_user_mt6739.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*/
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define LINUX
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.49.21.16.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.21.16.h"
#define SUPPORT_DBGDRV_EVENT_OBJECTS
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define ENABLE_EMULATED_LARGE_TEXTURES
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define PVRSRV_APPHINT_OSIDREGION0MIN "0x00000000 0x04000000 0x10000000 0x18000000 0x20000000 0x28000000 0x30000000 0x38000000"
#define PVRSRV_APPHINT_OSIDREGION0MAX "0x3FFFFFFF 0x0FFFFFFF 0x17FFFFFF 0x1FFFFFFF 0x27FFFFFF 0x2FFFFFFF 0x37FFFFFF 0x3FFFFFFF"
#define PVRSRV_APPHINT_OSIDREGION1MIN "0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000"
#define PVRSRV_APPHINT_OSIDREGION1MAX "0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF"
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define SUPPORT_MMU_PENDING_FAULT_PROTECTION
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define CACHEFLUSH_NO_KMRBF_USING_UMVA
#define PVR_BLOB_CACHE_SIZE_MEGABYTES 20
#define HWR_DEFAULT_ENABLED
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO_THRESHOLD 90
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_USE_HW_APM
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

174
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/include/config_kernel_user_mt6761.h
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@@ -1,174 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define LINUX
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define SUPPORT_ALT_REGBASE
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.68.54.30.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.54.30.h"
#define SUPPORT_DBGDRV_EVENT_OBJECTS
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define ENABLE_EMULATED_LARGE_TEXTURES
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define PVRSRV_APPHINT_OSIDREGION0MIN "0x00000000 0x04000000 0x10000000 0x18000000 0x20000000 0x28000000 0x30000000 0x38000000"
#define PVRSRV_APPHINT_OSIDREGION0MAX "0x3FFFFFFF 0x0FFFFFFF 0x17FFFFFF 0x1FFFFFFF 0x27FFFFFF 0x2FFFFFFF 0x37FFFFFF 0x3FFFFFFF"
#define PVRSRV_APPHINT_OSIDREGION1MIN "0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000"
#define PVRSRV_APPHINT_OSIDREGION1MAX "0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF"
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define SUPPORT_MMU_PENDING_FAULT_PROTECTION
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define CACHEFLUSH_NO_KMRBF_USING_UMVA
#define PVR_BLOB_CACHE_SIZE_MEGABYTES 20
#define HWR_DEFAULT_ENABLED
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO_THRESHOLD 90
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_PMR_TRANSLATE_UMA_ADDRESSES
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_USE_HW_APM
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

172
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/include/config_kernel_user_mt6779.h
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@@ -1,172 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*/
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define LINUX
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_24.50.208.504.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_24.V.208.504.h"
#define SUPPORT_DBGDRV_EVENT_OBJECTS
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define ENABLE_EMULATED_LARGE_TEXTURES
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define PVRSRV_APPHINT_OSIDREGION0MIN "0x00000000 0x04000000 0x10000000 0x18000000 0x20000000 0x28000000 0x30000000 0x38000000"
#define PVRSRV_APPHINT_OSIDREGION0MAX "0x3FFFFFFF 0x0FFFFFFF 0x17FFFFFF 0x1FFFFFFF 0x27FFFFFF 0x2FFFFFFF 0x37FFFFFF 0x3FFFFFFF"
#define PVRSRV_APPHINT_OSIDREGION1MIN "0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000 0x3F000000"
#define PVRSRV_APPHINT_OSIDREGION1MAX "0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF 0x3FFFFFFF"
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define SUPPORT_MMU_PENDING_FAULT_PROTECTION
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define CACHEFLUSH_NO_KMRBF_USING_UMVA
#define PVR_BLOB_CACHE_SIZE_MEGABYTES 20
#define HWR_DEFAULT_ENABLED
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO
#define PVRSRV_ENABLE_CCCB_UTILISATION_INFO_THRESHOLD 90
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_USE_HW_APM
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS
#define MTK_GPU_BM_SUPPORT

207
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6739/mtk_mfg_counter.c
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@@ -1,207 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE) ? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE) ? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter", gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

60
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6739/mtk_mfg_counter.h
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@@ -1,60 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mt-plat/mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(GPU_PMU *pmus, int pmu_size, int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

109
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6739/mtk_mfgsys.h
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@@ -1,109 +0,0 @@
/*
* Copyright (C) 2015 MediaTek Inc.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#else
#define MTK_PM_SUPPORT 0
#endif
#define MTCMOS_CONTROL 1
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData, PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData, PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
extern void mt_gpufreq_input_boost_notify_registerCB(gpufreq_input_boost_notify pCB);
extern void mt_gpufreq_power_limit_notify_registerCB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

204
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6761/mtk_mfg_counter.c
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@@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6761/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

106
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6761/mtk_mfgsys.h
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@@ -1,106 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
void mtk_fdvfs_update_cur_freq(int ui32GPUFreq);
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

204
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6765/mtk_mfg_counter.c
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@@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6765/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

106
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6765/mtk_mfgsys.h
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@@ -1,106 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
void mtk_fdvfs_update_cur_freq(int ui32GPUFreq);
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

205
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6779/mtk_mfg_counter.c
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@@ -1,205 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(struct GPU_PMU *pmus,
int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(struct GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6779/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

107
drivers/gpu/mediatek/gpu_rgx/m1.13ED5776728/services/system/rogue/rgx_mtk/mt6779/mtk_mfgsys.h
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@@ -1,107 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

165
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/include/config_kernel_eng_mt6761.h
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@@ -1,165 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#define PVRSRV_APPHINT_FIRMWARE_HEAP_POLICY 5
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define SUPPORT_ALT_REGBASE
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.68.54.30.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.54.30.h"
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_CACHEOPTHREADPRIORITY 1
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define PVRSRV_APPHINT_RISCVDMITEST 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define SUPPORT_DI_BRG_IMPL
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_PMR_TRANSLATE_UMA_ADDRESSES
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_MINI_PORTING
#define MTK_USE_HW_APM
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

165
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/include/config_kernel_user_mt6761.h
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@@ -1,165 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#define PVRSRV_APPHINT_FIRMWARE_HEAP_POLICY 5
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define SUPPORT_ALT_REGBASE
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.68.54.30.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.54.30.h"
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_CACHEOPTHREADPRIORITY 1
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define PVRSRV_APPHINT_RISCVDMITEST 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define SUPPORT_DI_BRG_IMPL
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_PMR_TRANSLATE_UMA_ADDRESSES
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_MINI_PORTING
#define MTK_USE_HW_APM
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

207
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6739/mtk_mfg_counter.c
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@@ -1,207 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE) ? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE) ? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter", gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

60
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6739/mtk_mfg_counter.h
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@@ -1,60 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mt-plat/mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(GPU_PMU *pmus, int pmu_size, int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

109
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6739/mtk_mfgsys.h
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@@ -1,109 +0,0 @@
/*
* Copyright (C) 2015 MediaTek Inc.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#else
#define MTK_PM_SUPPORT 0
#endif
#define MTCMOS_CONTROL 1
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData, PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData, PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
extern void mt_gpufreq_input_boost_notify_registerCB(gpufreq_input_boost_notify pCB);
extern void mt_gpufreq_power_limit_notify_registerCB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

204
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6761/mtk_mfg_counter.c
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@@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6761/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

106
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6761/mtk_mfgsys.h
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@@ -1,106 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
void mtk_fdvfs_update_cur_freq(int ui32GPUFreq);
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

204
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6765/mtk_mfg_counter.c
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@@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6765/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

106
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6765/mtk_mfgsys.h
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@@ -1,106 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
void mtk_fdvfs_update_cur_freq(int ui32GPUFreq);
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

205
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6779/mtk_mfg_counter.c
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@@ -1,205 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(struct GPU_PMU *pmus,
int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(struct GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6779/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

107
drivers/gpu/mediatek/gpu_rgx/m1.15ED5895968/services/system/rogue/rgx_mtk/mt6779/mtk_mfgsys.h
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@@ -1,107 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

168
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/include/config_kernel_eng_mt6761.h
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@@ -1,168 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#define PVRSRV_APPHINT_FIRMWARE_HEAP_POLICY 5
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define SUPPORT_ALT_REGBASE
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.68.54.30.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.54.30.h"
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_CACHEOPTHREADPRIORITY 1
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define PVRSRV_APPHINT_RISCVDMITEST 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define SUPPORT_DI_BRG_IMPL
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_PMR_TRANSLATE_UMA_ADDRESSES
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_MINI_PORTING
#define MTK_FULL_PORTING
#define MTK_USE_HW_APM
#define MTK_DEBUG
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

167
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/include/config_kernel_user_mt6761.h
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@@ -1,167 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#define PVRSRV_APPHINT_FIRMWARE_HEAP_POLICY 5
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define SUPPORT_ALT_REGBASE
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.68.54.30.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.54.30.h"
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_CACHEOPTHREADPRIORITY 1
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define PVRSRV_APPHINT_RISCVDMITEST 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define SUPPORT_DI_BRG_IMPL
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_PMR_TRANSLATE_UMA_ADDRESSES
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_MINI_PORTING
#define MTK_FULL_PORTING
#define MTK_USE_HW_APM
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

207
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6739/mtk_mfg_counter.c
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@@ -1,207 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE) ? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE) ? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter", gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

60
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6739/mtk_mfg_counter.h
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@@ -1,60 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mt-plat/mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(GPU_PMU *pmus, int pmu_size, int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

109
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6739/mtk_mfgsys.h
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@@ -1,109 +0,0 @@
/*
* Copyright (C) 2015 MediaTek Inc.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#else
#define MTK_PM_SUPPORT 0
#endif
#define MTCMOS_CONTROL 1
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData, PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData, PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
extern void mt_gpufreq_input_boost_notify_registerCB(gpufreq_input_boost_notify pCB);
extern void mt_gpufreq_power_limit_notify_registerCB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

204
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6761/mtk_mfg_counter.c
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@@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6761/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

106
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6761/mtk_mfgsys.h
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@@ -1,106 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
void mtk_fdvfs_update_cur_freq(int ui32GPUFreq);
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

204
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6765/mtk_mfg_counter.c
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@@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6765/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

106
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6765/mtk_mfgsys.h
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@@ -1,106 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
void mtk_fdvfs_update_cur_freq(int ui32GPUFreq);
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

205
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6779/mtk_mfg_counter.c
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@@ -1,205 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(struct GPU_PMU *pmus,
int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(struct GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6779/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

107
drivers/gpu/mediatek/gpu_rgx/m1.15ED5904022/services/system/rogue/rgx_mtk/mt6779/mtk_mfgsys.h
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@@ -1,107 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

169
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/include/config_kernel_eng_mt6761.h
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@@ -1,169 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#define PVRSRV_APPHINT_FIRMWARE_HEAP_POLICY 5
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define SUPPORT_ALT_REGBASE
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.68.54.30.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.54.30.h"
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_CACHEOPTHREADPRIORITY 1
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_KCCB_SIZE_LOG2 7
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define PVRSRV_APPHINT_RISCVDMITEST 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define SUPPORT_DI_BRG_IMPL
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_PMR_TRANSLATE_UMA_ADDRESSES
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_MINI_PORTING
#define MTK_FULL_PORTING
#define MTK_USE_HW_APM
#define MTK_DEBUG
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

168
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/include/config_kernel_user_mt6761.h
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@@ -1,168 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#define PVRSRV_APPHINT_FIRMWARE_HEAP_POLICY 5
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define SUPPORT_ALT_REGBASE
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.68.54.30.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.54.30.h"
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_CACHEOPTHREADPRIORITY 1
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_KCCB_SIZE_LOG2 7
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define PVRSRV_APPHINT_RISCVDMITEST 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define PVR_ANNOTATION_MAX_LEN 63
#define SUPPORT_DI_BRG_IMPL
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_PMR_TRANSLATE_UMA_ADDRESSES
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_MINI_PORTING
#define MTK_FULL_PORTING
#define MTK_USE_HW_APM
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

207
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6739/mtk_mfg_counter.c
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@@ -1,207 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE) ? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE) ? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter", gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

60
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6739/mtk_mfg_counter.h
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@@ -1,60 +0,0 @@
/*
* Copyright (C) 2016 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mt-plat/mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(GPU_PMU *pmus, int pmu_size, int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

109
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6739/mtk_mfgsys.h
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@@ -1,109 +0,0 @@
/*
* Copyright (C) 2015 MediaTek Inc.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#else
#define MTK_PM_SUPPORT 0
#endif
#define MTCMOS_CONTROL 1
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData, PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData, PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
extern void mt_gpufreq_input_boost_notify_registerCB(gpufreq_input_boost_notify pCB);
extern void mt_gpufreq_power_limit_notify_registerCB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

204
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6761/mtk_mfg_counter.c
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@@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6761/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

106
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6761/mtk_mfgsys.h
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@@ -1,106 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
void mtk_fdvfs_update_cur_freq(int ui32GPUFreq);
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

204
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6765/mtk_mfg_counter.c
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@@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6765/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

106
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6765/mtk_mfgsys.h
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@@ -1,106 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
void mtk_fdvfs_update_cur_freq(int ui32GPUFreq);
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

205
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6779/mtk_mfg_counter.c
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@@ -1,205 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(struct GPU_PMU *pmus,
int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(struct GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6779/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

107
drivers/gpu/mediatek/gpu_rgx/m1.15ED5935164/services/system/rogue/rgx_mtk/mt6779/mtk_mfgsys.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKDevPrePowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKDevPostPowerState(IMG_HANDLE hSysData,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

181
drivers/gpu/mediatek/gpu_rgx/m1.15ED5990020/include/config_kernel_eng_mt6761.h
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@@ -1,181 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#define PVRSRV_APPHINT_FIRMWARE_HEAP_POLICY 5
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define SUPPORT_ALT_REGBASE
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.68.54.30.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.54.30.h"
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define RGX_OSID_0_DEFAULT_PRIORITY (1 - 0)
#define RGX_OSID_1_DEFAULT_PRIORITY (1 - 1)
#define RGX_OSID_2_DEFAULT_PRIORITY (1 - 2)
#define RGX_OSID_3_DEFAULT_PRIORITY (1 - 3)
#define RGX_OSID_4_DEFAULT_PRIORITY (1 - 4)
#define RGX_OSID_5_DEFAULT_PRIORITY (1 - 5)
#define RGX_OSID_6_DEFAULT_PRIORITY (1 - 6)
#define RGX_OSID_7_DEFAULT_PRIORITY (1 - 7)
#define RGX_HCS_DEFAULT_DEADLINE_MS 0xFFFFFFFFU
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define CACHEFLUSH_NO_KMRBF_USING_UMVA
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_CACHEOPTHREADPRIORITY 1
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_KCCB_SIZE_LOG2 7
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGL 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define PVRSRV_APPHINT_RISCVDMITEST 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define RGXFW_SAFETY_WATCHDOG_PERIOD_IN_US 1000000
#define PVR_ANNOTATION_MAX_LEN 63
#define SUPPORT_DI_BRG_IMPL
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_PMR_TRANSLATE_UMA_ADDRESSES
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_MINI_PORTING
#define MTK_FULL_PORTING
#define MTK_USE_HW_APM
#define MTK_DEBUG
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

180
drivers/gpu/mediatek/gpu_rgx/m1.15ED5990020/include/config_kernel_user_mt6761.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#define PVRSRV_APPHINT_FIRMWARE_HEAP_POLICY 5
#define PVRSRV_ENABLE_CCCB_GROW
#define RGX_FW_FILENAME "rgx.fw"
#define RGX_SH_FILENAME "rgx.sh"
#define PVR_BUILD_DIR "mtk_android"
#define PVR_BUILD_TYPE "release"
#define PVRSRV_MODNAME "pvrsrvkm"
#define PVRSYNC_MODNAME "pvr_sync"
#define SUPPORT_RGX 1
#define RELEASE
#define SUPPORT_PHYSMEM_TEST
#define SUPPORT_ALT_REGBASE
#define RGX_BVNC_CORE_KM_HEADER "cores/rgxcore_km_22.68.54.30.h"
#define RGX_BNC_CONFIG_KM_HEADER "configs/rgxconfig_km_22.V.54.30.h"
#define PVRSRV_NEED_PVR_DPF
#define SUPPORT_RGXTQ_BRIDGE
#define PVRSRV_POISON_ON_ALLOC_VALUE 0xd9
#define PVRSRV_POISON_ON_FREE_VALUE 0x63
#define RGX_NUM_OS_SUPPORTED 1
#define RGX_OSID_0_DEFAULT_PRIORITY (1 - 0)
#define RGX_OSID_1_DEFAULT_PRIORITY (1 - 1)
#define RGX_OSID_2_DEFAULT_PRIORITY (1 - 2)
#define RGX_OSID_3_DEFAULT_PRIORITY (1 - 3)
#define RGX_OSID_4_DEFAULT_PRIORITY (1 - 4)
#define RGX_OSID_5_DEFAULT_PRIORITY (1 - 5)
#define RGX_OSID_6_DEFAULT_PRIORITY (1 - 6)
#define RGX_OSID_7_DEFAULT_PRIORITY (1 - 7)
#define RGX_HCS_DEFAULT_DEADLINE_MS 0xFFFFFFFFU
#define PVRSRV_APPHINT_DRIVERMODE 0x7FFFFFFF
#define RGX_FW_HEAP_SHIFT 25
#define SUPPORT_POWMON_COMPONENT
#define PVR_POWER_ACTOR
#define PVR_POWER_ACTOR_MEASUREMENT_PERIOD_MS 10U
#define PVR_POWER_MONITOR_HWPERF
#define PVR_LDM_DRIVER_REGISTRATION_NAME "pvrsrvkm"
#define PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN 256
#define ION_DEFAULT_HEAP_NAME "ion_system_heap"
#define ION_DEFAULT_HEAP_ID_MASK (1 << ION_HEAP_TYPE_SYSTEM)
#define CACHEFLUSH_NO_KMRBF_USING_UMVA
#define PVRSRV_APPHINT_HWRDEBUGDUMPLIMIT APPHNT_BLDVAR_DBGDUMPLIMIT
#define PVRSRV_APPHINT_ENABLETRUSTEDDEVICEACECONFIG IMG_FALSE
#define PVRSRV_APPHINT_GENERALNON4KHEAPPAGESIZE 0x4000
#define PVRSRV_APPHINT_HWPERFCLIENTBUFFERSIZE 786432
#define PVRSRV_APPHINT_ENABLESIGNATURECHECKS APPHNT_BLDVAR_ENABLESIGNATURECHECKS
#define PVRSRV_APPHINT_SIGNATURECHECKSBUFSIZE RGXFW_SIG_BUFFER_SIZE_MIN
#define PVRSRV_APPHINT_ENABLEFULLSYNCTRACKING IMG_FALSE
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG APPHNT_BLDVAR_ENABLEPAGEFAULTDEBUG
#else
#define PVRSRV_APPHINT_ENABLEPAGEFAULTDEBUG IMG_TRUE
#endif
#define PVRSRV_APPHINT_VALIDATEIRQ 0
#define PVRSRV_APPHINT_DISABLECLOCKGATING 0
#define PVRSRV_APPHINT_DISABLEDMOVERLAP 0
#define PVRSRV_APPHINT_ENABLECDMKILLINGRANDMODE 0
#define PVRSRV_APPHINT_ENABLERANDOMCONTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLESOFTRESETCNTEXTSWITCH 0
#define PVRSRV_APPHINT_ENABLEFWCONTEXTSWITCH RGXFWIF_INICFG_OS_CTXSWITCH_DM_ALL
#define PVRSRV_APPHINT_VDMCONTEXTSWITCHMODE RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX
#define PVRSRV_APPHINT_ENABLERDPOWERISLAND RGX_RD_POWER_ISLAND_DEFAULT
#define PVRSRV_APPHINT_FIRMWAREPERF FW_PERF_CONF_NONE
#define PVRSRV_APPHINT_FWCONTEXTSWITCHPROFILE RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN
#define PVRSRV_APPHINT_HWPERFDISABLECUSTOMCOUNTERFILTER 0
#define PVRSRV_APPHINT_HWPERFFWBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTBUFSIZEINKB 2048
#define PVRSRV_APPHINT_HWPERFHOSTTHREADTIMEOUTINMS 50
#define PVRSRV_APPHINT_JONESDISABLEMASK 0
#define PVRSRV_APPHINT_NEWFILTERINGMODE 1
#define PVRSRV_APPHINT_TRUNCATEMODE 0
#define PVRSRV_APPHINT_EMUMAXFREQ 0
#define PVRSRV_APPHINT_GPIOVALIDATIONMODE 0
#define PVRSRV_APPHINT_RGXBVNC ""
#define PVRSRV_APPHINT_CLEANUPTHREADPRIORITY 5
#define PVRSRV_APPHINT_WATCHDOGTHREADPRIORITY 0
#define PVRSRV_APPHINT_CACHEOPTHREADPRIORITY 1
#define PVRSRV_APPHINT_ASSERTONHWRTRIGGER IMG_FALSE
#define PVRSRV_APPHINT_ASSERTOUTOFMEMORY IMG_FALSE
#define PVRSRV_APPHINT_CHECKMLIST APPHNT_BLDVAR_DEBUG
#define PVRSRV_APPHINT_DISABLEFEDLOGGING IMG_FALSE
#define PVRSRV_APPHINT_KCCB_SIZE_LOG2 7
#define PVRSRV_APPHINT_ENABLEAPM RGX_ACTIVEPM_DEFAULT
#define PVRSRV_APPHINT_ENABLEHTBLOGGROUP 0
#define PVRSRV_APPHINT_ENABLELOGGROUP RGXFWIF_LOG_TYPE_NONE
#define PVRSRV_APPHINT_FIRMWARELOGTYPE 0
#define PVRSRV_APPHINT_FWTRACEBUFSIZEINDWORDS RGXFW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS
#define PVRSRV_APPHINT_FBCDCVERSIONOVERRIDE 0
#define PVRSRV_APPHINT_HTBOPERATIONMODE HTB_OPMODE_DROPOLDEST
#define PVRSRV_APPHINT_HTBUFFERSIZE 64
#define PVRSRV_APPHINT_ENABLEFTRACEGPU IMG_FALSE
#define PVRSRV_APPHINT_HWPERFFWFILTER 0
#define PVRSRV_APPHINT_HWPERFHOSTFILTER 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_SERVICES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_EGL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGLES 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENCL 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_VULKAN 0
#define PVRSRV_APPHINT_HWPERFCLIENTFILTER_OPENGL 0
#define PVRSRV_APPHINT_TIMECORRCLOCK 0
#define PVRSRV_APPHINT_ENABLEFWPOISONONFREE IMG_FALSE
#define PVRSRV_APPHINT_FWPOISONONFREEVALUE 0xBD
#define PVRSRV_APPHINT_ZEROFREELIST IMG_FALSE
#define PVRSRV_APPHINT_GPUUNITSPOWERCHANGE IMG_FALSE
#define PVRSRV_APPHINT_DISABLEPDUMPPANIC IMG_FALSE
#define PVRSRV_APPHINT_CACHEOPCONFIG 0
#define PVRSRV_APPHINT_CACHEOPUMKMHRESHOLDSIZE 0
#define PVRSRV_APPHINT_IGNOREHWREPORTEDBVNC IMG_FALSE
#define PVRSRV_APPHINT_PHYSMEMTESTPASSES APPHNT_PHYSMEMTEST_ENABLE
#define PVRSRV_APPHINT_TESTSLRINTERVAL 0
#define PVRSRV_APPHINT_RISCVDMITEST 0
#define SOC_TIMER_FREQ 20
#define PDVFS_COM_HOST 1
#define PDVFS_COM_AP 2
#define PDVFS_COM_PMC 3
#define PDVFS_COM_IMG_CLKDIV 4
#define PDVFS_COM PDVFS_COM_HOST
#define PVR_GPIO_MODE_GENERAL 1
#define PVR_GPIO_MODE_POWMON_PIN 2
#define PVR_GPIO_MODE PVR_GPIO_MODE_GENERAL
#define PVRSRV_ENABLE_PROCESS_STATS
#define SUPPORT_USC_BREAKPOINT
#define RGXFW_SAFETY_WATCHDOG_PERIOD_IN_US 1000000
#define PVR_ANNOTATION_MAX_LEN 63
#define SUPPORT_DI_BRG_IMPL
#define PVRSRV_ENABLE_MEMTRACK_STATS_FILE
#define PVR_LINUX_PHYSMEM_MAX_POOL_PAGES 10240
#define PVR_LINUX_PHYSMEM_MAX_EXCESS_POOL_PAGES 20480
#define PVR_LINUX_PHYSMEM_ZERO_ALL_PAGES
#define PVR_LINUX_PHYSMEM_SUPPRESS_DMA_AC
#define PVR_LINUX_PHYSMEM_USE_HIGHMEM_ONLY
#define PVR_PMR_TRANSLATE_UMA_ADDRESSES
#define PVR_DIRTY_BYTES_FLUSH_THRESHOLD 524288
#define PVR_LINUX_HIGHORDER_ALLOCATION_THRESHOLD 256
#define PVR_LINUX_PHYSMEM_MAX_ALLOC_ORDER_NUM 2
#if defined(CONFIG_MTK_ENABLE_GMO)
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 8192
#else
#define PVR_LINUX_KMALLOC_ALLOCATION_THRESHOLD 16384
#endif
#define SUPPORT_NATIVE_FENCE_SYNC
#define PVRSRV_STALLED_CCB_ACTION
#define UPDATE_FENCE_CHECKPOINT_COUNT 1
#define PVR_DRM_NAME "pvr"
#if defined(__arm64__) || defined(__aarch64__)
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 16
#else
#define DEVICE_MEMSETCPY_ALIGN_IN_BYTES 8
#endif
#define RGX_INITIAL_SLR_HOLDOFF_PERIOD_MS 0
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ3D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TQ2D 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_CDM 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TA 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_3D 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_SIZE_TDM 14
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TQ2D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_CDM 15
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TA 16
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_3D 17
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_KICKSYNC 13
#define PVRSRV_RGX_LOG2_CLIENT_CCB_MAX_SIZE_TDM 17
#define ANDROID
#define SUPPORT_ION
#define PVR_ANDROID_ION_HEADER "../drivers/staging/android/aosp_ion/ion.h"
#define PVR_ANDROID_ION_PRIV_HEADER "../drivers/staging/android/ion/ion_priv.h"
#define PVR_ANDROID_ION_USE_SG_LENGTH
#define PVR_ANDROID_SYNC_HEADER "linux/sync.h"
#define PVRSRV_ENABLE_PVR_ION_STATS
#define MTK_MINI_PORTING
#define MTK_FULL_PORTING
#define MTK_USE_HW_APM
#define MTK_DEBUG_PROC_PRINT
#define MTK_CONFIG_OF
#define ENABLE_COMMON_DVFS

204
drivers/gpu/mediatek/gpu_rgx/m1.15ED5990020/services/system/rogue/rgx_mtk/mt6761/mtk_mfg_counter.c
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@@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "mtk_mfg_counter.h"
static DEFINE_SPINLOCK(counter_info_lock);
/* FIX ME: volatile can not pass check patch
* static volatile void *g_MFG_base;
*/
static void *g_MFG_base;
static int mfg_is_power_on;
/* FIX ME: volatile can not pass check patch
* #define base_write32(addr, value) \
* do { *(volatile uint32_t *)(addr) = (uint32_t)(value) } while (0)
* #define base_read32(addr) (*(volatile uint32_t *)(addr))
*/
#define base_write32(addr, value) \
do { *(uint32_t *)(addr) = (uint32_t)(value) } while (0)
#define base_read32(addr) (*(uint32_t *)(addr))
#define MFG_write32(addr, value) base_write32(g_MFG_base+addr, value)
#define MFG_read32(addr) base_read32(g_MFG_base+addr)
typedef uint32_t (*mfg_read_pfn)(uint32_t offset);
static uint32_t RGX_read(uint32_t offset)
{
return (g_MFG_base) ? MFG_read32(offset) : 0u;
}
static struct {
const char *name;
uint32_t offset;
mfg_read_pfn read;
unsigned int sum;
unsigned int val_pre;
int overflow;
} mfg_counters[] = {
{"mem0_reads", RGX_CR_PERF_SLC0_READS, RGX_read, 0u, 0u, 0},
{"mem0_write", RGX_CR_PERF_SLC0_WRITES, RGX_read, 0u, 0u, 0},
{"mem0_read_stalls", RGX_CR_PERF_SLC0_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem0_write_stalls", RGX_CR_PERF_SLC0_WRITE_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_reads", RGX_CR_PERF_SLC1_READS, RGX_read, 0u, 0u, 0},
{"mem1_write", RGX_CR_PERF_SLC1_WRITES, RGX_read, 0u, 0u, 0},
{"mem1_read_stalls", RGX_CR_PERF_SLC1_READ_STALLS, RGX_read, 0u, 0u, 0},
{"mem1_write_stalls", RGX_CR_PERF_SLC1_WRITE_STALLS, RGX_read, 0u, 0u, 0},
};
#define MFG_COUNTER_SIZE (ARRAY_SIZE(mfg_counters))
/*
* require: power must be on
* require: get counters_lock
*/
static void mtk_mfg_counter_update(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
uint32_t val, diff;
val = mfg_counters[i].read(mfg_counters[i].offset);
diff = val - mfg_counters[i].val_pre;
/* TODO: counter is reset by fw, how to be notify? */
if (diff > 0xf7654321)
diff = 0u - diff;
if (mfg_counters[i].sum + diff < mfg_counters[i].sum) {
mfg_counters[i].overflow = 1;
mfg_counters[i].sum = (uint32_t)-1;
} else if (mfg_counters[i].overflow == 0)
mfg_counters[i].sum += diff;
mfg_counters[i].val_pre = val;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_record(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i) {
mfg_counters[i].sum = 0u;
mfg_counters[i].overflow = 0;
}
}
/*
* require: get counters_lock
*/
static void mtk_mfg_counter_reset_register(void)
{
int i;
for (i = 0; i < MFG_COUNTER_SIZE; ++i)
mfg_counters[i].val_pre = 0u;
}
static int img_get_gpu_pmu_init(GPU_PMU *pmus, int pmu_size, int *ret_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
for (i = 0; i < size; ++i) {
pmus[i].id = i;
pmus[i].name = mfg_counters[i].name;
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
}
if (ret_size)
*ret_size = MFG_COUNTER_SIZE;
return 0;
}
static int img_get_gpu_pmu_swapnreset(GPU_PMU *pmus, int pmu_size)
{
if (pmus) {
int size = (pmu_size > MFG_COUNTER_SIZE)
? MFG_COUNTER_SIZE : pmu_size;
int i;
spin_lock(&counter_info_lock);
/* update if gpu power on */
if (mfg_is_power_on)
mtk_mfg_counter_update();
/* swap */
for (i = 0; i < size; ++i) {
pmus[i].value = mfg_counters[i].sum;
pmus[i].overflow = mfg_counters[i].overflow;
}
/* reset */
mtk_mfg_counter_reset_record();
spin_unlock(&counter_info_lock);
}
return 0;
}
static void *_mtk_of_ioremap(const char *node_name)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, node_name);
if (node)
return of_iomap(node, 0);
pr_debug("cannot find [%s] of_node, please fix me\n", node_name);
return NULL;
}
static void gpu_power_change_notify_mfg_counter(int power_on)
{
spin_lock(&counter_info_lock);
if (!power_on) {
/* update before power off */
mtk_mfg_counter_update();
mtk_mfg_counter_reset_register();
}
mfg_is_power_on = power_on;
spin_unlock(&counter_info_lock);
}
/* ****************************************** */
void mtk_mfg_counter_init(void)
{
g_MFG_base = _mtk_of_ioremap("mediatek,AUSTIN");
mtk_get_gpu_pmu_init_fp = img_get_gpu_pmu_init;
mtk_get_gpu_pmu_swapnreset_fp = img_get_gpu_pmu_swapnreset;
mtk_register_gpu_power_change("mfg_counter",
gpu_power_change_notify_mfg_counter);
}
void mtk_mfg_counter_destroy(void)
{
mtk_unregister_gpu_power_change("mfg_counter");
}

54
drivers/gpu/mediatek/gpu_rgx/m1.15ED5990020/services/system/rogue/rgx_mtk/mt6761/mtk_mfg_counter.h
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@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef __MTK_MFG_COUNTER__
#define __MTK_MFG_COUNTER__
#include <mtk_gpu_utility.h>
/* mt6799 performance counter */
#define RGX_PERF_CONTROL (0x6000)
#define RGX_CR_PERF_TA_PHASES (0x00006008)
#define RGX_CR_PERF_3D_PHASES (0x00006010)
#define RGX_CR_PERF_COMPUTE_PHASES (0x00006018)
#define RGX_CR_PERF_TA_CYCLES (0x00006020)
#define RGX_CR_PERF_3D_CYCLES (0x00006028)
#define RGX_CR_PERF_COMPUTE_CYCLES (0x00006030)
#define RGX_CR_PERF_TA_OR_3D_CYCLES (0x00006038)
#define RGX_CR_PERF_INITIAL_TA_CYCLES (0x00006040)
#define RGX_CR_PERF_FINAL_3D_CYCLES (0x00006048)
#define RGX_CR_PERF_3D_SPINUP_CYCLES (0x00006220)
#define RGX_CR_PERF_SLC0_READS (0x000060A0)
#define RGX_CR_PERF_SLC0_WRITES (0x000060A8)
#define RGX_CR_PERF_SLC0_BYTE_WRITES (0x000060B0)
#define RGX_CR_PERF_SLC0_READ_STALLS (0x000060B8)
#define RGX_CR_PERF_SLC0_WRITE_STALLS (0x000060C0)
#define RGX_CR_PERF_SLC1_READS (0x000060C8)
#define RGX_CR_PERF_SLC1_WRITES (0x000060D0)
#define RGX_CR_PERF_SLC1_BYTE_WRITES (0x000060D8)
#define RGX_CR_PERF_SLC1_READ_STALLS (0x000060E0)
#define RGX_CR_PERF_SLC1_WRITE_STALLS (0x000060E8)
#define RGX_CR_PERF_SLC2_READS (0x00006140)
#define RGX_CR_PERF_SLC2_WRITES (0x00006148)
#define RGX_CR_PERF_SLC2_BYTE_WRITES (0x00006150)
#define RGX_CR_PERF_SLC2_READ_STALLS (0x00006158)
#define RGX_CR_PERF_SLC2_WRITE_STALLS (0x00006160)
#define RGX_CR_PERF_SLC3_READS (0x00006168)
#define RGX_CR_PERF_SLC3_WRITES (0x00006170)
#define RGX_CR_PERF_SLC3_BYTE_WRITES (0x00006178)
#define RGX_CR_PERF_SLC3_READ_STALLS (0x00006180)
#define RGX_CR_PERF_SLC3_WRITE_STALLS (0x00006188)
extern int (*mtk_get_gpu_pmu_init_fp)(struct GPU_PMU *pmus,
int pmu_size,
int *ret_size);
extern int (*mtk_get_gpu_pmu_swapnreset_fp)(struct GPU_PMU *pmus, int pmu_size);
void mtk_mfg_counter_init(void);
void mtk_mfg_counter_destroy(void);
#endif

106
drivers/gpu/mediatek/gpu_rgx/m1.15ED5990020/services/system/rogue/rgx_mtk/mt6761/mtk_mfgsys.h
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@@ -1,106 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#ifndef MTK_MFGSYS_H
#define MTK_MFGSYS_H
#include "servicesext.h"
#include "rgxdevice.h"
#include "ged_dvfs.h"
/* Control SW APM is enabled or not */
#ifndef MTK_BRINGUP
#define MTK_PM_SUPPORT 1
#define MTCMOS_CONTROL 1
#else
#define MTK_PM_SUPPORT 0
#endif
void mtk_fdvfs_update_cur_freq(int ui32GPUFreq);
PVRSRV_ERROR MTKMFGSystemInit(void);
void MTKMFGSystemDeInit(void);
void MTKFWDump(void);
/* below register interface in RGX sysconfig.c */
PVRSRV_ERROR MTKSysPrePowerState(IMG_HANDLE hSysData,
PVRSRV_SYS_POWER_STATE eNewPowerState,
PVRSRV_SYS_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSysPostPowerState(IMG_HANDLE hSysData,
PVRSRV_SYS_POWER_STATE eNewPowerState,
PVRSRV_SYS_POWER_STATE eCurrentPowerState,
IMG_BOOL bForced);
PVRSRV_ERROR MTKSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
PVRSRV_ERROR MTKSystemPostPowerState(PVRSRV_SYS_POWER_STATE eNewPowerState);
int MTKRGXDeviceInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
int MTKRGXDeviceDeInit(PVRSRV_DEVICE_CONFIG *psDevConfig);
extern int spm_mtcmos_ctrl_mfg0(int state);
extern int spm_mtcmos_ctrl_mfg1(int state);
extern int spm_mtcmos_ctrl_mfg2(int state);
extern int spm_mtcmos_ctrl_mfg3(int state);
extern void switch_mfg_clk(int src);
extern int mtcmos_mfg_series_on(void);
extern unsigned int mtk_notify_sspm_fdvfs_gpu_pow_status(unsigned int enable);
extern void mfgsys_mtcmos_check(void);
extern unsigned int mfgsys_cg_check(void);
extern void ged_log_trace_counter(char *name, int count);
/* from gpu/ged/src/ged_dvfs.c */
extern void (*ged_dvfs_cal_gpu_utilization_fp)(unsigned int *pui32Loading,
unsigned int *pui32Block,
unsigned int *pui32Idle);
extern void (*ged_dvfs_gpu_freq_commit_fp)(unsigned long ui32NewFreqID,
GED_DVFS_COMMIT_TYPE eCommitType,
int *pbCommited);
#ifdef CONFIG_MTK_HIBERNATION
extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
int gpu_pm_restore_noirq(struct device *device);
#endif
typedef void (*gpufreq_input_boost_notify)(unsigned int);
typedef void (*gpufreq_power_limit_notify)(unsigned int);
#define INPUT_BOOST_CB mt_gpufreq_input_boost_notify_registerCB
#define POWER_LIMIT_CB mt_gpufreq_power_limit_notify_registerCB
extern void INPUT_BOOST_CB(gpufreq_input_boost_notify pCB);
extern void POWER_LIMIT_CB(gpufreq_power_limit_notify pCB);
extern unsigned int (*mtk_get_gpu_loading_fp)(void);
extern unsigned int (*mtk_get_gpu_block_fp)(void);
extern unsigned int (*mtk_get_gpu_idle_fp)(void);
extern unsigned int (*mtk_get_gpu_power_loading_fp)(void);
extern void (*mtk_enable_gpu_dvfs_timer_fp)(bool bEnable);
extern void (*mtk_boost_gpu_freq_fp)(void);
extern void (*mtk_set_bottom_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_custom_get_gpu_freq_level_count_fp)(void);
extern void (*mtk_custom_boost_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern void (*mtk_custom_upbound_gpu_freq_fp)(unsigned int ui32FreqLevel);
extern unsigned int (*mtk_get_custom_boost_gpu_freq_fp)(void);
extern unsigned int (*mtk_get_custom_upbound_gpu_freq_fp)(void);
extern int* (*mtk_get_gpu_cur_owner_fp)(void);
#ifdef SUPPORT_PDVFS
extern unsigned int mt_gpufreq_get_volt_by_idx(unsigned int idx);
#endif
#if defined(MODULE)
int mtk_mfg_async_init(void);
int mtk_mfg_2d_init(void);
#endif
#endif

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