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clk: qcom: videocc: Add support to read efuse for video clock

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Read efuse register and update the frequency table and fmax tables for
video iris clock source to 200MHz.

Change-Id: Ib0c5f59738db3be9b74bfc377dcdbb667948e264
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das
2018-10-14 15:44:59 +05:30
committed by Gerrit - the friendly Code Review server
parent 93449487b7
commit 302d242dda
2 changed files with 50 additions and 4 deletions
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5
arch/arm64/boot/dts/qcom/sdmmagpie.dtsi
View File

@@ -848,8 +848,9 @@
clock_videocc: qcom,videocc@ab00000 {
compatible = "qcom,videocc-sdmmagpie", "syscon";
vdd_cx-supply = <&VDD_CX_LEVEL>;
reg = <0xab00000 0x10000>;
reg-names = "cc_base";
reg = <0xab00000 0x10000>,
<0x00786018 0x4>;
reg-names = "cc_base", "efuse";
#clock-cells = <1>;
#reset-cells = <1>;
};

49
drivers/clk/qcom/videocc-sdmmagpie.c
View File

@@ -36,6 +36,8 @@
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
#define IRIS_DISBALE_MULTIPIPE 10
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
enum {
@@ -77,7 +79,7 @@ static struct pll_vco fabia_vco[] = {
{ 125000000, 1000000000, 1 },
};
static const struct alpha_pll_config video_pll0_config = {
static struct alpha_pll_config video_pll0_config = {
.l = 0x19,
.frac = 0x0,
.config_ctl_val = 0x20485699,
@@ -118,6 +120,10 @@ static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_video_cc_iris_multipipe_clk_src[] = {
F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
};
static struct clk_rcg2 video_cc_iris_clk_src = {
.cmd_rcgr = 0x7f0,
.mnd_width = 0,
@@ -338,6 +344,43 @@ static const struct of_device_id video_cc_sdmmagpie_match_table[] = {
};
MODULE_DEVICE_TABLE(of, video_cc_sdmmagpie_match_table);
static int video_multipipe_fixup(struct platform_device *pdev,
struct regmap *regmap)
{
void __iomem *base;
struct resource *res;
struct device *dev = &pdev->dev;
u32 val;
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
val = readl_relaxed(base);
val = (val >> IRIS_DISBALE_MULTIPIPE) & 0x1;
if (val) {
video_pll0_config.l = 0x14;
video_cc_iris_clk_src.freq_tbl =
ftbl_video_cc_iris_multipipe_clk_src;
video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_LOWER] =
200000000;
video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_LOW] =
200000000;
video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_LOW_L1] =
200000000;
video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] =
200000000;
video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_HIGH] =
200000000;
}
clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
return 0;
}
static int video_cc_sdmmagpie_probe(struct platform_device *pdev)
{
struct regmap *regmap;
@@ -357,7 +400,9 @@ static int video_cc_sdmmagpie_probe(struct platform_device *pdev)
return PTR_ERR(regmap);
}
clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
ret = video_multipipe_fixup(pdev, regmap);
if (ret)
return ret;
ret = qcom_cc_really_probe(pdev, &video_cc_sdmmagpie_desc, regmap);
if (ret) {