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Merge "ARM: dts: msm: clean up cache-size properties"

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This commit is contained in:
qctecmdr
2020-04-30 09:18:49 -07:00
committed by Gerrit - the friendly Code Review server
parent c82004f2c6 69c2144679
commit d791c619b6
6 changed files with 0 additions and 111 deletions
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25
arch/arm64/boot/dts/qcom/atoll.dtsi
View File

@@ -66,20 +66,16 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x100000>;
cache-level = <3>;
};
};
@@ -106,14 +102,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
next-level-cache = <&L2_100>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -141,14 +134,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
next-level-cache = <&L2_200>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -175,14 +165,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
next-level-cache = <&L2_300>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -209,14 +196,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
next-level-cache = <&L2_400>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -243,14 +227,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
next-level-cache = <&L2_500>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -277,14 +258,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1740>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
d-cache-size = <0x10000>;
i-cache-size = <0x10000>;
next-level-cache = <&L2_600>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x48000>;
@@ -320,14 +298,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1740>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
d-cache-size = <0x10000>;
i-cache-size = <0x10000>;
next-level-cache = <&L2_700>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x48000>;

17
arch/arm64/boot/dts/qcom/sdmmagpie.dtsi
View File

@@ -62,19 +62,16 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x100000>;
cache-level = <3>;
};
};
@@ -101,13 +98,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_100>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -135,13 +130,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_200>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -168,13 +161,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_300>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -201,13 +192,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_400>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -234,13 +223,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_500>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -267,13 +254,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1740>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
cache-size = <0x10000>;
next-level-cache = <&L2_600>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x48000>;
@@ -309,13 +294,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1740>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
cache-size = <0x10000>;
next-level-cache = <&L2_700>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x48000>;

17
arch/arm64/boot/dts/qcom/sdmshrike.dtsi
View File

@@ -57,20 +57,17 @@
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x400000>;
cache-level = <3>;
};
};
@@ -92,14 +89,12 @@
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_1>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -121,14 +116,12 @@
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_2>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -150,14 +143,12 @@
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_3>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -179,14 +170,12 @@
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_4>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -208,14 +197,12 @@
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_5>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -237,14 +224,12 @@
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_6>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -266,14 +251,12 @@
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_7>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};

17
arch/arm64/boot/dts/qcom/sm6150.dtsi
View File

@@ -63,19 +63,16 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x100000>;
cache-level = <3>;
};
};
@@ -102,13 +99,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_100>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -136,13 +131,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_200>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -169,13 +162,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_300>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -202,13 +193,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_400>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -235,13 +224,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
cache-size = <0x8000>;
next-level-cache = <&L2_500>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -268,13 +255,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1740>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
cache-size = <0x10000>;
next-level-cache = <&L2_600>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x48000>;
@@ -310,13 +295,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1740>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
cache-size = <0x10000>;
next-level-cache = <&L2_700>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x48000>;

17
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@@ -75,20 +75,17 @@
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x200000>;
cache-level = <3>;
};
};
@@ -114,14 +111,12 @@
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_1>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -147,14 +142,12 @@
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_2>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -180,14 +173,12 @@
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_3>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@@ -213,14 +204,12 @@
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_4>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x88000>;
@@ -255,14 +244,12 @@
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_5>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x88000>;
@@ -297,14 +284,12 @@
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_6>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x88000>;
@@ -339,14 +324,12 @@
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_7>;
sched-energy-costs = <&CPU_COST_2 &CLUSTER_COST_2>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x110000>;

18
arch/arm64/boot/dts/qcom/trinket.dtsi
View File

@@ -66,14 +66,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
};
L1_I_0: l1-icache {
@@ -98,8 +95,6 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
@@ -126,8 +121,6 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
@@ -154,8 +147,6 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
@@ -182,14 +173,11 @@
enable-method = "psci";
capacity-dmips-mhz = <1638>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
d-cache-size = <0x10000>;
i-cache-size = <0x10000>;
next-level-cache = <&L2_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x100000>;
cache-level = <2>;
};
@@ -215,8 +203,6 @@
enable-method = "psci";
capacity-dmips-mhz = <1638>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
d-cache-size = <0x10000>;
i-cache-size = <0x10000>;
next-level-cache = <&L2_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
@@ -243,8 +229,6 @@
enable-method = "psci";
capacity-dmips-mhz = <1638>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
d-cache-size = <0x10000>;
i-cache-size = <0x10000>;
next-level-cache = <&L2_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;
@@ -271,8 +255,6 @@
enable-method = "psci";
capacity-dmips-mhz = <1638>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
d-cache-size = <0x10000>;
i-cache-size = <0x10000>;
next-level-cache = <&L2_1>;
qcom,lmh-dcvs = <&lmh_dcvs1>;
#cooling-cells = <2>;