gps: update gps version 4.12.0.40

Bug: 246482115

Test: atest CtsLocationGnssTestCases
atest VtsHalGnssTargetTest
Change-Id: I4a934dc096ddde223c3dfc56473f2378de08dfb4
This commit is contained in:
Edwin Tung 2023-05-02 08:01:12 +08:00
parent e5a182a9c2
commit c789c04e86
3 changed files with 3 additions and 7 deletions

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@ -14,11 +14,6 @@ gnss_device_type=K041
# Chip_Configuration_TrackerDebugMode = 0x10
# bit 0 set means CRC image
# bit 1 set means CL using a flat patch (one step) - this avoids the 32 byte alignment on
# xfr from AP mem to Ext Mem on S5300.
cl_options=2
# enables CHPP for SPI port
# uncomment the *chpp* lines below (and comment gnss_device-data_port_kepslim_present above) to use SPI+CHPP
# when using CHPP, make sure to enable the CHPP defines in build_settings.mak
@ -58,13 +53,13 @@ Chip_Configuration_RefClkControl=0x24
## 6- TXC 0W76870003
## E.g. Use Kyocera, and ignore CP's polynomial: DCXO_CrystalType=0x11
## E.g. Use KDS, and Use CP's polynomial: DCXO_CrystalType=0x05
Chip_Configuration_DCXO_CrystalType=0x13
Chip_Configuration_DCXO_CrystalType=0x11
## Optionally specify DXCO Inflection point temperature, ####
# This will override any default value or value in Crystal type ####
# Value is degrees C x 100 E.g. 2855 = 28.55 deg C
# Range should be 2000 to 3100
#Chip_Configuration_DCXO_InflectionPoint=2450
#Chip_Configuration_DCXO_InflectionPoint=2855
### 2C48 L1 only MCW ###
@ -73,6 +68,7 @@ Chip_Configuration_RfMiscCtrl=0x80008001
# DVS: 0 = Disabled (default), 1 = Enabled
# DFS: 0 = Disabled (default), 1 = Enabled
# JJM: disabling due to suspicion that DVFS is contributing to GAL BAD ISM
Chip_Configuration_FeatureCfg_DVS = 1
Chip_Configuration_FeatureCfg_DFS = 1