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Merge "disp: msm: sde: add dt property for QSEED scalar HW revision"

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This commit is contained in:
qctecmdr
2020-06-19 02:38:54 -07:00
committed by Gerrit - the friendly Code Review server
parent 4ebc0e1f34 fdf88f7853
commit 1bd126d328
10 changed files with 44 additions and 78 deletions
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6
msm/sde/sde_crtc.c
View File

@@ -5124,11 +5124,11 @@ static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
sde_kms_info_add_keyint(info, "max_blendstages",
catalog->max_mixer_blendstages);
if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED2)
if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED2)
sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3)
if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3)
sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3LITE)
if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3LITE)
sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");
if (catalog->ubwc_version) {

44
msm/sde/sde_hw_catalog.c
View File

@@ -186,7 +186,8 @@ enum sde_prop {
UBWC_VERSION,
UBWC_STATIC,
UBWC_SWIZZLE,
QSEED_TYPE,
QSEED_SW_LIB_REV,
QSEED_HW_VERSION,
CSC_TYPE,
PANIC_PER_PIPE,
SRC_SPLIT,
@@ -550,7 +551,10 @@ static struct sde_prop_type sde_prop[] = {
{UBWC_VERSION, "qcom,sde-ubwc-version", false, PROP_TYPE_U32},
{UBWC_STATIC, "qcom,sde-ubwc-static", false, PROP_TYPE_U32},
{UBWC_SWIZZLE, "qcom,sde-ubwc-swizzle", false, PROP_TYPE_U32},
{QSEED_TYPE, "qcom,sde-qseed-type", false, PROP_TYPE_STRING},
{QSEED_SW_LIB_REV, "qcom,sde-qseed-sw-lib-rev", false,
PROP_TYPE_STRING},
{QSEED_HW_VERSION, "qcom,sde-qseed-scalar-version", false,
PROP_TYPE_U32},
{CSC_TYPE, "qcom,sde-csc-type", false, PROP_TYPE_STRING},
{PANIC_PER_PIPE, "qcom,sde-panic-per-pipe", false, PROP_TYPE_BOOL},
{SRC_SPLIT, "qcom,sde-has-src-split", false, PROP_TYPE_BOOL},
@@ -1438,11 +1442,11 @@ static int _sde_sspp_setup_vigs(struct device_node *np,
sblk->format_list = sde_cfg->vig_formats;
sblk->virt_format_list = sde_cfg->virt_vig_formats;
if ((sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED2) ||
(sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) ||
(sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3LITE)) {
set_bit(sde_cfg->qseed_type, &sspp->features);
sblk->scaler_blk.id = sde_cfg->qseed_type;
if ((sde_cfg->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED2) ||
(sde_cfg->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3) ||
(sde_cfg->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3LITE)) {
set_bit(sde_cfg->qseed_sw_lib_rev, &sspp->features);
sblk->scaler_blk.id = sde_cfg->qseed_sw_lib_rev;
sblk->scaler_blk.base = PROP_VALUE_ACCESS(props->values,
VIG_QSEED_OFF, 0);
sblk->scaler_blk.len = PROP_VALUE_ACCESS(props->values,
@@ -1554,10 +1558,10 @@ static int _sde_sspp_setup_rgbs(struct device_node *np,
set_bit(SDE_PERF_SSPP_QOS_8LVL, &sspp->perf_features);
rgb_count++;
if ((sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED2) ||
(sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3)) {
if ((sde_cfg->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED2) ||
(sde_cfg->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3)) {
set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);
sblk->scaler_blk.id = sde_cfg->qseed_type;
sblk->scaler_blk.id = sde_cfg->qseed_sw_lib_rev;
sblk->scaler_blk.base = PROP_VALUE_ACCESS(props->values,
RGB_SCALER_OFF, 0);
sblk->scaler_blk.len = PROP_VALUE_ACCESS(props->values,
@@ -2882,9 +2886,10 @@ static int sde_ds_parse_dt(struct device_node *np,
if (!prop_exists[DS_LEN])
ds->len = DEFAULT_SDE_HW_BLOCK_LEN;
if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3)
if (sde_cfg->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3)
set_bit(SDE_SSPP_SCALER_QSEED3, &ds->features);
else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3LITE)
else if (sde_cfg->qseed_sw_lib_rev ==
SDE_SSPP_SCALER_QSEED3LITE)
set_bit(SDE_SSPP_SCALER_QSEED3LITE, &ds->features);
}
@@ -3726,6 +3731,8 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg,
cfg->pipe_order_type = PROP_VALUE_ACCESS(props->values,
PIPE_ORDER_VERSION, 0);
cfg->has_base_layer = PROP_VALUE_ACCESS(props->values, BASE_LAYER, 0);
cfg->qseed_hw_version = PROP_VALUE_ACCESS(props->values,
QSEED_HW_VERSION, 0);
}
static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
@@ -3787,20 +3794,21 @@ static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)
if (rc)
goto end;
rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type);
rc = of_property_read_string(np, sde_prop[QSEED_SW_LIB_REV].prop_name,
&type);
if (rc) {
SDE_DEBUG("invalid %s node in device tree: %d\n",
sde_prop[QSEED_TYPE].prop_name, rc);
sde_prop[QSEED_SW_LIB_REV].prop_name, rc);
rc = 0;
} else if (!strcmp(type, "qseedv3")) {
cfg->qseed_type = SDE_SSPP_SCALER_QSEED3;
cfg->qseed_sw_lib_rev = SDE_SSPP_SCALER_QSEED3;
} else if (!strcmp(type, "qseedv3lite")) {
cfg->qseed_type = SDE_SSPP_SCALER_QSEED3LITE;
cfg->qseed_sw_lib_rev = SDE_SSPP_SCALER_QSEED3LITE;
} else if (!strcmp(type, "qseedv2")) {
cfg->qseed_type = SDE_SSPP_SCALER_QSEED2;
cfg->qseed_sw_lib_rev = SDE_SSPP_SCALER_QSEED2;
} else {
SDE_DEBUG("Unknown type %s for property %s\n", type,
sde_prop[QSEED_TYPE].prop_name);
sde_prop[QSEED_SW_LIB_REV].prop_name);
}
rc = of_property_read_string(np, sde_prop[CSC_TYPE].prop_name, &type);

8
msm/sde/sde_hw_catalog.h
View File

@@ -674,7 +674,7 @@ enum sde_qos_lut_usage {
* @smart_dma_priority: hw priority of rect1 of multirect pipe
* @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
* @max_per_pipe_bw_high: maximum allowable bandwidth of this pipe in kBps
* in case of no VFE
* in case of no VFE
* @src_blk:
* @scaler_blk:
* @csc_blk:
@@ -1374,7 +1374,6 @@ struct sde_perf_cfg {
* @min_display_width minimum display width support.
* @min_display_height minimum display height support.
* @qseed_type qseed2 or qseed3 support.
* @csc_type csc or csc_10bit support.
* @smart_dma_rev Supported version of SmartDMA feature.
* @ctl_rev supported version of control path.
@@ -1409,6 +1408,8 @@ struct sde_perf_cfg {
* @dither_luma_mode_support Enables dither luma mode
* @has_base_layer Supports staging layer as base layer
* @demura_supported Demura pipe support flag(~0x00 - Not supported)
* @qseed_sw_lib_rev qseed sw library type supporting the qseed hw
* @qseed_hw_version qseed hw version of the target
* @sc_cfg: system cache configuration
* @uidle_cfg Settings for uidle feature
* @sui_misr_supported indicate if secure-ui-misr is supported
@@ -1446,7 +1447,6 @@ struct sde_mdss_cfg {
u32 min_display_width;
u32 min_display_height;
u32 qseed_type;
u32 csc_type;
u32 smart_dma_rev;
u32 ctl_rev;
@@ -1476,6 +1476,8 @@ struct sde_mdss_cfg {
bool has_base_layer;
bool has_demura;
u32 demura_supported[SSPP_MAX][2];
u32 qseed_sw_lib_rev;
u32 qseed_hw_version;
struct sde_sc_cfg sc_cfg[SDE_SYS_CACHE_MAX];

19
msm/sde/sde_hw_ds.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#include "sde_hw_ds.h"
@@ -20,14 +20,6 @@ static void sde_hw_ds_setup_opmode(struct sde_hw_ds *hw_ds,
SDE_REG_WRITE(hw, DEST_SCALER_OP_MODE, op_mode);
}
static u32 _sde_hw_ds_get_scaler3_ver(struct sde_hw_ds *ctx)
{
if (!ctx)
return 0;
return sde_hw_get_scaler3_ver(&ctx->hw, ctx->scl->base);
}
static void sde_hw_ds_setup_scaler3(struct sde_hw_ds *hw_ds,
void *scaler_cfg, void *scaler_lut_cfg)
{
@@ -59,10 +51,8 @@ static void _setup_ds_ops(struct sde_hw_ds_ops *ops, unsigned long features)
ops->setup_opmode = sde_hw_ds_setup_opmode;
if (test_bit(SDE_SSPP_SCALER_QSEED3, &features) ||
test_bit(SDE_SSPP_SCALER_QSEED3LITE, &features)) {
ops->get_scaler_ver = _sde_hw_ds_get_scaler3_ver;
test_bit(SDE_SSPP_SCALER_QSEED3LITE, &features))
ops->setup_scaler = sde_hw_ds_setup_scaler3;
}
}
static struct sde_ds_cfg *_ds_offset(enum sde_ds ds,
@@ -122,9 +112,8 @@ struct sde_hw_ds *sde_hw_ds_init(enum sde_ds idx,
hw_ds->scl = cfg;
_setup_ds_ops(&hw_ds->ops, hw_ds->scl->features);
if (hw_ds->ops.get_scaler_ver)
hw_ds->scl->version = hw_ds->ops.get_scaler_ver(hw_ds);
if (m->qseed_hw_version)
hw_ds->scl->version = m->qseed_hw_version;
rc = sde_hw_blk_init(&hw_ds->base, SDE_HW_BLK_DS, idx, &sde_hw_ops);
if (rc) {

9
msm/sde/sde_hw_ds.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _SDE_HW_DS_H
@@ -58,13 +58,6 @@ struct sde_hw_ds_ops {
void (*setup_scaler)(struct sde_hw_ds *hw_ds,
void *scaler_cfg,
void *scaler_lut_cfg);
/**
* get_scaler_ver - get scaler h/w version
* @ctx: Pointer to ds structure
*/
u32 (*get_scaler_ver)(struct sde_hw_ds *ctx);
};
/**

16
msm/sde/sde_hw_sspp.c
View File

@@ -613,16 +613,6 @@ static void sde_hw_sspp_setup_pre_downscale(struct sde_hw_pipe *ctx,
SDE_REG_WRITE(&ctx->hw, SSPP_PRE_DOWN_SCALE + idx, val);
}
static u32 _sde_hw_sspp_get_scaler3_ver(struct sde_hw_pipe *ctx)
{
u32 idx;
if (!ctx || _sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx))
return 0;
return sde_hw_get_scaler3_ver(&ctx->hw, idx);
}
/**
* sde_hw_sspp_setup_rects()
*/
@@ -1247,7 +1237,6 @@ static void _setup_layer_ops(struct sde_hw_pipe *c,
if (test_bit(SDE_SSPP_SCALER_QSEED3, &features) ||
test_bit(SDE_SSPP_SCALER_QSEED3LITE, &features)) {
c->ops.setup_scaler = _sde_hw_sspp_setup_scaler3;
c->ops.get_scaler_ver = _sde_hw_sspp_get_scaler3_ver;
c->ops.setup_scaler_lut = is_qseed3_rev_qseed3lite(
c->catalog) ? reg_dmav1_setup_scaler3lite_lut
: reg_dmav1_setup_scaler3_lut;
@@ -1346,10 +1335,9 @@ struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
_setup_layer_ops(hw_pipe, hw_pipe->cap->features,
hw_pipe->cap->perf_features, is_virtual_pipe);
if (hw_pipe->ops.get_scaler_ver) {
if (catalog->qseed_hw_version)
sde_init_scaler_blk(&hw_pipe->cap->sblk->scaler_blk,
hw_pipe->ops.get_scaler_ver(hw_pipe));
}
catalog->qseed_hw_version);
rc = sde_hw_blk_init(&hw_pipe->base, SDE_HW_BLK_SSPP, idx, &sde_hw_ops);
if (rc) {

6
msm/sde/sde_hw_sspp.h
View File

@@ -514,12 +514,6 @@ struct sde_hw_sspp_ops {
void (*setup_pre_downscale)(struct sde_hw_pipe *ctx,
struct sde_hw_inline_pre_downscale_cfg *pre_down);
/**
* get_scaler_ver - get scaler h/w version
* @ctx: Pointer to pipe context
*/
u32 (*get_scaler_ver)(struct sde_hw_pipe *ctx);
/**
* setup_sys_cache - setup system cache configuration
* @ctx: Pointer to pipe context

5
msm/sde/sde_hw_util.c
View File

@@ -442,12 +442,7 @@ end:
}
SDE_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode);
}
u32 sde_hw_get_scaler3_ver(struct sde_hw_blk_reg_map *c,
u32 scaler_offset)
{
return SDE_REG_READ(c, QSEED3_HW_VERSION + scaler_offset);
}
void sde_hw_csc_matrix_coeff_setup(struct sde_hw_blk_reg_map *c,

5
msm/sde/sde_hw_util.h
View File

@@ -197,9 +197,6 @@ void sde_hw_setup_scaler3(struct sde_hw_blk_reg_map *c,
struct sde_hw_scaler3_cfg *scaler3_cfg, u32 scaler_version,
u32 scaler_offset, const struct sde_format *format);
u32 sde_hw_get_scaler3_ver(struct sde_hw_blk_reg_map *c,
u32 scaler_offset);
void sde_hw_csc_matrix_coeff_setup(struct sde_hw_blk_reg_map *c,
u32 csc_reg_off, struct sde_csc_cfg *data,
u32 shift_bit);
@@ -220,7 +217,7 @@ uint32_t sde_get_linetime(struct drm_display_mode *mode,
static inline bool is_qseed3_rev_qseed3lite(struct sde_mdss_cfg *sde_cfg)
{
return ((sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3LITE) ?
return ((sde_cfg->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3LITE) ?
true : false);
}
#endif /* _SDE_HW_UTIL_H */

4
msm/sde/sde_plane.c
View File

@@ -3561,9 +3561,9 @@ static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
sde_kms_info_stop(info);
}
if (psde->pipe_hw && psde->pipe_hw->ops.get_scaler_ver)
if (psde->pipe_hw && catalog->qseed_hw_version)
sde_kms_info_add_keyint(info, "scaler_step_ver",
psde->pipe_hw->ops.get_scaler_ver(psde->pipe_hw));
catalog->qseed_hw_version);
sde_kms_info_add_keyint(info, "max_linewidth",
psde->pipe_sblk->maxlinewidth);