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disp: msm: dsi: avoid restoring bit clk & front porches during set mode

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Suppose there's a mode change in  Nth commit and N+1th commit mode
change request for dynamic clock came even before the Nth commit
mode is set in DSI. Now, restoring the bit clock and porches during
mode set of Nth commit will update the clock and porches according
to the new dynamic clock request which should have actually been
handled in N+1th commit mode set and this can lead to DSI underflow
/overflow.

Avoid restoring bit clock during bridge enable as it is already
taken care during bridge mode fixup.

Change-Id: Ieecb0020a77f5e082a8b9da0ecf461acdbe89e0c
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
This commit is contained in:
Anand Tarakh
2023-09-20 10:45:09 +05:30
parent 95b35463ed
commit 21dabac3b4
1 changed files with 0 additions and 6 deletions
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6
msm/dsi/dsi_display.c
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@@ -7805,12 +7805,6 @@ int dsi_display_set_mode(struct dsi_display *display,
}
}
rc = dsi_display_restore_bit_clk(display, &adj_mode);
if (rc) {
DSI_ERR("[%s] bit clk rate cannot be restored\n", display->name);
goto error;
}
rc = dsi_display_validate_mode_set(display, &adj_mode, flags);
if (rc) {
DSI_ERR("[%s] mode cannot be set\n", display->name);