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disp: msm: dp: add DP PHY support for 4nm target

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Changes include support for specific DP PHY
registers and related code changes for 4nm
target.

Change-Id: I9b349e47ff057421fa465a59e1206fd09f7e367a
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
This commit is contained in:
Soutrik Mukhopadhyay
2021-11-22 15:00:34 +05:30
parent ae1d2e9c54
commit 2bc4fbcd94
4 changed files with 62 additions and 12 deletions
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34
msm/dp/dp_catalog.c
View File

@@ -124,6 +124,7 @@ struct dp_catalog_private {
char exe_mode[SZ_4];
u32 dp_core_version;
u32 dp_phy_version;
};
static u32 dp_read_sw(struct dp_catalog_private *catalog,
@@ -452,12 +453,20 @@ static void dp_catalog_aux_get_irq(struct dp_catalog_aux *aux, bool cmd_busy)
static bool dp_catalog_ctrl_wait_for_phy_ready(
struct dp_catalog_private *catalog)
{
u32 reg = DP_PHY_STATUS, state;
u32 phy_version;
u32 reg, state;
void __iomem *base = catalog->io.dp_phy->io.base;
bool success = true;
u32 const poll_sleep_us = 500;
u32 const pll_timeout_us = 10000;
phy_version = dp_catalog_get_dp_phy_version(&catalog->dp_catalog);
if (phy_version >= 60000000) {
reg = DP_PHY_STATUS_V600;
} else {
reg = DP_PHY_STATUS;
}
if (readl_poll_timeout_atomic((base + reg), state,
((state & DP_PHY_READY) > 0),
poll_sleep_us, pll_timeout_us)) {
@@ -1975,6 +1984,29 @@ u32 dp_catalog_get_dp_core_version(struct dp_catalog *dp_catalog)
return dp_read(DP_HW_VERSION);
}
u32 dp_catalog_get_dp_phy_version(struct dp_catalog *dp_catalog)
{
struct dp_catalog_private *catalog;
struct dp_io_data *io_data;
if (!dp_catalog) {
DP_ERR("invalid input\n");
return 0;
}
catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog);
if (catalog->dp_phy_version)
return catalog->dp_phy_version;
io_data = catalog->io.dp_phy;
catalog->dp_phy_version = (dp_read(DP_PHY_REVISION_ID3) << 24) |
(dp_read(DP_PHY_REVISION_ID2) << 16) |
(dp_read(DP_PHY_REVISION_ID1) << 8) |
dp_read(DP_PHY_REVISION_ID0);
return catalog->dp_phy_version;
}
static int dp_catalog_reg_dump(struct dp_catalog *dp_catalog,
char *name, u8 **out_buf, u32 *out_buf_len)
{

1
msm/dp/dp_catalog.h
View File

@@ -337,4 +337,5 @@ struct dp_catalog_sub *dp_catalog_get_v200(struct device *dev,
struct dp_catalog *catalog, struct dp_catalog_io *io);
u32 dp_catalog_get_dp_core_version(struct dp_catalog *dp_catalog);
u32 dp_catalog_get_dp_phy_version(struct dp_catalog *dp_catalog);
#endif /* _DP_CATALOG_H_ */

36
msm/dp/dp_catalog_v420.c
View File

@@ -91,22 +91,33 @@ static void dp_catalog_aux_setup_v420(struct dp_catalog_aux *aux,
struct dp_catalog_private_v420 *catalog;
struct dp_io_data *io_data;
int i = 0;
u32 phy_version;
if (!aux || !cfg) {
DP_ERR("invalid input\n");
return;
}
catalog = dp_catalog_get_priv_v420(aux);
phy_version = dp_catalog_get_dp_phy_version(catalog->dpc);
if (phy_version >= 60000000) {
io_data = catalog->io->dp_phy;
dp_write(DP_PHY_PD_CTL, 0x79);
wmb(); /* make sure PD programming happened */
io_data = catalog->io->dp_phy;
dp_write(DP_PHY_PD_CTL, 0x67);
wmb(); /* make sure PD programming happened */
/* Turn on BIAS current for PHY/PLL */
io_data = catalog->io->dp_pll;
dp_write(QSERDES_COM_BIAS_EN_CLKBUFLR_EN_V600, 0x1D);
wmb(); /* make sure BIAS programming happened */
} else {
io_data = catalog->io->dp_phy;
dp_write(DP_PHY_PD_CTL, 0x67);
wmb(); /* make sure PD programming happened */
/* Turn on BIAS current for PHY/PLL */
io_data = catalog->io->dp_pll;
dp_write(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x17);
wmb(); /* make sure BIAS programming happened */
/* Turn on BIAS current for PHY/PLL */
io_data = catalog->io->dp_pll;
dp_write(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x17);
wmb(); /* make sure BIAS programming happened */
}
io_data = catalog->io->dp_phy;
/* DP AUX CFG register programming */
@@ -126,16 +137,19 @@ static void dp_catalog_aux_clear_hw_int_v420(struct dp_catalog_aux *aux)
struct dp_catalog_private_v420 *catalog;
struct dp_io_data *io_data;
u32 data = 0;
u32 phy_version;
if (!aux) {
DP_ERR("invalid input\n");
return;
}
catalog = dp_catalog_get_priv_v420(aux);
phy_version = dp_catalog_get_dp_phy_version(catalog->dpc);
io_data = catalog->io->dp_phy;
data = dp_read(DP_PHY_AUX_INTERRUPT_STATUS_V420);
if (phy_version >= 60000000)
data = dp_read(DP_PHY_AUX_INTERRUPT_STATUS_V600);
else
data = dp_read(DP_PHY_AUX_INTERRUPT_STATUS_V420);
dp_write(DP_PHY_AUX_INTERRUPT_CLEAR_V420, 0x1f);
wmb(); /* make sure 0x1f is written before next write */

3
msm/dp/dp_reg.h
View File

@@ -378,9 +378,11 @@
#define TXn_HIGHZ_DRVR_EN (0x0060)
#define DP_PHY_STATUS (0x00DC)
#define DP_PHY_STATUS_V600 (0x00E4)
#define DP_PHY_AUX_INTERRUPT_MASK_V420 (0x0054)
#define DP_PHY_AUX_INTERRUPT_CLEAR_V420 (0x0058)
#define DP_PHY_AUX_INTERRUPT_STATUS_V420 (0x00D8)
#define DP_PHY_AUX_INTERRUPT_STATUS_V600 (0x00E0)
#define DP_PHY_SPARE0_V420 (0x00C8)
#define TXn_TX_DRV_LVL_V420 (0x0014)
#define TXn_TRANSCEIVER_BIAS_EN_V420 (0x0054)
@@ -388,6 +390,7 @@
#define TXn_TX_POL_INV_V420 (0x005C)
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN (0x044)
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN_V600 (0x0DC)
/* DP MMSS_CC registers */
#define MMSS_DP_PIXEL_M (0x01B4)