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Merge 5215f2a6dd on remote branch

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Change-Id: Ie73340811ca6428287de369c87662de5912f1647
This commit is contained in:
Linux Build Service Account
2023-04-18 10:24:31 -07:00
parent 145f965b5e 5215f2a6dd
commit adb0083d20
10 changed files with 207 additions and 66 deletions
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17
msm/dp/dp_mst_drm.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
*/
@@ -1165,6 +1165,7 @@ static int dp_mst_connector_atomic_check(struct drm_connector *connector,
void *display, struct drm_atomic_state *state)
{
int rc = 0, slots, i;
bool vcpi_released = false;
struct drm_connector_state *old_conn_state;
struct drm_connector_state *new_conn_state;
struct drm_crtc *old_crtc;
@@ -1204,8 +1205,8 @@ static int dp_mst_connector_atomic_check(struct drm_connector *connector,
bridge->num_slots);
}
/* do not attempt to release vcpi slots if crtc state is enable */
if (drm_atomic_crtc_needs_modeset(crtc_state) && !crtc_state->enable) {
/*attempt to release vcpi slots on a modeset change for crtc state*/
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
if (WARN_ON(!old_conn_state->best_encoder)) {
rc = -EINVAL;
goto end;
@@ -1239,6 +1240,7 @@ static int dp_mst_connector_atomic_check(struct drm_connector *connector,
slots, rc);
goto end;
}
vcpi_released = true;
}
bridge_state->num_slots = 0;
@@ -1284,6 +1286,15 @@ mode_set:
goto end;
}
/*
* check if vcpi slots are trying to get allocated in same phase
* as deallocation. If so, go to end to avoid allocation.
*/
if (vcpi_released) {
DP_WARN("skipping allocation since vcpi was released in the same state \n");
goto end;
}
if (WARN_ON(bridge_state->num_slots)) {
rc = -EINVAL;
goto end;

23
msm/dsi/dsi_clk.h
View File

@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/
@@ -301,6 +302,15 @@ int dsi_display_clk_ctrl(void *handle, u32 clk_type, u32 clk_state);
int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq,
u32 index);
/**
* dsi_clk_get_link_frequencies() - get link clk frequencies
* @link_freq: Structure to get link clock frequencies
* @client: DSI clock client pointer.
* @index: Index of the DSI controller.
*
* return: error code in case of failure or 0 for success.
*/
int dsi_clk_get_link_frequencies(struct link_clk_freq *link_freq, void *client, u32 index);
/**
* dsi_clk_set_pixel_clk_rate() - set frequency for pixel_clk
@@ -311,7 +321,6 @@ int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq,
*/
int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index);
/**
* dsi_clk_set_byte_clk_rate() - set frequency for byte clock
* @client: DSI clock client pointer.
@@ -351,4 +360,16 @@ void dsi_clk_disable_unprepare(struct dsi_clk_link_set *clk);
*/
int dsi_display_dump_clk_handle_state(void *client);
/**
* dsi_clk_acquire_mngr_lock() - acquire clk manager mutex lock
* @client: DSI clock client pointer.
*/
void dsi_clk_acquire_mngr_lock(void *client);
/**
* dsi_clk_release_mngr_lock() - release clk manager mutex lock
* @client: DSI clock client pointer.
*/
void dsi_clk_release_mngr_lock(void *client);
#endif /* _DSI_CLK_H_ */

54
msm/dsi/dsi_clk_manager.c
View File

@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/
@@ -104,6 +105,30 @@ int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq,
return rc;
}
/**
* dsi_clk_get_link_frequencies() - get link clk frequencies
* @link_freq: Structure to get link clock frequencies
* @client: DSI clock client pointer.
* @index: Index of the DSI controller.
*
* return: error code in case of failure or 0 for success.
*/
int dsi_clk_get_link_frequencies(struct link_clk_freq *link_freq, void *client, u32 index)
{
struct dsi_clk_client_info *c = client;
struct dsi_clk_mngr *mngr;
if (!client || !link_freq) {
DSI_ERR("invalid params\n");
return -EINVAL;
}
mngr = c->mngr;
memcpy(link_freq, &mngr->link_clks[index].freq, sizeof(struct link_clk_freq));
return 0;
}
/**
* dsi_clk_set_pixel_clk_rate() - set frequency for pixel clock
* @clks: DSI link clock information.
@@ -1214,7 +1239,8 @@ int dsi_clk_req_state(void *client, enum dsi_clk_type clk,
if (changed) {
rc = dsi_recheck_clk_state(mngr);
if (rc)
DSI_ERR("Failed to adjust clock state rc = %d\n", rc);
DSI_ERR("[%s]%s: failed to adjust clock state rc = %d\n",
mngr->name, c->name, rc);
}
mutex_unlock(&mngr->clk_mutex);
@@ -1491,3 +1517,29 @@ int dsi_display_clk_mngr_deregister(void *clk_mngr)
kfree(mngr);
return rc;
}
/**
* dsi_clk_acquire_mngr_lock() - acquire clk manager mutex lock
* @client: DSI clock client pointer.
*/
void dsi_clk_acquire_mngr_lock(void *client)
{
struct dsi_clk_mngr *mngr;
struct dsi_clk_client_info *c = client;
mngr = c->mngr;
mutex_lock(&mngr->clk_mutex);
}
/**
* dsi_clk_release_mngr_lock() - release clk manager mutex lock
* @client: DSI clock client pointer.
*/
void dsi_clk_release_mngr_lock(void *client)
{
struct dsi_clk_mngr *mngr;
struct dsi_clk_client_info *c = client;
mngr = c->mngr;
mutex_unlock(&mngr->clk_mutex);
}

7
msm/dsi/dsi_ctrl.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/
@@ -1104,11 +1104,6 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
dsi_ctrl->clk_freq.pix_clk_rate = pclk_rate;
dsi_ctrl->clk_freq.esc_clk_rate = config->esc_clk_rate_hz;
rc = dsi_clk_set_link_frequencies(clk_handle, dsi_ctrl->clk_freq,
dsi_ctrl->cell_index);
if (rc)
DSI_CTRL_ERR(dsi_ctrl, "Failed to update link frequencies\n");
return rc;
}

66
msm/dsi/dsi_display.c
View File

@@ -2826,7 +2826,7 @@ int dsi_display_phy_configure(void *priv, bool commit)
struct dsi_display *display = priv;
struct dsi_display_ctrl *m_ctrl;
struct dsi_pll_resource *pll_res;
struct dsi_ctrl *ctrl;
struct link_clk_freq link_freq;
if (!display) {
DSI_ERR("invalid arguments\n");
@@ -2848,9 +2848,15 @@ int dsi_display_phy_configure(void *priv, bool commit)
return -EINVAL;
}
ctrl = m_ctrl->ctrl;
pll_res->byteclk_rate = ctrl->clk_freq.byte_clk_rate;
pll_res->pclk_rate = ctrl->clk_freq.pix_clk_rate;
rc = dsi_clk_get_link_frequencies(&link_freq, display->dsi_clk_handle,
display->clk_master_idx);
if (rc) {
DSI_ERR("Failed to get link frequencies\n");
return rc;
}
pll_res->byteclk_rate = link_freq.byte_clk_rate;
pll_res->pclk_rate = link_freq.pix_clk_rate;
rc = dsi_phy_configure(m_ctrl->phy, commit);
@@ -4458,6 +4464,26 @@ void dsi_display_update_byte_intf_div(struct dsi_display *display)
config->byte_intf_clk_div = 2;
}
static int dsi_display_set_link_frequencies(struct dsi_display *display)
{
int rc = 0, i = 0;
dsi_clk_acquire_mngr_lock(display->dsi_clk_handle);
display_for_each_ctrl(i, display) {
struct dsi_display_ctrl *ctrl = &display->ctrl[i];
rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle, ctrl->ctrl->clk_freq, i);
if (rc) {
DSI_ERR("Failed to update link frequencies of ctrl_%d, rc=%d\n", i, rc);
dsi_clk_release_mngr_lock(display->dsi_clk_handle);
return rc;
}
}
dsi_clk_release_mngr_lock(display->dsi_clk_handle);
return rc;
}
static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
u32 bit_clk_rate)
{
@@ -4540,12 +4566,6 @@ static int dsi_display_update_dsi_bitrate(struct dsi_display *display,
ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
ctrl->clk_freq.pix_clk_rate = pclk_rate;
rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle,
ctrl->clk_freq, ctrl->cell_index);
if (rc) {
DSI_ERR("Failed to update link frequencies\n");
goto error;
}
ctrl->host_config.bit_clk_rate_hz = bit_clk_rate;
error:
@@ -4556,6 +4576,12 @@ error:
return rc;
}
rc = dsi_display_set_link_frequencies(display);
if (rc) {
DSI_ERR("Failed to set display link frequencies\n");
return rc;
}
return 0;
}
@@ -5210,6 +5236,15 @@ static int dsi_display_set_mode_sub(struct dsi_display *display,
}
}
if (!(mode->dsi_mode_flags & (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
DSI_MODE_FLAG_DYN_CLK))) {
rc = dsi_display_set_link_frequencies(display);
if (rc) {
DSI_ERR("Failed to set display link frequencies\n");
goto error;
}
}
if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
(display->panel->panel_mode == DSI_OP_CMD_MODE)) {
u64 cur_bitclk = display->panel->cur_mode->timing.clk_rate_hz;
@@ -5279,7 +5314,7 @@ static int _dsi_display_dev_init(struct dsi_display *display)
rc = dsi_display_res_init(display);
if (rc) {
DSI_ERR("[%s] failed to initialize resources, rc=%d\n",
display->name, rc);
display->name, rc);
goto error;
}
error:
@@ -5896,7 +5931,7 @@ static int dsi_display_init(struct dsi_display *display)
rc = _dsi_display_dev_init(display);
if (rc) {
DSI_ERR("device init failed, rc=%d\n", rc);
DSI_ERR("device init failed for %s, rc=%d\n", display->display_type, rc);
goto end;
}
@@ -7408,6 +7443,13 @@ int dsi_display_update_transfer_time(void *display, u32 transfer_time)
return rc;
}
}
rc = dsi_display_set_link_frequencies(disp);
if (rc) {
DSI_ERR("Failed to set display link frequencies\n");
return rc;
}
atomic_set(&disp->clkrate_change_pending, 1);
return 0;

3
msm/sde/sde_color_processing.c
View File

@@ -2243,9 +2243,6 @@ void sde_cp_crtc_apply_properties(struct drm_crtc *crtc)
}
_sde_cp_flush_properties(crtc);
if (!sde_crtc->enabled)
return;
mutex_lock(&sde_crtc->crtc_cp_lock);
_sde_clear_ltm_merge_mode(sde_crtc);

15
msm/sde/sde_crtc.c
View File

@@ -4231,9 +4231,6 @@ static void _sde_crtc_atomic_begin(struct drm_crtc *crtc,
if (sde_kms_is_cp_operation_allowed(sde_kms))
sde_cp_crtc_apply_properties(crtc);
if (!sde_crtc->enabled)
sde_cp_crtc_mark_features_dirty(crtc);
/*
* PP_DONE irq is only used by command mode for now.
* It is better to request pending before FLUSH and START trigger
@@ -6665,6 +6662,16 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
vfree(info);
}
static bool _is_crtc_intf_mode_wb(struct drm_crtc *crtc)
{
enum sde_intf_mode intf_mode = sde_crtc_get_intf_mode(crtc, crtc->state);
if ((intf_mode != INTF_MODE_WB_BLOCK) && (intf_mode != INTF_MODE_WB_LINE))
return false;
return true;
}
static int _sde_crtc_get_output_fence(struct drm_crtc *crtc,
const struct drm_crtc_state *state, uint64_t *val)
{
@@ -7208,7 +7215,7 @@ static ssize_t _sde_debugfs_hw_fence_features_mask_wr(struct file *file,
{
struct sde_crtc *sde_crtc;
u32 bit, enable;
char buf[10];
char buf[25];
if (!file || !file->private_data)
return -EINVAL;

10
msm/sde/sde_crtc.h
View File

@@ -957,16 +957,6 @@ static inline bool sde_crtc_state_in_clone_mode(struct drm_encoder *encoder,
return false;
}
static inline bool _is_crtc_intf_mode_wb(struct drm_crtc *crtc)
{
enum sde_intf_mode intf_mode = sde_crtc_get_intf_mode(crtc, crtc->state);
if ((intf_mode != INTF_MODE_WB_BLOCK) && (intf_mode != INTF_MODE_WB_LINE))
return false;
return true;
}
/**
* sde_crtc_get_ds_io_res - populates the destination scaler src/dst w/h
* @state: pointer to drm crtc state

56
msm/sde/sde_encoder.c
View File

@@ -1986,8 +1986,10 @@ static void _sde_encoder_rc_restart_delayed(struct sde_encoder_virt *sde_enc,
{
struct drm_encoder *drm_enc = &sde_enc->base;
struct msm_drm_private *priv;
unsigned int lp, idle_pc_duration;
unsigned int lp, idle_pc_duration, frame_time_ms, fps;
struct msm_drm_thread *disp_thread;
unsigned int min_duration = IDLE_POWERCOLLAPSE_DURATION;
unsigned int max_duration = IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP;
/* return early if called from esd thread */
if (sde_enc->delay_kickoff)
@@ -2000,10 +2002,15 @@ static void _sde_encoder_rc_restart_delayed(struct sde_encoder_virt *sde_enc,
else
lp = SDE_MODE_DPMS_ON;
fps = sde_enc->mode_info.frame_rate;
if ((lp == SDE_MODE_DPMS_LP1) || (lp == SDE_MODE_DPMS_LP2))
idle_pc_duration = IDLE_SHORT_TIMEOUT;
else
idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
else {
frame_time_ms = 1000;
do_div(frame_time_ms, fps);
idle_pc_duration = max(4 * frame_time_ms, min_duration);
idle_pc_duration = min(idle_pc_duration, max_duration);
}
priv = drm_enc->dev->dev_private;
disp_thread = &priv->disp_thread[sde_enc->crtc->index];
@@ -2272,11 +2279,18 @@ static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
struct msm_drm_private *priv;
struct sde_kms *sde_kms;
struct drm_crtc *crtc = drm_enc->crtc;
struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
struct sde_crtc *sde_crtc;
struct sde_connector *sde_conn;
int crtc_id = 0;
priv = drm_enc->dev->dev_private;
if (!crtc || !sde_enc->cur_master || !priv->kms) {
SDE_ERROR("invalid args crtc:%d master:%d\n", !crtc, !sde_enc->cur_master);
return -EINVAL;
}
sde_crtc = to_sde_crtc(crtc);
sde_kms = to_sde_kms(priv->kms);
sde_conn = to_sde_connector(sde_enc->cur_master->connector);
@@ -2301,11 +2315,12 @@ static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
}
crtc_id = drm_crtc_index(crtc);
/**
/*
* Avoid power collapse entry for writeback crtc since HAL does not repopulate
* crtc, plane properties like luts for idlepc exit commit.
* crtc, plane properties like luts for idlepc exit commit. Here is_vid_mode will
* represents video mode panels and wfd baring CWB.
*/
if (is_vid_mode || _is_crtc_intf_mode_wb(crtc)) {
if (is_vid_mode) {
sde_encoder_irq_control(drm_enc, false);
_sde_encoder_pm_qos_remove_request(drm_enc);
} else {
@@ -2336,7 +2351,7 @@ static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
{
bool autorefresh_enabled = false;
struct msm_drm_thread *disp_thread;
int ret = 0;
int ret = 0, idle_pc_duration = 0;
if (!sde_enc->crtc ||
sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
@@ -2364,11 +2379,14 @@ static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
goto end;
}
if (!sde_crtc_frame_pending(sde_enc->crtc))
if (!sde_crtc_frame_pending(sde_enc->crtc)) {
kthread_mod_delayed_work(&disp_thread->worker,
&sde_enc->delayed_off_work,
msecs_to_jiffies(
IDLE_POWERCOLLAPSE_DURATION));
idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
}
} else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
/* enable all the clks and resources */
ret = _sde_encoder_resource_control_helper(drm_enc,
@@ -2396,12 +2414,13 @@ static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
&sde_enc->delayed_off_work,
msecs_to_jiffies(
IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
idle_pc_duration = IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP;
sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
}
SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state, SDE_ENC_RC_STATE_ON,
idle_pc_duration, SDE_EVTLOG_FUNC_CASE8);
end:
mutex_unlock(&sde_enc->rc_lock);
@@ -2423,8 +2442,10 @@ static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
}
sde_enc = to_sde_encoder_virt(drm_enc);
priv = drm_enc->dev->dev_private;
if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
is_vid_mode = true;
/* is_vid_mode represents vid mode panel and WFD for clocks and irq control. */
is_vid_mode = !((sde_encoder_get_intf_mode(drm_enc) == INTF_MODE_CMD) ||
sde_encoder_in_clone_mode(drm_enc));
/*
* when idle_pc is not supported, process only KICKOFF, STOP and MODESET
* events and return early for other events (ie wb display).
@@ -4443,8 +4464,13 @@ static void sde_encoder_input_event_work_handler(struct kthread_work *work)
struct sde_encoder_virt *sde_enc = container_of(work,
struct sde_encoder_virt, input_event_work);
if (!sde_enc) {
SDE_ERROR("invalid sde encoder\n");
if (!sde_enc || !sde_enc->input_handler) {
SDE_ERROR("invalid args sde encoder\n");
return;
}
if (!sde_enc->input_handler->private) {
SDE_DEBUG_ENC(sde_enc, "input handler is unregistered\n");
return;
}

22
msm/sde/sde_encoder_phys_wb.c
View File

@@ -35,10 +35,6 @@ static const u32 cwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, INTR_IDX_PP1_OVFL,
INTR_IDX_PP2_OVFL, INTR_IDX_PP3_OVFL, INTR_IDX_PP4_OVFL,
INTR_IDX_PP5_OVFL, SDE_NONE, SDE_NONE};
static const u32 dcwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, SDE_NONE,
SDE_NONE, SDE_NONE, SDE_NONE, SDE_NONE,
INTR_IDX_PP_CWB_OVFL, SDE_NONE};
/**
* sde_rgb2yuv_601l - rgb to yuv color space conversion matrix
*
@@ -1717,6 +1713,7 @@ static void sde_encoder_phys_wb_irq_ctrl(struct sde_encoder_phys *phys, bool ena
int index = 0, pp = 0;
u32 max_num_of_irqs = 0;
const u32 *irq_table = NULL;
enum sde_intr_idx intr_idx;
if (!wb_enc)
return;
@@ -1735,7 +1732,6 @@ static void sde_encoder_phys_wb_irq_ctrl(struct sde_encoder_phys *phys, bool ena
wb_cfg = wb_enc->hw_wb->caps;
if (wb_cfg->features & BIT(SDE_WB_HAS_DCWB)) {
max_num_of_irqs = 1;
irq_table = dcwb_irq_tbl;
} else {
max_num_of_irqs = CRTC_DUAL_MIXERS_ONLY;
irq_table = cwb_irq_tbl;
@@ -1748,9 +1744,11 @@ static void sde_encoder_phys_wb_irq_ctrl(struct sde_encoder_phys *phys, bool ena
if (test_bit(SDE_WB_PROG_LINE, &wb_cfg->features))
sde_encoder_helper_register_irq(phys, INTR_IDX_WB_LINEPTR);
for (index = 0; index < max_num_of_irqs; index++)
if (irq_table[index + pp] != SDE_NONE)
sde_encoder_helper_register_irq(phys, irq_table[index + pp]);
for (index = 0; index < max_num_of_irqs; index++) {
intr_idx = irq_table ? irq_table[index + pp] : INTR_IDX_PP_CWB_OVFL;
if (intr_idx != SDE_NONE)
sde_encoder_helper_register_irq(phys, intr_idx);
}
} else if (!enable && atomic_dec_return(&phys->wbirq_refcount) == 0) {
sde_encoder_helper_unregister_irq(phys, INTR_IDX_WB_DONE);
sde_encoder_helper_unregister_irq(phys, INTR_IDX_CTL_START);
@@ -1758,9 +1756,11 @@ static void sde_encoder_phys_wb_irq_ctrl(struct sde_encoder_phys *phys, bool ena
if (test_bit(SDE_WB_PROG_LINE, &wb_cfg->features))
sde_encoder_helper_unregister_irq(phys, INTR_IDX_WB_LINEPTR);
for (index = 0; index < max_num_of_irqs; index++)
if (irq_table[index + pp] != SDE_NONE)
sde_encoder_helper_unregister_irq(phys, irq_table[index + pp]);
for (index = 0; index < max_num_of_irqs; index++) {
intr_idx = irq_table ? irq_table[index + pp] : INTR_IDX_PP_CWB_OVFL;
if (intr_idx != SDE_NONE)
sde_encoder_helper_unregister_irq(phys, intr_idx);
}
}
}