anierin/display-drivers
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge "disp: msm: sde: fix the wd-timer-ctrl config for WD TE"

Browse Source
This commit is contained in:
qctecmdr
2022-03-01 23:14:43 -08:00
committed by Gerrit - the friendly Code Review server
parent 90bfd286b6 e55c68138b
commit e62a6512a1
1 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
msm/sde/sde_hw_intf.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/ */
@@ -459,7 +459,7 @@ static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf,
u32 frame_rate) u32 frame_rate)
{ {
struct sde_hw_blk_reg_map *c; struct sde_hw_blk_reg_map *c;
u32 reg; u32 reg = 0;
if (!intf) if (!intf)
return; return;
@@ -469,9 +469,9 @@ static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf,
SDE_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE, CALCULATE_WD_LOAD_VALUE(frame_rate)); SDE_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE, CALCULATE_WD_LOAD_VALUE(frame_rate));
SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */ SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */
reg = SDE_REG_READ(c, INTF_WD_TIMER_0_CTL2);
reg |= BIT(8); /* enable heartbeat timer */ reg |= BIT(8); /* enable heartbeat timer */
reg |= BIT(0); /* enable WD timer */ reg |= BIT(0); /* enable WD timer */
reg |= BIT(1); /* select default 16 clock ticks */
SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL2, reg); SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL2, reg);
/* make sure that timers are enabled/disabled for vsync state */ /* make sure that timers are enabled/disabled for vsync state */