45439a9ef4
Currently, we are always initializing PLL registers whenever PLL is configured. Re-initializing PLL registers during dynamic clock switch in case of cphy video mode is moving the PLL to some bad state resulting in display freeze. Avoid this by restricting initialization of PLL registers to only while turning on the PLL. This change is for 4nm PLL. Change-Id: I57c8cfe1927f83f1ac25238c696a606960f3a8c8 Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>