a26fe8667dffcc453da477f36a05679a21dce374
DSI PHY has various resets defined to reset analog, PLL and digital portions. In current sequence, these resets happen after PLL is locked which can result in introduction of jitter on PHY lanes.Reordering these resets to happen before PLL is programmed to have intended clean start of DSI PHY. Change-Id: I4eb5c05ea0e6015a5447728b2845b49817411c50 Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
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