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Aravind Venkateswaran acfd32f1b5 disp: pll: fix flags for DSI and DP PLL clocks

Remove the CLK_GET_RATE_NOCACHE flag from all the DP and DSI
pll clocks. This will eliminate the need to recalculate the
clock rates from HW registers when querying the rates for the
PLL clocks. This will ensure that no unclocked register accesses
are done when these clocks are queried while the display core
is power collapsed.

Change-Id: Ia5e993195cadc2bced32c052bb604e9980ecd4d8
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>

2019-04-23 16:54:41 -07:00

config

Display drivers kernel project initial snapshot

2019-04-14 22:20:59 -07:00

msm

disp: avoid encoder-connector checks with cont-splash

2019-04-14 22:21:13 -07:00

pll

disp: pll: fix flags for DSI and DP PLL clocks

2019-04-23 16:54:41 -07:00

rotator

Display drivers kernel project initial snapshot