f8e7d9d5d1addd7f17ab3bbcd4acc8f7ebb4ef13
As per current design misr enable sequence is happening at atomic check level. At this state, misr configuration may reset if clocks are enabled through atomic commit sequence. This change moves misr enable/disable sequence from debugfs context to encoder kickoff to avoid misr register reset with idle pc. Change-Id: Ia4faa200f96b76ba8c7ef3f45a26108e34b5e687 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
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