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pci: msm: Correct link width setting to PCIE20_CAP and GEN2_CTRL_OFF

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As per databook, when there are unused lanes in a system, you must
reprogram the following registers through the DBI. For this example, where
a 4-lane controller is connected to a 1-lane PHY:

1. Reprogram LINK_CAPABLE field of the PORT_LINK_CTRL_OFF register to 6h1
from 6h7. This is used by the LTSSM in Detect.

2. Reprogram NUM_OF_LANES[8:0] field of the GEN2_CTRL_OFF register to 9h1
from 9h4. This indicates to the LTSSM, the number of lanes to check for
exiting from L2.Idle or Polling.Active.

3. Reprogram PCIE_CAP_MAX_LINK_WIDTH field of the LINK_CAPABILITIES_REG
register to 6h1 from 6h4. This enables the RP to determine the Maximum
Link Width for this port.

We should not set link_width to PCIE20_CAP and GEN2_CTRL_OFF, but should
set the target_link_width. NUM_OF_LANES[8:0] field is recommended to set
as LINK_WIDTH_X1 even if there are more one lane.

Change-Id: I7b32160d6582b6ddc65d860b5e58f6ec77baf48d
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
This commit is contained in:
Qiang Yu
2023-12-11 18:26:17 +08:00
parent 2278fa4806
commit 6c873fcda8
1 changed files with 8 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/pci/controller/pci-msm.c
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@@ -8005,11 +8005,15 @@ static int msm_pcie_set_link_width(struct msm_pcie_dev_t *pcie_dev,
LINK_WIDTH_MASK << LINK_WIDTH_SHIFT,
link_width);
/* Set NUM_OF_LANES in GEN2_CTRL_OFF */
/*
* It's advisable to set NUM_OF_LANES[8:0] field to 0x1. It allows
* establishing connection on one line even if there is a termination
* on the second line. Otherwise the link will go to compliance.
*/
msm_pcie_write_reg_field(pcie_dev->dm_core,
PCIE_GEN3_GEN2_CTRL,
NUM_OF_LANES_MASK << NUM_OF_LANES_SHIFT,
link_width);
LINK_WIDTH_X1);
/* enable write access to RO register */
msm_pcie_write_mask(pcie_dev->dm_core + PCIE_GEN3_MISC_CONTROL, 0,
@@ -8017,7 +8021,8 @@ static int msm_pcie_set_link_width(struct msm_pcie_dev_t *pcie_dev,
/* Set Maximum link width as current width */
msm_pcie_write_reg_field(pcie_dev->dm_core, PCIE20_CAP + PCI_EXP_LNKCAP,
PCI_EXP_LNKCAP_MLW, link_width);
PCI_EXP_LNKCAP_MLW,
target_link_width >> PCI_EXP_LNKSTA_NLW_SHIFT);
/* disable write access to RO register */
msm_pcie_write_mask(pcie_dev->dm_core + PCIE_GEN3_MISC_CONTROL, BIT(0),