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Merge "clk: qcom: sdm845: Update the support for clock controllers"

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This commit is contained in:
qctecmdr
2023-12-26 04:29:06 -08:00
committed by Gerrit - the friendly Code Review server
parent 897561d96a 77709cd1bf
commit e3a0e2f01a
7 changed files with 2400 additions and 463 deletions
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18
drivers/clk/qcom/Kconfig
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@@ -460,13 +460,6 @@ config SC_VIDEOCC_7280
Say Y if you want to support video devices and functionality such as
video encode and decode.
config SDM_CAMCC_845
tristate "SDM845 Camera Clock Controller"
select SDM_GCC_845
help
Support for the camera clock controller on SDM845 devices.
Say Y if you want to support camera devices and camera functionality.
config SDM_GCC_660
tristate "SDM660 Global Clock Controller"
select QCOM_GDSC
@@ -507,9 +500,18 @@ config QCS_Q6SSTOP_404
Say Y if you want to use the Q6SSTOP branch clocks of the WCSS clock
controller to reset the Q6SSTOP subsystem.
config SDM_CAMCC_845
tristate "SDM845 Camera Clock Controller"
select SDM_GCC_845
help
Support for the camera clock controller on Qualcomm Technologies, Inc
SDM845 devices.
Say Y if you want to support camera devices and functionality such as
capturing pictures.
config SDM_GCC_845
tristate "SDM845 Global Clock Controller"
select QCOM_GDSC
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on SDM845 devices.
Say Y if you want to use peripheral devices such as UART, SPI,

771
drivers/clk/qcom/camcc-sdm845.c
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File diff suppressed because it is too large Load Diff

264
drivers/clk/qcom/dispcc-sdm845.c
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@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk.h>
@@ -19,6 +20,13 @@
#include "common.h"
#include "gdsc.h"
#include "reset.h"
#include "vdd-level-sdm845.h"
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
static struct clk_vdd_class *disp_cc_sdm845_regulators[] = {
&vdd_cx,
};
enum {
P_BI_TCXO,
@@ -33,18 +41,34 @@ enum {
P_DP_PHY_PLL_VCO_DIV_CLK,
};
static struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
{ 125000000, 1000000000, 1 },
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000 },
},
},
};
@@ -55,7 +79,7 @@ static const struct parent_map disp_cc_parent_map_0[] = {
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
{ .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
};
@@ -67,7 +91,7 @@ static const struct parent_map disp_cc_parent_map_1[] = {
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dp_link_clk_divsel_ten", .name = "dp_link_clk_divsel_ten" },
{ .fw_name = "dp_vco_divided_clk_src_mux", .name = "dp_vco_divided_clk_src_mux" },
};
@@ -77,7 +101,7 @@ static const struct parent_map disp_cc_parent_map_2[] = {
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
@@ -88,7 +112,7 @@ static const struct parent_map disp_cc_parent_map_3[] = {
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .fw_name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src" },
{ .fw_name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src" },
@@ -101,7 +125,7 @@ static const struct parent_map disp_cc_parent_map_4[] = {
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
{ .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" },
};
@@ -119,6 +143,16 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000,
[VDD_LOWER] = 150000000,
[VDD_LOW] = 240000000,
[VDD_LOW_L1] = 262500000,
[VDD_NOMINAL] = 358000000 },
},
};
/* Return the HW recalc rate for idle use case */
@@ -134,6 +168,16 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000,
[VDD_LOWER] = 150000000,
[VDD_LOW] = 240000000,
[VDD_LOW_L1] = 262500000,
[VDD_NOMINAL] = 358000000 },
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
@@ -154,6 +198,12 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000 },
},
};
static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
@@ -165,8 +215,19 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 12800000,
[VDD_LOWER] = 108000000,
[VDD_LOW] = 180000000,
[VDD_LOW_L1] = 360000000,
[VDD_NOMINAL] = 540000000 },
},
};
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
@@ -181,6 +242,16 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000,
[VDD_LOWER] = 162000000,
[VDD_LOW] = 270000000,
[VDD_LOW_L1] = 540000000,
[VDD_NOMINAL] = 810000000 },
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
@@ -195,6 +266,15 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000,
[VDD_LOWER] = 202500000,
[VDD_LOW] = 296735000,
[VDD_LOW_L1] = 675000000 },
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
@@ -209,6 +289,15 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000,
[VDD_LOWER] = 202500000,
[VDD_LOW] = 296735000,
[VDD_LOW_L1] = 675000000 },
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
@@ -226,8 +315,15 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000 },
},
};
static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
@@ -242,15 +338,35 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000 },
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(165000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(275000000, P_DISP_CC_PLL0_OUT_MAIN, 1.5, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(412500000, P_DISP_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sdm670[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(286666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
@@ -267,8 +383,18 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000,
[VDD_LOWER] = 165000000,
[VDD_LOW] = 300000000,
[VDD_NOMINAL] = 412500000 },
},
};
/* Return the HW recalc rate for idle use case */
@@ -284,6 +410,16 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000,
[VDD_LOWER] = 184000000,
[VDD_LOW] = 295000000,
[VDD_LOW_L1] = 350000000,
[VDD_NOMINAL] = 571428571 },
},
};
/* Return the HW recalc rate for idle use case */
@@ -299,9 +435,27 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000,
[VDD_LOWER] = 184000000,
[VDD_LOW] = 295000000,
[VDD_LOW_L1] = 350000000,
[VDD_NOMINAL] = 571428571 },
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(165000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(412500000, P_DISP_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src_sdm670[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
@@ -320,8 +474,18 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000,
[VDD_LOWER] = 165000000,
[VDD_LOW] = 300000000,
[VDD_NOMINAL] = 412500000 },
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
@@ -334,8 +498,15 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 19200000 },
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
@@ -829,7 +1000,7 @@ static const struct regmap_config disp_cc_sdm845_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sdm845_desc = {
static struct qcom_cc_desc disp_cc_sdm845_desc = {
.config = &disp_cc_sdm845_regmap_config,
.clks = disp_cc_sdm845_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sdm845_clocks),
@@ -837,23 +1008,86 @@ static const struct qcom_cc_desc disp_cc_sdm845_desc = {
.num_resets = ARRAY_SIZE(disp_cc_sdm845_resets),
.gdscs = disp_cc_sdm845_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sdm845_gdscs),
.clk_regulators = disp_cc_sdm845_regulators,
.num_clk_regulators = ARRAY_SIZE(disp_cc_sdm845_regulators),
};
static const struct of_device_id disp_cc_sdm845_match_table[] = {
{ .compatible = "qcom,sdm845-dispcc" },
{ .compatible = "qcom,sdm670-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sdm845_match_table);
static void disp_cc_sdm845_fixup_sdm670(void)
{
disp_cc_mdss_byte0_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] =
180000000;
disp_cc_mdss_byte0_clk_src.clkr.vdd_data.rate_max[VDD_LOW] =
275000000;
disp_cc_mdss_byte0_clk_src.clkr.vdd_data.rate_max[VDD_LOW_L1] =
358000000;
disp_cc_mdss_byte1_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] =
180000000;
disp_cc_mdss_byte1_clk_src.clkr.vdd_data.rate_max[VDD_LOW] =
275000000;
disp_cc_mdss_byte1_clk_src.clkr.vdd_data.rate_max[VDD_LOW_L1] =
358000000;
disp_cc_mdss_dp_pixel1_clk_src.clkr.vdd_data.rate_max[VDD_LOW] =
337500000;
disp_cc_mdss_dp_pixel_clk_src.clkr.vdd_data.rate_max[VDD_LOW] =
337500000;
disp_cc_mdss_mdp_clk_src.freq_tbl =
ftbl_disp_cc_mdss_mdp_clk_src_sdm670;
disp_cc_mdss_mdp_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] =
171428571;
disp_cc_mdss_mdp_clk_src.clkr.vdd_data.rate_max[VDD_LOW_L1] =
344000000;
disp_cc_mdss_mdp_clk_src.clkr.vdd_data.rate_max[VDD_NOMINAL] =
430000000;
disp_cc_mdss_pclk0_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] =
280000000;
disp_cc_mdss_pclk0_clk_src.clkr.vdd_data.rate_max[VDD_LOW] =
430000000;
disp_cc_mdss_pclk0_clk_src.clkr.vdd_data.rate_max[VDD_LOW_L1] =
430000000;
disp_cc_mdss_pclk1_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] =
280000000;
disp_cc_mdss_pclk1_clk_src.clkr.vdd_data.rate_max[VDD_LOW] =
430000000;
disp_cc_mdss_pclk1_clk_src.clkr.vdd_data.rate_max[VDD_LOW_L1] =
430000000;
disp_cc_mdss_rot_clk_src.freq_tbl =
ftbl_disp_cc_mdss_rot_clk_src_sdm670;
disp_cc_mdss_rot_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] =
171428571;
disp_cc_mdss_rot_clk_src.clkr.vdd_data.rate_max[VDD_LOW_L1] =
344000000;
disp_cc_mdss_rot_clk_src.clkr.vdd_data.rate_max[VDD_NOMINAL] =
430000000;
}
static int disp_cc_sdm845_probe(struct platform_device *pdev)
{
struct regmap *regmap;
struct alpha_pll_config disp_cc_pll0_config = {};
int ret;
bool sdm670;
sdm670 = of_device_is_compatible(pdev->dev.of_node,
"qcom,sdm670-dispcc");
regmap = qcom_cc_map(pdev, &disp_cc_sdm845_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
if (sdm670)
disp_cc_sdm845_fixup_sdm670();
disp_cc_sdm845_desc.gdscs = NULL;
disp_cc_sdm845_desc.num_gdscs = 0;
/* 960 MHz Configuration*/
disp_cc_pll0_config.l = 0x2c;
disp_cc_pll0_config.alpha = 0xcaaa;
@@ -862,7 +1096,19 @@ static int disp_cc_sdm845_probe(struct platform_device *pdev)
/* Enable hardware clock gating for DSI and MDP clocks */
regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
ret = qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register Display CC clocks\n");
return ret;
}
dev_info(&pdev->dev, "Registered Display CC clocks\n");
return ret;
}
static void disp_cc_sdm845_sync_state(struct device *dev)
{
qcom_cc_sync_state(dev, &disp_cc_sdm845_desc);
}
static struct platform_driver disp_cc_sdm845_driver = {
@@ -870,7 +1116,7 @@ static struct platform_driver disp_cc_sdm845_driver = {
.driver = {
.name = "disp_cc-sdm845",
.of_match_table = disp_cc_sdm845_match_table,
.sync_state = clk_sync_state,
.sync_state = disp_cc_sdm845_sync_state,
},
};

1144
drivers/clk/qcom/gcc-sdm845.c
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File diff suppressed because it is too large Load Diff

490
drivers/clk/qcom/gpucc-sdm845.c
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@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -17,6 +18,8 @@
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "gdsc.h"
#include "reset.h"
#include "vdd-level-sdm845.h"
#define CX_GMU_CBCR_SLEEP_MASK 0xf
#define CX_GMU_CBCR_SLEEP_SHIFT 4
@@ -25,51 +28,188 @@
#define CLK_DIS_WAIT_SHIFT 12
#define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT)
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_gfx, VDD_GX_NUM, 1, vdd_gx_corner);
static struct clk_vdd_class *gpu_cc_sdm845_regulators[] = {
&vdd_cx,
&vdd_mx,
&vdd_gfx,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_EVEN,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL0_OUT_ODD,
P_GPU_CC_PLL1_OUT_EVEN,
P_GPU_CC_PLL1_OUT_MAIN,
P_GPU_CC_PLL1_OUT_ODD,
P_CRC_DIV,
};
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1a,
.alpha = 0xaab,
static struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
{ 125000000, 1000000000, 1 },
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
.vdd_data = {
.vdd_class = &vdd_mx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000 },
},
},
};
static const struct clk_div_table post_div_table_fabia_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ 0x7, 8 },
{},
};
static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
.vdd_data = {
.vdd_class = &vdd_mx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000 },
},
},
};
static struct clk_fixed_factor crc_div = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "crc_div",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_pll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },
{ .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_EVEN, 1 },
{ P_GPU_CC_PLL0_OUT_ODD, 2 },
{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
{ P_GPU_CC_PLL1_OUT_ODD, 4 },
{ P_GPLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll0_out_even.clkr.hw },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_CRC_DIV, 1 },
{ P_GPU_CC_PLL0_OUT_ODD, 2 },
{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
{ P_GPU_CC_PLL1_OUT_ODD, 4 },
{ P_GPLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &crc_div.hw },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src_sdm670[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
{ }
};
@@ -83,8 +223,160 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 200000000,
[VDD_LOW] = 400000000 },
},
};
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
F(147000000, P_CRC_DIV, 1, 0, 0),
F(210000000, P_CRC_DIV, 1, 0, 0),
F(280000000, P_CRC_DIV, 1, 0, 0),
F(338000000, P_CRC_DIV, 1, 0, 0),
F(425000000, P_CRC_DIV, 1, 0, 0),
F(487000000, P_CRC_DIV, 1, 0, 0),
F(548000000, P_CRC_DIV, 1, 0, 0),
F(600000000, P_CRC_DIV, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src_sdm670[] = {
F(180000000, P_CRC_DIV, 1, 0, 0),
F(267000000, P_CRC_DIV, 1, 0, 0),
F(355000000, P_CRC_DIV, 1, 0, 0),
F(430000000, P_CRC_DIV, 1, 0, 0),
F(504000000, P_CRC_DIV, 1, 0, 0),
F(565000000, P_CRC_DIV, 1, 0, 0),
F(610000000, P_CRC_DIV, 1, 0, 0),
F(650000000, P_CRC_DIV, 1, 0, 0),
F(700000000, P_CRC_DIV, 1, 0, 0),
F(750000000, P_CRC_DIV, 1, 0, 0),
F(780000000, P_CRC_DIV, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x101c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
.flags = FORCE_ENABLE_RCG,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_gfx,
.num_rate_max = VDD_GX_NUM,
.rate_max = (unsigned long[VDD_GX_NUM]) {
[VDD_GX_MIN] = 147000000,
[VDD_GX_LOWER] = 210000000,
[VDD_GX_LOW] = 280000000,
[VDD_GX_LOW_L1] = 338000000,
[VDD_GX_NOMINAL] = 425000000,
[VDD_GX_NOMINAL_L1] = 487000000,
[VDD_GX_HIGH] = 548000000,
[VDD_GX_HIGH_L1] = 600000000 },
},
};
static struct clk_branch gpu_cc_acd_ahb_clk = {
.halt_reg = 0x1168,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1168,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_acd_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_acd_cxo_clk = {
.halt_reg = 0x1164,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1164,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_acd_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_apb_clk = {
.halt_reg = 0x1088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
.halt_reg = 0x10a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
.halt_reg = 0x10a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gfx3d_slv_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
@@ -105,6 +397,32 @@ static struct clk_branch gpu_cc_cx_gmu_clk = {
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
@@ -118,6 +436,55 @@ static struct clk_branch gpu_cc_cxo_clk = {
},
};
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_vsense_clk = {
.halt_reg = 0x1058,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_vsense_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
@@ -140,15 +507,34 @@ static struct gdsc gpu_gx_gdsc = {
};
static struct clk_regmap *gpu_cc_sdm845_clocks[] = {
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,
[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
[GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr,
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
};
static struct gdsc *gpu_cc_sdm845_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
static const struct qcom_reset_map gpu_cc_sdm845_resets[] = {
[GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
[GPUCC_GPU_CC_SPDM_BCR] = { 0x1110 },
[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
};
static const struct regmap_config gpu_cc_sdm845_regmap_config = {
@@ -159,30 +545,90 @@ static const struct regmap_config gpu_cc_sdm845_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sdm845_desc = {
static struct gdsc *gpu_cc_sdm845_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static struct qcom_cc_desc gpu_cc_sdm845_desc = {
.config = &gpu_cc_sdm845_regmap_config,
.clks = gpu_cc_sdm845_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks),
.resets = gpu_cc_sdm845_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sdm845_resets),
.gdscs = gpu_cc_sdm845_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs),
.clk_regulators = gpu_cc_sdm845_regulators,
.num_clk_regulators = ARRAY_SIZE(gpu_cc_sdm845_regulators),
};
static const struct of_device_id gpu_cc_sdm845_match_table[] = {
{ .compatible = "qcom,sdm845-gpucc" },
{ .compatible = "qcom,sdm670-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);
static void gpu_cc_sdm845_fixup_sdm670(void)
{
gpu_cc_gmu_clk_src.freq_tbl = ftbl_gpu_cc_gmu_clk_src_sdm670;
gpu_cc_gmu_clk_src.clkr.vdd_data.rate_max[VDD_LOW] = 200000000;
/* GFX clocks */
gpu_cc_gx_gfx3d_clk_src.freq_tbl =
ftbl_gpu_cc_gx_gfx3d_clk_src_sdm670;
gpu_cc_gx_gfx3d_clk_src.clkr.vdd_data.rate_max[VDD_GX_MIN] = 180000000;
gpu_cc_gx_gfx3d_clk_src.clkr.vdd_data.rate_max[VDD_GX_LOWER] =
267000000;
gpu_cc_gx_gfx3d_clk_src.clkr.vdd_data.rate_max[VDD_GX_LOW] = 355000000;
gpu_cc_gx_gfx3d_clk_src.clkr.vdd_data.rate_max[VDD_GX_LOW_L1] =
430000000;
gpu_cc_gx_gfx3d_clk_src.clkr.vdd_data.rate_max[VDD_GX_NOMINAL] =
565000000;
gpu_cc_gx_gfx3d_clk_src.clkr.vdd_data.rate_max[VDD_GX_NOMINAL_L1] =
650000000;
gpu_cc_gx_gfx3d_clk_src.clkr.vdd_data.rate_max[VDD_GX_HIGH] = 750000000;
gpu_cc_gx_gfx3d_clk_src.clkr.vdd_data.rate_max[VDD_GX_HIGH_L1] =
780000000;
}
static int gpu_cc_sdm845_probe(struct platform_device *pdev)
{
struct regmap *regmap;
unsigned int value, mask;
struct alpha_pll_config gpu_cc_pll0_config = {};
int ret;
bool sdm670;
sdm670 = of_device_is_compatible(pdev->dev.of_node,
"qcom,sdm670-gpucc");
regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/* Register clock fixed factor for CRC divide. */
ret = devm_clk_hw_register(&pdev->dev, &crc_div.hw);
if (ret) {
dev_err(&pdev->dev, "Failed to register hardware clock\n");
return ret;
}
if (sdm670)
gpu_cc_sdm845_fixup_sdm670();
gpu_cc_sdm845_desc.gdscs = NULL;
gpu_cc_sdm845_desc.num_gdscs = 0;
/* 560 MHz configuration */
gpu_cc_pll0_config.l = 0x1d,
gpu_cc_pll0_config.alpha = 0x2aaa,
clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
/* 512 Mhz configuration */
gpu_cc_pll0_config.l = 0x1a,
gpu_cc_pll0_config.alpha = 0xaaaa,
clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll0_config);
/*
* Configure gpu_cc_cx_gmu_clk with recommended
@@ -197,7 +643,19 @@ static int gpu_cc_sdm845_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
8 << CLK_DIS_WAIT_SHIFT);
return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
ret = qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
return ret;
}
dev_info(&pdev->dev, "Registered GPU CC clocks\n");
return ret;
}
static void gpu_cc_sdm845_sync_state(struct device *dev)
{
qcom_cc_sync_state(dev, &gpu_cc_sdm845_desc);
}
static struct platform_driver gpu_cc_sdm845_driver = {
@@ -205,7 +663,7 @@ static struct platform_driver gpu_cc_sdm845_driver = {
.driver = {
.name = "sdm845-gpucc",
.of_match_table = gpu_cc_sdm845_match_table,
.sync_state = clk_sync_state,
.sync_state = gpu_cc_sdm845_sync_state,
},
};

58
drivers/clk/qcom/vdd-level-sdm845.h Normal file
View File

@@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_SDM845_H
#define __DRIVERS_CLK_QCOM_VDD_LEVEL_SDM845_H
#include <linux/regulator/consumer.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
enum vdd_levels {
VDD_NONE,
VDD_MIN, /* MIN SVS */
VDD_LOWER, /* SVS2 */
VDD_LOW, /* SVS */
VDD_LOW_L1, /* SVSL1 */
VDD_NOMINAL, /* NOM */
VDD_HIGH, /* TURBO */
VDD_NUM,
};
static int vdd_corner[] = {
[VDD_NONE] = 0,
[VDD_MIN] = RPMH_REGULATOR_LEVEL_MIN_SVS,
[VDD_LOWER] = RPMH_REGULATOR_LEVEL_LOW_SVS,
[VDD_LOW] = RPMH_REGULATOR_LEVEL_SVS,
[VDD_LOW_L1] = RPMH_REGULATOR_LEVEL_SVS_L1,
[VDD_NOMINAL] = RPMH_REGULATOR_LEVEL_NOM,
[VDD_HIGH] = RPMH_REGULATOR_LEVEL_TURBO,
};
enum vdd_gx_levels {
VDD_GX_NONE,
VDD_GX_MIN, /* MIN SVS */
VDD_GX_LOWER, /* SVS2 */
VDD_GX_LOW, /* SVS */
VDD_GX_LOW_L1, /* SVSL1 */
VDD_GX_NOMINAL, /* NOM */
VDD_GX_NOMINAL_L1, /* NOM1 */
VDD_GX_HIGH, /* TURBO */
VDD_GX_HIGH_L1, /* TURBO1 */
VDD_GX_NUM,
};
static int vdd_gx_corner[] = {
[VDD_GX_NONE] = 0, /* VDD_GX_NONE */
[VDD_GX_MIN] = RPMH_REGULATOR_LEVEL_MIN_SVS, /* VDD_GX_MIN */
[VDD_GX_LOWER] = RPMH_REGULATOR_LEVEL_LOW_SVS, /* VDD_GX_LOWER */
[VDD_GX_LOW] = RPMH_REGULATOR_LEVEL_SVS, /* VDD_GX_LOW */
[VDD_GX_LOW_L1] = RPMH_REGULATOR_LEVEL_SVS_L1, /* VDD_GX_LOW_L1 */
[VDD_GX_NOMINAL] = RPMH_REGULATOR_LEVEL_NOM, /* VDD_GX_NOMINAL */
[VDD_GX_NOMINAL_L1] = RPMH_REGULATOR_LEVEL_NOM_L1, /* VDD_GX_NOMINAL_L1 */
[VDD_GX_HIGH] = RPMH_REGULATOR_LEVEL_TURBO, /* VDD_GX_HIGH */
[VDD_GX_HIGH_L1] = RPMH_REGULATOR_LEVEL_TURBO_L1, /* VDD_GX_HIGH_L1 */
};
#endif

118
drivers/clk/qcom/videocc-sdm845.c
View File

@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -17,58 +18,102 @@
#include "clk-regmap.h"
#include "clk-pll.h"
#include "gdsc.h"
#include "reset.h"
#include "vdd-level-sdm845.h"
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
static struct clk_vdd_class *video_cc_sdm845_regulators[] = {
&vdd_cx,
};
enum {
P_BI_TCXO,
P_VIDEO_PLL0_OUT_EVEN,
P_VIDEO_PLL0_OUT_MAIN,
/* P_VIDEO_PLL0_OUT_EVEN, */
/* P_VIDEO_PLL0_OUT_ODD, */
P_VIDEO_PLL0_OUT_ODD,
};
static const struct alpha_pll_config video_pll0_config = {
static struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
{ 125000000, 1000000000, 1 },
};
/*320 MHz configuration */
static struct alpha_pll_config video_pll0_config = {
.l = 0x10,
.alpha = 0xaaab,
.cal_l = 0x32,
.alpha = 0xaaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.test_ctl_hi_val = 0x00000002,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00004805,
};
static struct clk_alpha_pll video_pll0 = {
.offset = 0x42c,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "video_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 615000000,
[VDD_LOW] = 1066000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000 },
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
/* { P_VIDEO_PLL0_OUT_EVEN, 2 }, */
/* { P_VIDEO_PLL0_OUT_ODD, 3 }, */
{ P_VIDEO_PLL0_OUT_EVEN, 2 },
{ P_VIDEO_PLL0_OUT_ODD, 3 },
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "bi_tcxo" },
{ .hw = &video_pll0.clkr.hw },
{ .hw = &video_pll0.clkr.hw },
{ .hw = &video_pll0.clkr.hw },
/* { .name = "video_pll0_out_even" }, */
/* { .name = "video_pll0_out_odd" }, */
};
static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(320000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(380000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_video_cc_venus_clk_src_sdm670[] = {
F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(330000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(364700000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_venus_clk_src = {
.cmd_rcgr = 0x7f0,
.mnd_width = 0,
@@ -81,6 +126,17 @@ static struct clk_rcg2 video_cc_venus_clk_src = {
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_MIN] = 100000000,
[VDD_LOWER] = 200000000,
[VDD_LOW] = 320000000,
[VDD_LOW_L1] = 380000000,
[VDD_NOMINAL] = 444000000,
[VDD_HIGH] = 533000000 },
},
};
@@ -305,31 +361,65 @@ static const struct regmap_config video_cc_sdm845_regmap_config = {
.fast_io = true,
};
static const struct qcom_cc_desc video_cc_sdm845_desc = {
static struct qcom_cc_desc video_cc_sdm845_desc = {
.config = &video_cc_sdm845_regmap_config,
.clks = video_cc_sdm845_clocks,
.num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),
.gdscs = video_cc_sdm845_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_sdm845_gdscs),
.clk_regulators = video_cc_sdm845_regulators,
.num_clk_regulators = ARRAY_SIZE(video_cc_sdm845_regulators),
};
static const struct of_device_id video_cc_sdm845_match_table[] = {
{ .compatible = "qcom,sdm845-videocc" },
{ .compatible = "qcom,sdm670-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table);
static void video_cc_sdm845_fixup_sdm670(void)
{
video_cc_venus_clk_src.freq_tbl = ftbl_video_cc_venus_clk_src_sdm670;
video_cc_venus_clk_src.clkr.vdd_data.rate_max[VDD_LOW] = 330000000;
video_cc_venus_clk_src.clkr.vdd_data.rate_max[VDD_LOW_L1] =
404000000;
}
static int video_cc_sdm845_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
bool sdm670;
sdm670 = of_device_is_compatible(pdev->dev.of_node,
"qcom,sdm670-videocc");
regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
if (sdm670)
video_cc_sdm845_fixup_sdm670();
video_cc_sdm845_desc.gdscs = NULL;
video_cc_sdm845_desc.num_gdscs = 0;
clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
ret = qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register Video CC clocks\n");
return ret;
}
dev_info(&pdev->dev, "Registered Video CC clocks\n");
return ret;
}
static void video_cc_sdm845_sync_state(struct device *dev)
{
qcom_cc_sync_state(dev, &video_cc_sdm845_desc);
}
static struct platform_driver video_cc_sdm845_driver = {
@@ -337,7 +427,7 @@ static struct platform_driver video_cc_sdm845_driver = {
.driver = {
.name = "sdm845-videocc",
.of_match_table = video_cc_sdm845_match_table,
.sync_state = clk_sync_state,
.sync_state = video_cc_sdm845_sync_state,
},
};