Evolution-X-Devices/kernel_xiaomi_raphael
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Revert "ARM: dts: Make crypto address part of host controller node"

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This reverts commit 4abe03d70b.

Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com>
This commit is contained in:
UtsavBalar1231
2020-08-28 19:54:51 +05:30
parent d2ac4991b5
commit 7ad73e1306
4 changed files with 18 additions and 14 deletions
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9
arch/arm64/boot/dts/qcom/atoll.dtsi
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@@ -2679,12 +2679,13 @@
sdhc_1: sdhci@7c4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7c8000 0x8000>;
reg-names = "hc_mem", "cmdq_mem", "cmdq_ice";
reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;
reg-names = "hc_mem", "cmdq_mem";
interrupts = <GIC_SPI 641 IRQ_TYPE_NONE>,
<GIC_SPI 644 IRQ_TYPE_NONE>;
interrupt-names = "hc_irq", "pwr_irq";
sdhc-msm-crypto = <&sdcc1_ice>;
qcom,bus-width = <8>;
qcom,large-address-bus;
@@ -2834,11 +2835,11 @@
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
reg-names = "ufs_mem", "ufs_ice";
reg = <0x1d84000 0x3000>;
interrupts = <0 265 0>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
ufs-qcom-crypto = <&ufs_ice>;
lanes-per-direction = <1>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */

9
arch/arm64/boot/dts/qcom/sdmmagpie.dtsi
View File

@@ -2121,12 +2121,13 @@
sdhc_1: sdhci@7c4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>;
reg-names = "hc_mem", "cmdq_mem", "cmdq_ice";
reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;
reg-names = "hc_mem", "cmdq_mem";
interrupts = <IRQ_TYPE_NONE 641 IRQ_TYPE_NONE>,
<IRQ_TYPE_NONE 644 IRQ_TYPE_NONE>;
interrupt-names = "hc_irq", "pwr_irq";
sdhc-msm-crypto = <&sdcc1_ice>;
qcom,bus-width = <8>;
qcom,large-address-bus;
@@ -2338,11 +2339,11 @@
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
reg-names = "ufs_mem", "ufs_ice";
reg = <0x1d84000 0x3000>;
interrupts = <0 265 0>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
ufs-qcom-crypto = <&ufs_ice>;
lanes-per-direction = <1>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */

9
arch/arm64/boot/dts/qcom/sm6150.dtsi
View File

@@ -1409,11 +1409,12 @@
sdhc_1: sdhci@7c4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>;
reg-names = "hc_mem", "cmdq_mem", "cmdq_ice";
reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;
reg-names = "hc_mem", "cmdq_mem";
interrupts = <0 641 0>, <0 644 0>;
interrupt-names = "hc_irq", "pwr_irq";
sdhc-msm-crypto = <&sdcc1_ice>;
qcom,bus-width = <8>;
qcom,large-address-bus;
@@ -1622,11 +1623,11 @@
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
reg-names = "ufs_mem", "ufs_ice";
reg = <0x1d84000 0x3000>;
interrupts = <0 265 0>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
ufs-qcom-crypto = <&ufs_ice>;
lanes-per-direction = <1>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */

5
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@@ -2281,6 +2281,7 @@
reg = <0x1d87000 0xda8>; /* PHY regs */
reg-names = "phy_mem";
#phy-cells = <0>;
ufs-qcom-crypto = <&ufs_ice>;
lanes-per-direction = <2>;
@@ -2296,11 +2297,11 @@
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x2500>, <0x1d90000 0x8000>;
reg-names = "ufs_mem", "ufs_ice";
reg = <0x1d84000 0x2500>;
interrupts = <0 265 0>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
ufs-qcom-crypto = <&ufs_ice>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */