3568 Commits

Author SHA1 Message Date
qctecmdr
a96b1353ae Merge "disp: msm: dp: modify hdcp wait loop to not add to cpu load" 2022-11-01 00:12:36 -07:00
qctecmdr
c22f425795 Merge "disp: msm: dp: avoid releasing vcpi for active crtc" 2022-11-01 00:12:36 -07:00
Andrew Bartfeld
2b91001521 disp: msm: dp: modify hdcp wait loop to not add to cpu load
Currently, hdcp wait loops uses the wait_event() macro which sets the
status of the thread to WAIT_UNINTERRUPTIBLE and contributes to system
load. The macro wait_event_idle() polls for a changing condition in the
same way but instead sets the thread status to WAIT_IDLE which does not
contribute to system load. This prevents hdcp threads from appearing as
hung threads in system load summaries while still properly polling for
status changes.

Change-Id: Ie6991881d912ba6fca6bb0fd9558633b1fb83492
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
2022-10-31 10:22:26 -07:00
Ingrid Gallardo
7ef45409a5 disp: msm: sde: fix to avoid creating output hw-fence for CWB
Current code creates an output hw fence for any virtual
connector with a retire fence attached. This is a problem
for CWB, where the output-fence should be handled as a
sw-fence as current hw can only support a single hw-fence
per ctl path.
Fix this issue by adding a check to only create a retire
output hw-fence for virtual connectors that are not CWB.

Change-Id: I5863282d24ef8940b1f45c1fbd7584f91d28f0b8
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
2022-10-31 10:13:47 -07:00
Amine Najahi
e525225c94 disp: msm: sde: use panel dimension on full frame RC ROI
Currently, RC is using displayh and displayv variables
which are pointing to the LM dimension on a full frame
setting. If DS is enable and HW RC was not disabled the
the full frame ROI will not match the panel resolution
and cause an invalid hardware configuration.

This change uses the height and width values coming
from the mode information when a full frame ROI is
detected.

Change-Id: I274d15cbca61076ea7e95a984f907201e97b76ec
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-31 10:05:45 -07:00
Linux Build Service Account
fba06e2000 Merge 2ea74a3bb2 on remote branch
Change-Id: Ib69c361653fa5bf5a4e9c9438a80669fdf326f74
2022-10-31 01:39:37 -07:00
qctecmdr
61dd86f625 Merge "disp: msm: dsi: clear the panel esd_recovery_pending in power on commit" 2022-10-30 18:45:20 -07:00
qctecmdr
d1d8ced211 Merge "disp: msm: dp: enable aux switch from display HPD handler" 2022-10-29 10:31:21 -07:00
qctecmdr
4e43939572 Merge "disp: msm: sde: disable RC in case of configuration mismatch" 2022-10-29 10:31:21 -07:00
Andrew Bartfeld
28cde80bd3 disp: msm: dp: avoid releasing vcpi for active crtc
In MST atomic check function, add a check to ensure it's a disable call
before releasing vcpi slots to ensure atomic_release_vcpi_slots() and
atomic_find_vcpi_slots() are never called in the same atomic check
as mentioned in the kernel docs.

Change-Id: I36cf689b4d3bf9d2469a6c402b6377a667f01c12
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
2022-10-27 14:06:50 -07:00
Ingrid Gallardo
4bfae64bbe disp: msm: sde: remove unnecessary debug message
Move print message from error to debug for a failure that is not fatal
but can be expected when a crtc doesn't have a hw ctl, in this case
driver will handle the output fence as a sw-fence.

Change-Id: I908135dce4336b0c9ec3fa388dc9211c6df97f68
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
2022-10-26 12:21:55 -07:00
Ingrid Gallardo
e6499cbbd0 disp: msm: sde: add events to input and output hw-fences
Add extra display driver debug events for input and output
hw-fences.

Change-Id: I32be1d25d98c510ebba5d39f8aff2a0c54144ba1
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
2022-10-25 17:30:03 -07:00
Ingrid Gallardo
504fdd06db disp: msm: sde: fix to avoid creating hw-fences for empty spec fences
Current display driver sets the hw-fences as valid even when
the speculative fence is empty. Avoid this issue by doing a
positive check and only create hw-fences if all the fences in
the speculative fence are valid.

Change-Id: Iec9636641ac9146eb651be08615e2478994c2508
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
2022-10-25 17:19:31 -07:00
Amine Najahi
7191219f9e disp: msm: sde: disable RC in case of configuration mismatch
Currently when there is a modeset and usermode does not disable
or reprogram the RC mask, driver will compute an invalid configuration.

This change checks the RC mask with panel resolution and disables
RC HW internally if there is a mismatch.

Change-Id: I0e6afcf38cfc9165a6c0d2c12bfbc7b2b5f2ce65
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-24 16:37:47 -04:00
Veera Sundaram Sankaran
3c72f95aa3 disp: msm: sde: program read pointer after configuring vsync_counter_en
Program the read pointer after configuring the tearcheck registers.
The read pointer register should be configured after VSYNC_COUNTER_EN
is set as per hw programming sequence. Since the register programming
sequence is changed during the tearcheck configuration, remove the
redundant override call from idle-pc path.

Change-Id: I2fa1429798fab51d08091e74a33f1b1c4382eafe
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-10-24 13:12:32 -07:00
qctecmdr
2ea74a3bb2 Merge "disp: msm: sde: override qsync read pointer during IPC" 2022-10-20 19:18:13 -07:00
qctecmdr
adfcb0f857 Merge "disp: msm: sde: improve qsync trigger window accuracy" 2022-10-20 19:18:13 -07:00
qctecmdr
8ff2ca9b94 Merge "disp: msm: sde: avoid setting plane qos_dirty during cwb modeset" 2022-10-20 19:18:13 -07:00
Ritesh Kumar
a01dc18dd2 disp: msm: dsi: fix compressed RGB101010 support
The destination format for compressed rgb101010 should be
the same as rgb888. After adding uncompressed RGB101010 support,
the programming for compressed rgb101010 went wrong.
Fix this to re-enable compressed rgb101010 format support.

Change-Id: I805e15df14dda8ff0653a0dba8c4efe3fe0681fd
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
2022-10-19 13:55:29 -07:00
Amine Najahi
5421008a85 disp: msm: sde: improve qsync trigger window accuracy
Currently, panel jitter and loss of precision are not
compensated when calculating the trigger window size
for a QSYNC panel. These errors can be signigicant on
panels supporting very slow frame rate (10 Hz).

This change improves fixed point calculation and take
into account panel jitter when calculating the minimum
qsync time period.

Change-Id: Ibe620862afbd853580992fccec09cac8307b92bd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-18 06:50:27 -07:00
Amine Najahi
5b30b4e9db disp: msm: sde: override qsync read pointer during IPC
Currently, when there is an idle power collapse HW resets
the internal read pointer value to 0. This causes the trigger
window to be out of sync when power is restored until the
next vsync is received.

This change overrides the internal read pointer value to
the maximum qsync timeout value on restore and defers frame
trigger to next vsync.

Change-Id: Ibdad3f8eb367136ee0d766bed10742a281e36b4e
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-18 06:49:57 -07:00
qctecmdr
f6fb5df623 Merge "disp: msm: sde: add support for wait on multiple hw fences" 2022-10-17 05:49:43 -07:00
qctecmdr
f2e56f2eeb Merge "disp: msm: sde: add line counter logging" 2022-10-17 05:49:43 -07:00
Linux Build Service Account
26b0bbdf66 Merge 99e01152fa on remote branch
Change-Id: I25136915f3744c208b38dddaf505112e997ca2c7
2022-10-16 22:57:35 -07:00
Sandeep Gangadharaiah
89469d1de1 disp: msm: dp: enable aux switch from display HPD handler
Currently, aux switch is enabled by usbpd handler before
handing over the control to dispaly HPD handler. However,
in some scenarios there is a chance that altmode would
directly call into display HPD handler bypassing the usbpd
handler. This would lead to aux errors since aux switch
is not enabled. This change will enable aux switch in
display HPD handler which would avoid the resulting aux
errors. This issue is a regression caused by this change
b6466ca7f5.

Change-Id: I425991ba95b22411740f88cba5ca2083d13969e1
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-10-14 17:52:03 -07:00
Narendra Muppalla
7802222177 disp: msm: sde: fix typo in trace message
This change fix trace message in sde trace.

Change-Id: I73a873984564f995f84e0c08f9e49164cb67063a
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
2022-10-14 13:11:39 -07:00
qctecmdr
8fbfedfc80 Merge "disp: msm: fix register offset logging with debugfs register access" 2022-10-13 20:28:13 -07:00
Veera Sundaram Sankaran
6f3f3e7839 disp: msm: sde: avoid setting plane qos_dirty during cwb modeset
The encoder modeset updates all the plane's qos_dirty flag attached
to the crtc to make sure the qos params are updated during seamless
mode-switch cases like fps or resolution switch. But this is not
required for cwb encoder modeset as it does not have any effect on
the planes attached to the main display. Add check to avoid this
reprogramming.

Change-Id: I1ab7a71971b7200a50e6643407327734b1c9cbc5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-10-13 14:47:26 -07:00
Veera Sundaram Sankaran
1055b42576 disp: msm: sde: cache cwb enc mask to use during seamless transitions
The cwb_enc_mask is set by the wb phys encoder during the validate
phase and this is in-turn used during the commit phase. During
seamless transition cases like poms with cwb, the encoders are
disabled and then enabled back after the validate phase. The cwb
flags are reset during this time leading to issues. Cache the flag
and reapply it during the modeset to avoid this case.

Change-Id: I5df1be18a5e30bb1107dc0f2e87d771a735f1ab6
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-10-11 14:55:29 -07:00
Christina Oliveira
ea0ad0a45e disp: msm: sde: add support for wait on multiple hw fences
This change adds support to wait on multiple hardware fences by
creating a fence array so each dpu-client only gets signaled until all
the hw fences going to the same ctl-path are signaled. It also
accounts for if a fence is a fence array.

Change-Id: Iba4b1d2b7322aea64dc197ca7655920b79dbb919
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-10-10 12:25:07 -07:00
Srihitha Tangudu
9688168454 disp: msm: dsi: clear the panel esd_recovery_pending in power on commit
Currently the panel esd_recovery_pending flag is cleared for every mode
set. The ESD recovery completes only after the suspend and resume. Clear
the flag only during power on commit.

Change-Id: I97e370feba0aad34558e4675168b4bcb7f5901ca
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
2022-10-05 23:12:54 -07:00
Amine Najahi
40ac02b833 disp: msm: sde: add line counter logging
Add logs to track the read/write line counters
and tear check configuration during key events.

Change-Id: Ife8afecc63a9008a8d9fc746d0ec8579a311b335
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-10-05 23:42:23 -04:00
Narendra Muppalla
99e01152fa disp: msm: dsi: add dsi ramdump support without DEBUG_FS
This change adds dsi display ramdump support when DEBUG_FS
is not enabled.

Change-Id: Ic6659a9380acd5eb55a3270d3e3b7016a9cd2bd7
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2022-10-04 09:41:53 -07:00
qctecmdr
f8b4991fce Merge "drm: msm: disable LTM hardware during encoder disable" 2022-10-03 19:20:40 -07:00
V S Ganga VaraPrasad (VARA) Adabala
a1d035f4cc Merge commit '3272f7e726e51dac9f79b06c930e79a4d85b66bd' into display-kernel.lnx.5.15.r1-rel
Change-Id: Ia13bc0331c276c87a523d1f6207fb589f382ea43
Signed-off-by: V S Ganga VaraPrasad (VARA) Adabala <quic_vadabala@quicinc.com>
2022-10-01 23:25:13 +05:30
Gopikrishnaiah Anandan
a8a920e7f3 drm: msm: disable LTM hardware during encoder disable
LTM block should be disabled when encoder is being disabled to avoid
display hang when all driver clients have been closed.
Change disables LTM hardware block when encoder is disabled.

Change-Id: I279296b566ab93c302e6166b6fa4b7197c2cc0ab
Signed-off-by: Gopikrishnaiah Anandan <quic_agopik@quicinc.com>
2022-09-30 10:39:26 -07:00
Veera Sundaram Sankaran
eebe3e83dd disp: msm: fix register offset logging with debugfs register access
The register offsets are decremented instead of incrementing during
the logging of registers through the debugfs option. Fix it to be
incremental to help in debugging.

Change-Id: Iefc98c40143554fa7169ff220793431d774f57ce
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-09-29 14:13:23 -07:00
Yashwanth
3c695fabab disp: msm: sde: detach dsc/vdc encoder blocks properly during modeswitch
In the current code if there is a switch from DSC to non-DSC
mode, all the DSC blocks attached to the sde_encoder are not
cleaned up properly. Due to this, during virt disable these
DSC blocks are disabled and flushed resulting in underruns
on other ctl paths which might be using them. This change
properly cleans up all the dsc/vdc attached to the sde
encoder to avoid such issues.

Change-Id: Ie644701cbda6b4d056bc7ef30300be96096c5214
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
2022-09-28 13:07:34 -07:00
Veera Sundaram Sankaran
23f0eec24b disp: msm: sde: move some frame_events from crtc commit to event thread
Move frame data stats collection/notification during frame-done and
retire fence sysfs notification to event thread. This will free up
some interrupt time.

Change-Id: I2648ac4287ce8712e9a059edd408a59753aa6d32
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Signed-off-by: V S Ganga VaraPrasad (VARA) Adabala <quic_vadabala@quicinc.com>
2022-09-24 10:37:23 -07:00
Dmitry Baryshkov
df3ab4c237 drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs
There is little sense in reading interrupt statuses and right after that
going after the array of statuses to dispatch them. Merge both loops
into single function doing read and dispatch.

Change-Id: I1259476549bcaf9f9f4e12591a7e182796e150dd
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Git-commit: 0abdba47dc1df708c365421d481734d3f7fecb01
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Signed-off-by: V S Ganga VaraPrasad (VARA) Adabala <quic_vadabala@quicinc.com>
2022-09-24 10:37:05 -07:00
Amine Najahi
d3516bd83f disp: msm: update RSC bandwidth during solver mode transition
Currently when disconnecting a secondary monitor, RSC will
transition to solver mode. If the bandwidth remains the same
for primary display, SW will not update BW indication register
causing stale TCS wait values.

This change forces a register update when RSC mode is
changed to solver mode.

Change-Id: I99d2332621bad75a7b6abdb64d6aedd35c30ca63
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Signed-off-by: V S Ganga VaraPrasad (VARA) Adabala <quic_vadabala@quicinc.com>
2022-09-24 10:36:57 -07:00
Renchao Liu
43dbaf14b4 disp: msm: sde: fix null pointer dereference issue
This changes fixes null pointer dereference issue.

Change-Id: I9a9628f1fb274aea86a15792dc85b8505f25d28f
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
Signed-off-by: V S Ganga VaraPrasad (VARA) Adabala <quic_vadabala@quicinc.com>
2022-09-24 10:36:48 -07:00
V S Ganga VaraPrasad (VARA) Adabala
65216e3693 Revert "disp: msm: dp: free DP sim ports during DP sim disable"
This reverts commit 2e9d68e174.

Change-Id: I02602dd6e1add1ac1a2ec474625a44880c0f45d7
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Signed-off-by: V S Ganga VaraPrasad (VARA) Adabala <quic_vadabala@quicinc.com>
2022-09-24 23:03:41 +05:30
qctecmdr
3272f7e726 Merge "disp: msm: sde: avoid connector remove in dual display recovery" 2022-09-20 14:59:39 -07:00
ntarte
543b4d62d4 Revert "disp: msm: sde: fix null pointer dereference issue"
This reverts commit b2f3452dbe.
Change-Id: I3b7dbb75b954a5b6b20c7186ac2a333d21de0fce
Signed-off-by: Nikhil Tarte <quic_ntarte@quicinc.com>
2022-09-20 12:09:57 +05:30
ntarte
769e9693c7 Revert "Revert "disp: msm: dp: free DP sim ports during DP sim disable""
This reverts commit ac1ab5fb46.
Change-Id: I200a765112d7c85f5a069716dfae2c5418cf7c7b
Signed-off-by: Nikhil Tarte <quic_ntarte@quicinc.com>
2022-09-20 12:07:33 +05:30
Raviteja Tamatam
00bc3bc06a disp: msm: sde: avoid connector remove in dual display recovery
Add changes to get drm object reference for connector and
remove out fb in dual display recovery case.

Change-Id: I1fd0c4818575b3f532d51ad41285031e8320c5fe
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
2022-09-16 15:37:29 -07:00
qctecmdr
a38699990d Merge "disp: msm: sde: fix crtc count based on layer mixer" 2022-09-16 07:28:28 -07:00
qctecmdr
698e1406b8 Merge "drm: msm: re-enable driver disabled color features" 2022-09-16 07:28:28 -07:00
qctecmdr
1ee58e528f Merge "disp: msm: sde: expose cdm block count through connector" 2022-09-16 07:28:28 -07:00