Fix error messages in the parsing of DSI PHY tuning parameters
e.g. platform lane config, strength control and regulator
settings.
Change-Id: I15806ccfa9fbe46ef0df06d4000169a0ae1a1f94
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
The inactive simulated DP MST connectors will not have a panel assigned.
So, the driver needs check for a valid panel before dereferencing the
panel object.
Change-Id: I60a4ca666f3c7c81a4e92e08cf572d5abac4ee78
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Wait for the userspace to disable DP when usb cable is removed
during DP simulation. The usb notifier is a blocking call.
Change-Id: I6c00cc684b4d99da30a129f034eb17bf505738bb
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Do not wait for the panel to be enabled to send the first SDP
with color information. The color information is sent before
the panel is enabled.
Change-Id: I74391df3493652397d0456c43feba38521baadb5
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
DCS is misspelled as DSC in qcom,bl-dsc-cmd-state property. Correct it as
qcom,bl-dcs-cmd-state to avoid confusion between display command set and
display stream compression.
Change-Id: I9813574d55610738259d2cdf2a66c5857a83f821
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Qsync ON/OFF commands have to be sent to the panel before connector
kickoff and sending them in the commit thread blocks it for few
millliseconds, and can lead to frame drops. Avoid this by sending
them asyncronously.
Change-Id: Ia7bc694871faf02b7c1a068b3d0ee7056c272506
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
The current scenario is as follows commit N with autorefresh
enabled and frame starts processing. On suspend commit N+1,
during virt_disable software resets CTL path after autorefresh
config is disabled. Since in hardware frame is still processing
sw reset is causing fifo underflow. This change waits for
vsync so that current autorefresh frame transaction completes
before issuing a CTL_SW_RESET.
Change-Id: I79fa81531d9f479d84d3873b5e855fcd73dc88c3
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
When wfd display is connected, qseed3 coefficient lut
programming is getting erased due to idle pc entry for wfd pipes.
On idlepc exit commit, plane properties are not reconfigured from
userspace since support is not present for writeback crtc. This patch
updates idle pc handling to avoid gdsc power off when writeback
crtc is connected.
Change-Id: Ic4a4b5a6e4ccd59aaa4a076d6d8f1f7cfa27974f
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
In Certain targets where two WB blocks are present, the dcwb
tries to adds its address to sub_range_list more than once.
This change avoids such duplicate entries added to sub_ranage_list.
Change-Id: If9fcdc0682ab4bb4347d47c08a35452da7251d1e
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This gerrit reverts the change I330f6fc162f3366a9ca0aeb64956927dceca4c80
(disp: msm: dp: check for display status before SDP config)
Change-Id: I74391df3493652397d0456c43feba38521baadb5
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
When broadcast command is sent with command DMA window scheduling enabled,
DSI_TRIG_CTRL.COMMAND_MODE_DMA_TRG_MUX does not get reset after command
transfer. Due to this next unicast command on slave fails.
This change resets DMA trigger mux during DSI_TRIG_CTRL initialization.
Change-Id: I74503d82ab1cb6ca4d61a9d14f2b3cd2c3936ea7
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
In DMA start window scheduling, TRIG_CTRL.COMMAND_MODE_DMA_TRIGGER_SEL
is programmed to SW + DMA start window trigger. But if DMS switch
comes after command is scheduled, COMMAND_MODE_DMA_TRIGGER_SEL gets
reprogrammed to SW trigger leading to command transfer failure.
Program the COMMAND_MODE_DMA_TRIGGER_SEL only from the CMD DMA Tx path.
Change-Id: I01062497bb70aa5fdcb25be3715c7cbc4c68b681
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Currently we are always doing command transfer cleanup which includes
disabling command engine, clocks, gdsc and unmasking overflow interrupt
as part of post command transfer function only after CMD DMA wait is
done. Cleanup should also be done if an ESD failure happens before
kickoff of a batch command. Organize code so that command transfer
cleanup can be done irrespective of whether command kickoff is done
or not.
Change-Id: Ieb92daa7f5da62c16c71f1b23ceff20adfbf3621
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
add memory barrier before and after last command to avoid
out of order packet queuing to lut dma packet queue.
add memory barrier after ctrl flush to ensure lut dma
trigger, dspp flush and ctrl flush all are written to dpu
before control start.
Change-Id: I7e1613034af8407d55529cf3f95c70994334af82
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
msm_release needs to wait until all sw datapaths are idle.
There can be a scenario where in a crtc is blocked on input fence
and has not yet completed its processing.
The change will loop through all the active crtcs and will use
the union of timeouts before proceeding cleanup in msm_release.
Change-Id: I4e4b487e1dc6549717bd42f598f13a8c799d8424
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
This change adds debug changes to dump the input fences during a
commit done timeout, when input hw-fences are enabled.
Change-Id: Ia778d3d73ab8ee795613587da70ef9bebb7c73ca
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Increase the log level of the prink statements to dev_err
when a register dump is triggered. This will allow user to
capture the values independently of the target default log level.
Change-Id: I67f8c854a274b70d1595e74136095ef91584ca90
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Wait for the userspace to disable DP when usb cable is removed
during DP simulation. The usb notifier is a blocking call.
Change-Id: I6c00cc684b4d99da30a129f034eb17bf505738bb
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
In some cases while transitioning between vm, vblank
work might be get executed on event thread after handoff is
completed on commit thread leading to crash. This change
flush the event thread queue during vm pre-release before
lending the io resources to the other vm.
Change-Id: Ife1fea54dd236cc4cbca70f7636d27c4de1280ec
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
For calculating bit rate in cphy, we multiply bit rate by a factor of
7/16 where 7 is the number of symbols and 16 is the bits per symbol.
But we are currently not considering the 7/16 factor while calculating
minimum bit clk value for command mode which is resulting in a smaller
bit rate value than the minimum bit clk.
Bit rate should always be greater than the minimum bit clk which otherwise
can lead to discrepancies. Correct minimum bit clk calculation for command
mode, by multiplying a factor of 7/16 if cphy.
Change-Id: I39b202dcafe60e2047549f84ff9388b46ae490a5
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
After triggering dynamic refresh, if there is any dsi_ctrl_isr, dynamic
refresh done status also gets cleared as part of it. Because of this,
wait4dynamic_refresh_done timeout error is seen even though dynamic refresh
is done successfully.
Change-Id: I39b42c60d15d9cb0557669f95ff2ed83989f9cd3
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Currently, num of 3dmux used is incremented or decremented based
on LM allotment. This was leading to wrong bookkeeping in few
corner cases. This change maintains a 3d mux mask to track the
usage and update the count accordingly.
Change-Id: Idf25eff827462f3f0263d01a1aa733a1cbaf0a83
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Currently, we are always initializing PLL registers whenever PLL is
configured. Re-initializing PLL registers during dynamic clock switch in
case of cphy video mode is moving the PLL to some bad state resulting in
display freeze. Avoid this by restricting initialization of PLL registers
to only while turning on the PLL. This change is for 4nm PLL.
Change-Id: I57c8cfe1927f83f1ac25238c696a606960f3a8c8
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
This change adds a device-tree configurable property to define
the ipcc client id of the dpu used for registers access and
configuration. Starting pineapple, this is the ipcc client physical
id, distinct from the ipcc client virtual id.
Change-Id: Icb59111c85c7132c0efd7b207eaa5417cca013eb
Signed-off-by: Grace An <quic_gracan@quicinc.com>
When calculating the Rate Governor parameters for MST, if the
stream is compressed, the calculator expects the input bpp to be
the compressed bpp, but currently the driver is passing uncompressed
bpp. This change updates the driver to pass compressed bpp to the
calculator.
Change-Id: Iac51d75843bd0072bbe07142ac4533d841f795f5
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
During DP sim test cases there is a chance that userspace would
call into SDP config ops even when display is not active which
would lead to NOC errors. This change checks for display status
during SDP config operation.
Change-Id: I330f6fc162f3366a9ca0aeb64956927dceca4c80
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
In some cases while transitioning between vm, vblank
work might be get executed on event thread after handoff is
completed on commit thread leading to crash. This change
flush the event thread queue during vm pre-release before
lending the io resources to the other vm.
Change-Id: Ife1fea54dd236cc4cbca70f7636d27c4de1280ec
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
When using the TU calculator for SST DSC usecase, the calculator
expects the bpp to be 24 irrespective of the actual panel bpp.
Change-Id: Ifdab2c00a2a99b4d7d7dea7eadb33bc34e3cfa8b
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Pipe csc configuration is being cached in the sde plane which can cause
race conditions between hardware programming and caching.
All drm properties should be cached in sde plane state to avoid race
conditions. Change moves caching to sde plane state.
Change-Id: I22470a82b2fc2812f8c526ababc2b517db13a3ce
Signed-off-by: Gopikrishnaiah Anand <quic_agopik@quicinc.com>
As per DP HPG recommendation, controller flush mode is
set to be synchronous with a vsync. This requires a
peripheral flush to be issued for HDR SDP to be processed.
Currently in a static HDR use case, since the peripheral
flush is not issued after queueing an HDR SDP, it never
gets sent to the sink and it stays in SDR mode. This change
issues a peripheral flush on every DP commit, so that
any pending SDPs are flushed.
Change-Id: I0ed82b6cd8df33539a3067c6ad9827f74de2ed51
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
