Each rectangle is listed as an individual DRM plane, and since
they share a common VBIF register, there is no need to
reprogram the QOS remapper for the virtual plane.
Change-Id: I7af6aca1953cd61e622ef5b15353d5ea20fd73cd
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
To set frequencies for link clks, the clk manager index of
ctrl is require. Use ctrl cell index to get clk manager index.
Change-Id: I175d0721e672fb4d368349584c8b448ba63f4224
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
To set frequencies for link clks, the clk manager index of
ctrl is require. Use ctrl cell index to get clk manager index.
Change-Id: I175d0721e672fb4d368349584c8b448ba63f4224
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
This change clears all link info capabilities as a part of
panel deinitialisation during a disconnect sequence. Without
this change, the link info capabilities like the CRC flag will be
retained for the next hotplugged device. Now if, a MST is connected
after a SST connection, the base panel will have the CRC value of the
previous sink, which will be invalid for the case when the hub doesn't
support CRC.
Change-Id: I3a820070fd5006a707328b4d192893a465c04448
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Add changes to validate the plane fb_translation mode of
drm_gem_obj attached to plane. It avoids device panic on S2
translation fault and fails the drm_atomic_commit for which
mismatch is detected. In current codeflow, only S1 mappings are
modified when dma_buf is detached from Non_sec CB and attached
to secure SB as part of msm_gem_get_iova_locked API, but S2
mapping entries are not modified and this causes crash.
Change-Id: Ib4c9fab4cd647d4ee3fb33f885ba2d578e2d46e7
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
When there is CPU processing delay between first INTR clear and
second INTR clear there is a chance that the second register
write might clear the next frames interrupts which will avoid
triggering the irq callbacks causing software hung. This
patch avoids such a scenario by removing such double clearing
of INTR registers.
Change-Id: I3b0c9cbb1fb0c45f6703a0df7ed20453dba7d468
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Acquire mngr clk_mutex before updating link clock frequencies.
Failing this may lead to race around condition while setting the
link clock frequency rates.
Make sure byteclk and pclk rates of PLL are configured according
to clock manager and not the controller.
Change-Id: I2cd26e659ce166d5bc55eb6c060672eeee192bea
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
In the current SW, cwb overflow interrupt is not enabled for
mid and low tier targets due to which CWB retire fence is
not signaled, causing HWCBufferSyncHandler SyncWait timeouts
on fence. This change enables the cwb overflow interrupt
always to detect the overflow and signal the retire fence in
such cases.
Change-Id: I4841814d91bcd7b31f00554da6b2369078ce4693
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change updates the time required to enter idle_pc based
on frame rate instead of default time. In the current issue,
customer is facing janks where frame rate is 30fps and race
happens between sde_encoder_off_work and drm_atomic_commit
scheduled from userspace. It also sets max and min bound for
optimized performance.
Change-Id: I5e95e920a2f7b2142b5f63e8ce6b82cf1d482db1
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
The issue is as follows:
Commit N:
1. VIG sspp qseed block programmed through lutdma. LUTDMA packet with
(ram offset, length_0) is queued to internal HW queue to enable
scaler.
2. Input_fence timeout seen on VIG plane.
3. White color solid fill layer staged on VIG plane.
4. Disable VIG sspp qseed block through LUTDMA. LUTDMA packet is queued
by overriding buffer with (ram offset, length_1) to internal HW queue
to disable scaler.
5. Trigger_flush is picked by HW on vsync.
Since 2 LUTDMA packets are queued on single vsync boundary pp_done timeout
with lutdma HW hang is seen. The only way to fix this is to reset LUTDMA
in step4 and then flush the Hardware. The current SW does not support this
reset sequence, so the change avoids staging solid fill on input fence
timeout.
Change-Id: Ia243e42c863f56b11bee5aeed2dd434efcbd5d75
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change checks for the atomic state and ensures
that allocation and deallocation of vcpi slots is
prevented in the same phase.
Change-Id: I05c87db43eca8ba749ed8a0907dcaf95945dd645
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
The issue is as follows:
Commit N:
1. VIG sspp qseed block programmed through lutdma. LUTDMA packet with
(ram offset, length_0) is queued to internal HW queue to enable
scaler.
2. Input_fence timeout seen on VIG plane.
3. White color solid fill layer staged on VIG plane.
4. Disable VIG sspp qseed block through LUTDMA. LUTDMA packet is queued
by overriding buffer with (ram offset, length_1) to internal HW queue
to disable scaler.
5. Trigger_flush is picked by HW on vsync.
Since 2 LUTDMA packets are queued on single vsync boundary pp_done timeout
with lutdma HW hang is seen. The only way to fix this is to reset LUTDMA
in step4 and then flush the Hardware. The current SW does not support this
reset sequence, so the change avoids staging solid fill on input fence
timeout.
Change-Id: Ia243e42c863f56b11bee5aeed2dd434efcbd5d75
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Current implementation we apply the color properties when atomic begin
is called and mark features as dirty if crtc is not enabled.
For some of the non double buffered features in video mode we will
see a corruption. Change removes marking color properties as dirty
based on crtc on/off.
Change-Id: I4d93b14627d2bc06fcbca3ea9538a4baedb00e56
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
In MST atomic check function, allow to release vcpi slots for
any case of changes in modes, active state or connectors for a crtc state.
This reverts the commmit id 28cde80bd3.
Change-Id: Ice13790f2e652b336619e1d78b42ddb708b4cb2e
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
During PM suspend in dual display usecase, the power off commit to
turn off primary and secondary crtcs is done with only one
drm_atomic_state scheduled on primary crtc_commit thread. At the
same, touch events can happen on secondary panel, which will
run input_event_work and schedule the sde_enc->delayed_off_work
to turn off its enabled resources. There can be race between primary
crtc_commit thread which unregisters input_event, cancels
all the pending works before setting sde_enc->cur_master to NULL
and input_event_work_handler which schedules the delayed_off_work
without checking the input_event_handler state.
This change adds input handler unregister check before triggering
_sde_encoder_rc_early_wakeup.
Change-Id: I553843f81078810784f18e92347f918ab6e4a9fe
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Improve logs for dual display case to differentiate between
primary and secondary display.
Change-Id: I8947ddcdce3f75095f4d74143ef8256ed5dd5b7d
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Check for array out of bounds while accessing
phys_encs lists.
Change-Id: If0af4bd274df5729d8edb62199cbd848586ef0d7
Signed-off-by: Gaurav LNU <quic_glnu@quicinc.com>
This change increases the buf array size to
accommodate all the characters as the buf array
will store each digit of bit and enable as a char.
Bit and enable variables are uint32 which could
have max value of 2^32(10 digit), each digit of
both variable will be stored as a char in buf
(char)array.
Change-Id: Iab6fcddc425642a29c6c0a59884121e328707465
Signed-off-by: Gaurav LNU <quic_glnu@quicinc.com>
When wfd display is connected, qseed3 coefficient lut programming
is getting erased due to idle pc entry for wfd pipes. On idlepc
exit commit, plane properties are not reconfigured from userspace
since support is not present for writeback crtc. This patch
updates idle pc handling to avoid gdsc power off when writeback
crtc is connected and for CWB encoder gdsc power off will happen
on idle pc entry.
Change-Id: I5dbab75bdc647b8f3c2a23cbb4e9d82239fe533d
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
CPU qos_mask populated from devicetree can have defective cpu cores
included. This change identifies and replaces the defective cores
in the qos mask with the next possible working cpu cores.
Change-Id: I0f32205e7f0abf0482d7dbbd288b7d7f3088726a
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
Large allocations using kvzalloc can lead to timeouts.
This updates the allocation calls accordingly to use
vzalloc to remove requirements on physically
contiguous memory.
Change-Id: I437913b3bf2e46bfeeb2c511bdfc153470fcbc24
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
Add check to avoid programming the color processing HW if sde_crtc is
not enabled.
Change-Id: I7ffd341147f0caebefb647486a139df5c0aeab31
Signed-off-by: Ping Li <quic_pingli@quicinc.com>
