In CWB use case along with suspend commit, the function
drm_crtc_funcs.get_vblank_counter returns a zero vsync count
value. This causes blocking of drm_crtc_funcs.disable_vblank,
leading to a wait for vsync timeout while disabling the encoder.
hence clear a cwb encoder mask in encoder disable and set it
while performing mode set.
Change-Id: Ic994aa0a86faf48e2b25955cf6fe12166fe9d328
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In POMS use case, the handling of the wait for vsync event
completion coincides with the concurrent
drm_crtc_funcs.enable_vblank. This concurrency causes a vsync
event complete timeout while disabling the encoder. to fix this
concurrency problem, increment the vblank refcount in encoder
disable and release the vblank refcount in encoder enable.
Change-Id: I79671e4a2bafdd01a6b2523a80fe511bff23d6b6
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
This change adds out of bound check for interrupt id.
Change-Id: I10e786ee434629b0735c96da3c03eeac708935a1
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
Ensure to allocate switch type as bypass in case of dp aux switch
node missing in device tree entry and prevent any scope of null
pointer dereferencing.
Change-Id: I1d50d785e028f2e69a0effaedb2dbb6568a473dd
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
In the current SW design for a CWB commit the need for 3D-Merge
and number of CWB mux which needed to tap the LMs are decided
based on number of mixers on crtc. When there is a partial update
commit in single LM these 3D-Merge and CWB mux active are used
leading to WB commit failures. This change properly check whether
3D-Merge is needed in CWB path based on number of LMs in a partial
update commit.
Change-Id: I2c838a24ad3a259923f6b26934e681cb9a5829b6
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
The issue scenario is as follows
1. A CWB commit has run and it has disabled. Composer kill is
done.
2. If Composer starts again or another client has open DRM
the previous cwb state is intact.
3. When userspace is trying to query wb modes, primary modes
which are attached to wb as part of cwb commit is exposed.
This leads to commit failures if userspace is trying to trigger wb
on the same CRTC of what primary has run cwb before. This change
properly clears wb mode and the cached encoder mask to avoid commit
failures.
Change-Id: I4ca8bd2b52a980630b7fb1319bf67b718ebb2ac2
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
* changes:
disp: config: add support for fsa and wcd aux switch for crow target
disp: msm: dp: Parse device tree to find specific aux switch
disp: msm: dp: Add abstract and wcd939x aux switch support
Add support for fsa and wcd aux switch for crow target.
Change-Id: If50226c5f9f7cbb3a1ab1d469bc2c9efa0b541c4
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
Changes to select particular dp_aux_switch based on board
requirements. Currently provision to support both fsa4480
and wcd939x as aux switches are provided.
Change-Id: Iafbee4d91d14aafb1e7a37ddfa2b1ea0d0e5e784
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Add functionality to change which aux switch is used
at compile time for different targets. Add wcd939x
switch support.
Change-Id: Iced3b11733009680063790dfa8f180b19002f963
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
In POMS use case while disabling the virtual encoder, the virt
reset function sets the current master to null. concurrently, if
there is a query from the DRM client for the current vsync count,
it returns a zero value. This results in the blocking of the
drm_crtc_funcs.disable_vblank function. since the vsync count
has been relocated to the virtual encoder, remove the physical
encoder structure.
Change-Id: Ie692df657b5a86b6b8915a15e9a070642243fcfb
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Add support for fsa and wcd aux switch for crow target.
Change-Id: If50226c5f9f7cbb3a1ab1d469bc2c9efa0b541c4
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
Changes to select particular dp_aux_switch based on board
requirements. Currently provision to support both fsa4480
and wcd939x as aux switches are provided.
Change-Id: Iafbee4d91d14aafb1e7a37ddfa2b1ea0d0e5e784
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Add functionality to change which aux switch is used
at compile time for different targets. Add wcd939x
switch support.
Change-Id: Iced3b11733009680063790dfa8f180b19002f963
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
If continuous splash is enabled crtc_state active is set to true
from the driver. During the handoff commit this new_state is compared
with the older state and active change will be set to false. If there
is a race condition between the continuous splash config and atomic
check of the first commit, an improper state with active change to
true is formed leading to commit failure. This change makes sure drm
device will get initialized and registered after continuous splash
config which will block the userspace from the handoff commit.
Change-Id: I91aa64c480a3341488f1e2c9422c9a2b8200fe53
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Set the number of layer mixer for each wb mode based on the
current mode hdisplay width. If the hdisplay width of current
mode is greater than the maximum layer mixer width of HW supported,
set dual layer mixers for this mode and check if the split
hdisplay width is an even number.
Change-Id: I0190830ed559f008f9e2c0752858ddc5e7cb83cd
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Change log level for unavailable slave pll from warn to debug
to avoid redundant logs as parrot supports only one DSI.
Change-Id: I200a2f382a1dca7035e4960d3bb0c877867f8ba8
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Add property to parse the ddr type and select the vbif QOS
values based on the detected ddr type.
Change-Id: Ifc980b5bdadc38b7b0882568a1f07e4e8441303a
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Introduce vsync count variable in virtual encoder structure
to keep the vsync count variable value in sync while performing
the poms. Consequently, this prevents the blocking of
drm_vblank_put and the invocation of
drm_crtc_funcs.disable_vblank.
Change-Id: I74903a89b17a8f46fb1b21338500553f36771dd0
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
This change decrements the specific drm connector's reference count
after it has been used for reading crc frame value. Without this
change, there might be a chance of a connector's reference count
still remaining positive, even if it is not accessed anywhere
further in code.
Change-Id: I9058ca046fa114bc10159045f98c40ac68ade751
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Disable CWB in quad pipe for quad LM CWB not supported
to avoid out of bound access.
Change-Id: I0348a7fa318b9fa9886d35d5e233d81c8135d2ee
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
When continuous splash is disabled current drm mode is not assigned
in old crtc state. While enabling quad-pipe topology invalid layout
split is populated from this mode causing commit check failure. This
change properly gets the required mode from the new drm_crtc_state
to avoid such issues.
Change-Id: I198fd1c9c91995e282927e246d96373b4f0fc8b1
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Currently, ctrl lock is taken while waiting for CMD DMA done even in
case of ASYNC command transfer, which doesn't allow any other operation
on the controller until the command transfer is done. Avoid this by not
taking ctrl lock while waiting for CMD DMA done.
Change-Id: I91f2638fa02f48ec4c7a41c750daa46b52c5e2f2
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
The dptx link and pclk rcg clocks will be using byte2_ops
and expects the frequency to be set in hz.
Change-Id: Ia961dbd3441c8e37ba3afa5a68bbb76ea9be7f07
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
Convert clock operation to byte2 ops to meet DISPCC requirement.
Clock unit is changed from KHZ to HZ. Added link clock parent as
freq table is no longer supported in byte2 ops.
Change-Id: Iefeca1ecf7fb6335c45f7664a661d1bbe2d6f1e5
Signed-off-by: Xiaowen Wu <wxiaowen@codeaurora.org>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
When there is runtime PM suspend and a video mode panel is Doze
state or Doze suspend state PM suspend will fail as clocks are on.
To avoid this do a suspend commit while entering runtime PM suspend
so that xo shutdown will be successful.
Change-Id: I108184bf2e5ea18ef54eab879556e9c941514176
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Before pm_suspend is called when there is a vsync enable event
from sf and disabling is not done pm_suspend will fail.
Following are the commit states when a pm_suspend is called:
1. Normal Active Commit - When an active commit is going on
and pm_suspend is called then forcefully do a disable
commit. This will make sure in encoder virt_disable
wait for vsync disable is exited only after vsync is
disabled.
2. Suspend Commit - When suspend commit is going on
the wait for vblank disable in encoder virt_disable will
make sure the pending vsync event from sf is already
triggered.
3. Doze mode - When in doze mode in pm_suspend we will
forcefully do a commit to change to doze suspend.
In this case, we will make sure that the commit is
completed and rc_idle is kicked in. There is a chance
disabling of vblank irq is not done in this case.
4. Doze Suspend mode- This is same as Doze Mode where
vblank irq may not be disabled.
To resolve the issue in Case3 and 4 wait for a vblank irq is added
which will queue the vblank disable work to event_thread and make
sure the queued work is completed by doing a kthread_flush.
Change-Id: I8f9969c3865f7396d6e87819d65c7b16be73ad39
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
