For a proxy-scheduled VCPU like the TUI VM, assignment to a
physical core is a runtime decision made by the HLOS scheduler,
and it may change frequently. pm_qos vote added by PVM for
specific CPUs won't be sufficient for addressing irq latency.
This change updates votes for all possible CPUs during TVM
entry and also removes the vote during exit.
Change-Id: Iab5cb5f57e2389ee57689ba2ab69394376f59788
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
The dp_display_disconnect_sync is disabling the aux switch during
the attention hpd low processing. Ideally, the aux switch needs to
be turned off only when the dp cable is disconnected. With aux switch
getting turned off even while cable is connected is leading to HDCP
compliance test failure. This change will turn off aux switch only
when the cable is disconnected. It reverts the commit id
b6466ca7f5.
Change-Id: I90cc5f31b2be1afda61f74ea4e0a44332811ead3
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Default mode of dump_mode in sde_dbg module is in_mem, and
it changes to in_coredump when hw_recovery feature is enabled.
This change allows developer to redefine in_log_limited as
default mode, and it's unchangeable even when hw_recovery is enabled.
Change-Id: I51574b3ac297f32f28ae7a69d008d1a5f443a781
Signed-off-by: Bruce Hoo <quic_bingchua@quicinc.com>
Add rc feature disable handling in case set rc feature fails.
This will disable rc feature for all instances if set rc feature
fails for any instance.
Change-Id: I159b9bd3ed1416c4b2d32440d10132cb024f9529
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
Reset number of bytes read from panel to the expected value when panel
sends more bytes than requested during DSI read. This can otherwise lead
to negative value of repeated bytes and array out of bounds access.
Change-Id: I9310c521a862108940142ba7c1a8c39838be0f79
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Use macros for corresponding registers offset in DSI_R32/DSI_W32.
Change-Id: I91052e9124a11f67e3056c79918820c476a39ad0
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Add debug log to dump qtimer information after the input hw-fence
signal configuration.
Change-Id: I7617b1a6bae3db1e003c42bfe306dbe7f552ad83
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Add display event log for the display input hw-fence.
Change-Id: Id0fc19565c7b83c8009ab518dae7323db534b66e
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Add rc feature disable handling in case set rc feature fails.
This will disable rc feature for all instances if set rc feature
fails for any instance.
Change-Id: I159b9bd3ed1416c4b2d32440d10132cb024f9529
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
Starting with HW-Fencing, the frames hw kickoff
can take longer to trigger, given that HW will wait for the
input fences signal. Therefore, this change increments
the time-outs to wait up to ~10 secs, which corresponds
to the current input dma-fences timeout. This ~10secs
wait is given in intervals, where the dma-fence is also
checked, so in case that the client producer of the fence
signals the dma-fence, but misses the hw-fence signaling,
Display driver can handle this case and do a sw-override
to start the fetching of the incoming frame without waiting
for the input hw-fence ipc signal.
Change-Id: I6fcacbbaa79ca9847da616bd52efdda4bb8fccae
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Provide more information in the failure case of panel
TE source parsing by improving the error log.
Change-Id: Iaa492886af9c16effca0744950772bd621fb0f50
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
The link maintenance irq_hpd events triggered while the DP hdcp
session is active, require hdcp session disable and reauthentication.
These changes will disable hdcp before processing the link update
irq_hpd and enable hdcp soon after successful relink training and
video enable.
Change-Id: I35f622cc2e058d892ce6f091070f868eabac43d2
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
In some vm transitions, pp work might get executed on event thread
after handoff is completed on commit thread leading to crash.
This change flushes the pp event thread queue during vm pre-release
before lending the io resources to the other vm.
Change-Id: I53b76e48bc15084aa5519409fae0e692f49e7558
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
In some corner cases there is pending vsync timestamp event to
sf when encoder is getting disabled. This is keeping vblank irq
to be enabled after sde_encoder_virt_reset leading to NULL ptr
access. In these cases, wait for vsync event to be completed which
disables the irq.
Change-Id: If0a6be1fc282906fb1b9c0fd18ede1d31d2549b3
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
There is race condition in below scenario leading to crash
in sde_encoder_virt_enable as sde_enc->cur_master is set to
NULL in sde_encoder_virt_reset in earlier CWB disable commit.
1) commit1-CWB retire fence signalled.
2) commit1-CWB disable commit still in progress.
3) commit2-New WB commit in progress.
4) commit1-sde_enc->cur_master is set to NULL in CWB disable commit.
5) commit2-Crash seen in sde_encoder_virt_enable in WB commit.
Also, as WB HW is still attached to commit1 till the next wr_ptr,
new WB session cannot be allowed. Adding validate check to fail
WB session when CWB is still not cleared in CTL path.
Change-Id: I62aca05f8380d3621d4980c0820cdd4da37b3dc1
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
The read_u64() of dsi parser utils function can also return
-ERANGE for the overflow in case of dsi parser. Handle this
error for the overflow case.
Change-Id: I3994d1b9c650f6c265913c50a2cca72907a4703d
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
disable encoder post processing module for all ping pong
modules in a given topology.
Change-Id: If81aa7c392e2270dab599e1d15c2ea905cb437d8
Signed-off-by: Sanskar Omar <quic_sansomar@quicinc.com>
There can be a scenario where fps change along with dynamic clock
happen in a same commit. This makes newer dynamic clock configuration
come to impact while leaving panel vblank to function as per the older
configured fps. This is invalid modeset, add validation check for the
same.
Change-Id: I32f15de5260d3abdb16a4b1c3f8eefc8bd634848
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Implement dsi parser u64_read function which is used to
read 64 bit clk rate.
Change-Id: I4671fb2d3d91df0fbac8ac623b38377447184ee3
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Clock rates are calculated in dsi_display_update_dsi_bitrate(),
not dsi_display_dynamic_clk_switch() in case of dynamic clock.
Correct the comment in dsi_ctrl_update_host_config()
to avoid confusion.
Change-Id: Ie949938accae028a0b7e9dc976508fee355a8e8a
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
In the case of DMS the dsi phy timings get updated in
dsi_display_set_mode() and the clock in pre_kickoff().
This brings a mismatch between phy timing and the clock between the
above two operations. For example, during dsi_display_enable(),
the HW is programmed with the new phy timings but the clock is still
running at the older rate. This mismatch can lead to screen flicker
or error.
Update the phy timings and clocks together during pre_kickoff().
Change-Id: I30198e91aba5879b1773103c088d94175639790c
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
When broadcast command is sent with command DMA window scheduling enabled,
DSI_TRIG_CTRL.COMMAND_MODE_DMA_TRG_MUX does not get reset after command
transfer. Due to this next unicast command on slave fails.
This change resets DMA trigger mux during DSI_TRIG_CTRL initialization.
Change-Id: I74503d82ab1cb6ca4d61a9d14f2b3cd2c3936ea7
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
In DMA start window scheduling, TRIG_CTRL.COMMAND_MODE_DMA_TRIGGER_SEL
is programmed to SW + DMA start window trigger. But if DMS switch
comes after command is scheduled, COMMAND_MODE_DMA_TRIGGER_SEL gets
reprogrammed to SW trigger leading to command transfer failure.
Program the COMMAND_MODE_DMA_TRIGGER_SEL only from the CMD DMA Tx path.
Change-Id: I01062497bb70aa5fdcb25be3715c7cbc4c68b681
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
clear cached rectangles when PU ROI is set to avoid incorrect
cached rois when two subsequent state duplications occur due
to timing. This will lead to commit N and commit N+1 to have
same cached ROIs as commit N-1. This results in issues when
commit N-1 is PU, N is full frame and N+1 is PU with same
ROI as N-1.
Change-Id: I3bb9390e500d327e703e41d64f7aaae5e5f1b4f2
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
