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disp: msm: sde: add memory barrier to avoid out of order writes

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add memory barrier before and after last command to avoid
out of order packet queuing to lut dma packet queue.

add memory barrier after ctrl flush to ensure lut dma
trigger, dspp flush and ctrl flush all are written to dpu
before control start.

Change-Id: I7e1613034af8407d55529cf3f95c70994334af82
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
This commit is contained in:
Anjaneya Prasad Musunuri
2022-11-06 16:41:37 +05:30
committed by Gerrit - the friendly Code Review server
parent a0cf3e61af
commit dd632ed2f7
2 changed files with 13 additions and 0 deletions
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3
msm/sde/sde_hw_ctl.c
View File

@@ -818,6 +818,9 @@ static inline int sde_hw_ctl_trigger_flush_v1(struct sde_hw_ctl *ctx)
SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
/* ensure all register writes are written without re-ordering*/
wmb();
return 0;
}

10
msm/sde/sde_hw_reg_dma_v1.c
View File

@@ -709,6 +709,13 @@ static int write_kick_off_v1(struct sde_reg_dma_kickoff_cfg *cfg)
SDE_EVT32(val);
}
if (cfg->last_command) {
/* ensure all packets are queued in packet queue before
* queuing last command descriptor (last command)
*/
wmb();
}
if (cfg->dma_type == REG_DMA_TYPE_DB) {
SDE_REG_WRITE(&hw, reg_dma_ctl_queue_off[cfg->ctl->idx],
cfg->dma_buf->iova);
@@ -722,6 +729,9 @@ static int write_kick_off_v1(struct sde_reg_dma_kickoff_cfg *cfg)
}
if (cfg->last_command) {
/* ensure last command is queued before lut dma trigger */
wmb();
mask = ctl_trigger_done_mask[cfg->ctl->idx][cfg->queue_select];
SDE_REG_WRITE(&hw, reg_dma_intr_clear_offset, mask);
/* DB LUTDMA use SW trigger while SB LUTDMA uses DSPP_SB