This changes fixes null pointer dereference issue.
Change-Id: I9a9628f1fb274aea86a15792ac85b8505f25d28f
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
Signed-off-by: Bruce Levy <quic_blevy@quicinc.com>
This change adds robustness to hpd notification by resending
it if there was no action in 2 seconds, just in case, the
first notification didn't make it to the usermode.
Change-Id: Iaf00669ec77e8c50618ee5618735a98518ad7f1a
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
With real DP over Type-C sinks, DP driver requests access to USB
combo PHY from USB driver. But in DP SIM mode, there is no real
sink and PD management, so the combo PHY is managed by USB driver
and DP driver uses it without actually claiming it. If the USB
cable is unplugged in this scenario, USB driver notifies the
disconnection through an atomic notifier call. It does not expect
the handler to go into sleep, but the disconnect handler inside
DP driver has multiple wait for events and also sleeps to wait for
HW state updates.
This change passes a skip_wait flag to all the disable functions
to complete disconnect processing by skipping all processor sleeps
and event waits.
Change-Id: Ia98de0e7fa6b0573e644615ee59015914a93f4cf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
DP sim ports created during DP sim enable aren't cleared
during disable path. This would retain the last status of
the DP sim port or the connector. This would impact the
next iteration of DP sim test, if done without device
reset. This change will set the port number to 0 during
DP sim disable and clear the memory allocated for these
ports.
Change-Id: I386a62e87fcaf006db8dd18e5751b33bbe70fc9b
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Use with the new connector state during validation phase for
checking the 3d-merge topology, since this is the state that
needs to be validated.
Change-Id: Ie212f948affa4dc439ef508363bac6713e560006
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Avoid shutting down DSI PHY and lanes before entering into
idle collapse.
Change-Id: I62fb40c2398e544b08b8cb8788ac2dc1143a82ce
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
DSI PHY has various resets defined to reset analog, PLL and digital
portions. In current sequence, these resets happen after PLL is locked
which can result in introduction of jitter on PHY lanes.Reordering these
resets to happen before PLL is programmed to have intended clean start
of DSI PHY.
Change-Id: I4eb5c05ea0e6015a5447728b2845b49817411c50
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Change the debug message to error during the writeback
encoder validate for wb output buffer. The output buffer
can be NULL only during disable frame and all other frames
need to have a valid output buffer.
Change-Id: I4d6fecfeaf863e56fe25e17ab1200849003b3309
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This reverts commit 14e7e9b409346aa77fd08cca6eab85252d9ccabe.
Reverting this for now until we properly understand the reason
for command transfer timeouts that we are hitting for 5k panel.
Change-Id: I0390af66f9ca06abc1ebb81996bb683dea35beac
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
This change adds a debug node named 'crc' to drm_dp to read
the frame CRC values for DP controller and DP Sink. In order
to facilitate the immediate read of the CRC values when
accessed, it enables the CRC calculation on the controller
and sink automatically when the stream is enabled. In addition
to the frame CRC values it also reads the MISR values from
controller and PHY to validate the data flow from controller
to PHY.
Change-Id: I1acee2dba931e4635caf4a400e336a72c86e88bf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Add validation during crtc_atomic_check to have crtc width as
multiple of 4 when dualpipe 3d-mux is enabled and multiple of 8
when quadpipe 3d-mux is enabled. This ensures each layer mixer
is having an even width.
Change-Id: I5dc173c1b0349430a8e12a7b1c9440c7854e7ecd
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, driver is determining the amount of memory to allocate
based on the event log object indexes (first, last). The last index
can change if there is additional logging done during the coredump
phase and potentially cause an out-of-bound memory access during
buffer traversal.
This change restrict the event log object traversal to a maximum
of the output buffer size.
Change-Id: I91e5734362d2d7a796129fce85e27611bab2245f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
During MST scenario, plugging out all the downstream monitors connected
to the MST hub would trigger a disconnect handler which would cleanup
display structure. This isn't required since MST hub is still connected
and the display cleanup would be taken care during the actual MST hub
disconnect. Also, handling the disconnect immediately on port status
notification leaves the usermode in an invalid state where it assumes
the display is still enabled and results in commit errors.
Change-Id: Ia9a58fadd89bd05746da25f142b54b31e8567258
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Currently, dnsc_blur hardware block is not updated when the connector
dnsc_blur property is set to NULL or when dnsc_blur_count is 0. Update
the dnsc_blur hw block configs to avoid stale configs affecting the
current frame.
Change-Id: I39934a8b9490a13a0f77f3b5dbc5053b76a9370b
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Use with the new connector state during validation phase for
checking the 3d-merge topology, since this is the state that
needs to be validated.
Change-Id: Ie212f948affa4dc439ef508363bac6713e560006
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
MDSS 9.0.0 supports 10 pipes, so modify the max_planes
accordingly. This is used for the frame_data transfer
between user/kernel and since its a new feature added
there is no backward compatibility that needs to be handled
for this uapi change. Add corresponding bound check during
the usage.
Change-Id: I0853fcc55395855d798f2c1b03cf9bf7b4bd3c96
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change skips msm_lastclose, when splash enabled builtin-displays
equals number of actual displays and are stuck in continuous splash.
It fixes the issue seen with change commit 548b17185e95
("disp: msm: send power_on event in dual display composer kill scenario").
Change-Id: I1f5417d8945db621dc20ab0a9cc0146eabae5e22
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This patch cancels all the delayed_off_works if scheduled and flushes
the display threads for completion during msm_lastclose. The commit
from msm_lastclose client modeset to disable any crtcs if enabled is
always scheduled on primary crtc_commit thread. In the current issue,
delayed_off_work is scheduled on secondary display crtc_commit thread
and primary crtc_commit thread is scheduled to turn off active crtcs
from msm_lastclose leading to null dereference access of sde_enc's
cur_master. This race is avoided by serializing the operations in
msm_lastclose.
Change-Id: I30cc95b925c8134f0064816ebe2cfdb86a49fb36
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Currently, driver is determining the amount of memory to allocate
based on the event log object indexes (first, last). The last index
can change if there is additional logging done during the coredump
phase and potentially cause an out-of-bound memory access during
buffer traversal.
This change restrict the event log object traversal to a maximum
of the output buffer size.
Change-Id: I91e5734362d2d7a796129fce85e27611bab2245f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add validation during crtc_atomic_check to have crtc width as
multiple of 4 when dualpipe 3d-mux is enabled and multiple of 8
when quadpipe 3d-mux is enabled. This ensures each layer mixer
is having an even width.
Change-Id: I5dc173c1b0349430a8e12a7b1c9440c7854e7ecd
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
