Merge "ARM: dts: msm: Add a node for cpufreq cycle counter driver"
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18
qcom/sm6150-walt.dtsi
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18
qcom/sm6150-walt.dtsi
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@@ -0,0 +1,18 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&soc {
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walt {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qcom,cycle-cntr {
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compatible = "qcom,cycle-cntr-hw";
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reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
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reg-names = "freq-domain0", "freq-domain1";
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};
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};
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};
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258
qcom/sm6150.dtsi
258
qcom/sm6150.dtsi
@@ -867,6 +867,245 @@
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cap-based-alloc-and-pwr-collapse;
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};
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llcc_pmu: llcc-pmu@90cc000 {
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compatible = "qcom,llcc-pmu-ver2";
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reg = <0x090cc000 0x300>;
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reg-names = "lagg-base";
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};
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cpu_pmu: cpu-pmu {
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compatible = "arm,armv8-pmuv3";
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qcom,irq-is-percpu;
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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qcom,pmu {
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compatible = "qcom,pmu";
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qcom,long-counter;
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qcom,pmu-events-tbl =
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< 0x0008 0xFF 0xFF 0xFF >,
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< 0x0011 0xFF 0xFF 0xFF >,
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< 0x0017 0xFF 0xFF 0xFF >,
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< 0x002A 0xFF 0xFF 0xFF >,
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< 0x1000 0xFF 0xFF 0xFF >;
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};
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ddr_freq_table: ddr-freq-table {
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qcom,freq-tbl =
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< 200000 >,
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< 300000 >,
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< 451000 >,
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< 547000 >,
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< 681000 >,
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< 768000 >,
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< 1017000 >,
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< 1353000 >,
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< 1555000 >,
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< 1804000 >;
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};
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llcc_freq_table: llcc-freq-table {
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qcom,freq-tbl =
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< 150000 >,
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< 300000 >,
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< 466000 >,
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< 600000 >,
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< 806000 >,
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< 933000 >;
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};
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qcom_dcvs: qcom,dcvs {
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compatible = "qcom,dcvs";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qcom_ddr_dcvs_hw: ddr {
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compatible = "qcom,dcvs-hw";
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qcom,dcvs-hw-type = <0>;
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qcom,bus-width = <4>;
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qcom,freq-tbl = <&ddr_freq_table>;
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ddr_dcvs_sp: sp {
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compatible = "qcom,dcvs-path";
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qcom,dcvs-path-type = <0>;
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interconnects = <&mc_virt MASTER_LLCC
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&mc_virt SLAVE_EBI1>;
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};
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};
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qcom_llcc_dcvs_hw: llcc {
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compatible = "qcom,dcvs-hw";
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qcom,dcvs-hw-type = <1>;
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qcom,bus-width = <16>;
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qcom,freq-tbl = <&llcc_freq_table>;
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llcc_dcvs_sp: sp {
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compatible = "qcom,dcvs-path";
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qcom,dcvs-path-type = <0>;
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&gem_noc SLAVE_LLCC>;
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};
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};
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qcom_l3_dcvs_hw: l3 {
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compatible = "qcom,dcvs-hw";
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qcom,dcvs-hw-type = <2>;
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qcom,bus-width = <32>;
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qcom,ftbl-row-size = <0x20>;
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reg = <0x18321000 0x4000>, <0x18321110 0x500>;
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reg-names = "l3-base", "l3tbl-base";
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l3_dcvs_sp: sp {
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compatible = "qcom,dcvs-path";
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qcom,dcvs-path-type = <0>;
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qcom,shared-offset = <0x0920>;
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};
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};
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};
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qcom_memlat: qcom,memlat {
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compatible = "qcom,memlat";
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ddr {
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compatible = "qcom,memlat-grp";
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qcom,target-dev = <&qcom_ddr_dcvs_hw>;
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qcom,sampling-path = <&ddr_dcvs_sp>;
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qcom,miss-ev = <0x1000>;
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silver {
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compatible = "qcom,memlat-mon";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
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qcom,cpufreq-memfreq-tbl =
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< 748000 300000 >,
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< 1017600 451000 >,
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< 1209600 547000 >,
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< 1516800 768000 >,
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< 1804800 1017000 >;
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qcom,sampling-enabled;
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};
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silver-compute {
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compatible = "qcom,memlat-mon";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
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qcom,cpufreq-memfreq-tbl =
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< 748800 300000 >,
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< 1209600 451000 >,
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< 1593600 547000 >,
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< 1804800 768000 >;
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qcom,sampling-enabled;
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qcom,compute-mon;
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};
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gold {
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compatible = "qcom,memlat-mon";
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qcom,cpulist = <&CPU6 &CPU7>;
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qcom,cpufreq-memfreq-tbl =
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< 768000 451000 >,
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< 1017600 547000 >,
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< 1209600 1017000 >,
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< 1708800 1555000 >,
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< 2208000 1804000 >;
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qcom,sampling-enabled;
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};
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gold-compute {
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compatible = "qcom,memlat-mon";
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qcom,cpulist = <&CPU6 &CPU7>;
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qcom,cpufreq-memfreq-tbl =
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< 1017600 300000 >,
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< 1209600 547000 >,
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< 1516800 768000 >,
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< 1708800 1017000 >,
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< 2208000 1804000 >;
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qcom,sampling-enabled;
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qcom,compute-mon;
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};
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};
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llcc {
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compatible = "qcom,memlat-grp";
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qcom,target-dev = <&qcom_llcc_dcvs_hw>;
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qcom,sampling-path = <&llcc_dcvs_sp>;
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qcom,miss-ev = <0x2A>;
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silver {
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compatible = "qcom,memlat-mon";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
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qcom,cpufreq-memfreq-tbl =
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< 748000 150000 >,
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< 1209600 300000 >,
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< 1516800 466000 >,
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< 1804800 600000 >;
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qcom,sampling-enabled;
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};
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gold {
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compatible = "qcom,memlat-mon";
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qcom,cpulist = <&CPU6 &CPU7>;
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qcom,cpufreq-memfreq-tbl =
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< 768000 300000 >,
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< 1017600 466000 >,
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< 1209600 600000 >,
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< 1708800 806000 >,
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< 2208000 933000 >;
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qcom,sampling-enabled;
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};
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};
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l3 {
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compatible = "qcom,memlat-grp";
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qcom,target-dev = <&qcom_l3_dcvs_hw>;
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qcom,sampling-path = <&l3_dcvs_sp>;
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qcom,miss-ev = <0x17>;
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silver {
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compatible = "qcom,memlat-mon";
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qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
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qcom,cpufreq-memfreq-tbl =
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< 576000 300000 >,
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< 1017600 556800 >,
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< 1209660 806400 >,
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< 1516800 940800 >,
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< 1804800 1363200 >;
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qcom,sampling-enabled;
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};
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gold {
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compatible = "qcom,memlat-mon";
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qcom,cpulist = <&CPU6 &CPU7>;
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qcom,cpufreq-memfreq-tbl =
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< 1017600 556800 >,
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< 1209600 806400 >,
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< 1516800 940800 >,
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< 1708800 1209600 >,
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< 2208000 1363200 >;
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qcom,sampling-enabled;
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};
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};
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};
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bwmon_llcc: qcom,bwmon-llcc@90b6400 {
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compatible = "qcom,bwmon4";
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reg = <0x90b6300 0x300>, <0x90b6200 0x200>;
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reg-names = "base", "global_base";
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interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
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qcom,mport = <0>;
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qcom,hw-timer-hz = <19200000>;
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qcom,count-unit = <0x10000>;
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qcom,target-dev = <&qcom_llcc_dcvs_hw>;
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};
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bwmon_ddr: qcom,bwmon-ddr@90cd000 {
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compatible = "qcom,bwmon5";
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reg = <0x90cd000 0x1000>;
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reg-names = "base";
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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qcom,hw-timer-hz = <19200000>;
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qcom,count-unit = <0x10000>;
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qcom,target-dev = <&qcom_ddr_dcvs_hw>;
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};
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ufsphy_mem: ufsphy_mem@1d87000 {
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reg = <0x1d87000 0xe00>; /* PHY regs */
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reg-names = "phy_mem";
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@@ -1223,6 +1462,24 @@
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};
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};
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reboot_reason {
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compatible = "qcom,reboot-reason";
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qcom,no-nvmem-cell-support;
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};
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qcom,chd {
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compatible = "qcom,core-hang-detect";
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label = "core";
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qcom,chd-percpu-info = <&CPU0 0x18000058 0x18000060>,
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<&CPU1 0x18010058 0x18010060>,
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<&CPU2 0x18020058 0x18020060>,
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<&CPU3 0x18030058 0x18030060>,
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<&CPU4 0x18040058 0x18040060>,
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<&CPU5 0x18050058 0x18050060>,
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<&CPU6 0x18060058 0x18060060>,
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<&CPU7 0x18070058 0x18070060>;
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};
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qcom,mpm2-sleep-counter@c221000 {
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compatible = "qcom,mpm2-sleep-counter";
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reg = <0xc221000 0x1000>;
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@@ -1635,6 +1892,7 @@
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#include "sm6150-qupv3.dtsi"
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#include "sm6150-usb.dtsi"
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#include "sm6150-dma-heaps.dtsi"
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#include "sm6150-walt.dtsi"
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&tlmm {
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status = "okay";
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