For calculating bit rate in cphy, we multiply bit rate by a factor of
7/16 where 7 is the number of symbols and 16 is the bits per symbol.
But we are currently not considering the 7/16 factor while calculating
minimum bit clk value for command mode which is resulting in a smaller
bit rate value than the minimum bit clk.
Bit rate should always be greater than the minimum bit clk which otherwise
can lead to discrepancies. Correct minimum bit clk calculation for command
mode, by multiplying a factor of 7/16 if cphy.
Change-Id: I39b202dcafe60e2047549f84ff9388b46ae490a5
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
After triggering dynamic refresh, if there is any dsi_ctrl_isr, dynamic
refresh done status also gets cleared as part of it. Because of this,
wait4dynamic_refresh_done timeout error is seen even though dynamic refresh
is done successfully.
Change-Id: I39b42c60d15d9cb0557669f95ff2ed83989f9cd3
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Currently, we are always initializing PLL registers whenever PLL is
configured. Re-initializing PLL registers during dynamic clock switch in
case of cphy video mode is moving the PLL to some bad state resulting in
display freeze. Avoid this by restricting initialization of PLL registers
to only while turning on the PLL. This change is for 4nm PLL.
Change-Id: I57c8cfe1927f83f1ac25238c696a606960f3a8c8
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
This change adds a device-tree configurable property to define
the ipcc client id of the dpu used for registers access and
configuration. Starting pineapple, this is the ipcc client physical
id, distinct from the ipcc client virtual id.
Change-Id: Icb59111c85c7132c0efd7b207eaa5417cca013eb
Signed-off-by: Grace An <quic_gracan@quicinc.com>
When calculating the Rate Governor parameters for MST, if the
stream is compressed, the calculator expects the input bpp to be
the compressed bpp, but currently the driver is passing uncompressed
bpp. This change updates the driver to pass compressed bpp to the
calculator.
Change-Id: Iac51d75843bd0072bbe07142ac4533d841f795f5
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
During DP sim test cases there is a chance that userspace would
call into SDP config ops even when display is not active which
would lead to NOC errors. This change checks for display status
during SDP config operation.
Change-Id: I330f6fc162f3366a9ca0aeb64956927dceca4c80
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
In some cases while transitioning between vm, vblank
work might be get executed on event thread after handoff is
completed on commit thread leading to crash. This change
flush the event thread queue during vm pre-release before
lending the io resources to the other vm.
Change-Id: Ife1fea54dd236cc4cbca70f7636d27c4de1280ec
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
When using the TU calculator for SST DSC usecase, the calculator
expects the bpp to be 24 irrespective of the actual panel bpp.
Change-Id: Ifdab2c00a2a99b4d7d7dea7eadb33bc34e3cfa8b
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Pipe csc configuration is being cached in the sde plane which can cause
race conditions between hardware programming and caching.
All drm properties should be cached in sde plane state to avoid race
conditions. Change moves caching to sde plane state.
Change-Id: I22470a82b2fc2812f8c526ababc2b517db13a3ce
Signed-off-by: Gopikrishnaiah Anand <quic_agopik@quicinc.com>
As per DP HPG recommendation, controller flush mode is
set to be synchronous with a vsync. This requires a
peripheral flush to be issued for HDR SDP to be processed.
Currently in a static HDR use case, since the peripheral
flush is not issued after queueing an HDR SDP, it never
gets sent to the sink and it stays in SDR mode. This change
issues a peripheral flush on every DP commit, so that
any pending SDPs are flushed.
Change-Id: I0ed82b6cd8df33539a3067c6ad9827f74de2ed51
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Currently, hdcp wait loops uses the wait_event() macro which sets the
status of the thread to WAIT_UNINTERRUPTIBLE and contributes to system
load. The macro wait_event_idle() polls for a changing condition in the
same way but instead sets the thread status to WAIT_IDLE which does not
contribute to system load. This prevents hdcp threads from appearing as
hung threads in system load summaries while still properly polling for
status changes.
Change-Id: Ie6991881d912ba6fca6bb0fd9558633b1fb83492
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
Current code creates an output hw fence for any virtual
connector with a retire fence attached. This is a problem
for CWB, where the output-fence should be handled as a
sw-fence as current hw can only support a single hw-fence
per ctl path.
Fix this issue by adding a check to only create a retire
output hw-fence for virtual connectors that are not CWB.
Change-Id: I5863282d24ef8940b1f45c1fbd7584f91d28f0b8
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Currently, RC is using displayh and displayv variables
which are pointing to the LM dimension on a full frame
setting. If DS is enable and HW RC was not disabled the
the full frame ROI will not match the panel resolution
and cause an invalid hardware configuration.
This change uses the height and width values coming
from the mode information when a full frame ROI is
detected.
Change-Id: I274d15cbca61076ea7e95a984f907201e97b76ec
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
In MST atomic check function, add a check to ensure it's a disable call
before releasing vcpi slots to ensure atomic_release_vcpi_slots() and
atomic_find_vcpi_slots() are never called in the same atomic check
as mentioned in the kernel docs.
Change-Id: I36cf689b4d3bf9d2469a6c402b6377a667f01c12
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
Move print message from error to debug for a failure that is not fatal
but can be expected when a crtc doesn't have a hw ctl, in this case
driver will handle the output fence as a sw-fence.
Change-Id: I908135dce4336b0c9ec3fa388dc9211c6df97f68
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Add extra display driver debug events for input and output
hw-fences.
Change-Id: I32be1d25d98c510ebba5d39f8aff2a0c54144ba1
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Current display driver sets the hw-fences as valid even when
the speculative fence is empty. Avoid this issue by doing a
positive check and only create hw-fences if all the fences in
the speculative fence are valid.
Change-Id: Iec9636641ac9146eb651be08615e2478994c2508
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Currently when there is a modeset and usermode does not disable
or reprogram the RC mask, driver will compute an invalid configuration.
This change checks the RC mask with panel resolution and disables
RC HW internally if there is a mismatch.
Change-Id: I0e6afcf38cfc9165a6c0d2c12bfbc7b2b5f2ce65
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Program the read pointer after configuring the tearcheck registers.
The read pointer register should be configured after VSYNC_COUNTER_EN
is set as per hw programming sequence. Since the register programming
sequence is changed during the tearcheck configuration, remove the
redundant override call from idle-pc path.
Change-Id: I2fa1429798fab51d08091e74a33f1b1c4382eafe
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, panel jitter and loss of precision are not
compensated when calculating the trigger window size
for a QSYNC panel. These errors can be signigicant on
panels supporting very slow frame rate (10 Hz).
This change improves fixed point calculation and take
into account panel jitter when calculating the minimum
qsync time period.
Change-Id: Ibe620862afbd853580992fccec09cac8307b92bd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Currently, when there is an idle power collapse HW resets
the internal read pointer value to 0. This causes the trigger
window to be out of sync when power is restored until the
next vsync is received.
This change overrides the internal read pointer value to
the maximum qsync timeout value on restore and defers frame
trigger to next vsync.
Change-Id: Ibdad3f8eb367136ee0d766bed10742a281e36b4e
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Currently, aux switch is enabled by usbpd handler before
handing over the control to dispaly HPD handler. However,
in some scenarios there is a chance that altmode would
directly call into display HPD handler bypassing the usbpd
handler. This would lead to aux errors since aux switch
is not enabled. This change will enable aux switch in
display HPD handler which would avoid the resulting aux
errors. This issue is a regression caused by this change
b6466ca7f5.
Change-Id: I425991ba95b22411740f88cba5ca2083d13969e1
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
The encoder modeset updates all the plane's qos_dirty flag attached
to the crtc to make sure the qos params are updated during seamless
mode-switch cases like fps or resolution switch. But this is not
required for cwb encoder modeset as it does not have any effect on
the planes attached to the main display. Add check to avoid this
reprogramming.
Change-Id: I1ab7a71971b7200a50e6643407327734b1c9cbc5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
The cwb_enc_mask is set by the wb phys encoder during the validate
phase and this is in-turn used during the commit phase. During
seamless transition cases like poms with cwb, the encoders are
disabled and then enabled back after the validate phase. The cwb
flags are reset during this time leading to issues. Cache the flag
and reapply it during the modeset to avoid this case.
Change-Id: I5df1be18a5e30bb1107dc0f2e87d771a735f1ab6
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds support to wait on multiple hardware fences by
creating a fence array so each dpu-client only gets signaled until all
the hw fences going to the same ctl-path are signaled. It also
accounts for if a fence is a fence array.
Change-Id: Iba4b1d2b7322aea64dc197ca7655920b79dbb919
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Currently the panel esd_recovery_pending flag is cleared for every mode
set. The ESD recovery completes only after the suspend and resume. Clear
the flag only during power on commit.
Change-Id: I97e370feba0aad34558e4675168b4bcb7f5901ca
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Add logs to track the read/write line counters
and tear check configuration during key events.
Change-Id: Ife8afecc63a9008a8d9fc746d0ec8579a311b335
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds dsi display ramdump support when DEBUG_FS
is not enabled.
Change-Id: Ic6659a9380acd5eb55a3270d3e3b7016a9cd2bd7
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
