Add dsiclk_sel support for both DPHY and CPHY, update pclk_div
calculation w.r.t dsiclk_sel as per HPG.
Change-Id: I573addd62c77d1c9f089b7aadf386cd2e579f442
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Rename dsi_clk mux as dsiclk_sel to match the naming convention
with HPG.
Change-Id: I50671a78fccdd10d74d43fdf8ef4ede0c55fd09b
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Dither, unsharp should not be enable when VLUT
is disabled. This change ties dither, unsharp to VLUT
enable/disable and not during init property.
Change-Id: Idfad899a13252b22104c9746c86f4e158d9b0980
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
Currently revalidation of features happening for mode change(like
fps change, resolution change). This change limits revalidation
of feature only to resolution switch.
Change-Id: I3678e0e94eaad51e7b7a342eb451aa6329e8279d
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
In case of DATABUS_WIDEN, follow the HPG to calculate bitclk,
byteclk and pclk. Configure the DST_FORMAT and the clock
dividers in DSI PHY and DISP_CC w.r.t. the bpp before
compression.
Change-Id: I526eab5bc88b8d667b8b1a0d257b2f147998286a
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
When there is CWB enablement + dynamic clock change request in
single commit, during modeset enables the cwb seamless check
is hit for primary connector causing bridge pre enable
and enable calls skipped for dsi connector. This change ensures
the above seamless transition is taken care with any modeset case
as well.
Change-Id: I8d7ef4f8c579d44ddb0bfd5dc584fe5c778df886
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Suppose there's a mode change in Nth commit and N+1th commit mode
change request for dynamic clock came even before the Nth commit
mode is set in DSI. Now, restoring the bit clock and porches during
mode set of Nth commit will update the clock and porches according
to the new dynamic clock request which should have actually been
handled in N+1th commit mode set and this can lead to DSI underflow
/overflow.
Avoid restoring bit clock during bridge enable as it is already
taken care during bridge mode fixup.
Change-Id: Ieecb0020a77f5e082a8b9da0ecf461acdbe89e0c
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Since PLL UNLOCK status bit is a sticky bit, ensure this bit
is cleared before unmasking PLL UNLOCK error.
Otherwise unnecessarily DSI controller will trigger error
interrupts for the stale status, the moment error is
unmasked.
Change-Id: I7b7aa63b5e508dde446a4469d9a6625a071dae00
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Currently we are enabling all the lanes irrespective of the
lanes we are actually going to use. Add support to enable
only those lanes that are required and thus save power.
Change-Id: I9aae76eeaa05a79337d4e4b1f2e36ea9842bd580
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
If cont splash is enabled, wait for autorefresh_status to be idle for
1 vsync in prepare kickoff. This patch also prevents entering to
rsc_solver_mode if autorefresh_status is busy.
Change-Id: Ic4458dcbe8e06ff6f338dd264eb9371365120dd1
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
This change fixes the 'commit 1aacef1e1d ("disp: msm:
sde: fix UBWC decoder version support for Kalama")'.
Ubwc_ctrl must be set with global ubwc encoder version populated
from devicetree setting.
Change-Id: I85dc80e2e0436536a9b14e7e43199dc7b4421485
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
In back to back partial update cases with CWB the CROP
registers are not reset causing WB timeout in the
following sequence-
1) Nth commit WB_roi != LM_PU_roi, WB CROP registers
are programmed.
2) N+1th commit WB_roi == LM_PU_roi, WB CROP registers
are not cleared retaining old values.
Clear the WB CROP registers in the second case to fix
the issue.
Change-Id: If09a697f48ecaf5ee08d6313be444748d048b20d
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
During a seamless transition commit, the driver takes the values
of bandwidth (BW) and clock that were set during the set_property
phase of the commit, after the transition is completed. However,
during a non-seamless transition commit, the BW and clock
properties set by userspace cause the bw_control to be set to true.
When crtc is disabled, this bw_control is set to false. If there
are no updates to BW/clock for subsequent commits, the driver will
set the maximum value, which will affect the power consumed by the
display hardware. This change prevents bw_control from being set to
false if it is not a power-off commit.
Change-Id: I3348aacfb9ce338fe4625978364d14c11c2c26bc
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change limits reglog feature by default to user debug
builds only and provides debug option to selectively disable
reglog for power and perf profiling if required. This change
is needed as reglog is considerably heavy on commit thread
execution.
Change-Id: I781ae73cee09ce0fcddb6d2b3c847343c69f6c59
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
There is null pointer dereference seen due to concurrency
of wb_get_modes from userspace and clearing of writeback
modes in wb_reset. This change acquires mutex lock to provide
exclusive access to wb_dev effectively preventing such
concurrency issues.
Change-Id: Idd38e38696c839f557b94aa9313761d4d7738902
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
This change fixes an issue, where in CTL_2 was programmed for
secondary display and handoff was not done as the list traversal
logic was restricting it.
Change-Id: Icd945cfb3401ecc9c9c33059f5208a87979ada77
Signed-off-by: Yojana <quic_yjuadi@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Check for null value before dereferencing pointer to
drm_connector.
Change-Id: I38845ccab521e6e5e9ad052df57b25eba6bae9c0
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Change swaps right mixer flag when swapping mixer.
Histogram IRQ is registered to unexpected mixer
index if both mixers' right mixer flag set as false.
Change-Id: I0243d70129dc0c3bff24cabc8877c626101acd83
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
In userspace, the backlight scale of LTM will be set to the maximum value
in the suspend case. However, sometimes this value is sent to the driver
after resume. This will cause a backlight flicker issue.
For fix this issue, this change resets the backlight scale in the suspend
case.
Change-Id: I0eb586eeefbf3444d6f44281d58789460300dffc
Signed-off-by: Yuchao Ma <quic_yuchaom@quicinc.com>
Provision to vote for pm qos as a part of DP display host
initialisation and removing the same during host
deinitialisation sequence.
Change-Id: I5cd1b3783ddd2e93cab357855a090ec8b16adbdf
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
In CWB use case along with suspend commit, the function
drm_crtc_funcs.get_vblank_counter returns a zero vsync count
value. This causes blocking of drm_crtc_funcs.disable_vblank,
leading to a wait for vsync timeout while disabling the encoder.
hence clear a cwb encoder mask in encoder disable and set it
while performing mode set.
Change-Id: Ic994aa0a86faf48e2b25955cf6fe12166fe9d328
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In POMS use case, the handling of the wait for vsync event
completion coincides with the concurrent
drm_crtc_funcs.enable_vblank. This concurrency causes a vsync
event complete timeout while disabling the encoder. to fix this
concurrency problem, increment the vblank refcount in encoder
disable and release the vblank refcount in encoder enable.
Change-Id: I79671e4a2bafdd01a6b2523a80fe511bff23d6b6
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
This change adds out of bound check for interrupt id.
Change-Id: I10e786ee434629b0735c96da3c03eeac708935a1
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
Ensure to allocate switch type as bypass in case of dp aux switch
node missing in device tree entry and prevent any scope of null
pointer dereferencing.
Change-Id: I1d50d785e028f2e69a0effaedb2dbb6568a473dd
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
In the current SW design for a CWB commit the need for 3D-Merge
and number of CWB mux which needed to tap the LMs are decided
based on number of mixers on crtc. When there is a partial update
commit in single LM these 3D-Merge and CWB mux active are used
leading to WB commit failures. This change properly check whether
3D-Merge is needed in CWB path based on number of LMs in a partial
update commit.
Change-Id: I2c838a24ad3a259923f6b26934e681cb9a5829b6
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
The issue scenario is as follows
1. A CWB commit has run and it has disabled. Composer kill is
done.
2. If Composer starts again or another client has open DRM
the previous cwb state is intact.
3. When userspace is trying to query wb modes, primary modes
which are attached to wb as part of cwb commit is exposed.
This leads to commit failures if userspace is trying to trigger wb
on the same CRTC of what primary has run cwb before. This change
properly clears wb mode and the cached encoder mask to avoid commit
failures.
Change-Id: I4ca8bd2b52a980630b7fb1319bf67b718ebb2ac2
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
In POMS use case while disabling the virtual encoder, the virt
reset function sets the current master to null. concurrently, if
there is a query from the DRM client for the current vsync count,
it returns a zero value. This results in the blocking of the
drm_crtc_funcs.disable_vblank function. since the vsync count
has been relocated to the virtual encoder, remove the physical
encoder structure.
Change-Id: Ie692df657b5a86b6b8915a15e9a070642243fcfb
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
